Planar t-coil and integrated circuit including the same

Abstract

The integrated circuit may include a T-coil formed on a first metal layer, and the T-coil may include a first inductor connected to a first terminal and a second terminal, and a second inductor connected to a second terminal and a third terminal, and the first inductor and the second inductor may each include a first pattern and a second pattern extending mutually parallel to each other from the second terminal in a first direction in the first metal layer, and the first pattern and the second pattern may form a bridge capacitor of the T-coil.

Description

Technology Field

[0001] The technical concept of the present disclosure relates to T-coils, and more specifically, to planar T-coils and integrated circuits including the same. Background Technology

[0002] Capacitance in a signal path can arise from various causes. For example, signal path capacitance may include parasitic capacitance of the conductors and / or capacitance provided by components connected to the signal path. Signal path capacitance can affect impedance matching, gain, noise, and other factors, and consequently degrade signal integrity (SI). Accordingly, it may be important to effectively reduce the impact of signal path capacitance in high-speed signal transmission. The problem to be solved

[0003] The technical concept of the present disclosure provides a planar T-coil that effectively reduces the effect of capacitance in a signal path and an integrated circuit including the same. means of solving the problem

[0004] To achieve the above objectives, an integrated circuit according to one aspect of the technical concept of the present disclosure may include a T-coil formed on a first metal layer, the T-coil may include a first inductor connected to a first terminal and a second terminal, and a second inductor connected to a second terminal and a third terminal, and the first inductor and the second inductor may each include a first pattern and a second pattern extending mutually parallel to each other from the second terminal in a first direction in the first metal layer, and the first pattern and the second pattern may form a bridge capacitor of the T-coil.

[0005] An integrated circuit according to one aspect of the technical concept of the present disclosure may include a T-coil formed on a first metal layer, and the T-coil may include a first inductor connected to a first terminal and a second terminal, and a second inductor connected to a second terminal and a third terminal, and the first inductor may include a first pattern extending in a first direction from a second terminal in the first metal layer, a second pattern connected to the first pattern and extending in a second direction perpendicular to the first direction in the first metal layer, a third pattern connected to the second pattern and extending in a first direction in the first metal layer, and a fourth pattern connected to the third pattern and the first terminal and extending in a second direction in the first metal layer.

[0006] An integrated circuit according to one aspect of the technical concept of the present disclosure may include a first T-coil comprising a first inductor connected to a first terminal and a second terminal and a second inductor connected to a second terminal and a third terminal, a first pad electrically connected to a first terminal, a first ESD (electrostatic discharge) element electrically connected to a second terminal, and a first active circuit electrically connected to a third terminal, wherein the first inductor and the second inductor may be formed on a first metal layer. Effects of the invention

[0007] According to the T-coil and integrated circuit according to the exemplary embodiment of the present disclosure, a T-coil formed on a single metal layer can be provided, and accordingly, the T-coil can be effectively designed in an integrated circuit having limited metal layers.

[0008] In addition, according to the T-coil and integrated circuit of the exemplary embodiment of the present disclosure, a T-coil of higher reliability can be provided by being formed on a single metal layer, and accordingly, the operational reliability of the integrated circuit can be improved.

[0009] In addition, according to the T-coil and integrated circuit of the exemplary embodiment of the present disclosure, a T-coil having improved characteristics can be designed, and accordingly, the capacitance of the signal path can be effectively reduced or eliminated.

[0010] In addition, according to the T-coil and integrated circuit of the exemplary embodiment of the present disclosure, a signal can be transmitted at high speed due to the reduction or elimination of capacitance in the signal path, and the performance of the integrated circuit and the system including the integrated circuit can be improved.

[0011] The effects obtainable from the exemplary embodiments of the present disclosure are not limited to those mentioned above, and other unmentioned effects can be clearly derived and understood by those skilled in the art to which the exemplary embodiments of the present disclosure belong from the description below. That is, unintended effects resulting from the implementation of the exemplary embodiments of the present disclosure can also be derived by those skilled in the art from the exemplary embodiments of the present disclosure. Brief explanation of the drawing

[0012] FIG. 1 is a block diagram showing an integrated circuit according to an exemplary embodiment of the present disclosure. Figures 2a and 2b are drawings showing a T-coil according to a comparative example. FIGS. 3a and FIGS. 3b are drawings showing a T-coil according to an exemplary embodiment of the present disclosure. Figures 4a and 4b are graphs showing the characteristics of T-coils. FIG. 5 is a drawing showing a T-coil according to an exemplary embodiment of the present disclosure. FIG. 6 is a block diagram showing a system according to an exemplary embodiment of the present disclosure. FIGS. 7a and 7b are plan views illustrating examples of memory devices according to exemplary embodiments of the present disclosure. FIG. 8 is a drawing showing a memory module according to an exemplary embodiment of the present disclosure. FIG. 9 is a drawing showing a cross-section of a system according to an exemplary embodiment of the present disclosure. Specific details for implementing the invention

[0013] FIG. 1 is a block diagram showing an integrated circuit (10) according to an exemplary embodiment of the present disclosure. The integrated circuit (10) can be manufactured through a semiconductor process. As shown in FIG. 1, the integrated circuit (10) may include a pin (11), a T-coil (TC), an ESD capacitor (Ca), a termination resistor (Rt), and an active circuit (CKT).

[0014] The pin (11) may be composed of a conductive material (e.g., metal) and may be exposed to the outside of the integrated circuit (10). For example, as shown in FIG. 1, the pin (11) may be a bidirectional pin, and the integrated circuit (10) may receive a signal through the pin (11) in a receiving mode, while the integrated circuit (10) may output a signal through the pin (11) in a transmitting mode. In some embodiments, the pin (11) may be an input pin, and the integrated circuit (10) may receive a signal from the outside through the pin (11). In some embodiments, the pin (11) may be an output pin, and the integrated circuit (10) may output a signal to the outside through the pin (11).

[0015] If an electrostatic discharge (ESD) occurs at an externally exposed pin (11), the components inside the integrated circuit (10) may be damaged. For example, the ESD resistance of the components included in the integrated circuit (10) may depend on the breakdown voltage of the gate oxide of the transistor, and as the thickness of the gate oxide gradually decreases, the breakdown voltage may decrease, and accordingly, the integrated circuit (10) may include components that are more sensitive to ESD. To prevent damage to the components due to ESD, the integrated circuit (10) may include ESD components such as diodes, capacitors, etc. The ESD components can protect the components of the integrated circuit (10) from ESD by accommodating charges generated by ESD.

[0016] An ESD device can provide capacitance to a signal path including a pin (11), and the capacitance of the ESD device can limit high-speed transmission of the signal. For example, as illustrated in FIG. 1, the ESD device can be modeled as an ESD capacitor (Ca), and the ESD capacitor (Ca) may be required to have reduced capacitance as the frequency of the signal input / output through the pin (11) increases. However, due to the limited space for ESD-sensitive devices and / or the ESD device included in the integrated circuit (10), designing an ESD device with reduced capacitance may not be easy. Accordingly, the integrated circuit (10) may include a T-coil (TC) to reduce or eliminate the capacitance of the ESD capacitor (Ca).

[0017] A T-coil (TC) may have three terminals. For example, as illustrated in FIG. 1, a T-coil (TC) may include a first terminal (A) connected to a pin (11), a second terminal (B) connected to a capacitor (Ca), and a third terminal (C) connected to an active circuit (CKT). A T-coil (TC) may include a first inductor (L1) connected to the first terminal (A) and the second terminal (B), a second inductor (L2) connected to the second terminal (B) and the third terminal (C), and a bridge capacitor (Cb) connected to the first terminal (A) and the third terminal (C). As described below with reference to the drawings, the bridge capacitor can be formed by mutually adjacent first inductors (L1) and second inductors (L2) and can have a capacitance generated by a part of the first inductor (L1) and second inductor (L2). A high-frequency signal passing through the pin (11) may not be affected by the ESD capacitor (Ca) by the first inductor (L1) and second inductor (L2) of the T-coil (TC). Additionally, a signal of a frequency lower than the first frequency may pass through the first inductor (L1) and second inductor (L2) of the T-coil (TC), while a signal of a frequency higher than the first frequency may pass through the bridge capacitor (Cb). The first frequency and the second frequency can be defined by the inductance of the first inductor (L1), the inductance of the second inductor (L2), and the capacitance of the bridge capacitor (Cb).

[0018] In the T-coil (TC), the inductance of the first inductor (L1), the inductance of the second inductor (L2), and the capacitance of the bridge capacitor (Cb) can be determined based on the capacitance of the ESD capacitor (Ca). For example, the inductance L1 of the first inductor (L1) and the inductance L2 of the second inductor (L2) of the T-coil (TC) are determined based on the capacitance C of the ESD capacitor (Ca). a It can be calculated from based on the following [Equation 1].

[0019]

[0020] In [Mathematical Equation 1], R t θ may be the resistance value of the termination resistor (Rt), and the termination resistor (Rt) may have a variable resistance value for impedance matching. In some embodiments, the termination resistor (Rt) may be omitted. Additionally, the coupling coefficient k between the first inductor (L1) and the second inductor (L2) can be calculated based on [Equation 2] below.

[0021]

[0022] In addition, the capacitance C of the bridge capacitor (Cb) b is the capacitance C of the ESD capacitor (Ca). a It can be calculated based on the following [Equation 3].

[0023]

[0024] In [Equation 1], [Equation 2] and [Equation 3], ζ can be the damping factor of the network transfer function.

[0025] The active circuit (CKT) can be connected to the T-coil (TC) and can process a signal received through pin (11) or generate a signal to be output through pin (11). For example, as illustrated in FIG. 1, the active circuit (CKT) may include a TX buffer (BUF1) and an RX buffer (BUF2). The TX buffer (BUF1) can generate a signal to be output to the outside of the integrated circuit (10) through pin (11) in transmission mode, and the RX buffer (BUF2) can process a signal received from the outside of the integrated circuit (10) through pin (11) in reception mode. In some embodiments, if pin (11) is an input pin, the TX buffer (BUF1) in the active circuit (CKT) may be omitted. In some embodiments, if pin (11) is an output pin, the RX buffer (BUF2) in the active circuit (CKT) may be omitted.

[0026] As described below with reference to the drawings, the T-coil (TC) can be formed on a single metal layer, and thus the T-coil (TC) can be effectively designed when the integrated circuit (10) includes limited metal layers. Additionally, the T-coil (TC) formed on a single metal layer can provide higher reliability, and thus the operational reliability of the integrated circuit (100) can be improved. Furthermore, the T-coil (TC) can be designed to have improved characteristics, and thus the capacitance of the ESD capacitor (Ca) can be effectively reduced or eliminated. Consequently, due to the reduced or eliminated capacitance of the ESD capacitor (Ca), a signal can be transmitted at high speed through the pin (11), and the performance of the integrated circuit (10) and the system including the integrated circuit (10) can be improved.

[0027] FIGS. 2a and FIGS. 2b are drawings showing a T-coil (20) according to a comparative example. Specifically, FIG. 2a includes a plan view showing the T-coil (20) in a plane formed by the X-axis and the Y-axis, and a cross-sectional view showing a cross-section of the T-coil (20) cut along the line X1-X1', and FIG. 2b shows a first inductor (L1) and a second inductor (L2) included in the T-coil (20).

[0028] In this specification, the direction parallel to the Y-axis and the direction parallel to the X-axis may be referred to as the first direction and the second direction, respectively, and the direction parallel to the Z-axis may be referred to as the third direction or the vertical direction. The plane formed by the X-axis and the Y-axis may be referred to as the horizontal plane, a component positioned in the +Z direction relative to another component may be referred to as being above another component, and a component positioned in the -Z direction relative to another component may be referred to as being below another component. Additionally, the area of ​​a component may refer to the size occupied by the component in a plane parallel to the horizontal plane, and the width of a component may refer to the length in a direction orthogonal to the direction in which the component extends. Furthermore, if components are coupled or electrically connected, they may be referred to as being connected. In the drawings of this specification, only some layers may be depicted for convenience of illustration. Additionally, a pattern composed of a conductive material, such as a pattern of a metal layer, may be referred to as a conductive pattern or simply a pattern.

[0029] Referring to FIG. 2a, the T-coil (20) may be formed on two metal layers. For example, the first terminal (A), the second terminal (B), and the third terminal (C) of the T-coil (20) may be formed on the upper metal layer, and the T-coil (20) may include patterns connected to the first terminal (A), the second terminal (B), and / or the third terminal (C) on the upper metal layer. Additionally, the T-coil (20) may include patterns on the lower metal layer at the intersection of the first inductor (L1) and the second inductor (L2). For example, the T-coil (20) may include two vias connecting the patterns on the upper metal layer and the patterns on the lower metal layer in a via metal layer between the upper metal layer and the lower metal layer.

[0030] To prevent the generation of reflected waves, the T-coil (20) may include patterns extending with a constant width. For example, as shown in FIG. 2a, the T-coil (20) may include patterns extending in a direction parallel to the X-axis or Y-axis with a first width (W1) in the upper metal layer. Additionally, the T-coil (20) may include patterns extending in a direction parallel to the X-axis or Y-axis with a first width (W1) in the lower metal layer. As previously described, the T-coil (20) may include vias connecting the patterns of the upper metal layer and the patterns of the lower metal layer, and accordingly, the first width (W) may depend on the area of ​​the vias. For example, as shown in the cross-sectional view of FIG. 2a, the first pattern (T1) of the upper metal layer and the second pattern (T2) of the lower metal layer may have an area greater than the area of ​​the via (V) in the portion contacting the via (V) in order to be fully connected to the via (V) by a semiconductor process. Accordingly, the first width (W1) may be wider than the second width (W2) described later with reference to FIG. 3a and FIG. 3b.

[0031] Referring to FIG. 2b, the first inductor (L1) and the second inductor (L2) included in the T-coil (20) are shown separately, and the second terminal (B) is shown redundantly for convenience of illustration. When current flows from the first terminal (A) to the second terminal (B) in the first inductor (L1), magnetic flux may be generated within the first inductor (L1) as shown in FIG. 2b. Additionally, when current flows from the second terminal (B) to the third terminal (C) in the second inductor (L2), magnetic flux may be generated within the second inductor (L2) as shown in FIG. 2b.

[0032] As illustrated in FIG. 2b, the first inductor (L1) and the second inductor (L2) may have different shapes. In particular, the second inductor (L2) may include only a pattern formed on the upper metal layer, whereas the first inductor (L1) may include not only a pattern formed on the upper metal layer but also a pattern and vias formed on the lower metal layer. Accordingly, the first inductor (L1) and the second inductor (L2) may be asymmetric, and it may not be easy to design the first inductor (L1) and the second inductor (L2) to have the same inductance.

[0033] FIGS. 3a and 3b are drawings showing a T-coil (30) according to an exemplary embodiment of the present disclosure. Specifically, FIG. 3a includes a plan view showing the T-coil (30) in a plane formed by the X-axis and the Y-axis, and a cross-sectional view showing a cross section of the T-coil (30) cut along the line X2-X2', and FIG. 3b shows a first inductor (L1) and a second inductor (L2) included in the T-coil (30).

[0034] Referring to FIG. 3a, the T-coil (30) may be formed on a single metal layer. For example, the first terminal (A), the second terminal (B), and the third terminal (C) of the T-coil (30) may be formed on an upper metal layer, and the T-coil (30) may include patterns connected to the first terminal (A), the second terminal (B), and / or the third terminal (C) on the upper metal layer. In the T-coil (30) formed on a single metal layer, i.e., the upper metal layer, vias and patterns formed on the lower metal layer may be omitted, and the T-coil (30) may have a simpler structure than the T-coil (20) of FIG. 2a. Due to the simple structure of the T-coil (30), the T-coil (20) may be manufactured at a lower cost (e.g., lower complexity of the semiconductor process) and may provide higher reliability.

[0035] To prevent the generation of reflected waves, the T-coil (30), like the T-coil (20) of FIG. 2a, may include patterns that extend with a constant width. For example, as shown in FIG. 3a, the T-coil (30) may include patterns that extend in a direction parallel to the X-axis or Y-axis with a second width (W2) in the upper metal layer. By omitting vias for connecting to the patterns of the lower metal layer, the patterns of the T-coil (30) may have a second width (W2) independent of the vias, and accordingly, the patterns of the T-coil (30) may have a second width (W2) smaller than the first width (W1) of FIG. 2a. Accordingly, the T-coil (30) may have a higher degree of design freedom than the T-coil (20) of FIG. 2a, and an optimal T-coil (30) may be designed. Additionally, as described below with reference to FIGS. 4a and 4b, the T-coil (30) of FIG. 3a may have better characteristics than the T-coil (20) of FIG. 2a.

[0036] In some embodiments, the metal layer on which the T-coil (30) is formed may be the uppermost metal layer in the integrated circuit. For example, as illustrated in the cross-sectional view of FIG. 3a, the T-coil (30) may include patterns formed in the upper metal layer, and the upper metal layer may be the uppermost metal layer among the metal layers below which the pads exposed to the outside in the integrated circuit are formed. In some embodiments, the integrated circuit may further include at least one rewiring layer for routing the pads between the metal layer on which the pads are formed and the upper metal layer on which the T-coil (30) is formed. In the integrated circuit, the metal layers may have a thickness that increases as they go upward (i.e., length in the direction parallel to the Z-axis), and accordingly, the cross-sectional area of ​​the pattern included in the T-coil (30) may increase. In this specification, the upper metal layer may be referred to as the first metal layer.

[0037] Referring to FIG. 3b, the first inductor (L1) and the second inductor (L2) included in the T-coil (30) are shown separately, and the second terminal (B) is shown redundantly for convenience of illustration. When current flows from the first terminal (A) to the second terminal (B) in the first inductor (L1), magnetic flux may be generated within the first inductor (L1) as shown in FIG. 3b. Additionally, when current flows from the second terminal (B) to the third terminal (C) in the second inductor (L2), magnetic flux may be generated within the second inductor (L2) as shown in FIG. 3b.

[0038] As illustrated in FIG. 3b, the first inductor (L1) and the second inductor (L2) may have a symmetrical structure centered on a line parallel to the Y-axis. For example, the first inductor (L1) and the second inductor (L2) may include only a pattern formed on an upper metal layer, and thus can be easily designed to have a mutually symmetrical structure. Accordingly, the first inductor (L1) and the second inductor (L2) satisfying [Equation 1] and [Equation 2] can be easily designed.

[0039] FIGS. 4a and 4b are graphs showing the characteristics of T-coils. Specifically, the graph in FIG. 4a shows the total inductance according to frequency of the T-coil (20) in FIG. 2a and the T-coil (30) in FIG. 3a, and the graph in FIG. 4b shows the quality factor according to frequency of the T-coil (20) in FIG. 2a and the T-coil (30) in FIG. 3a. Below, FIGS. 4a and 4b will be explained with reference to FIGS. 2a and 3a.

[0040] Referring to FIG. 4a, curve (41) may correspond to the T-coil (20) of FIG. 2a, and curve (42) may correspond to the T-coil (30) of FIG. 3a. As shown in FIG. 4a, the T-coil (20) of FIG. 2a has a relatively large variation in total inductance with frequency change, whereas the T-coil (30) of FIG. 3a has a relatively small variation in total inductance with frequency change. Accordingly, the T-coil (30) of FIG. 3a can provide more stable performance over a wide frequency range.

[0041] Referring to FIG. 4b, curve (43) may correspond to the T-coil (20) of FIG. 2a, and curve (44) may correspond to the T-coil (30) of FIG. 3a. The Q-factor can be defined as 'inductance / resistance value', and a higher Q-factor may be advantageous. As shown in FIG. 4b, the T-coil (20) of FIG. 2a may have a relatively low Q-factor at high frequencies, whereas the T-coil (30) of FIG. 3a may have a relatively high Q-factor at high frequencies. Accordingly, the T-coil (30) of FIG. 3a may provide higher performance in the high frequency range.

[0042] FIG. 5 is a drawing showing a T-coil (50) according to an exemplary embodiment of the present disclosure. As described above with reference to the drawings, the T-coil (50) may include a first terminal (A), a second terminal (B), and a third terminal (C), and may include a first inductor (L1) and a second inductor (L2).

[0043] The first inductor (L1) and the second inductor (L2) may include patterns formed on the upper metal layer. For example, as shown in FIG. 5, the first inductor (L1) may include a first pattern (T1), a second pattern (T2), a third pattern (T3), and a fourth pattern (T4) in the upper metal layer. The first pattern (T1) may extend from the second terminal (B) in a direction parallel to the Y-axis. The second pattern (T2) may be connected to the first pattern (T1) and may extend in a direction parallel to the X-axis. The third pattern (T3) may be connected to the second pattern (T2) and may extend in a direction parallel to the Y-axis. The fourth pattern (T4) may be connected to the third pattern (T3) and the first terminal (A) and may extend in a direction parallel to the X-axis. Additionally, the second inductor (L2) may include a fifth pattern (T5), a sixth pattern (T6), a seventh pattern (T7), and an eighth pattern (T8) in the upper metal layer. The fifth pattern (T5) may extend from the second terminal (B) in a direction parallel to the Y-axis. The sixth pattern (T6) may be connected to the fifth pattern (T5) and may extend in a direction parallel to the X-axis. The seventh pattern (T7) may be connected to the sixth pattern (T6) and may extend in a direction parallel to the Y-axis. The eighth pattern (T8) may be connected to the seventh pattern (T7) and may extend in a direction parallel to the X-axis.

[0044] The first inductor (L1) and the second inductor (L2) may have a symmetrical structure centered on a line (Y1) passing through the second terminal (B) in a direction parallel to the Y-axis. Accordingly, the length (H1) of the first inductor (L1) in a direction parallel to the X-axis may be the same as the length (H2) of the second inductor (L2) in a direction parallel to the X-axis, and the length (V1) of the first inductor (L1) in a direction parallel to the Y-axis may be the same as the length (V2) of the second inductor (L2) in a direction parallel to the Y-axis. When the lengths of the first inductor (L1) and the second inductor (L2) in the direction parallel to the X-axis are equal to H and the lengths of the first inductor (L1) and the second inductor (L2) in the direction parallel to the Y-axis are equal to V, the inductance L1 of the first inductor (L1) and the inductance L2 of the second inductor (L2) can be calculated based on the following [Equation 4].

[0045]

[0046] [Equation 4] μ0 may be intrinsic permeability, and W may be the width of the patterns of the first inductor (L1) and the second inductor (L2). As described above with reference to the drawings, the first pattern (T1), second pattern (T2), third pattern (T3), and fourth pattern (T4) of the first inductor (L1), and the fifth pattern (T5), sixth pattern (T6), seventh pattern (T7), and eighth pattern (T8) of the second inductor (L2) may each be extended in a direction parallel to the X-axis or Y-axis with the same width.

[0047] The bridge capacitor (Cb) of the T-coil (50) can be formed by a part of the first inductor (L1) and a part of the second inductor (L2). For example, as shown in FIG. 5, the first pattern (T1) of the first inductor (L1) and the fifth pattern (T5) of the second inductor (L2) can be adjacent to each other in a direction parallel to the X-axis and can be extended parallel to each other. The capacitance of the bridge capacitor (Cb) can be determined based on the lengths of the first pattern (T1) and the fifth pattern (T5) and the distance between the first pattern (T1) and the fifth pattern (T5), and accordingly, a bridge capacitor (Cb) satisfying [Equation 3] can be easily designed.

[0048] FIG. 6 is a block diagram illustrating a system (60) according to an exemplary embodiment of the present disclosure. As illustrated in FIG. 6, the system (60) may include a memory controller (61) and a memory device (62). In some embodiments, the memory controller (61) and the memory device (62) may each be an independent die (or chip) manufactured by a semiconductor process, may communicate with each other through wires, and may include pins connected to the wires. In this specification, the memory device (62) may be referred to as a semiconductor memory device.

[0049] The memory controller (61) can write data to the memory device (62) and read data stored in the memory device (62). For example, the memory controller (61) can provide a control signal (CTR) and an address signal (ADR) to the memory device (62) to write data, and can provide the data to be written to the memory device (62) through a data signal (DQ). Additionally, the memory controller (61) can provide a control signal (CTR) and an address signal (ADR) to the memory device (62) to read data, and can receive the read data from the memory device (62) through the data signal (DQ). In some embodiments, the memory controller (61) may provide a command to the memory device (62) through the address signal (ADR). In some embodiments, the memory controller (61) may be included in a system-on-chip (SoC), such as an application processor (AP), and may be referred to as a memory interface.

[0050] The memory device (62) can store data received from the memory controller (61) and can provide the stored data to the memory controller (61). For example, the memory device (62) can store data received via a data signal (DQ) in response to a control signal (CTR) in an area corresponding to an address signal (ADR). Additionally, the memory device (62) can provide data stored in the area corresponding to the address signal (ADR) to the memory controller (61) via the data signal (DQ) in response to a control signal (CTR). In some embodiments, the memory device (62) may store data or output the stored data in response to a command received via the address signal (ADR).

[0051] The memory device (62) may have any structure capable of storing data. For example, the memory device (62) may include volatile memory such as DRAM (dynamic random access memory) and SRAM (static random access memory), and / or non-volatile memory such as flash memory and RRAM (resistive random access memory). In some embodiments, the memory device (62) may further receive a clock signal, a data strobe signal, etc. from the memory controller (61).

[0052] The memory controller (61) and the memory device (62) may include a plurality of pins for transmitting or receiving a control signal (CTR), an address signal (ADR), and a data signal (DQ). As described above with reference to the drawings, each of the memory controller (61) and the memory device (62) may include a plurality of ESD elements corresponding to the plurality of pins to protect internal elements from ESD. As the signal bandwidth between the memory controller (61) and the memory device (62) increases, the capacitance attributable to the ESD elements may have a significant impact on signal integrity (SI), and the T-coil described above with reference to the drawings may be included in the memory controller (61) and / or the memory device (62). Accordingly, the capacitance of the ESD elements may be effectively reduced or eliminated, and a reduction in the bandwidth between the memory controller (61) and the memory device (62) may be prevented. In the following, the T-coil included in the memory device (62) will be mainly described, but it should be noted that exemplary embodiments of the present disclosure are not limited thereto.

[0053] FIGS. 7a and 7b are plan views illustrating examples of memory devices according to exemplary embodiments of the present disclosure. Specifically, the plan views of FIGS. 7a and 7b schematically illustrate some pads included in memory devices (70a, 70b) and some patterns connected to some pads. As described above with reference to FIG. 6, memory devices (70a, 70b) may include an ESD element and may include a T-coil formed on an upper metal layer to reduce or eliminate the capacitance of the ESD element. In the following description of FIGS. 7a and 7b, mutually overlapping content will be omitted.

[0054] Referring to FIG. 7a, the memory device (70a) may include pads aligned in a direction parallel to the X-axis. The pads may be exposed to the outside from the memory device (70a) formed as a die (or chip) and may be composed of a conductive material. As illustrated in FIG. 7a, a series of pads including a first pad (P1), a second pad (P2), a third pad (P3), a fourth pad (P4), and a fifth pad (P5) may be aligned in a direction parallel to the X-axis, and a series of pads including a sixth pad (P6), a seventh pad (P7), an eighth pad (P8), a ninth pad (P9), and a tenth pad (P10) may be aligned in a direction parallel to the X-axis. Additionally, the first pad (P1), the second pad (P2), the third pad (P3), the fourth pad (P4), and the fifth pad (P5) may each face the sixth pad (P6), the seventh pad (P7), the eighth pad (P8), the ninth pad (P9), and the tenth pad (P10) in a direction parallel to the Y-axis.

[0055] In some embodiments, a T-coil may be connected to a pad through which a data signal of the memory device (70a) passes. For example, as illustrated in FIG. 7a, the memory device (70a) may include a first T-coil (TC1) for a second pad (P2) through which a data signal (DQ11) passes, a second T-coil (TC2) for a fourth pad (P4) through which a data signal (DQ12) passes, a third T-coil (TC3) for a seventh pad (P7) through which a data signal (DQ21) passes, and a fourth T-coil (TC4) for a ninth pad (P9) through which a data signal (DQ22) passes. In some embodiments, a T-coil for a pad to which a positive supply voltage (VDD) or a negative supply voltage (or ground potential) (VSS) is applied may be omitted in order to supply power to the memory device (70a). For example, as shown in FIG. 7a, T-coils for the first pad (P1), fifth pad (P5), sixth pad (P6) and tenth pad (P10) to which a positive supply voltage (VDD) is applied may be omitted, and T-coils for the third pad (P3) and eighth pad (P8) to which a negative supply voltage (VSS) is applied may be omitted.

[0056] In some embodiments, the T-coil may extend in a direction away from the pad opposite to the pad connected to it. For example, the first T-coil (TC1) for the second pad (P2) may include a pattern extending away from the seventh pad (P7) opposite the second pad (P2) in a direction parallel to the Y-axis (i.e., -Y-axis direction). The second T-coil (TC2) for the fourth pad (P4) may include a pattern extending away from the ninth pad (P9) opposite the fourth pad (P4) in a direction parallel to the Y-axis (i.e., -Y-axis direction). The third T-coil (TC3) for the seventh pad (P7) may include a pattern extending away from the second pad (P2) opposite the seventh pad (P7) in a direction parallel to the Y-axis (i.e., +Y-axis direction). The fourth T-coil (TC4) for the ninth pad (P9) may include a pattern extending away from the fourth pad (P4) in a direction parallel to the Y-axis (i.e., +Y-axis direction) to the ninth pad (P9). As described above, the T-coil may extend from the pad toward the edge of the memory device (70a) and thus may not affect the patterns (not shown) of the upper metal layer positioned between the series of pads aligned parallel to the X-axis and the series of pads aligned parallel to the X-axis.

[0057] Referring to FIG. 7b, the memory device (70b) may include a first pad (P1), a second pad (P2), a third pad (P3), a fourth pad (P4), and a fifth pad (P5) aligned in a direction parallel to the X-axis, and may include a sixth pad (P6), a seventh pad (P7), an eighth pad (P8), a ninth pad (P9), and a tenth pad (P10) aligned in a direction parallel to the X-axis. Additionally, the memory device (70b) may include a first T-coil (TC1), a second T-coil (TC2), a third T-coil (TC3), and a fourth T-coil (TC4) for data signals.

[0058] In some embodiments, pads for a power supply and pads for a data signal may be arranged alternately in a series of pads aligned in a direction parallel to the X-axis. For example, as shown in FIG. 7b, a second pad (P2) for a data signal (DQ11) may be placed between a first pad (P1) for a positive supply voltage (VDD) and a third pad (P3) for a negative supply voltage (VSS). A third pad (P3) for a negative supply voltage (VSS) may be placed between a second pad (P2) for a data signal (DQ11) and a fourth pad (P4) for a data signal (DQ12). A fourth pad (P4) for a data signal (DQ12) may be placed between a third pad (P3) for a negative supply voltage (VSS) and a fifth pad (P5) for a positive supply voltage (VDD). Additionally, the seventh pad (P7) for the data signal (DQ21) may be placed between the sixth pad (P6) for the positive supply voltage (VDD) and the eighth pad (P8) for the negative supply voltage (VSS). The eighth pad (P8) for the negative supply voltage (VSS) may be placed between the seventh pad (P7) for the data signal (DQ21) and the ninth pad (P9) for the data signal (DQ22). The ninth pad (P9) for the data signal (DQ22) may be placed between the eighth pad (P8) for the negative supply voltage (VSS) and the tenth pad (P10) for the positive supply voltage (VDD).

[0059] In some embodiments, the memory device (70b) may include a shield pattern disposed between mutually adjacent T-coils. For example, as illustrated in FIG. 7b, the memory device (70b) may include a first pattern (T1) connected to a first pad (P1) for a positive supply voltage (VDD), and the first pattern (T1) may extend in a direction parallel to the Y-axis adjacent to the first T-coil (TC1). The memory device (70b) may include a second pattern (T2) connected to a third pad (P3) for a negative supply voltage (VSS), and the second pattern (T2) may extend in a direction parallel to the Y-axis between the first T-coil (TC1) and the second T-coil (TC2). The memory device (70b) may include a third pattern (T3) connected to a fifth pad (P5) for a positive supply voltage (VDD), and the third pattern (T3) may extend in a direction parallel to the Y-axis adjacent to the second T-coil (TC2). Additionally, the memory device (70b) may include a fourth pattern (T4) connected to a sixth pad (P6) for a positive supply voltage (VDD), and the fourth pattern (T4) may extend in a direction parallel to the Y-axis adjacent to the third T-coil (TC3). The memory device (70b) may include a fifth pattern (T5) connected to an eighth pad (P8) for a negative supply voltage (VSS), and the fifth pattern (T5) may extend in a direction parallel to the Y-axis between the third T-coil (TC3) and the fourth T-coil (TC4). The memory device (70b) may include a sixth pattern (T6) connected to a first pad (P10) for a positive supply voltage (VDD), and the sixth pattern (T6) may extend in a direction parallel to the Y-axis adjacent to a fourth T-coil (TC4).Due to the positive supply voltage (VDD) and negative supply voltage (VSS) functioning as signal grounds, each of the first pattern (T1), second pattern (T2), third pattern (T3), fourth pattern (T4), fifth pattern (T5), and sixth pattern (T6) can function as a shield for adjacent T-coils, and thus interference between T-coils can be reduced or eliminated.

[0060] FIG. 8 is a drawing showing a memory module (80) according to an exemplary embodiment of the present disclosure. As shown in FIG. 8, the memory module (80) may include a printed circuit board (PCB) (81), a plurality of DRAM chips (81_1 to 82_8) and a buffer chip (83).

[0061] A plurality of DRAM chips (81_1 to 82_8) and a buffer chip (83) may be mounted on a printed circuit board (81), and connectors (84) may be formed along one edge of the printed circuit board (81). When a memory module (80) is inserted into a socket, the connectors (84) may come into contact with pins included in the socket, and control signals, address signals, clock signals, data signals, etc. may be transmitted to the plurality of DRAM chips (81_1 to 82_8) and / or the buffer chip (83) through the connectors (84). The plurality of DRAM chips (82_1 to 82_8) and / or the buffer chip (83) may include an ESD element and may include the T-coil described above with reference to the drawings for reducing or eliminating the capacitance of the ESD element.

[0062] A plurality of DRAM chips (82_1 to 82_8) may include clock-synchronous DRAM such as SDRAM (synchronous dynamic random access memory). For example, each of the plurality of DRAM chips (82_1 to 82_8) may include DDR (double data rate) SDRAM, LPDDR (low power double data rate) SDRAM, GDDR (graphics double data rate) SDRAM, RDRAM (rambus dynamic random access memory), etc. The buffer chip (83) may receive and buffer signals from an external device of the memory module (80) (e.g., 61 in FIG. 6) and provide the buffered signals to the plurality of DRAM chips (82_1 to 82_8).

[0063] FIG. 9 is a cross-sectional view of a system (90) according to an exemplary embodiment of the present disclosure. As shown in FIG. 9, the system (90) may include a high bandwidth memory (HBM) device (91), a processing circuit (92), an interposer (93), and a printed circuit board (94).

[0064] The HBM device (91) may include a first memory die (MD1), a second memory die (MD2), a third memory die (MD3), a fourth memory die (MD4), and a base die (BD), and may be referred to as an HBM system. As illustrated in FIG. 9, the first memory die (MD1), the second memory die (MD2), the third memory die (MD3), and the fourth memory die (MD4) may be stacked on the base die (BD), and microbumps (MB) may be disposed between the first memory die (MD1), the second memory die (MD2), the third memory die (MD3), the fourth memory die (MD4), and the base die (BD). The microbumps (MB) may be connected to through silicon vias (TSVs) that penetrate each of the first memory die (MD1), the second memory die (MD2), the third memory die (MD3), and the fourth memory die (MD4). In some embodiments, the first to fourth memory dies (MD1 to MD4) may be collectively referred to as HBM.

[0065] A base die (BD) may be placed on an interposer (93), and first bumps (B1) may be placed between the base die (BD) and the interposer (93). Address signals, control signals, and data signals for accessing a first memory die (MD1), a second memory die (MD2), a third memory die (MD3), and a fourth memory die (MD4) may pass through the first bumps (B1). In some embodiments, the first memory die (MD1), the second memory die (MD2), the third memory die (MD3), the fourth memory die (MD4) and / or the base die (BD) may include an ESD element and may include the T-coil described above with reference to the drawings.

[0066] A processing circuit (92) may be disposed on an interposer (93), and second bumps (B2) may be disposed between the processing circuit (92) and the interposer (93). The processing circuit (92) may communicate with the base die (BD) through some of the second bumps (B2), patterns formed on the interposer (93), and some of the first bumps (B1), and may write data to the HBM device (91) or read data from the HBM device (91). For example, the processing circuit (92) may include a central processing unit (CPU), a graphic processing unit (GPU), a neural processing unit (NPU), etc. In some embodiments, the processing circuit (92) may include an ESD element and may include the T-coil described above with reference to the drawings.

[0067] An interposer (93) may be disposed on a printed circuit board (94), and third bumps (B3) may be disposed between the interposer (93) and the printed circuit board (94). In some embodiments, the third bumps (B3) may be flip-die bumps. The interposer (93) may include a plurality of patterns for interconnecting the HBM device (91) and the processing circuit (92). Fourth bumps (B4) may be disposed on the lower surface of the printed circuit board (94), and the system (90) may communicate with the outside through the fourth bumps (B4).

[0068] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims.

Claims

Claim 1 An integrated circuit comprising a T-coil formed only on a first metal layer, wherein the T-coil comprises: a first inductor connected to a first terminal and a second terminal; and a second inductor connected to the second terminal and a third terminal, wherein the first inductor comprises a first pattern connected to the second terminal in the first metal layer, and the second inductor comprises a second pattern connected to the second terminal in the first metal layer, and wherein the first pattern and the second pattern extend mutually parallel from the second terminal in the first metal layer and are configured to form a bridge capacitor of the T-coil. Claim 2 An integrated circuit according to claim 1, wherein the first inductor and the second inductor are mutually symmetrical with respect to a line passing through the second terminal in the first direction. Claim 3 An integrated circuit according to claim 1, wherein the first pattern and the second pattern have a width narrower than the width of the pattern connected to the via of the lower via layer in the first metal layer. Claim 4 An integrated circuit according to claim 1, further comprising an electrostatic discharge (ESD) element connected to the second terminal. Claim 5 An integrated circuit according to claim 4, wherein the inductance of each of the first inductor and the second inductor is proportional to the capacitance of the ESD element, and the capacitance of the bridge capacitor is proportional to the capacitance of the ESD element. Claim 6 An integrated circuit comprising a T-coil formed only on a first metal layer, wherein the T-coil comprises: a first inductor connected to a first terminal and a second terminal; and a second inductor connected to the second terminal and a third terminal, wherein the first inductor comprises: a first pattern connected to the second terminal and extending in a first direction from the second terminal in the first metal layer; a second pattern connected to the first pattern and extending in a second direction perpendicular to the first direction in the first metal layer; a third pattern connected to the second pattern and extending in the first direction in the first metal layer; and a fourth pattern connected to the third pattern and the first terminal and extending in the second direction in the first metal layer. Claim 7 An integrated circuit according to claim 6, wherein the first inductor and the second inductor are mutually symmetrical with respect to a line passing through the second terminal in the first direction. Claim 8 An integrated circuit comprising: a first T-coil including a first inductor connected to a first terminal and a second terminal and a second inductor connected to the second terminal and a third terminal; a first pad electrically connected to the first terminal; a first ESD (electrostatic discharge) element electrically connected to the second terminal; and a first active circuit electrically connected to the third terminal, wherein the first inductor and the second inductor are formed only on a first metal layer. Claim 9 An integrated circuit according to claim 8, further comprising: a second T-coil including a third inductor connected to a fourth terminal and a fifth terminal and a fourth inductor connected to the fifth terminal and a sixth terminal; a second pad electrically connected to the fourth terminal; a second ESD element electrically connected to the fifth terminal; and a second active circuit electrically connected to the sixth terminal, wherein the third inductor and the fourth inductor are formed only on the first metal layer. Claim 10 An integrated circuit according to claim 9, further comprising: a third pad between the first pad and the second pad; and a shield pattern electrically connected to the third pad, formed on the first metal layer, and extending between the first T-coil and the second T-coil.

Images