Display apparatus

Abstract

The present invention discloses a display device. The present invention comprises a substrate including a display area and a peripheral area, a partition wall disposed in the peripheral area, and a wiring disposed on the substrate and extending from the display area to the peripheral area, inserted into the interior of the partition wall or penetrating the interior of the partition wall, wherein at least one through hole is formed in the wiring.

Description

Technology Field

[0001] Embodiments of the present invention relate to a device, and more specifically, to a display device. Background Technology

[0002] Mobile-based electronic devices are being widely used. In addition to small electronic devices such as mobile phones, tablet PCs have recently become widely used as mobile electronic devices.

[0003] Such portable electronic devices include a display device to support various functions and to provide visual information, such as images or videos, to the user. Recently, as other components for driving the display device have become miniaturized, the proportion of the display device within the electronic device is gradually increasing, and structures capable of bending from a flat state to a predetermined angle are also being developed. The problem to be solved

[0004] Generally, a display device may include various wirings. In this case, the wiring may not be arranged flat but may have a curved shape in the vertical direction. In such cases, a disconnection may occur in the wiring, and a disconnection in the wiring may cause a malfunction or non-operation of the display device. Embodiments of the present invention provide a display device that prevents a disconnection of the wiring. means of solving the problem

[0005] One embodiment of the present invention discloses a display device comprising a substrate including a display area and a peripheral area, a partition wall disposed in the peripheral area, and wiring disposed on the substrate and extending from the display area to the peripheral area, inserted into the interior of the partition wall or penetrating the interior of the partition wall, wherein the wiring has at least one through hole formed therein.

[0006] In the present embodiment, the through holes are provided in plurality, and the through holes may be arranged to be spaced apart from each other along one direction.

[0007] In this embodiment, the through hole on the plane may be placed in the wiring portion disposed inside the bulkhead.

[0008] In this embodiment, the through holes are provided in plurality, and the plurality of through holes may be arranged in a serpentine shape.

[0009] In the present embodiment, the partition wall may include a first layer disposed below the wiring and a second layer disposed above the wiring.

[0010] In the present embodiment, the partition wall may further include a third layer disposed on the second layer.

[0011] In this embodiment, the second layer or the third layer may further include a black material.

[0012] In the present embodiment, the partition wall may further include a fourth layer disposed on the third layer.

[0013] In this embodiment, the first layer and the second layer may include organic material.

[0014] In this embodiment, the partition wall may be arranged to surround the outer edge of the display area.

[0015] Another aspect of the present invention discloses a display device comprising a substrate including a display area and a peripheral area, a partition wall disposed in the peripheral area, wiring disposed on the substrate and extending from the display area to the peripheral area and inserted into the interior of the partition wall or penetrating the interior of the partition wall, and touch wiring disposed on the substrate and extending from the display area to the peripheral area and disposed on the upper portion of the partition wall, wherein the wiring has at least one through hole formed therein.

[0016] In the present embodiment, the through holes are provided in plurality, and the through holes may be arranged to be spaced apart from each other along the length direction of the wiring.

[0017] In this embodiment, the through hole on the plane can be placed in the wiring disposed inside the bulkhead.

[0018] In this embodiment, the through holes are provided in plurality, and the plurality of through holes may be arranged in a serpentine shape.

[0019] In the present embodiment, the partition wall may include a first layer disposed below the wiring and a second layer disposed above the wiring.

[0020] In this embodiment, the first layer and the second layer may include organic material.

[0021] In the present embodiment, the partition wall may further include a third layer disposed on the second layer.

[0022] In this embodiment, the second layer or the third layer may further include a black material.

[0023] In this embodiment, the partition wall may be arranged to surround the outer edge of the display area.

[0024] In this embodiment, a terminal portion may be further included that is disposed in the surrounding area and connected to the wiring and the touch wiring.

[0025] In this embodiment, the partition wall may be disposed in an area located between the terminal portion and the display area.

[0026] Another embodiment of the present invention discloses a display device comprising a substrate including a display area and a peripheral area, a partition wall disposed in the peripheral area, a wiring disposed on the substrate and extending from the display area to the peripheral area and inserted into the interior of the partition wall or penetrating the interior of the partition wall, and a terminal portion disposed in the peripheral area and spaced apart from the display area and connected to the wiring, wherein the partition wall is disposed between the terminal portion and the display area, and the wiring has at least one through hole formed therein.

[0027] In this embodiment, the through hole on the plane can be placed in the wiring disposed inside the bulkhead.

[0028] In this embodiment, the through holes are provided in plurality, and the plurality of through holes may be arranged in a serpentine shape.

[0029] In this embodiment, the partition wall may be arranged to surround the outer edge of the display area.

[0030] Other aspects, features, and advantages other than those described above will become clear from the following drawings, claims, and detailed description of the invention. Effects of the invention

[0031] The display device according to the embodiments of the present invention can prevent or reduce disconnection of the touch wiring. The display device according to the embodiments of the present invention can prevent deformation of the shape of the partition wall when the partition wall is formed. The display device according to the embodiments of the present invention is capable of accurately recognizing the user's touch signal input. Brief explanation of the drawing

[0032] FIG. 1 is a plan view showing a display device according to one embodiment of the present invention. FIG. 2 is a plan view showing a display device according to one embodiment of the present invention. FIG. 3 is a cross-sectional view showing a display device according to one embodiment of the present invention. FIGS. 4a to 4f are plan views showing the relationship between the first common voltage supply wiring and the second partition wall shown in FIG. 3. FIGS. 5a to 5c are cross-sectional views showing a second partition and a first common voltage supply wiring according to an embodiment of the present invention. FIG. 6a is a plan view showing the relationship between the first common voltage supply wiring and the second partition of a display device according to another embodiment of the present invention. FIG. 6b is a cross-sectional view showing the relationship between the first common voltage supply wiring and the second partition wall shown in FIG. 6a. FIG. 7 is a cross-sectional view showing a display device according to another embodiment of the present invention. FIG. 8 is a cross-sectional view showing a display device according to another embodiment of the present invention. FIG. 9 is a cross-sectional view showing a display device according to another embodiment of the present invention. FIG. 10 is a cross-sectional view showing a display device according to another embodiment of the present invention. FIG. 11 is a cross-sectional view showing a display device according to another embodiment of the present invention. FIG. 12 is a cross-sectional view showing a display device according to another embodiment of the present invention. FIG. 13 is a cross-sectional view showing a display device according to another embodiment of the present invention. FIG. 14 is a cross-sectional view showing a display device according to another embodiment of the present invention. FIG. 15 is a plan view showing a display device according to another embodiment of the present invention. Figure 16 is a plan view showing an enlarged view of section C of Figure 15. Fig. 17a is a plan view showing an enlarged view of section D of Fig. 16. Fig. 17b is a plan view showing an enlarged view of section E of Fig. 16. Fig. 17c is a plan view showing an enlarged view of section F of Fig. 16. FIG. 17d is a cross-sectional view taken along G-G' of FIG. 17c. Figure 18 is a plan view showing an enlarged view of section H of Figure 15. Specific details for implementing the invention

[0033] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0034] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0035] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0036] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0037] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0038] In the following embodiments, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of another part, but also cases where another film, region, or component is interposed in between.

[0039] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is illustrated.

[0040] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to three axes in an orthogonal coordinate system and can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0041] Where an embodiment can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described consecutively may be performed substantially simultaneously or proceed in the reverse order of the description.

[0042] FIG. 1 is a plan view showing a display device according to one embodiment of the present invention.

[0043] Referring to FIG. 1, the display device (10) may include a substrate (100), a display layer (not shown) disposed on a display area (DA), a thin film encapsulation layer (not shown) disposed on the display layer, and an input sensing member (not shown) disposed on the thin film encapsulation layer. In addition, the display device (10) may include a circuit that supplies power to the display layer or applies a signal in addition to the above configuration.

[0044] The substrate (100) may include an organic or inorganic material. In one embodiment, the substrate (100) may be a glass substrate with a main component of a material containing silicon (Si) elements, such as SiO2. In another embodiment, the substrate (100) may include a transparent plastic material. For convenience of explanation, the following description will focus on the case where the substrate (100) includes a transparent plastic material. The substrate (100) may include a display area (DA) and a peripheral area (PA) outside the display area (DA).

[0045] The display area (DA) is an area where pixels (P) are placed. The display area (DA) can provide an image using light emitted from each pixel (P). Pixels (P) can be connected to signal lines such as a scan line (SL) extended in the x-direction and a data line (DL) extended in the y-direction. Although not shown in FIG. 1, pixels (P) can be connected to power lines that transmit DC signals, such as driving power lines and common power lines. At this time, although not shown in the drawing, multiple pixels (P) may be provided. In this case, some of the multiple pixels (P) may emit a first color, some of the multiple pixels (P) may emit a second color, and the remainder of the multiple pixels (P) may emit a third color.

[0046] Such a pixel (P) may include a pixel circuit electrically connected to the aforementioned signal line and power line, and a display element, such as an organic light-emitting diode (OLED), in the pixel circuit. The pixel (P) may emit light, for example, red, green, blue, or white, through the organic light-emitting diode. In this case, the first color may be one of red, green, or blue, the second color may be another of red, green, or blue, and the third color may be yet another of red, green, or blue. As another embodiment, it is also possible for the first color, the second color, and the third color to all be white.

[0047] The peripheral area (PA) may include a first scan driver (11), a second scan driver (12), a terminal section (20), a driving voltage supply wire (30), a common voltage supply wire (40), and a wiring layer (50).

[0048] The first scan driver (11) and the second scan driver (12) may be placed in the peripheral area (PA). The first scan driver (11) and the second scan driver (12) may be spaced apart from each other with the display area (DA) in between. The first scan driver (11) and / or the second scan driver (12) may generate and transmit a scan signal to each pixel (P) through a scan line (SL). FIG. 1 illustrates a case where two scan drivers are placed, but the present invention is not limited thereto. In another embodiment, a single scan driver may be placed on one side of the display area (DA).

[0049] The terminal portion (20) may be disposed at one end of the peripheral area (PA) and includes terminals (21, 22, 23, 24). The terminal portion (20) may be exposed without being covered by an insulating layer and may be connected to a driver IC (13). The driver IC (13) may include a data driver.

[0050] The driving voltage supply wiring (30) can provide driving voltage to the pixels (P). The driving voltage supply wiring (30) can be placed in a peripheral area (PA) adjacent to one side of the display area (DA).

[0051] The common voltage supply wiring (40) can provide a common voltage to the pixels (P). The common voltage is a voltage applied to the cathode electrode of an organic light-emitting diode, and the common voltage supply wiring (40) can be placed in a surrounding area (PA) to partially surround a display area (DA). At this time, a partition (120) can be placed between the common voltage supply wiring (40) and the display area (DA). In another embodiment, the partition (120) may be placed so as to overlap with the common voltage supply wiring (40) on a plane. In such a case, the common voltage supply wiring (40) may include a first common voltage supply wiring (116) and a second common voltage supply wiring (210) to be described later.

[0052] The common voltage supply wiring (40) described above may be arranged to overlap at least a part of the partition wall (120) in a planar manner. At this time, it is also possible to arrange the entire common voltage supply wiring (40) to overlap at least a part of the partition wall (120) or for a part of the common voltage supply wiring (40) to overlap at least a part of the partition wall (120).

[0053] The first wiring (51), the second wiring (52), the third wiring (53), and the fourth wiring (54) are positioned between one end of the display area (DA) and the terminal section (20) and may extend along the Y direction. The first wiring (51) electrically connects the signal line of the display area (DA) and the terminal section (20), and the second wiring (52) electrically connects the driving voltage supply wiring (30) and the terminal section (20). The third wiring (53) electrically connects the first scan driver (11) and the second scan driver (12), respectively, to the terminal section (20), and the fourth wiring (54) electrically connects the common voltage supply wiring (40) and the terminal section (20).

[0054] In FIG. 1, the terminals (21, 22, 23, 24) of the terminal section (20) are described with different reference numbers as the first wiring (51), the second wiring (52), the third wiring (53), and the fourth wiring (54), but each of the terminals (21, 22, 23, 24) can be understood as a part of the first wiring (51), the second wiring (52), the third wiring (53), and the fourth wiring (54). That is, the end portion of the first wiring (51) corresponds to terminal (21), the end portion of the second wiring (52) corresponds to terminal (22), the end portion of the third wiring (53) corresponds to terminal (23), and the end portion of the fourth wiring (54) corresponds to terminal (24).

[0055] FIG. 2 is a plan view showing a display device according to one embodiment of the present invention.

[0056] Referring to FIG. 2, a plurality of organic light-emitting elements to be described later may be disposed on a substrate (100). The organic light-emitting elements may be shielded by a thin film encapsulation layer (500). The thin film encapsulation layer (500) may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. At least one organic encapsulation layer and at least one inorganic encapsulation layer may be stacked alternately. An input sensing member may be disposed on the thin film encapsulation layer (500). The display device (10) may further include an optical functional member disposed on the input sensing member or disposed between the input sensing member and the thin film encapsulation layer (500).

[0057] The input sensing member includes various patterns of touch electrodes (TD) for touchscreen functions. The touch electrodes (TD) include first touch electrodes (TD1) connected to each other along a first direction (x direction) and second touch electrodes (TD2) connected to each other along a first direction (y direction) intersecting the first direction.

[0058] Such touch electrodes (TD) may be provided with a transparent electrode material so that light from the light-emitting regions of pixels disposed below the input sensing member can be transmitted. Alternatively, the touch electrodes (TD) may be provided in a mesh shape so that light from the light-emitting regions of pixels can be transmitted. In this case, the touch electrodes (TD) are not limited to a transparent electrode material. For example, the touch electrodes (TD) may be a single film or a multilayer film made of a conductive material including aluminum (Al), copper (Cu), and / or titanium (Ti), etc.

[0059] The touch electrode (TD) is connected to a touch wiring (TL) for transmitting a signal detected by the touch electrode (TD), and the touch wiring (TL) can extend from the top of the thin film encapsulation layer (500) along one side of the thin film encapsulation layer (500) to the surrounding area (PA).

[0060] The touch wiring (TL) is connected to the touch electrode (TD) of the input sensing member of the display area (DA) and can be connected to the terminal of the terminal section (not shown) by extending from the top of the thin film encapsulation layer (500). At this time, the touch wiring (TL) may be in a straight line shape. In addition, the touch wiring (TL) may have various shapes other than a straight line shape, such as a curved shape or a zigzag shape. The touch wiring (TL) is connected to the touch terminal (25) of the terminal section (20) and can exchange electrical signals with the input sensing member.

[0061] These touch wires (TL) can pass through the partition wall (120) and be connected to a terminal (not shown). At this time, the touch wires (TL) may be disconnected due to the partition wall (120). To prevent this, a hole may be formed in the common voltage supply wire (40) that penetrates the partition wall (120). A detailed explanation of this will be provided below.

[0062] A cover member (not shown) may be disposed on an input sensing member. In this case, the cover member may include a transparent synthetic resin, thin glass, etc. Additionally, an optical functional member may be disposed between the cover member and the input sensing member. The optical functional member may reduce the reflectivity of light (external light) incident from the outside toward the display device (10) and / or improve the color purity of light emitted from the display device (10).

[0063] In one embodiment, the optical functional member may include a phase retarder and a polarizer. The phase retarder may be of the film type or liquid crystal coating type and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may also be of the film type or liquid crystal coating type. The film type may include a stretched synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a predetermined arrangement.

[0064] In another embodiment, the optical functional member may include a black matrix and color filters. The color filters may be arranged considering the color of light emitted from each pixel of the display device (10). Each of the color filters may include a red, green, or blue pigment or dye. Alternatively, each of the color filters may further include quantum dots in addition to the aforementioned pigment or dye. Alternatively, some of the color filters may not include the aforementioned pigment or dye and may include scattering particles such as titanium oxide.

[0065] In another embodiment, the optical functional member may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a first reflective layer disposed on different layers. The first reflected light and the first reflected light reflected from the first reflective layer and the first reflective layer, respectively, may undergo destructive interference, and accordingly, the external light reflectance may be reduced.

[0066] FIG. 3 is a cross-sectional view showing a display device according to one embodiment of the present invention.

[0067] Referring to FIG. 3, the display device (10) may include a substrate (100), an inorganic insulating layer (ILD), an organic insulating layer (109, 111, 112), a thin-film transistor (not shown), an organic light-emitting diode (300), a thin-film encapsulation layer (500), a touchscreen layer (700), and a partition (120).

[0068] A substrate (100) includes a display area (DA) and a peripheral area (PA) outside the display area (DA). A plurality of pixels may be arranged in the display area (DA) of the substrate (100) to display an image. Various display elements, such as an organic light-emitting device (300, OLED), thin-film transistors, capacitors, etc., may be arranged in the display area (DA), and pixels may be formed by electrical coupling of the organic light-emitting device (300), thin-film transistors, capacitors, etc., to display an image. A driving current is generated through the display elements according to a gate signal, data signal, driving voltage (ELVDD), and common voltage (ELVSS) supplied to the pixels, and the display elements may emit light with a brightness corresponding to the driving current.

[0069] A peripheral area (PA) is positioned outside the display area (DA). Wiring that supplies various signals and / or power applied to the display area (DA) may be positioned in the peripheral area (PA). In this case, the wiring may include a drive circuit. For example, the drive circuit may include at least one of a scan drive circuit (not shown), a terminal section (not shown), a drive power supply wiring (not shown), and a common voltage supply wiring (40), and may further include a thin-film transistor for controlling electrical signals applied within the display area (DA). Additionally, a partition (120) or a trench, etc., may be positioned in the peripheral area (PA) to block the flow of an organic film used when manufacturing the display device (10). In the above case, at least one of the scan driving circuit, the terminal part, the driving power supply wiring and common voltage supply wiring (40), and the third thin-film transistor (T3) may be placed in one of the peripheral area (PA) placed on the long side or the peripheral area (PA) placed on the short side of the display device (10).

[0070] The display device (10) includes a substrate (100) comprising a display area (DA) and a peripheral area (PA), and a thin film encapsulation layer (500) that seals the display area (DA).

[0071] The substrate (100) may include various materials. For example, the substrate (100) may be made of a transparent glass material with SiO2 as the main component. However, the substrate (100) is not necessarily limited to this and may be formed of a transparent plastic material. The plastic material may be an organic material selected from the group consisting of polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene napthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide, polycarbonate (PC), cellulose triacetate (TAC), and cellulose acetate propionate (CAP). Additionally, the substrate (100) may have a multilayer structure including a layer containing the aforementioned plastic material and an inorganic layer (not shown).

[0072] A buffer layer (101) is positioned on a substrate (100) to reduce or block the penetration of foreign matter, moisture, or outside air from the bottom of the substrate (100) and to provide a flat surface on the substrate (100). The buffer layer (101) may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite, and may be composed of a single layer or a multilayer structure of inorganic and organic materials.

[0073] The first thin-film transistor (T1) includes a first semiconductor layer (A1), a first gate electrode (G1), a first source electrode (S1), and a first drain electrode (D1), and the second thin-film transistor (T2) includes a second semiconductor layer (A2), a second gate electrode (G2), a second source electrode (S2), and a second drain electrode (D2).

[0074] The following describes a case where the first and second thin-film transistors (T1, T2) are of the top gate type. However, this embodiment is not limited thereto, and various types of thin-film transistors, such as bottom gate type, may be employed.

[0075] Additionally, the following describes a case where there are two first and second thin-film transistors (T1, T2), but is not limited thereto. In embodiments of the present invention, the display device (10) may employ two or more first and second thin-film transistors (T1, T2) for a single pixel. In some embodiments, various variations are possible, such as employing six to seven first and second thin-film transistors (T1, T2) for a single pixel.

[0076] The first and second semiconductor layers (A1, A2) may include amorphous silicon or polycrystalline silicon. In another embodiment, the first and second semiconductor layers (A1, A2) may include an oxide of at least one material selected from the group comprising indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The first and second semiconductor layers (A1, A2) may include a channel region and a source region and a drain region having a carrier concentration higher than that of the channel region.

[0077] A first gate electrode (G1) is disposed on the first semiconductor layer (A1) with the first gate insulating layer (103) in between. The first gate electrode (G1) may be composed of a single layer or multiple layers, including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. As an example, the first gate electrode (G1) may be a single layer of Mo.

[0078] The inorganic insulating layer (ILD) may include at least one layer among a barrier layer (not shown), a buffer layer (101), a first gate insulating layer (103), a second gate insulating layer (105), and an interlayer insulating layer (107).

[0079] The first gate insulating layer (103) is intended to insulate the first semiconductor layer (A1) and the first gate electrode (G1), and is made of silicon oxide (SiO2) or silicon nitride (SiN x It may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0080] On the second semiconductor layer (A2), a second gate electrode (G2) is disposed with the first gate insulating layer (103) and the second gate insulating layer (105) in between. The second gate electrode (G2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. As an example, the second gate electrode (G2) may be a single layer of Mo or a multilayer with a Mo / Al / Mo structure.

[0081] The second gate insulating layer (105) may include an inorganic material including an oxide or a nitride. For example, the second gate insulating layer (105) may include the same material as the first gate insulating layer (103).

[0082] The first and second source electrodes (S1, S2) and the first and second drain electrodes (D1, D2) are disposed on the interlayer insulating layer (107). The first and second source electrodes (S1, S2) and the first and second drain electrodes (D1, D2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. As an example, the first and second source electrodes (S1, S2) and the first and second drain electrodes (D1, D2) may be formed as a multilayer structure of Ti / Al / Ti.

[0083] The interlayer insulation layer (107) may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0084] As described above, the first gate electrode (G1) of the first thin-film transistor (T1) and the second gate electrode (G2) of the second thin-film transistor (T2) can be placed on different layers. Accordingly, the driving ranges of the first thin-film transistor (T1) and the second thin-film transistor (T2) can be adjusted differently.

[0085] The first electrode (CE1) of the storage capacitor (Cst) can be formed of the same material on the same layer as the first gate electrode (G1). The second electrode (CE2) of the storage capacitor (Cst) overlaps with the first electrode (CE1) with the second gate insulating layer (105) in between. The second electrode (CE2) can be formed of the same material on the same layer as the second gate electrode (G2).

[0086] In FIG. 3, the storage capacitor (Cst) is shown not overlapping with the first thin-film transistor (T1) and the second thin-film transistor (T2). However, it is not limited thereto. For example, the storage capacitor (Cst) may be arranged to overlap with the first thin-film transistor (T1). In some embodiments, the first electrode (CE1) of the storage capacitor (Cst) may be formed integrally with the first gate electrode (G1). That is, the first gate electrode (G1) of the first thin-film transistor (T1) can function as the first electrode (CE1) of the storage capacitor (Cst).

[0087] A planarization layer (109, 111) is positioned on the first and second source electrodes (S1, S2) and the first and second drain electrodes (D1, D2), and an organic light-emitting diode (OLED) may be positioned on the planarization layer (109, 111). The planarization layer (109, 111) may be formed as a single layer or a multilayer film made of organic material. The organic material may include general-purpose polymers such as polymethylmethacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof. Additionally, the planarization layer (109, 111) may be formed as a composite laminate of an inorganic insulating film and an organic insulating film. For convenience of explanation, the following description will focus on the case where the flattening layer (109, 111) includes the first flattening layer (109) and the second flattening layer (111).

[0088] An organic light-emitting element (300) may be disposed on a second planarization layer (111) within a display area (DA) of a substrate (100). The organic light-emitting element (300) may include a pixel electrode (310), a counter electrode (330), and an intermediate layer (320) interposed between them.

[0089] The pixel electrode (310) may be electrically connected to the first thin-film transistor (T1) or the second thin-film transistor (T2). However, for the convenience of explanation, the following description will focus on the case where the pixel electrode (310) is electrically connected to the second thin-film transistor (T2).

[0090] The pixel electrode (310) is electrically connected to the second thin-film transistor (T2) by contacting either the second source electrode (S2) or the second drain electrode (D2) of the second thin-film transistor (T2) through an opening formed in the planarization layer (109, 111), etc. For example, the pixel electrode (310) can be electrically connected to the second drain electrode (D2) of the second thin-film transistor (T2). At this time, if the planarization layer (109, 111) is formed in multiple layers as described above, the pixel electrode (310) can be connected to the second drain electrode (D2) of the second thin-film transistor (T2) through a connecting electrode (130). At this time, the connecting electrode (130) can be placed on the first planarization layer (109). These connecting electrodes (130) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. In one embodiment, the contact metal layer (CM) may be formed as a multilayer (Ti / Al / Ti) in which a titanium layer, an aluminum layer, and a titanium layer are sequentially stacked. In one embodiment, if the planarization layer (109, 111) is a single layer, the contact metal layer (CM) may be omitted.

[0091] The pixel electrode (310) may be a reflective electrode. For example, the pixel electrode (310) may have a reflective film formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, and a transparent or translucent electrode layer formed on the reflective film. The transparent or translucent electrode layer may have at least one selected from the group comprising indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO).

[0092] A pixel defining film (112) may be disposed on the upper portion of the second planarization layer (111). This pixel defining film (112) serves to define pixels by having openings corresponding to each subpixel, that is, openings that expose at least the central portion of the pixel electrode (310). Additionally, the pixel defining film (112) can serve to prevent arcs from occurring at the edge of the pixel electrode (310) by increasing the distance between the edge of the pixel electrode (310) and the opposing electrode (330) above the pixel electrode (310). Such a pixel defining film (112) may be formed from an organic material such as polyimide or HMDSO (hexamethyldisiloxane). As another embodiment, the pixel defining film (112) may also include a black dye (e.g., ink, carbon black, etc.) in addition to an organic material such as polyimide or HMDSO. In such cases, the pixel defining film (112) may not be transparent, and if the pixel defining film (112) contains a black dye, the optical functional member may not include a phase delayer or a polarizer. However, for convenience of explanation, the following description will focus on cases where the pixel defining film (112) is formed from an organic material such as polyimide or HMDSO (hexamethyldisiloxane).

[0093] The intermediate layer (320) of the organic light-emitting diode may include low-molecular-weight or high-molecular-weight materials. When including low-molecular-weight materials, the structure may have a stacked structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) are stacked in a single or composite structure, and may include various organic materials including copper phthalocyanine (CuPc), N,N-di(naphthalene-1-yl)-N,N'-diphenyl-benzidine (NPB), and tris-8-hydroxyquinoline aluminum (Alq3). These layers may be formed by a vacuum deposition method.

[0094] When the intermediate layer (320) includes a polymer material, it may generally have a structure including a hole transport layer (HTL) and an emitting layer (EML). In this case, the hole transport layer may include PEDOT, and the emitting layer may include polymer materials such as PPV (Poly-Phenylenevinylene) and Polyfluorene. This intermediate layer (320) can be formed by screen printing, inkjet printing, laser induced thermal imaging (LITI), or vacuum deposition using a mask.

[0095] Of course, the intermediate layer (320) is not necessarily limited to this and may have various structures. Also, the intermediate layer (320) may include a layer that is integral across a plurality of pixel electrodes (310), or may include a layer patterned to correspond to each of the plurality of pixel electrodes (310).

[0096] The counter electrode (330) is positioned above the display area (DA), and in one embodiment, the counter electrode (330) may be positioned to cover the display area (DA). That is, the counter electrode (330) may be formed integrally with a plurality of organic light-emitting elements and positioned to correspond to a plurality of pixel electrodes (310). At this time, it is also possible for the counter electrode (330) to be positioned to cover the upper part of the display area (DA) and the upper part of a portion of the surrounding area (PA). For convenience of explanation, the following description will focus on the case where the counter electrode (330) is positioned to cover the upper part of the display area (DA) and the upper part of a portion of the surrounding area (PA).

[0097] The counter electrode (330) may be a transparent electrode. For example, the counter electrode (330) may be a transparent or translucent electrode and may be formed from a metal thin film with a low work function comprising Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and compounds thereof. Additionally, a transparent conductive oxide (TCO) film, such as ITO, IZO, ZnO, or In2O3, may be further disposed on the metal thin film.

[0098] As the pixel electrode (310) is provided as a reflective electrode and the counter electrode (330) is provided as a transparent electrode, the light emitted from the intermediate layer (320) may be of the full-surface emitting type, emitted toward the counter electrode (330). However, the present embodiment is not limited thereto, and the light emitted from the intermediate layer (320) may be of the back-surface emitting type, emitted toward the substrate (100). In this case, the pixel electrode (310) may be composed of a transparent or semi-transparent electrode, and the counter electrode (330) may be composed of a reflective electrode. Additionally, the display panel of the present embodiment may be of the double-sided emitting type, emitting light in both the front and back directions.

[0099] A capping layer (400) may be disposed on the upper side of the counter electrode (330). At this time, the capping layer (400) may be in direct contact with the counter electrode (330). The capping layer (400) may have a lower refractive index than the counter electrode (330) and a higher refractive index than the first inorganic encapsulation layer (510). The capping layer (400) may serve to improve light efficiency by reducing the proportion of light generated in the intermediate layer (320) including the organic light-emitting layer that is totally reflected and not emitted to the outside.

[0100] The capping layer (400) described above may include inorganic materials. For example, the inorganic materials may include zinc oxide, titanium oxide, zirconium oxide, silicon nitride, niobium oxide, tantalum oxide, tin oxide, nickel oxide, indium nitride, and gallium nitride.

[0101] The capping layer (400) may have a refractive index greater than that of the first inorganic encapsulation layer (510). For example, the refractive index of the capping layer (400) may be greater than the refractive index of the first inorganic encapsulation layer (510) by 0.24 or more. In this case, if the difference between the refractive index of the capping layer (400) and the refractive index of the first inorganic encapsulation layer (510) is less than 0.24, total internal reflection may occur significantly at the boundary between the capping layer (400) and the first inorganic encapsulation layer (510), or light corresponding to the resonant frequency of the light-emitting layer may not pass through, thereby lowering the brightness. In this case, the refractive index of the capping layer (400) may be 1.8 or more. If the refractive index of the capping layer (400) is less than 1.8, as described above, light may be reflected between the first inorganic encapsulation layer (510) and the capping layer (400), thereby lowering the brightness of the light-emitting layer.

[0102] In addition, in the above case, the thickness of the capping layer (400) may be 1000 Å or less. Specifically, the capping layer (400) may be measured based on the Z-axis direction of FIG. 3. At this time, if the thickness of the capping layer (400) exceeds 1000 Å, a large amount of time and energy may be required when forming the capping layer (400). Furthermore, if the thickness of the capping layer (400) exceeds 1000 Å, it may be difficult to achieve a clear image because the light emitted from the light-emitting layer cannot pass through or the wavelength is variable.

[0103] The thin film encapsulation layer (500) can cover a portion of the display area (DA) and the surrounding area (PA) to prevent the penetration of external moisture and oxygen. The thin film encapsulation layer (500) may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. In FIG. 3, an example is shown in which the thin film encapsulation layer (500) includes two inorganic encapsulation layers (510, 530) and one organic encapsulation layer (520), but the stacking order and the number of stacking layers are not limited to the embodiment shown in FIG. 3.

[0104] The first inorganic sealing layer (510) covers the counter electrode (330) and may include silicon oxide, silicon nitride and / or silicon oxynitride, etc. Of course, other layers such as a capping layer (400) may be interposed between the first inorganic sealing layer (510) and the counter electrode (330) as needed. Since this first inorganic sealing layer (510) is formed along the structure below it, its upper surface is not flat as shown in FIG. 3. The organic sealing layer (520) covers this first inorganic sealing layer (510), but unlike the first inorganic sealing layer (510), its upper surface can be made approximately flat. Specifically, the organic sealing layer (520) can be made approximately flat in the portion corresponding to the display area (DA). These organic encapsulation layers (520) may include one or more materials selected from the group consisting of polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane. The second inorganic encapsulation layer (530) covers the organic encapsulation layer (520) and may include silicon oxide, silicon nitride and / or silicon oxynitride, etc.

[0105] In this way, the thin film encapsulation layer (500) includes a first inorganic encapsulation layer (510), an organic encapsulation layer (520), and a second inorganic encapsulation layer (530). Through this multilayer structure, even if a crack occurs within the thin film encapsulation layer (500), such cracks can be prevented from connecting between the first inorganic encapsulation layer (510) and the organic encapsulation layer (520), or between the organic encapsulation layer (520) and the second inorganic encapsulation layer (530). This prevents or minimizes the formation of a path through which moisture or oxygen from the outside penetrates into the display area (DA) and the surrounding area (PA). By the second inorganic encapsulation layer (530) contacts the first inorganic encapsulation layer (510) at its edge located outside the display area (DA), the organic encapsulation layer (520) can be prevented from being exposed to the outside.

[0106] In the above case, the first inorganic sealing layer (510) can come into direct contact with the capping layer (400) on the partition wall (120). Specifically, the capping layer (400), the first inorganic sealing layer (510), and the second inorganic sealing layer (530) can be sequentially stacked on the partition wall (120).

[0107] The common voltage supply wiring (40) may include a first common voltage supply wiring (116) and a second common voltage supply wiring (210). The first common voltage supply wiring (116) may be formed in the same layer as the connecting electrode (130) and may be placed on the flat surface of the first flattening layer (109) and the partition wall (120) as shown in FIG. 3. In this case, the first common voltage supply wiring (116) may be formed simultaneously with the connecting electrode (130) using the same material. In this case, the first common voltage supply wiring (116) may be connected to the opposing electrode (330). In this case, the first common voltage supply wiring (116) may be directly connected to the opposing electrode (330), or it may be connected to the opposing electrode (330) through a separate common voltage connecting wiring (not shown), although this is not shown in the drawing. In particular, the above common voltage connection wiring may be formed on a flat surface on the second flattening layer (111), connected to the opposing electrode (330), and may be extended to the upper surface of the first common voltage supply wiring (116) and connected to the first common voltage supply wiring (116). However, for convenience of explanation, the following description will focus on the case where the first common voltage supply wiring (116) is directly connected to the opposing electrode (330).

[0108] The first common voltage supply wiring (116) can stably provide a common voltage (ELVSS) to the opposing electrode (330) together with the second common voltage supply wiring (210) by increasing the contact area with the opposing electrode (330). At this time, at least a portion of the first common voltage supply wiring (116) can shield part or all of the second common voltage supply wiring (210). In particular, the first common voltage supply wiring (116) can be arranged to shield the front of the second common voltage supply wiring (210) and extend to the upper part of a portion of the bulkhead (120). In another embodiment, the first common voltage supply wiring (116) can be arranged to completely shield the upper part of a portion of the bulkhead (120). For convenience of explanation, the first common voltage supply wiring (116) will be described in detail below, focusing on the case where it is arranged to completely shield the upper part of a portion of the bulkhead (120).

[0109] In addition to the above cases, a second common voltage supply wiring (210) and a partition (120) are disposed in the peripheral area (PA) of the substrate (100). The second common voltage supply wiring (210) may be wiring for supplying power to the display area (DA) and may be provided with the same material on the same layer as the first and second source electrodes (S1, S2) and the first and second drain electrodes (D1, D2). In some embodiments, the second common voltage supply wiring (210) may function as wiring that transmits a common voltage (ELVSS) by being connected to the counter electrode (330) of the organic light-emitting diode (300). In one embodiment, the second common voltage supply wiring (210) may be directly connected to the counter electrode (330) through an extended counter electrode (330). As another embodiment, as shown in FIG. 3, the second common voltage supply wiring (210) may also be connected to the opposing electrode (330) by the first common voltage supply wiring (116). In this case, the first common voltage supply wiring (116) may be formed simultaneously with the connecting electrode (130) using the same material. However, the present invention is not limited thereto, and the second common voltage supply wiring (210) may come into contact with the opposing electrode (330) in various ways. For convenience of explanation, the following description will focus on the case where the second common voltage supply wiring (210) is connected to the opposing electrode (330) through the first common voltage supply wiring (116).

[0110] The partition (120) may be positioned to cover at least a portion of the second common voltage supply wiring (210). In some embodiments, the partition (120) may be positioned to cover the edge region far from the marked area (DA) of the second common voltage supply wiring (210) and not cover the edge region adjacent to the marked area (DA). However, it is not limited thereto. Various variations are possible, such as the partition (120) being positioned to cover the entire second common voltage supply wiring (210).

[0111] The partition (120) can prevent the organic material from flowing toward the edge of the substrate (100) when forming the organic encapsulation layer (520) of the thin film encapsulation layer (500) for sealing the display area (DA) and the surrounding area (PA), thereby preventing the formation of an edge tail of the organic encapsulation layer (520).

[0112] At least one partition wall (120) as described above may be provided. For convenience of explanation, the following description will focus on the case where two partition walls (120) are provided and spaced apart from each other.

[0113] The partition wall (120) includes a first partition wall (120a) and a second partition wall (120b) that are spaced apart from each other. At this time, at least one of the first partition wall (120a) and the second partition wall (120b) may be penetrated by the second common voltage supply wiring (210). For convenience of explanation, the following description will focus on the case where the second common voltage supply wiring (210) is positioned to penetrate the second partition wall (120b).

[0114] The first partition (120a) and the second partition (120b) may be placed on the second common voltage supply wiring (210) in the surrounding area (PA). Additionally, at least one of the first partition (120a) and the second partition (120b) may be formed in a plurality of layers. In this case, at least one of the layers forming at least one of the first partition (120a) and the second partition (120b) may be an organic material. In FIG. 3, the first partition (120a) may have a stacked structure comprising a first layer (121a) formed of the same material as the second flattening layer (111) and a second layer (122a) formed of the same material as the pixel defining film (112). The second partition (120b) illustrates a stacked structure comprising a first layer (121b) formed of the same material as the first flattening layer (109), a second layer (123b) formed of the same material as the second flattening layer (111), and a third layer (124b) formed of the same material as the pixel defining film (112). However, it is not limited thereto. Various variations are possible, such as one of the first partition (120a) and the second partition (120b) being formed as a single layer, both having a two-layer structure, or both having a three-layer structure. Additionally, an additional partition may be included that is spaced apart from the first partition (120a) and the second partition (120b).

[0115] As the partition (120) includes multiple partitions, the overflow of organic matter can be prevented more effectively when forming the organic bag layer (520).

[0116] The first common voltage supply wiring (116), which is connected to the second common voltage supply wiring (210), may be arranged to extend to the upper part of the first layer (121b) of the second partition (120b). At this time, the first common voltage supply wiring (116) may be extended by passing between the first layer (121b) and the second layer (123b) of the second partition (120b). Additionally, the second common voltage supply wiring (210) may be arranged at the lower part of the first partition (120a) and connected to the first common voltage supply wiring (116). Accordingly, the contact area of ​​the first common voltage supply wiring (116) with the second common voltage supply wiring (210) is increased, thereby reducing the contact resistance between the second common voltage supply wiring (210) and the first common voltage supply wiring (116).

[0117] The first common voltage supply wiring (116) as described above may have a first through hole (116a). The first through hole (116a) may be placed in the first common voltage supply wiring (116) that overlaps with the partition wall (120) when viewed in a planar view. In this case, the range of the first common voltage supply wiring (116) that overlaps with the partition wall (120) may refer to the entire area where the partition wall (120) is formed. For example, based on FIG. 3, it may refer to the area from the end of the first partition wall (120a) to the end of the second partition wall (120b), and may be a concept that includes the space between the first partition wall (120a) and the second partition wall (120b). In another embodiment, the range of the first common voltage supply wiring (116) overlapping with the partition wall (120) may refer to the first common voltage supply wiring (116) overlapping with the partition wall (120) when viewed on a plane. For example, based on FIG. 3, it may refer to at least one of the lower part of the first partition wall (120a) and the lower part of the second partition wall (120b). In this case, the space between the first partition wall (120a) and the second partition wall (120b) based on FIG. 3 may be excluded. In yet another embodiment, the range of the first common voltage supply wiring (116) overlapping with the partition wall (120) may refer to the portion of the first common voltage supply wiring (116) overlapping with the partition wall (120) in which the first common voltage supply wiring (116) is inserted in the middle of the partition wall (120). For example, based on FIG. 3, the first common voltage supply wiring (116) is positioned at the bottom of the first partition (120a) and inserted into the second partition (120b), so the first through hole (116a) may be formed only in the portion of the first common voltage supply wiring (116) that overlaps with the portion of the second partition (120b). For convenience of explanation, the following description will focus on the case where the first through hole (116a) is formed in the portion of the first common voltage supply wiring (116) that is inserted into the second partition (120b), as shown in FIG. 3.

[0118] At least one first through hole (116a) may be provided. In particular, when multiple first through holes (116a) are provided, the first through holes (116a) may be arranged in various directions. For example, as in one embodiment, multiple first through holes (116a) may be arranged such that the first through holes (116a) are spaced apart from each other in the direction in which the partition wall (120) is formed (e.g., the DI1 axis direction or the DI2 axis direction of FIG. 2). For example, in the case of a first common voltage supply wiring (116) placed on the side of a display area (DA), the first through holes (116a) may be arranged such that they are spaced apart from each other in the DI2 axis direction of FIG. 2. In another embodiment, the first through-hole (116a) of the first common voltage supply wiring (116) portion, which is arranged to overlap with the partition wall (120) placed on the lower surface of the display area (DA) based on FIG. 2 and when viewed in a planar view, may be arranged so as to be spaced apart from each other in the DI1 axis direction of FIG. 2. In addition, in another embodiment, a plurality of first through-holes (116a) may be arranged in directions different from the DI1 axis and DI2 axis of FIG. 2. In yet another embodiment, a plurality of first through-holes (116a) may be arranged in a curved shape or in a zigzag shape. However, for convenience of explanation, the following description will focus on the case where the first through-holes (116a) are arranged so as to be spaced apart from each other in the direction in which the partition wall (120) is formed.

[0119] In this case, the first through hole (116a) may be placed in the first common voltage supply wiring (116) portion that overlaps with the partition wall (120) on a plane. At this time, the first through hole (116a) may be arranged in various forms and may have various shapes.

[0120] The first through hole (116a) as described above may be placed throughout the first common voltage supply wiring (116) or in a part of the first common voltage supply wiring (116). In particular, the first through hole (116a) may be placed in a part of the first common voltage supply wiring (116) that overlaps with the second partition (120b).

[0121] The touchscreen layer (700) may have a structure in which a first touch conductive layer (711), a first insulating layer (712), a second touch conductive layer (713), and a second insulating layer (714) are sequentially stacked. The touch electrode (710) may include the first touch conductive layer (711) and the second touch conductive layer (713). In this case, the touch electrode (710) may correspond to the touch electrode (TD) described in FIG. 2.

[0122] In some embodiments, the second touch conductive layer (713) acts as a sensor part that detects whether contact is made, and the first touch conductive layer (711) may act as a connecting part that connects the patterned second touch conductive layer (713) in one direction. For example, the second touch conductive layer (713) may correspond to the first touch electrode (TD1) or the second touch electrode (TD2) of FIG. 2.

[0123] In some embodiments, both the first touch conductive layer (711) and the second touch conductive layer (713) may function as sensor parts. For example, the first insulating layer (712) may include a via hole that exposes the upper surface of the first touch conductive layer (711), and the first touch conductive layer (711) and the second touch conductive layer (713) may be connected through the via hole. By using the first touch conductive layer (711) and the second touch conductive layer (713) in this manner, the resistance of the touch electrode (710) is reduced, and the response speed of the touch screen layer (700) may be improved. In this case, the first touch conductive layer (711) or the second touch conductive layer (713) may correspond to the first touch electrode (TD1) or the second touch electrode (TD2) shown in FIG. 2.

[0124] In some embodiments, the touch electrode (710) may be formed with a mesh structure to allow light emitted from the organic light-emitting element (300) to pass through. Accordingly, the first touch conductive layer (711) and the second touch conductive layer (713) of the touch electrode (710) may be arranged so as not to overlap with the light-emitting region of the organic light-emitting element (300) (for example, the region where the pixel electrode (310) is exposed outside the pixel defining film (112).

[0125] The first touch conductive layer (711) and the second touch conductive layer (713) may each be a single film or a multilayer film made of a conductive material with good conductivity. For example, the first touch conductive layer (711) and the second touch conductive layer (713) may each be a single film or a multilayer film made of a conductive material including a transparent conductive layer, aluminum (Al), copper (Cu) and / or titanium (Ti), etc. The transparent conductive layer may include a transparent conductive oxide such as ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), etc. In addition, the transparent conductive layer may include a conductive polymer such as PEDOT, metal nanowires, graphene, etc. In some embodiments, the first touch conductive layer (711) and the second touch conductive layer (713) may each have a Ti / Al / Ti stacked structure.

[0126] The first insulating layer (712) and the second insulating layer (714) may each be provided with an inorganic or organic material. The inorganic material may be at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, or silicon oxynitride. The organic material may be at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, and perylene resin.

[0127] Although not shown, a touch buffer layer may be further provided between the thin film encapsulation layer (500) and the touch screen layer (700). The touch buffer layer may prevent damage to the thin film encapsulation layer (500) and may serve to block interference signals that may occur during operation of the touch screen layer (700). The touch buffer layer may contain inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, titanium oxide, or titanium nitride, or organic materials such as polyimide, polyester, or acrylic, and may be formed from a plurality of laminates of the materials exemplified.

[0128] Since the touch buffer layer and / or touchscreen layer (700) is formed directly on the thin film encapsulation layer (500) by deposition or the like, a separate adhesive layer on the thin film encapsulation layer (500) is not required. Therefore, the thickness of the display device can be reduced.

[0129] The cover layer (730) has flexible properties and can be formed from polymethylmethacrylate, polydimethylsiloxane, polyimide, acrylate, polyethylene terephthalate, polyethylene naphthalate, etc. The cover layer (730) is placed on the touchscreen layer (700) and can serve to protect the touchscreen layer (700). The cover layer (730) can be formed extending to the surrounding area (PA). However, it is not limited thereto. Various variations are possible, such as the cover layer (730) being placed only on the display area (DA).

[0130] The touch wiring (TL) can be connected to either the first touch conductive layer (711) or the second touch conductive layer (713) and connected to a terminal (not shown). At this time, the touch wiring (TL) can be placed and connected on the second inorganic encapsulation layer (530). In this case, the touch wiring (TL) can be placed on the first partition (120a) and the second partition (120b).

[0131] When the touch wiring (TL) described above is placed on the second partition (120b), it may be disconnected depending on the condition of the second partition (120b). In particular, when the first common voltage supply wiring (116) passes between at least one layer of the second partition (120b) and another layer, such as the second partition (120b), heat can be applied to each layer of the second partition (120b) to cure it. At this time, gas may be generated in a part of the second partition (120b) placed below the first common voltage supply wiring (116) (for example, the first layer (121b) of the partition (120b)), but this gas is blocked by the first common voltage supply wiring (116), so that a part of the second partition (120b) placed below the first common voltage supply wiring (116) may swell. In this case, the height of the entire second partition (120b) rises, and severe bending may occur near the second partition (120b) due to the second partition (120b).

[0132] In the above case, the touch wiring (TL) is placed on the second partition (120b), and the touch wiring (TL) may be disconnected due to the bending as described above. At this time, the first through hole (116a) of the first common voltage supply wiring (116) is placed in the first common voltage supply wiring (116) that overlaps the second partition (120b) in a planar manner, so that gas generated at the bottom of the first common voltage supply wiring (116) can be smoothly discharged when each layer of the second partition (120b) is formed. That is, when at least one of the second layer (123b) and the third layer (124b) of the second partition (120b) is formed based on FIG. 3, gas generated in the first layer (121b) of the second partition (120b) can be discharged to the outside through the first through hole (116a). Therefore, when the second partition (120b) is formed, the gas in the layer placed below the first common voltage supply line (116) is not discharged, thereby preventing the layer placed below the second common voltage supply line (210) from swelling.

[0133] In particular, when forming the touch wiring (TL) in the above case, the touch wiring (TL) can be formed in a designed shape considering the height, width, shape, etc. of the second partition (120b). In such a case, if a part of the layer of the partition (120) placed below the first common voltage supply wiring (116) swells up as described above, a problem may occur as the first common voltage supply wiring (116) becomes different from the designed shape. For example, if the height of the second partition (120b) becomes greater than the designed height, the amount of material required to form the first common voltage supply wiring (116) increases, or the material must be supplied to the second partition (120b) for a longer period of time to form the first common voltage supply wiring (116). However, as explained above, since it is almost impossible to change and perform these conditions every time during the first common voltage supply wiring (116), the height, width, shape, etc. of the second partition (120b) must be maintained to be almost identical or similar to the designed one. To this end, as explained above, by forming a first through hole (116a) in the first common voltage supply wiring (116), it is possible to effectively remove gas generated in the layer placed below the first common voltage supply wiring (116).

[0135] FIGS. 4a to 4f are plan views showing the relationship between the first common voltage supply wiring and the second partition wall shown in FIG. 3.

[0136] Referring to FIGS. 4a through 4f, the second partition (120b) may be placed on the inorganic insulating layer (ILD) shown in FIG. 3, although not shown in the drawings. The first common voltage supply wiring (116) and the second partition (120b) may overlap each other when viewed in a planar view. For example, the first common voltage supply wiring (116) may pass through the lower part of the second partition (120b) or pass through the second partition (120b) by being placed on the upper part of at least some of the layers of the second partition (120b). For example, the second partition (120b) may be formed in the DI1 direction or DI2 direction of FIG. 1 and may be placed to surround the display area (DA).

[0137] The touch wiring (TL) may form a certain angle with the direction in which the second partition (120b) extends or the direction in which at least a part of the first common voltage supply wiring (116) extends. For example, the second partition (120b) and the first common voltage supply wiring (116) may extend in either the DI1 direction or the DI2 direction. At this time, the touch wiring (TL) may extend in the other direction of the DI1 direction or the DI2 direction, which is perpendicular to the direction in which at least one of the second partition (120b) and the first common voltage supply wiring (116) extends. That is, based on FIGS. 4a to 4f, if at least one of the second partition (120b) and the first common voltage supply wire (116) is extended in the DI1 direction, the touch wire (TL) is extended in the DI2 direction, and if at least one of the second partition (120b) and the first common voltage supply wire (116) is extended in the DI2 direction, the touch wire (TL) can be extended in the DI1 direction.

[0138] In the above case, at least a portion of the partition wall (120) may overlap with the first common voltage supply wiring (116) when viewed in a planar view. For convenience of explanation, the partition wall (120) will be described in detail below, focusing on the case where it is placed inside the first common voltage supply wiring (116). For example, as shown in FIGS. 4a to 4f, the partition wall (120) may be placed inside the first common voltage supply wiring (116) when viewed in a planar view. As another embodiment, although not shown in the drawings, it is also possible for a portion of the partition wall (120) to overlap with the first common voltage supply wiring (116) when viewed in a planar view. In this case, the partition wall (120) may be a concept that includes both the first partition wall (120a) and the second partition wall (120b). That is, when the entire partition wall (120) is arranged to overlap with the first common voltage supply wiring (116) in a plane, both the first partition wall (120a) and the second partition wall (120b) may be arranged inside the first common voltage supply wiring (116) in a plane. On the other hand, when a part of the partition wall (120) overlaps with the first common voltage supply wiring (116) in a plane, only one of the first partition wall (120a) or the second partition wall (120b) may overlap with the first common voltage supply wiring (116), or a part of the first partition wall (120a) and the second partition wall (120b) may overlap with the first common voltage supply wiring (116). In such cases, a portion of the first partition (120a) and the second partition (120b) may overlap with the first common voltage supply wiring (116), or a portion of the first partition (120a) and a portion of the second partition (120b) may overlap. For convenience of explanation, the following description will focus on the case where both the first partition (120a) and the second partition (120b) are positioned inside the first common voltage supply wiring (116) when viewed in a planar view. Additionally, for convenience of explanation, the first through hole (116a) will be described in detail focusing on the case where it is positioned in the first common voltage supply wiring (116) that overlaps with the second partition (120b) when viewed in a planar view.

[0139] A first through hole (116a) may be provided in the first common voltage supply wiring (116) as described above. At this time, the first through hole (116a) may be provided in various forms and in various ways. For example, the first through hole (116a) may be in the shape of a square as shown in FIG. 4a. At this time, a plurality of first through holes (116a) may be provided, and the plurality of first through holes (116a) may be arranged spaced apart from each other. The plurality of first through holes (116a) may be arranged in a zigzag shape or a serpentine shape.

[0140] As shown in FIG. 4b, the first through hole (116a) may be square in shape. In this case, each first through hole (116a) may be arranged in a line and may be spaced apart from one another in one direction. As another embodiment, as shown in FIG. 4a, it is also possible for the first through holes (116a) to be arranged in a zigzag shape or a serpentine shape.

[0141] Referring to FIG. 4c, the first through hole (116a) may be a rectangular shape formed along the length direction of the touch wiring (TL) (e.g., the DI2 axis direction in FIG. 4c). In this case, the first through hole (116a) may be arranged in a line in one direction (e.g., the DI1 axis direction in FIG. 4c). As another embodiment, it is also possible for the first through hole (116a) to be arranged in a zigzag shape or a serpentine shape, as shown in FIG. 4a.

[0142] Referring to FIG. 4d, the first through hole (116a) may be rectangular in shape, and the long side of the first through hole (116a) may be positioned in a direction perpendicular to the length direction of the touch wiring (TL) (e.g., the DI1 axis direction in FIG. 4d). In this case, a plurality of first through holes (116a) may be arranged in a line in one direction. As another embodiment, it is also possible for the first through holes (116a) to be arranged in a zigzag shape or a serpentine shape, as shown in FIG. 4a.

[0143] Referring to FIG. 4e, the first through hole (116a) may be formed in a circular shape. In this case, the first through hole (116a) may be provided in multiple numbers, and the multiple first through holes (116a) may be arranged in a line in one direction. As another embodiment, as shown in FIG. 4a, it is also possible for the first through hole (116a) to be arranged in a zigzag shape or a serpentine shape.

[0144] Referring to FIG. 4f, the first through hole (116a) may be formed in an elliptical shape. In this case, the first through hole (116a) may be provided in multiple numbers, and the multiple first through holes (116a) may be arranged in a line in one direction. As another embodiment, as shown in FIG. 4a, it is also possible for the first through hole (116a) to be arranged in a zigzag shape or a serpentine shape.

[0145] The first through hole (116a) described above may be formed in various shapes other than the shape described above. For example, the first through hole (116a) may be in the shape of a polygon, such as a triangle, a square, or a pentagon. As another embodiment, the first through hole (116a) may include a star shape, an amorphous shape, etc.

[0146] The first through hole (116a) may be arranged in various forms in addition to the above arrangement. For example, when multiple first through holes (116a) are provided, the shape formed by connecting the centers of the multiple first through holes (116a) may be arranged in a polygonal shape, or in an amorphous shape such as a circle, ellipse, or star shape, in addition to a straight line.

[0147] FIGS. 5a to 5c are cross-sectional views showing a second partition and a first common voltage supply wiring according to an embodiment of the present invention.

[0148] Referring to FIG. 5a, touch wiring (TL) may be disposed on the second partition (120b). At this time, the second partition (120b), the first inorganic sealing layer (510), the second inorganic sealing layer (530), the first insulating layer (712), and the touch wiring (TL) may be stacked sequentially. As another embodiment, although not shown in the drawings, the first insulating layer (712) may not exist, and the touch wiring (TL) may be disposed on the second inorganic sealing layer (530) so as to be in direct contact with the second inorganic sealing layer (530). As yet another embodiment, although not shown in the drawings, the cover layer (730) and / or the second insulating layer (714) shown in FIG. 3 may be disposed on the touch wiring (TL).

[0149] The second partition (120b) and the first common voltage supply wiring (116) can be arranged in various forms. For example, the first layer (121b), second layer (123b), and third layer (124b) of the second partition (120b) can be stacked with a rectangular cross-section. In this case, the cross-sectional width of the first layer (121b), the cross-sectional width of the second layer (123b), and the cross-sectional width of the third layer (124b) may be the same. In such a case, the first common voltage supply wiring (116) may be placed on the upper part of the first layer (121b) and extend along the outer surface of the first layer (121b). In this case, a first through hole (116a) may be provided in the first common voltage supply wiring (116).

[0150] In the above case, after forming the first layer (121b), the first common voltage supply wiring (116) may be formed, and the second layer (123b) and the third layer (124b) may be formed sequentially. At this time, the first layer (121b) may include organic material, and at least one of the second layer (123b) and the third layer (124b) may include organic material. For convenience of explanation, the following description will focus on the case where both the second layer (123b) and the third layer (124b) include organic material.

[0151] As described above, when forming a second layer (123b) while the first layer (121b) and the first common voltage supply wire (116) are stacked, the second layer (123b) can be formed by placing the material forming the second layer (123b) on the first common voltage supply wire (116) and then curing it. At this time, due to the heat applied during the formation of the second layer (123b), the gas contained inside the first layer (121b) may be discharged to the outside. At this time, the movement of the gas may be blocked or hindered by the first common voltage supply wire (116) placed on the outer surface of the first layer (121b). In such a case, the first layer (121b) may swell, and the height of the first layer (121b) may increase compared to the existing height (or designed height) before the second layer (123b) is formed. In this case, the height of the first common voltage supply wiring (116) may also be larger than the existing height (or designed height), or the upper side of the cross-sectional shape of the first layer (121b) and the first common voltage supply wiring (116) may become convex. At this time, gas generated in the first layer (121b) can be passed through the first through hole (116a) formed in the first common voltage supply wiring (116). In this case, the first layer (121b) and the first common voltage supply wiring (116) may not become convex due to the first through hole (116a). In the same case as above, even when forming the third layer (124b), the gas from the first layer (121b) can be discharged in the same way through the first through hole (116a).

[0152] The first through hole (116a) described above may not necessarily be placed on the upper surface of the first layer (121b). For example, although not shown in the drawing, the first through hole (116a) may be placed on the side of the cross-section of the first layer (121b). In this case as well, gas generated in the first layer (121b) can be discharged to the outside through the first through hole (116a).

[0153] Referring to FIG. 5b, each layer of the bulkhead (120) can be arranged in a pyramid shape. For example, as shown in FIG. 5b, the first layer (121b), second layer (123b), and third layer (124b) of the second bulkhead (120b) can be formed so that their width narrows from the bottom to the top. In this case, the first common voltage supply wiring (116) can be formed along the outer surface of the first layer (121b) and can be placed between the first layer (121b) and the second layer (123b). The first common voltage supply wiring (116) includes a first through hole (116a), and the first through hole (116a) can be arranged in various forms as shown in FIG. 4a to 4f.

[0154] Referring to FIG. 5c, each layer of the bulkhead (120) may be arranged in a pyramid shape such that the layer placed at the top surrounds the layer placed at the bottom. For example, the first layer (121b) of the second bulkhead (120b) may be placed at the very bottom, and the first common voltage supply wiring (116) may surround the first layer (121b). Additionally, the second layer (123b) may completely surround the first layer (121b) and may be arranged to surround a portion of the outer surface of the first common voltage supply wiring (116). Additionally, the third layer (124b) may be arranged to surround the second layer (123b). In this case, the first layer (121b) and the second layer (123b) may not be exposed to the outside. In this case, the first common voltage supply wiring (116) includes a first through hole (116a), and the first through hole (116a) can be arranged in various forms as shown in FIGS. 4a to 4f. Additionally, the first through hole (116a) can be positioned on the upper side of the outer surface of the first layer (121b).

[0155] A portion of the second layer (123b) may be inserted into the first through hole (116a) as described above. In this case, the first layer (121b) and the second layer (123b) may be connected to each other.

[0156] When the first through hole (116a) as described above is arranged as shown in FIG. 3, the first through hole (116a) may be positioned so as to be offset to the left side of FIG. 5a to FIG. 5c, although FIG. 5a to FIG. 5c is not shown in FIG. 5a to FIG. 5c.

[0157] On the second partition wall (120b) as described above, a first inorganic sealing layer (510), a second inorganic sealing layer (520), a first insulating layer (712), and a touch wiring (TL) can be sequentially laminated.

[0158] FIG. 6a is a plan view showing the relationship between a first common voltage supply wiring and a second partition wall of a display device according to another embodiment of the present invention. FIG. 6b is a cross-sectional view showing the relationship between the first common voltage supply wiring and the second partition wall shown in FIG. 6a.

[0159] Referring to FIGS. 6a and 6b, the first common voltage supply wiring (116) and the second partition (120b) may overlap in a plane, and the first common voltage supply wiring (116) may be positioned between the first layer (121b) and the second layer (123b) of the second partition (120b). At this time, at least a portion of the first common voltage supply wiring (116) and the second partition (120b) may extend in the same direction.

[0160] In the above case, the first common voltage supply wiring (116) can be arranged to wrap around the first layer (121b) as shown in FIG. 6b when viewed in cross-section.

[0161] The first common voltage supply wiring (116) may include a plurality of first through holes (116a). At this time, the plurality of first through holes (116a) may be arranged in various forms and may have various shapes. For example, at least two of the plurality of first through holes (116a) may be arranged in a first direction and a second direction. That is, as shown in FIG. 6a, two may be arranged in the DI2 direction, and two or more first through holes (116a) may be arranged in a line in the DI1 direction. At this time, the two first through holes (116a) arranged in the DI2 direction may be arranged to overlap with the touch wiring (TL) on a plane.

[0162] Among the plurality of first through holes (116a), the number of first through holes (116a) arranged in the DI2 direction may be arranged differently in the DI1 direction. For example, one first through hole (116a) may be arranged next to a portion where two first through holes (116a) are arranged in the DI2 direction. The first through holes (116a) may be arranged in the first common voltage supply wiring (116) so that such combinations of first through holes (116a) are repeated along the DI1 direction. As another embodiment, it is also possible to arrange two first through holes (116a) in the DI2 direction and each first through hole (116a) in a line in the DI1 direction. As another embodiment, a plurality of first through holes (116a) are arranged in the DI2 direction, and it is also possible for these plurality of first through holes (116a) to form a group and be repeatedly arranged in the DI1 direction.

[0163] In the above case, it is possible to effectively discharge the gas generated in the first layer (121b) through the first through hole (116a) due to the heat applied when forming at least one of the second layer (123b) and the third layer (124b) of the second partition wall (120b).

[0164] In the above case, the first through hole (116a) may include various planar shapes. For example, the first through hole (116a) may include a planar shape shown in at least one of FIGS. 4a to 4f. Additionally, the first through hole (116a) may be formed as shown in the cross-section of FIG. 6b.

[0165] Referring to FIG. 6b, a first common voltage supply wire (116) may be placed on the second partition (120b) among the partitions. A touch wire (TL) may be placed on the first common voltage supply wire (116). At this time, the first common voltage supply wire (116) and the touch wire (TL) may be extended in different directions.

[0166] The first common voltage supply wiring (116) may have a plurality of through holes (116a). At this time, at least two of the plurality of through holes (116a) may be placed on the cross-section of the first layer (121b) of the second partition (120b). In such a case, gas generated in the first layer (121b) due to heat applied when forming the second layer (123b) and the third layer (124b) after the first layer (121b) is formed can be smoothly discharged through the through holes (116a).

[0167] On the second partition wall (120b) as described above, a first inorganic sealing layer (510), a second inorganic sealing layer (520), a first insulating layer (712), and a touch wiring (TL) can be sequentially laminated.

[0168] FIG. 7 is a cross-sectional view showing a display device according to another embodiment of the present invention.

[0169] Referring to FIG. 7, the display device (10) may be similar to the form shown in FIG. 3. For convenience of explanation, the parts that differ from FIG. 3 will be described in detail below.

[0170] The display device (10) may include a spacer (170). In this case, the spacer (170) may be placed on the pixel defining film (112). The spacer (170) may be placed on the pixel defining film (112) or formed integrally with the pixel defining film (112). The spacer (170) may have various shapes. For example, the spacer (170) may be formed in the shape of a protrusion and provided in multiple numbers, and the multiple spacers (170) may be placed on the pixel defining film (112) so as to be spaced apart from each other. As another embodiment, it is also possible to provide one spacer (170) in the space between adjacent subpixels (or between adjacent intermediate layers). At this time, the spacer (170) is not limited to the above, and can prevent defects such as damage or breakage to a part of the substrate (100) from occurring when each mask sheet enters the opening of the pixel defining film (112) or when a deposition material is deposited on the substrate (100), by the mask sheet adhering to the pixel defining film (112) and the mask sheet contacting the substrate (100). In particular, the spacer (170) can maintain a gap between the end of the opening area of ​​the pixel defining film (112) and each mask assembly when each mask assembly is adhering to the substrate (100). In such a case, the spacer (170) can be positioned so as not to overlap with each intermediate layer.

[0171] The spacer (170) described above may be formed integrally with the pixel defining film (112) at the time of forming the pixel defining film (112), or may be formed separately on the pixel defining film (112) after forming the pixel defining film (112). In this case, the spacer (170) may use a material that is the same as or different from the pixel defining film (112). For convenience of explanation, the following description will focus on the case where the spacer (170) uses the same material as the pixel defining film (112).

[0172] The first partition (120a) may include a first layer (121a) disposed on the first common voltage supply line (116) and the second common voltage supply line (210), a second layer (122a) disposed on the first layer (121a), and a third layer (123a) disposed on the second layer (122a). At this time, the first layer (121a) may be made of the same material as the second flattening layer (111), the second layer (122a) may be made of the same material as the pixel defining film (112), and the third layer (123a) may be made of the same material as the spacer (170).

[0173] The second partition (120b) may include a first layer (121b), a second layer (123b) disposed on the first common voltage supply wiring (116), a third layer (124b) disposed on the second layer (123b), and a fourth layer (125b) disposed on the third layer (124b). In this case, the first common voltage supply wiring (116) may be disposed between the first layer (121b) and the second layer (123b). At this time, the first common voltage supply wiring (116) may have a first through hole (116a) of the form shown in one of FIGS. 4a to 4f and FIG. 6a.

[0174] The first partition (120a) and the second partition (120b) as described above may have a cross-sectional shape as illustrated in FIGS. 5a to FIGS. 5. In this case, it is also possible for the first partition (120a) and the second partition (120b) to have different shapes from each other.

[0175] In the above case, when the second partition (120b) is formed, the gas generated in the first layer (121b) can be discharged to the outside of the first layer (121b) through the first through hole (116a). At this time, a part of the second layer (123b) can be inserted into the first through hole (116a).

[0176] FIG. 8 is a cross-sectional view showing a display device according to another embodiment of the present invention.

[0177] Referring to FIG. 8, the display device (10) may be similar to that shown in FIG. 3. Below, details that differ from those shown in FIG. 3 will be described in detail.

[0178] The display device (10) may include an intermediate flattening layer (110) disposed on the first flattening layer (109) and a second flattening layer (111) disposed on the intermediate flattening layer (110). At this time, the connecting electrode (130) may be disposed on the upper surface of at least one of the intermediate flattening layer (110) and the second flattening layer (111). For convenience of explanation, the following description will focus on the case where the connecting electrode (130) is disposed on the intermediate flattening layer (110).

[0179] In the above case, the first partition (120a) placed on the first common voltage supply wiring (116) and the second common voltage supply wiring (210) may include a first layer (121a) formed of the same material as the intermediate flattening layer (110), a second layer (122a) placed on the first layer (121a) and formed of the same material as the second flattening layer (111), and a third layer (123a) formed of the same material as the pixel defining film (112).

[0180] A second partition wall (120b) spaced apart from a first partition wall (120a) may include a first layer (121b) formed of the same material as the first flattening layer (109), a second layer (123b) formed of the same material as the intermediate flattening layer (110) disposed on the first layer (121b) and disposed on the first common voltage supply wiring (116), a third layer (124b) disposed on the second layer (123b) and formed of the same material as the second flattening layer (111), and a fourth layer (125b) disposed on the third layer (124b) and formed of the same material as the pixel defining film (112). In this case, the first common voltage supply wiring (116) may have a first through hole (116a) identical or similar to the form described in at least one of FIGS. 4a to 4f and FIG. 6a.

[0181] In the above case, when forming the second partition (120b), heat may be applied during each process when forming the second layer (123b), the third layer (124b), or the fourth layer (125b). In this case, if the first through hole (116a) does not exist in the first common voltage supply wiring (116), gas may be generated in the first layer (121b) of the second partition (120b) that overlaps with the first common voltage supply wiring (116) in a plane due to the heat applied during the formation of the second layer (123b), the third layer (124b), or the fourth layer (125b) as above. The gas generated in the first layer (121b) may remain inside the first layer (121b) as it is blocked by the first common voltage supply wiring (116). In this case, as described above, the first layer (121b) may swell, and the first common voltage supply wiring (116) may be formed into a curved surface. At this time, the second layer (123b), the third layer (124b), and the fourth layer (125b) placed on the first common voltage supply wiring (116) may be spaced further from the upper surface of the substrate (100) than designed, thereby affecting the touch wiring (TL) placed on the fourth layer (125b). However, as described above, the first through hole (116a) is formed, so that the gas of the first layer (121b) can be smoothly discharged through the first through hole (116a).

[0182] FIG. 9 is a cross-sectional view showing a display device according to another embodiment of the present invention.

[0183] Referring to FIG. 9, the display device (10) may be similar to that shown in FIG. 8. Below, details that differ from those shown in FIG. 8 will be described in detail.

[0184] The display device (10) may include a spacer (170). In this case, the spacer (170) is identical or similar to the one described in FIG. 7, so a detailed description is omitted.

[0185] In the above case, the first partition (120a) may include a first layer (121a), a second layer (122a), and a third layer (123a). At this time, the first layer (121a) may be an intermediate flattening layer (110), the second layer (122a) may be a second flattening layer (111), and the third layer (123a) may be a pixel defining film (112) or a spacer (170). In another embodiment, the first layer (121a) may be an intermediate flattening layer (110), the second layer (122a) may be a second flattening layer (111) or a pixel defining film (112), and the third layer (123a) may be a spacer (170). In another embodiment, the first layer (121a) may be an intermediate flattening layer (110) or a second flattening layer (111), the second layer (122a) may be a pixel defining film (112), and the third layer (123a) may be a spacer (170).

[0186] The second partition (120b) may include a first layer (121b), a second layer (123b), a third layer (124b), a fourth layer (125b), and a fifth layer (127b). In this case, the first layer (121b) may be the same material as the first flattening layer (109), the second layer (123b) may be the same material as the intermediate flattening layer (110), the third layer (124b) may be the same material as the second flattening layer (111), the fourth layer (125b) may be the same material as the pixel defining film (112), and the fifth layer (127b) may be the same material as the spacer (170). In the above case, the second partition (120b) is not limited to the above and may include any structure in which at least one of the second layer (123b), third layer (124b), fourth layer (125b) and fifth layer (127b) is stacked on the first common voltage supply wiring (116).

[0187] In the above case, a first through hole (116a) is provided in the first common voltage supply wiring (116) to provide a space for the gas generated in the first layer (121b) to be discharged to the outside of the first layer (121b).

[0188] FIG. 10 is a cross-sectional view showing a display device according to another embodiment of the present invention.

[0189] Referring to FIG. 10, the display device (10) can be formed similarly to that shown in FIG. 5.

[0190] A display device according to one embodiment of the present invention comprises an inorganic insulating layer having a lower valley (VAW1) in an area between a plurality of pixel circuits (PC1, PC2), and a first organic planarization layer (161) filling the lower valley (VAW1). In this specification, the lower valley (VAW1) refers to an opening or groove formed by removing a portion of the inorganic insulating layer.

[0191] Additionally, the display device according to the present embodiment may be disposed on the interlayer insulation layer (107) and may include a horizontal connecting wire (140) crossing the interlayer insulation layer (107) in a first direction and / or a vertical connecting wire crossing the interlayer insulation layer (107) in a second direction.

[0192] In an embodiment of the present invention, a barrier layer (100a), a buffer layer (101), a first gate insulating layer (103), a second gate insulating layer (105), and an interlayer insulating layer (107) comprising an inorganic material are disposed below a horizontal connecting wire (140) and may be collectively referred to as an inorganic insulating layer. This inorganic insulating layer may include a lower valley (VAW1) formed as an opening or groove in the region between adjacent pixel circuits.

[0193] FIG. 10 illustrates that the inorganic insulating layer has a lower valley (VAW1) formed as a groove. That is, the barrier layer (100a) may be continuous across the first pixel circuit (PC1) and the second pixel circuit (PC2), which are adjacent pixels. And the buffer layer (101), the first gate insulating layer (103), the second gate insulating layer (105), and the interlayer insulating layer (107) may have openings in the region between adjacent pixels.

[0194] Accordingly, an inorganic insulating layer comprising a barrier layer (100a), a buffer layer (101), a first gate insulating layer (103), a second gate insulating layer (105), and an interlayer insulating layer (107) can be understood to have a lower valley (VAW1) formed as a groove in the region between adjacent pixels. The groove may refer to a trench formed in the inorganic insulating layer.

[0195] Meanwhile, the term "opening of the inorganic insulating layer" may mean that openings are formed in the barrier layer (100a), buffer layer (101), first gate insulating layer (103), second gate insulating layer (105), and interlayer insulating layer (107), so that the substrate (100) is exposed.

[0196] Of course, the inorganic insulating layer may include various types of grooves different from this. For example, a portion of the upper surface of the barrier layer (100a) may be removed, while the lower surface of the buffer layer (101) may remain intact without being removed, and various modifications are possible.

[0197] To form the lower valley (VAW1) formed by such an opening or groove (GR), after forming the interlayer insulating layer (107), a separate mask process and etching process may be used. The openings of the buffer layer (101), the first gate insulating layer (103), the second gate insulating layer (105), and the interlayer insulating layer (107) can be formed by the etching process. The etching process may be a dry etching process.

[0198] The lower valley (VAW1) of the above-mentioned inorganic insulation layer may be filled with a first organic flattening layer (161). And the horizontal connecting wire (140) is located on the upper part of the interlayer insulation layer (107) and the first organic flattening layer (161).

[0199] The lower valley (VAW1) of such an inorganic insulating layer and the first organic flattening layer (161) filling it may be introduced to minimize the impact received by the display device from external shocks. Since the hardness of the inorganic insulating layer is higher than that of the first organic flattening layer (161), there is a very high probability that a crack will occur due to an external shock. If a crack occurs in the inorganic insulating layer, cracks will also occur in the various signal lines placed in the middle or upper part of the inorganic insulating layer, and there is a very high probability that defects such as disconnection will occur.

[0200] However, in the case of the display device according to the present embodiment, the inorganic insulating layer has a lower valley (VAW1) in the region between a plurality of pixel circuits, and the lower valley (VAW1) is filled by the first organic flattening layer (161), so the probability of crack propagation is extremely low even if there is an external impact. In addition, since the hardness of the first organic flattening layer (161) is lower than that of the inorganic layer, the first organic flattening layer (161) absorbs stress caused by external impact, so the concentration of stress on the connecting wires (140) located on the first organic flattening layer (161) can be effectively minimized.

[0201] Meanwhile, the horizontal connecting wire (140) is placed on the first organic flattening layer (161), and although not shown in the drawing, the vertical connecting wire is placed on the second flattening layer (111) to connect multiple pixel circuits to each other. These horizontal connecting wire (140) and vertical connecting wire can function as wires that transmit electrical signals to multiple pixels.

[0202] A barrier layer (100a) may be further included between the substrate (100) and the buffer layer (101). The barrier layer (100a) may serve to prevent or minimize the penetration of impurities from the substrate (100), etc., into the semiconductor layer. The barrier layer (100a) may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite, and may be composed of a single layer or a multilayer structure of inorganic and organic materials.

[0203] The buffer layer (101) can serve to increase the smoothness of the upper surface of the substrate (100) and may include inorganic materials such as silicon oxide, silicon nitride and / or silicon oxynitride.

[0204] The first semiconductor layer (A1) includes a first channel region, a first source region (S1) and a first drain region (D1) on both sides of the first channel region. For example, the first source region (S1) and the first drain region (D1) may be doped with impurities, and the impurities may include N-type impurities or P-type impurities. The first source region (S1) and the first drain region (D1) correspond to the first source electrode and the first drain electrode, respectively. Hereinafter, the terms first source region (S1) and first drain region (D1) are used instead of first source electrode or first drain electrode.

[0205] A first gate insulating layer (103) is located on the first semiconductor layer (A1). The first gate insulating layer (103) may include an inorganic material including an oxide or a nitride.

[0206] In this embodiment, the semiconductor layers of each of the plurality of pixel circuits are formed separately from one another. For example, the semiconductor layer of the first pixel circuit (PC1) is formed spaced apart from the semiconductor layer of the second pixel circuit (PC2).

[0207] Although not shown in the drawing, a scan line, a light emission control line, and a first gate electrode (G1) are disposed on the first gate insulating layer (103). The scan line, the light emission control line, and the first gate electrode (G1) are disposed on the same layer and contain the same material. For example, the scan line, the light emission control line, and the first gate electrode (G1) may contain molybdenum (Mo), copper (Cu), titanium (Ti), etc., and may be made of a single layer or multiple layers.

[0208] The first gate electrode (G1) is of the island type and is arranged to overlap with the first channel region of the first semiconductor layer (A1). The first gate electrode (G1) can perform the function of a gate electrode of the first thin-film transistor (T1), as well as the function of a first electrode (CE1) of the storage capacitor (Cst). That is, the first gate electrode (G1) and the first electrode (CE1) can be understood as being an integral unit.

[0209] The second electrode (CE2) of the storage capacitor (Cst) and the initial voltage line may be located on the second gate insulation layer (105).

[0210] The second electrode (CE2) of the storage capacitor (Cst) and the initial voltage line are placed on the same layer and contain the same material. In this embodiment, the second electrode (CE2) of the storage capacitor (Cst) and the initial voltage line of each of the plurality of pixel circuits (PC1, PC2) are formed separately from each other. For example, the second electrode (CE2) of the storage capacitor (Cst) of the first pixel circuit (PC1) and the second electrode (CE2) of the storage capacitor (Cst) of the second pixel circuit (PC2) are spaced apart from each other, and the initial voltage line of the first pixel circuit (PC1) and the initial voltage line of the second pixel circuit (PC2) are spaced apart from each other.

[0211] An interlayer insulation layer (107) is located on the second electrode (CE2) of the storage capacitor (Cst) and on the initialization voltage line.

[0212] The interlayer insulation layer (107) is silicon oxide (SiO₂). x ), silicon nitride (SiN x It may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc. A lower valley (VAW1) may be disposed in the interlayer insulation layer (107).

[0213] A first organic flattening layer (161) may be disposed inside the lower valley (VAW1). At this time, the first organic flattening layer (161) may include one or more materials selected from the group consisting of acrylic, methacrylic, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane.

[0214] A horizontal connecting wire (140) extending in a first direction is positioned on the interlayer insulation layer (107) and the first organic flattening layer (161). The horizontal connecting wire (140) extends from the first pixel circuit (PC1) to the second pixel circuit (PC2) and connects the first pixel circuit (PC1) and the second pixel circuit (PC2). The horizontal connecting wire (140) can connect multiple pixels arranged in the first direction.

[0215] In this embodiment, conductive layers such as the semiconductor layer and signal lines, initialization voltage line, and the first electrode (CE1) and second electrode (CE2) of the storage capacitor, which are disposed below the horizontal connecting wire (140), are formed separately for each pixel circuit. Accordingly, stress that may occur in one pixel circuit can be prevented from propagating to other pixels. Meanwhile, the horizontal connecting wire (140) can be formed of a material with high elongation, thereby minimizing defects caused by stress.

[0216] The horizontal connecting wire (140) may include a light-emitting control connecting wire, a mesh connecting wire (142), a scan connecting wire, a previous scan connecting wire, and an initialization voltage connecting wire.

[0217] The light-emitting control connection line connects the light-emitting control line of the first pixel circuit (PC1) and the light-emitting control line of the second pixel circuit (PC2) through a contact hole formed by penetrating the interlayer insulation layer (107) and the second gate insulation layer (105). The light-emitting control connection line can be extended in a first direction while overlapping with the light-emitting control line of the first pixel circuit (PC1) and the light-emitting control line of the second pixel circuit (PC2).

[0218] The mesh connection line (142) connects the second electrode (CE2) of the first pixel circuit (PC1) and the second electrode (CE2) of the second pixel circuit (PC2) through contact holes (CNT3a, CNT2b) formed by penetrating the interlayer insulation layer (107). Since the second electrode (CE2) of the storage capacitor (Cst) is connected to the driving voltage line to receive the driving voltage, the mesh connection line (142) can serve to transmit the driving voltage across multiple pixels arranged in the first direction. By means of the mesh connection line (142), a driving voltage line with a mesh structure can be formed without securing space for a separate driving voltage line extending in the first direction. Accordingly, more space can be secured for the storage capacitor (Cst), thereby enabling the implementation of a high-definition display device.

[0219] The scan connection line connects the scan line of the first pixel circuit (PC1) and the scan line of the second pixel circuit (PC2) through a contact hole formed by penetrating the interlayer insulation layer (107) and the second gate insulation layer (105). The scan connection line can be extended in a first direction while overlapping with the scan line of the first pixel circuit (PC1) and the scan line of the second pixel circuit (PC2).

[0220] The previous scan connection line connects the previous scan line of the first pixel circuit (PC1) and the previous scan line of the second pixel circuit (PC2) through a contact hole formed by penetrating the interlayer insulation layer (107) and the second gate insulation layer (105). The previous scan connection line can be extended in a first direction while overlapping with the previous scan line of the first pixel circuit (PC1) and the previous scan line of the second pixel circuit (PC2).

[0221] The initial voltage connection line connects the initial voltage line of the first pixel circuit (PC1) and the initial voltage line of the second pixel circuit (PC2) through a contact hole formed by penetrating the interlayer insulation layer (107). The initial voltage connection line can be extended in a first direction while overlapping with the initial voltage line of the first pixel circuit (PC1) and the initial voltage line of the second pixel circuit (PC2).

[0222] In this way, the horizontal connecting wire (140) connects the first pixel circuit (PC1) and the second pixel circuit (PC2), and can serve to supply electrical signals to multiple pixels.

[0223] A wiring protection layer (PVX) may be disposed on the horizontal connecting wiring (140). At this time, the wiring protection layer (PVX) may shield only a part of the horizontal connecting wiring (140) or shield the entire front surface. This wiring protection layer (PVX) may include an inorganic insulating material, such as silicon oxide, silicon nitride, or / and silicon oxynitride, and may include a single layer or multiple layers of the aforementioned material.

[0224] The first flattening layer (109) is located on the interlayer insulation layer (107) and the wiring protection layer (PVX).

[0225] A vertical connecting wire extending in a second direction is located on the first flattening layer (109). The vertical connecting wire is insulated from the horizontal connecting wire (140) by the first flattening layer (109). The vertical connecting wire may include a data line, a driving voltage line, a first node connecting line, a second node connecting line, and an intermediate connecting line.

[0226] The first organic planarization layer (161) is positioned between the first pixel circuit (PC1) and the second pixel circuit (PC2), filling the lower valley (VAW1) of the inorganic insulating layer, and simultaneously between the first pixel circuit (PC1) region and the second pixel circuit (PC2) region.

[0227] This first organic planarization layer (161) may comprise one or more materials selected from the group consisting of acrylic, methacrylic, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane. In some embodiments, the first organic planarization layer (161) may be formed from a high-heat-resistant organic material based on polyimide, phenylene, or siloxane. Such materials may be advantageous for forming contact holes in the first organic planarization layer (161). However, the present invention is not limited thereto.

[0228] The inorganic insulating layer has a higher hardness than the first organic planarization layer (161) but may be vulnerable to stress. Meanwhile, the first organic planarization layer (161) can absorb stress due to the characteristics of the organic material.

[0229] The inorganic insulating layer has a lower valley (VAW1) formed by removing a portion thereof, and the first organic planarization layer (161) is arranged to fill the lower valley (VAW1), thereby preventing stress that may be applied to the display device or cracks caused by said stress from propagating between pixel circuits (PC1, PC2).

[0230] In addition, the first organic flattening layer (161) can reduce defects that may occur when forming the horizontal connecting wire (140) formed on its upper surface, and can reduce coupling that may occur between the vertical connecting wires placed on the upper surface of the horizontal connecting wire (140).

[0231] If the upper surface of the first organic flattening layer (161) is not flat and a part thereof is convex, the width of the horizontal connecting wire (140) may be formed differently during the process of patterning the conductive layer to form the horizontal connecting wire (140). Additionally, if the horizontal connecting wire (140) is formed convexly along the shape of the first organic flattening layer (161), coupling with the vertical connecting wire placed on top thereof may occur. Therefore, it is preferable to form the upper surface of the first organic flattening layer (161) flat.

[0232] A horizontal connecting wire (140) is disposed on the first organic flattening layer (161). The horizontal connecting wire (140) is disposed overlapping with a lower valley (VAW1) disposed in the area between the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0233] An organic light-emitting element (300) having a pixel electrode (310), a counter electrode (330), and an intermediate layer (320) interposed between them and including a light-emitting layer may be positioned on the second flattening layer (111).

[0234] The pixel electrode (310) is connected to an intermediate connection line through a contact hole defined in the second flattening layer (111), and is connected to the drain region of the sixth thin-film transistor by the intermediate connection line.

[0235] A pixel defining film (112) may be disposed on the upper portion of the second planarization layer (111). This pixel defining film (112) serves to define pixels by having openings corresponding to each pixel, that is, openings that expose at least the central portion of the pixel electrode (310). Additionally, the pixel defining film (112) serves to prevent arcs from occurring at the edge of the pixel electrode (310) by increasing the distance between the edge of the pixel electrode (310) and the opposing electrode (330) above the pixel electrode (310). The intermediate layer (320) of the organic light-emitting element (300) may include a low-molecular or high-molecular material. When low molecular weight materials are included, the structure may have a stacked structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) are stacked in a single or composite manner, and may include various organic materials such as copper phthalocyanine (CuPc), N,N-di(naphthalene-1-yl)-N,N'-diphenyl-benzidine (NPB), and tris-8-hydroxyquinoline aluminum (Alq3). These layers can be formed by vacuum deposition.

[0236] When the intermediate layer (320) includes a polymer material, it may generally have a structure including a hole transport layer (HTL) and an emitting layer (EML). In this case, the hole transport layer may include PEDOT, and the emitting layer may include polymer materials such as PPV (Poly-Phenylenevinylene) and Polyfluorene. Such an intermediate layer (320) can be formed by screen printing, inkjet printing, laser thermal imaging (LITI), etc.

[0237] Of course, the intermediate layer (320) is not necessarily limited to this and may have various structures. Also, the intermediate layer (320) may include a layer that is integral across a plurality of pixel electrodes (310), or may include a layer patterned to correspond to each of the plurality of pixel electrodes (310).

[0238] The counter electrode (330) is positioned above the display area (DA) and can be positioned to cover the display area (DA). That is, the counter electrode (330) is formed integrally with a plurality of organic light-emitting elements and can correspond to a plurality of pixel electrodes (310).

[0239] Since these organic light-emitting elements (300) can be easily damaged by moisture or oxygen from the outside, a thin film encapsulation layer (500) can cover these organic light-emitting elements to protect them. The thin film encapsulation layer (500) covers the display area (DA) and can extend to the outside of the display area (DA). This thin film encapsulation layer (500) may include a first inorganic encapsulation layer (510), an organic encapsulation layer (520), and a second inorganic encapsulation layer (530).

[0240] If necessary, other layers, such as a capping layer, may be interposed between the first inorganic sealing layer (510) and the opposing electrode (330). Since this first inorganic sealing layer (510) is formed along the structure below it, the upper surface of the first inorganic sealing layer (510) is not flat.

[0241] Although not shown, a spacer for preventing mask imprinting may be further included on the pixel definition film (112), and various functional layers such as a polarizing layer for reducing external light reflection, a black matrix, a color filter, and / or a touchscreen layer equipped with a touch electrode may be provided on the thin film encapsulation layer (500).

[0242] The above-mentioned display device may include a partition and common voltage supply wiring as shown in FIGS. 3 to 9, although not shown in the drawings.

[0243] FIG. 11 is a cross-sectional view showing a display device according to another embodiment of the present invention.

[0244] Referring to FIG. 11, the display device (10) may be similar to that shown in FIG. 10. Below, the parts that differ from FIG. 10 will be described in detail.

[0245] The first organic flattening layer (161) can be placed on the front of the display area (DA), including the lower valley (VAW1). At this time, the upper surface of the first organic flattening layer (161) is not only flat but can also absorb shocks applied from the outside. At this time, a horizontal connecting wire (140) can be placed on the first organic flattening layer (161).

[0246] A first flattening layer (109) is disposed on the horizontal connecting wire (140) as described above, and an intermediate flattening layer (110) and a second flattening layer (111) can be disposed sequentially on the first flattening layer (109).

[0247] Although the above-mentioned display device is not shown in the drawings, it may include a partition wall and common voltage supply wiring shown in FIGS. 3 to 9 in the surrounding area.

[0248] FIG. 12 is a cross-sectional view showing a display device according to another embodiment of the present invention.

[0249] Referring to FIG. 12, the display device (10) may be similar to the display device shown in FIG. 3. Below, the parts that differ from the display device shown in FIG. 3 will be described in detail.

[0250] The display device (10) includes a first common voltage supply wire (116) and a second common voltage supply wire (210), and may include a common voltage connection wire (119) connecting the first common voltage supply wire (116) and the opposing electrode (330).

[0251] The common voltage connection wiring (119) may be placed on the second flattening layer (111). At this time, the common voltage connection wiring (119) is placed between the second flattening layer (111) and the pixel definition film (112), and may be formed of the same material as the pixel electrode (310). Additionally, the common voltage connection wiring (119) may be connected to the opposing electrode (330) and may be connected to the first common voltage supply wiring (116).

[0252] The common voltage connection wiring (119) may be placed on the upper surface of the first common voltage supply wiring (116) and may extend along the upper surfaces of the first partition (120a) and the second partition (120b). In this case, the common voltage connection wiring (119) may have a first connection wiring through-hole (119a) placed on the upper surface of the first partition (120a) and the upper surface of the second partition (120b). This first connection wiring through-hole (119a) may perform a similar function to the first through-hole (116a) described above.

[0253] The first partition (120a) and the second partition (120b) are not limited to those shown in FIG. 12, and may also be formed in the same way as shown in FIG. 7 to 9. In this case, the common voltage connection wiring (119) may extend along the outer surface of the first partition (120a) and the second partition (120b) in a direction away from the second partition (120b).

[0254] Meanwhile, the second partition (120b) and the first common voltage supply wiring (116) as described above may be arranged in the form shown in at least one of FIGS. 4a to 4f and FIGS. 6a and in the form shown in FIGS. 5a to 5c and FIGS. 6b.

[0255] Therefore, the display device (10) can reduce the occurrence of defects by ensuring that the touch wiring (TL) is not disconnected. The display device (10) can not only provide a clear image but also accurately receive user signals.

[0256] FIG. 13 is a cross-sectional view showing a display device according to another embodiment of the present invention.

[0257] Referring to FIG. 13, a display device (not shown) may include a display area (DA) and a surrounding area (not shown). In this case, since the surrounding area is identical or similar to that shown in FIG. 1 to FIG. 12, a different part of the display area (DA) will be described in detail.

[0258] The above display device may include a buffer layer (101) and an additional buffer layer (102). In this case, the buffer layer (101) and the additional buffer layer (102) may be silicon oxide (SiO2) or silicon nitride (SiN x It may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0259] A bias electrode (BSM) may be disposed between the buffer layer (101) and the additional buffer layer (102) to correspond to the first thin-film transistor (T1). That is, the bias electrode (BSM) may be formed to overlap with the first semiconductor layer (A1) of the first thin-film transistor (T1). A voltage may be applied to the bias electrode (BSM). The bias electrode (BSM) may serve to prevent external light from reaching the first semiconductor layer (A1). Accordingly, the characteristics of the first thin-film transistor (T1) may be stabilized. Meanwhile, the bias electrode (BSM) may be omitted in some cases.

[0260] The first thin-film transistor (T1) includes a first semiconductor layer (A1), a first gate electrode (G1), a first source electrode (S1), and a first drain electrode (D1). At this time, the first semiconductor layer (A1) may include amorphous silicon or polysilicon. In another embodiment, the first semiconductor layer (A1) may include an oxide of at least one material selected from the group comprising indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). In some embodiments, the first semiconductor layer (A1) may be formed of a Zn oxide-based material, such as Zn oxide, In-Zn oxide, Ga-In-Zn oxide, etc. In another embodiment, the first semiconductor layer (A1) may be an IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O) semiconductor containing metals such as indium (In), gallium (Ga), and tin (Sn) in ZnO. The first semiconductor layer (A1) may include a first channel region and a first source region and a first drain region disposed on both sides of the channel region. Additionally, the first semiconductor layer (A1) may be composed of a single layer or multiple layers.

[0261] On the first semiconductor layer (A1) as described above, a first gate insulating layer (103), a first gate electrode (G1), a second gate insulating layer (105), an interlayer insulating layer (107), a first flattening layer (109), and a second flattening layer (111) can be sequentially stacked.

[0262] A first gate electrode (G1) is disposed on a first gate insulating layer (103) so as to overlap at least partially with the first semiconductor layer (A1). The first gate electrode (G1) may be composed of a single layer or multiple layers and may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. A first electrode (not shown) of a storage capacitor (Cst) may be disposed on the same layer as the first gate electrode (G1). The first electrode may be formed of the same material as the first gate electrode (G1).

[0263] Additionally, an organic light-emitting element (300) may be disposed on the second planarization layer (111). Such an organic light-emitting element (300) may form a plurality of pixels (P1, P2, P3). At this time, the intermediate layer (320) of the organic light-emitting element (300) disposed in each pixel (P1, P2, P3) may be provided in common. Accordingly, the organic light-emitting element (300) included in each pixel (P1, P2, P3) may emit light of the same color. For example, the intermediate layer (320) may include an organic light-emitting layer containing a fluorescent or phosphorescent material that emits blue light. Functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be optionally disposed below and above the organic light-emitting layer.

[0264] A pixel defining film (112) may be disposed on the pixel electrode (310) of the organic light-emitting element (300) as described above. Additionally, an intermediate layer (320) and a counter electrode (330) may be disposed on the front of the display area (DA) on each pixel (P1, P2, P3) and the pixel defining film (112).

[0265] A thin film encapsulation layer (500) may be disposed on the organic light-emitting element (300) as described above. In this case, the thin film encapsulation layer (500) may include a first inorganic encapsulation layer (510), an organic encapsulation layer (520), and a second inorganic encapsulation layer (530).

[0266] An optical functional member (not shown) may be disposed on the upper portion of the thin film encapsulation layer (500) so as to face the substrate (100). At this time, the optical functional member may include an upper substrate (800) disposed to face the substrate (100), a color conversion layer (QD1, QD2), a transmission layer (TW), and a light blocking pattern (810) disposed on the upper substrate (800).

[0267] The color conversion layer (QD1, QD2) may be a layer that makes the color of light emitted from the organic light-emitting diode (300) vivid or converts the color to a different color. The color conversion layer (QD1, QD2) may be composed of a quantum conversion layer including quantum dots. Quantum dots are semiconductor particles with a diameter of only 2-10 nm that possess unique electrical and optical properties, and when exposed to light, quantum dots can emit light of a specific frequency depending on the size of the particles and the type of material. For example, depending on the size of the particles and / or the type of material, quantum dots can emit red, green, and blue light when exposed to light.

[0268] The core of the quantum dot can be selected from group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof.

[0269] Group II-VI compounds are diatomic compounds selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, and mixtures thereof; ternary compounds selected from the group consisting of AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS, and mixtures thereof; and may be selected from the group consisting of four-element compounds selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof.

[0270] III-V compounds may be selected from the group consisting of diatomic compounds selected from GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and mixtures thereof; ternary compounds selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InNAs, InNSb, InPAs, InPSb, GaAlNP, and mixtures thereof; and quaternary compounds selected from the group consisting of GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and mixtures thereof.

[0271] Group IV-VI compounds may be selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe, and mixtures thereof; ternary compounds selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and mixtures thereof; and quaternary compounds selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe, and mixtures thereof. Group IV elements may be selected from the group consisting of Si, Ge, and mixtures thereof. Group IV compounds may be ternary compounds selected from the group consisting of SiC, SiGe, and mixtures thereof.

[0272] In this case, the binary, ternary, or quaternary compounds may exist within the particle at a uniform concentration, or they may exist within the same particle with concentration distributions partially divided into different states. Additionally, the structure may have a core / shell configuration where one quantum dot surrounds another. The interface between the core and the shell may have a concentration gradient in which the concentration of the element present in the shell decreases towards the center.

[0273] In some embodiments, the quantum dot may have a core-shell structure comprising a core containing the aforementioned nanocrystal and a shell surrounding the core. The shell of the quantum dot may serve as a protective layer to maintain semiconductor properties by preventing chemical degradation of the core and / or as a charging layer to impart electrophoretic properties to the quantum dot. The shell may be a single layer or a multilayer. The interface between the core and the shell may have a concentration gradient in which the concentration of elements present in the shell decreases toward the center. Examples of the shell of the quantum dot include oxides of metals or non-metals, semiconductor compounds, or combinations thereof.

[0274] For example, the oxide of the metal or nonmetal mentioned above may be exemplified as a binary compound such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, NiO, or a ternary compound such as MgAl2O4, CoFe2O4, NiFe2O4, CoMn2O4, but the present invention is not limited thereto.

[0275] In addition, the above semiconductor compounds may be examples of CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc., but the present invention is not limited thereto.

[0276] Quantum dots can have a full width of half maximum (FWHM) of the emission wavelength spectrum of about 45 nm or less, preferably about 40 nm or less, and more preferably about 30 nm or less, and color purity or color reproducibility can be improved in this range. In addition, since the light emitted through these quantum dots is emitted in all directions, the viewing angle can be improved.

[0277] In addition, the shape of the quantum dots is not specifically limited to shapes commonly used in the field, but more specifically, shapes such as spherical, pyramidal, multi-arm, or cubic nanoparticles, nanotubes, nanowires, nanofibers, and nanoplate particles may be used.

[0278] The color conversion layers (QD1, QD2) may be arranged to correspond at least partially to the light-emitting region defined by the opening (OP) of the pixel defining film (112). For example, the first color conversion layer (QD1) may be arranged to correspond to the light-emitting region of the first pixel (P1), and the second color conversion layer (QD2) may be arranged to correspond to the light-emitting region of the second pixel (P2). The color conversion layer may not correspond to the light-emitting region of the third pixel (P3), and a transparent window (TW) may be arranged therein. The transparent window (TW) may be provided with an organic material that allows light to be emitted without wavelength conversion of the light emitted from the organic light-emitting element (300) of the third pixel (P3). However, it is not limited thereto. Of course, the color conversion layer may also be arranged in the light-emitting region (EA) of the third pixel (P3).

[0279] Scattering particles may be distributed in the color conversion layer (QD1, QD2) and the transmission window (TW). Accordingly, color spreading can be made uniform.

[0280] A light blocking pattern (810) may be placed between the color conversion layers (QD1, QD2) and the transmission window (TW). The light blocking pattern (810) may be a black matrix and may be a component for improving color clarity and contrast. The light blocking pattern (810) may be placed between the light-emitting regions of each pixel (P1, P2, P3). The light blocking pattern (810) may be provided as a black matrix that absorbs visible light, thereby preventing color mixing of light emitted from the light-emitting regions of neighboring pixels and improving visibility and contrast.

[0281] In some embodiments, a plurality of organic light-emitting elements (300) may all emit blue light. In this case, the first color conversion layer (QD1) may include a quantum dot that emits red light, and the second color conversion layer (QD2) may include a quantum dot that emits green light. Accordingly, the light emitted outside the display device may be red, green, and blue, and various color expressions may be possible through combinations of these colors.

[0282] A filler material (610) may be further disposed between the substrate (100) and the upper substrate (800). The filler material (610) can act as a buffer against external pressure, etc. The filler material (610) may be composed of organic materials such as methyl silicone, phenyl silicone, and polyimide. However, it is not limited thereto, and the filler material (610) may also be composed of organic sealants such as urethane resin, epoxy resin, acrylic resin, or inorganic sealants such as silicone.

[0283] Although the above-mentioned display device is not shown in the drawings, it may include a partition wall and common voltage supply wiring shown in FIGS. 3 to 9 in the surrounding area.

[0284] FIG. 14 is a cross-sectional view showing a display device according to another embodiment of the present invention.

[0285] Referring to FIG. 14, the display device may be similar to the display device shown in FIG. 13. Below, we will describe in detail the differences from the display device shown in FIG. 13.

[0286] Organic light-emitting elements (300) included in a plurality of pixels (P1, P2, P3) may be provided with a plurality of intermediate layers (320a, 320b) and a plurality of counter electrodes (330a, 330b) stacked thereon.

[0287] For example, an organic light-emitting device (300) may be provided with a first intermediate layer (320a), a first counter electrode (330a), a second intermediate layer (320b), and a second counter electrode (330b) sequentially stacked on a pixel electrode (310). The first intermediate layer (320a) and the second intermediate layer (320b) may include an organic light-emitting layer comprising a fluorescent or phosphorescent material that emits red, green, blue, or white light. The organic light-emitting layer may be a low-molecular-weight organic material or a high-molecular-weight organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be optionally further disposed below and above the organic light-emitting layer. In some embodiments, the first intermediate layer (320a) and the second intermediate layer (320b) may include an organic light-emitting layer that emits blue light.

[0288] The first counter electrode (330a) and the second counter electrode (330b) may be transparent electrodes or reflective electrodes. In some embodiments, the counter electrode (330) may be a transparent or translucent electrode and may be formed of a metal thin film with a low work function comprising Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and compounds thereof. Additionally, a transparent conductive oxide (TCO) film, such as ITO, IZO, ZnO, or In2O3, may be further disposed on the metal thin film. The first counter electrode (330a) may be a floating electrode.

[0289] The first intermediate layer (320a), the second intermediate layer (320b), the first counter electrode (330a), and the second counter electrode (330b) can be integrally formed in a plurality of pixels.

[0290] In this embodiment, color filters (CF1, CF2, CF3) may be provided on the upper substrate (800). The color filters (CF1, CF2, CF3) may be introduced to realize a full-color image, improve color purity, and improve outdoor visibility.

[0291] Color filters (CF1, CF2, CF3) can be arranged on the upper substrate (800) to correspond to the light-emitting areas of each pixel (P1, P2, P3). A light-blocking pattern (810) can be arranged between the color filters (CF1, CF2, CF3).

[0292] The protective layer (220) may be provided to cover the light-blocking pattern (810) and the color filters (CF1, CF2, CF3). The protective layer (220) may be silicon oxide (SiO2) or silicon nitride (SiN x It may include inorganic materials such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The protective layer (220) may also include organic materials such as polyimide or epoxy.

[0293] The first color conversion layer (QD1), the second color conversion layer (QD2), and the transmission window (TW) may be arranged to overlap with the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3), respectively, with the protective layer (220) in between. On the upper substrate (800), an additional protective layer (230) may be further provided to cover the first color conversion layer (QD1), the second color conversion layer (QD2), and the transmission window (TW). The additional protective layer (230) may be provided with an organic material or an inorganic material.

[0294] The first color conversion layer (QD1) and the second color conversion layer (QD2) may include quantum dots that emit different colors. For example, the first color conversion layer (QD1) may emit red light, and the second color conversion layer (QD2) may emit green light. Additionally, the transmission window (TW) may transmit blue light emitted from the organic light-emitting element (300) of the third pixel (P3).

[0295] In this case, the first color filter (CF1) may be a red color filter, the second color filter (CF2) may be a green color filter, and the third color filter (CF3) may be a blue color filter.

[0296] Although the above-mentioned display device is not shown in the drawings, it may include a partition wall and common voltage supply wiring shown in FIGS. 3 to 9 in the surrounding area.

[0297] FIG. 15 is a plan view showing a display device according to another embodiment of the present invention.

[0298] Referring to FIG. 15, the display device (10) may include a substrate (100), a display layer (not shown) disposed on a display area (DA), a thin film encapsulation layer (not shown) disposed on the display layer, and an input sensing member (not shown) disposed on the thin film encapsulation layer. In addition, the display device (10) may include a circuit that supplies power to the display layer or applies a signal in addition to the above configuration.

[0299] A plurality of pixels (Px) are arranged on the display area (DA), and the surrounding area (PA) may include a first scan driver (11), a second scan driver (12), a terminal part (20), a driving voltage supply wire (30), a common voltage supply wire (40), and a wiring layer (50). At this time, the wiring layer (50) may include a first wire (51), a second wire (52), a third wire (53), and a fourth wire (54). Below, the parts that differ from the display device (10) of FIG. 1 will be described in detail.

[0300] The common voltage supply wiring (40) can be arranged similarly to that shown in FIG. 1. At this time, a plurality of common voltage supply wirings (40) may be provided, and one of the plurality of common voltage supply wirings (40) may be placed at the lower center of the substrate (100). In addition, another of the plurality of common voltage supply wirings (40) may be arranged to surround the display area (DA), and a portion of it may be folded and arranged to face one of the plurality of common voltage supply wirings (40).

[0301] The driving voltage supply wiring (30) can be positioned between common voltage supply wirings (40) that are spaced apart from each other. At this time, the driving voltage supply wiring (30) can be electrically insulated from the common voltage supply wiring (40). The common voltage supply wiring (40) and the driving voltage supply wiring (30) can each be connected to the terminal portion (20) through wiring.

[0302] Based on FIG. 15, the common voltage supply wiring (40) and the driving voltage supply wiring (30) positioned at the lower side of the display area (DA) may be positioned to overlap with the partition wall (120). At this time, at least one partition wall (120) may be provided. For example, one partition wall (120) may be provided. In another embodiment, two or more partition walls (120) may be provided. In this case, the common voltage supply wiring (40) and the driving voltage supply wiring (30) positioned at the lower side of the display area (DA) may overlap with at least one of the two or more partition walls (120). In particular, the common voltage supply wiring (40) and the driving voltage supply wiring (30) positioned at the lower side of the display area (DA) may overlap with the partition wall closest to the terminal portion (20) among the two or more partition walls (120). As described above, when there are two or more partitions (120), the partition (120) closest to the terminal portion (20) may be identical or similar to the second partition (120b) shown in FIG. 3. On the other hand, when there are two or more partitions (120), the remaining partitions (120), excluding the partition (120) closest to the terminal portion (20), may be identical or similar in shape to the first partition (120a) shown in FIG. 3. However, for convenience of explanation, the following description will focus on the case where the partition (120) includes the first partition (120a) and the second partition (120b).

[0303] FIG. 16 is a plan view showing an enlarged view of section C of FIG. 15. FIG. 17a is a plan view showing an enlarged view of section D of FIG. 16. FIG. 17b is a plan view showing an enlarged view of section E of FIG. 16.

[0304] Referring to FIGS. 16 to 17b, the common voltage supply wiring (40) may include a first through hole (116a) in a portion that overlaps with the second partition (120b). At this time, at least one first through hole (116a) may be provided. The arrangement and number of such first through holes (116a) may be the same or similar as described in FIGS. 3 to 5c.

[0305] The common voltage supply wiring (40) described above may be divided into an area where at least one touch wiring (TL) intersects (e.g., area D in FIG. 17b or FIG. 16) and an area where the touch wiring (TL) is not arranged to intersect (e.g., area E in FIG. 17c or FIG. 16). In such a case, the touch wiring (TL) may not be arranged on the common voltage supply wiring (40) where the touch wiring (TL) is not arranged to intersect.

[0306] A plurality of first through holes (116a) can be arranged at regular intervals in a regular pattern on the two areas as described above.

[0307] Regions D and E shown in FIG. 16 may also be arranged on the driving voltage supply wiring (30). For example, although not shown in the drawing, region F of FIG. 16 may have touch wiring (TL) arranged similarly to region D of FIG. 16. In another embodiment, region F of FIG. 16 may not have touch wiring (TL) arranged similarly to region E of FIG. 16. In yet another embodiment, touch wiring (TL) may be arranged in part of region F of FIG. 16, and touch wiring (TL) may not be arranged in another part of region F of FIG. 16. In yet another embodiment, touch wiring (TL) may be arranged in region F of FIG. 16, and it is also possible for touch wiring (TL) not to be arranged in the driving voltage supply wiring (30) portion other than region F of FIG. 16. As another embodiment, touch wiring (TL) may not be placed in the F region, and it is also possible to place touch wiring (TL) in the driving voltage supply wiring (30) portion other than the F region of FIG. 16.

[0308] However, for the convenience of explanation, the following description will focus on the case where the touch wiring (TL) passes through the F area of ​​FIG. 16.

[0309] FIG. 17c is a plan view showing an enlarged view of section F of FIG. 16. FIG. 17d is a cross-sectional view taken along G-G' of FIG. 17c.

[0310] Referring to FIGS. 17c and 17d, the driving voltage supply wiring (30) may include a first driving voltage supply wiring (31) and a second driving voltage supply wiring (32), similar to the common voltage supply wiring (40). In this case, the second driving voltage supply wiring (32) and the first driving voltage supply wiring (31) may be placed on different layers and connected to each other. That is, the second driving voltage supply wiring (32) may be placed on an inorganic insulating layer (ILD) comprising at least one layer among a barrier layer (not shown), a buffer layer (101), a first gate insulating layer (103), a second gate insulating layer (105), and an interlayer insulating layer (107), and the first driving voltage supply wiring (31) may be placed on a first flattening layer (109) and electrically connected to the second driving voltage supply wiring (32). At this time, the first driving voltage supply wire (31) and the second driving voltage supply wire (32) may be connected through a separate contact hole formed on the first flattening layer (109), or as shown in FIG. 17d, the second driving voltage supply wire (32) exposed at the end of the first flattening layer (109) and the first driving voltage supply wire (31) may meet and be connected to each other.

[0311] In addition to being placed on the first flattening layer (109), the first driving voltage supply wiring (31) as described above may also be placed on the second flattening layer (111).

[0312] In the above case, the second driving voltage supply wire (32) and the first driving voltage supply wire (31) may be placed at the bottom of the first partition (120a). Additionally, the second driving voltage supply wire (32) may be placed at the bottom of the second partition (120b), and the first driving voltage supply wire (31) may be placed at the top of the first layer (121b) of the second partition (120b) so as to penetrate the second partition (120b). At this time, a second through hole (31a) may be provided in the first driving voltage supply wire (31). This second through hole (31a) may be identical or similar to the first through hole (116a) described above.

[0313] In the above case, due to the heat applied when forming the partition wall (120), the gas inside the first layer (121b) of the second partition wall (120b) can be discharged to the outside through the second through hole (31a).

[0314] In particular, in the case described above, even when the touch wiring (TL) is formed on the second partition (120b), the touch wiring (TL) can be prevented from being disconnected by the second partition (120b) swelling up or becoming too high.

[0315] Figure 18 is a plan view showing an enlarged view of section H of Figure 15.

[0316] Referring to FIG. 18, a common voltage supply wire (40) and a driving voltage supply wire (30) may be arranged in the central part of a substrate (not shown). At this time, a first through hole (116a) and a second through hole (31a) may be arranged in the common voltage supply wire (40) and the driving voltage supply wire (30), respectively. In this case, the first through hole (116a) and the second through hole (31a) may have the same size and the same arrangement.

[0317] As such, the present invention has been described with reference to an embodiment illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and variations of the embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0318] 10: Display device 120b: Second bulkhead 100: Substrate 130: Connecting electrode 101: Buffer layer 140: Horizontal connection wiring 102: Additional buffer layer 161: First organic planarization layer 103: First gate insulation layer 170: Spacer 105: Second gate insulation layer 20: Terminal part 107: Interlayer insulation layer 210: Second common voltage supply wiring 109: First leveling layer 220: Protective layer 110: Intermediate leveling layer 230: Additional protective layer 111: Second flattening layer 30: Driving voltage supply wiring 112: Pixel defining layer 300: Organic light-emitting diode 116: 1st Common Voltage Supply Wiring 40: Common Voltage Supply Wiring 116a: Through hole 500: Thin film encapsulation layer 119: Common voltage connection wiring 610: Filler material 119a: Connection wiring through-hole 700: Touchscreen layer 120: Bulkhead 800: Upper substrate 120a: First bulkhead 810: Light blocking pattern

Claims

Claim 1 A display device comprising: a substrate including a display area and a peripheral area; a partition disposed in the peripheral area; and wiring disposed on the substrate and extending from the display area to the peripheral area, inserted into the interior of the partition or penetrating the interior of the partition, wherein at least one through hole is formed in the wiring, and the partition comprises: a first layer disposed below the wiring; a second layer disposed above the wiring; and a third layer disposed on the second layer and comprising a black material. Claim 2 A display device according to claim 1, wherein the through holes are provided in plurality and the through holes are arranged to be spaced apart from each other along one direction. Claim 3 In claim 1, the through hole on the plane is a display device disposed in the wiring disposed inside the bulkhead. Claim 4 A display device according to claim 1, wherein the through holes are provided in plurality and the plurality of through holes are arranged in a serpentine shape. Claim 5 delete Claim 6 delete Claim 7 delete Claim 8 A display device according to claim 1, wherein the partition wall further comprises a fourth layer disposed on the third layer. Claim 9 In claim 1, the first layer and the second layer are a display device comprising an organic material. Claim 10 In claim 1, the partition is a display device arranged to surround the outer edge of the display area. Claim 11 A display device comprising: a substrate including a display area and a peripheral area; a partition wall disposed in the peripheral area; wiring disposed on the substrate and extending from the display area to the peripheral area, inserted into the interior of the partition wall or penetrating the interior of the partition wall; and touch wiring disposed on the substrate and extending from the display area to the peripheral area, disposed on the upper portion of the partition wall; wherein the wiring has at least one through hole formed therein. Claim 12 In claim 11, the through holes are provided in plurality, and the through holes are arranged to be spaced apart from each other along the longitudinal direction of the wiring. Claim 13 In claim 11, the through hole on the plane is a display device disposed in the wiring disposed inside the bulkhead. Claim 14 A display device according to claim 11, wherein the through holes are provided in plurality and the plurality of through holes are arranged in a serpentine shape. Claim 15 In claim 11, the bulkhead comprises: a first layer disposed below the wiring; and a second layer disposed above the wiring; a display device. Claim 16 In claim 15, the first layer and the second layer are a display device comprising an organic material. Claim 17 In claim 15, the above bulkhead further comprises a third layer disposed on the second layer; a display device. Claim 18 In claim 17, the display device wherein the second layer or the third layer further comprises a black material. Claim 19 In claim 11, the bulkhead is a display device arranged to surround the outer edge of the display area. Claim 20 A display device further comprising, in any one of claims 11 to 19, a terminal portion disposed in the surrounding area and connected to the wiring and the touch wiring. Claim 21 In claim 20, the partition wall is a display device disposed in an area disposed between the terminal portion and the display area. Claim 22 A display device further comprising, in any one of claims 1 to 4 and claims 8 to 10, a terminal portion disposed in the surrounding area and spaced apart from the display area and connected to the wiring. Claim 23 delete Claim 24 delete Claim 25 delete

Images