Memory test device and operation method thereof

Abstract

A memory test device according to the present invention comprises: a user interface configured to output a setting signal pointing to a memory to be tested; a processor configured to calculate first information corresponding to a first operation to be performed in the memory based on the setting signal and to output a first request signal including the calculated first information; a request module configured to perform first communication with the memory based on the first request signal so that the memory performs the first operation; and a vector configured to record the first communication between the memory and the request module.

Description

Technology Field

[0001] The present invention relates to a test device and a method of operating the same, and more specifically, to a memory test device for testing the function of a semiconductor memory device and a method of operating the same. Background Technology

[0002] A semiconductor memory device is a device that stores data. Recently, as electronic devices and semiconductor memory devices have become smaller and more highly integrated, the designs of semiconductor memory devices have become more diverse, and the process of testing the functions of designed or manufactured semiconductor memory devices has become more complex.

[0003] For example, a significant amount of time and effort is required to newly set the conditions of the memory test device for each semiconductor memory device, taking into account the type of memory device to be tested, the standard specifications applied to the memory device, the content of the test operation to be performed on the memory device, the range of memory cells to be tested among the memory cells of the memory device, and the protocol used for communication with the memory device. The problem to be solved

[0004] The present invention aims to solve the aforementioned problems, and the objective of the present invention is to provide a memory test device having a structure that facilitates reuse according to changes in test conditions, and a method of operating the same. means of solving the problem

[0005] A memory test device according to an embodiment of the present invention comprises: a user interface configured to output a setting signal pointing to a memory to be tested; a processor configured to calculate first information corresponding to a first operation to be performed in the memory based on the setting signal and to output a first request signal including the calculated first information; a request module configured to perform first communication with the memory based on the first request signal so that the memory performs the first operation; and a vector configured to record the first communication between the memory and the request module.

[0006] A method of operating a memory test device according to an embodiment of the present invention comprises the steps of: setting test conditions; calculating information corresponding to an operation to be performed in a memory that meets the test conditions and generating a request signal including the calculated information; communicating with the memory to perform the operation based on the request signal; and recording the communication. Effects of the invention

[0007] According to an embodiment of the present invention, a memory test device having a structure that facilitates reuse according to changes in test conditions and a method of operating the same are provided.

[0008] In addition, a memory test device and a method of operation thereof are provided, in which the readability of the source code of each structure is improved and modification according to changes in test conditions is easy as the structures have independent structures according to function. Brief explanation of the drawing

[0009] FIG. 1 is a block diagram showing a memory test device according to an embodiment of the present invention. FIG. 2 is a block diagram exemplarily embodying the memory test device of FIG. 1. FIG. 3 is a block diagram that exemplarily embodies the user interface of FIG. 2. FIG. 4 is a block diagram that exemplarily embodies the processor of FIG. 2. FIG. 5 is a block diagram that exemplarily embodies the request module of FIG. 2. Figure 6 is a block diagram that exemplarily embodies the vector of Figure 2. FIG. 7 is a block diagram that exemplarily embodies the memory of FIG. 2. FIG. 8 is a flowchart showing the operation method of a memory test device according to an embodiment of the present invention. FIG. 9 is a flowchart exemplarily showing the operation method of a memory test device according to an embodiment of the present invention. Specific details for implementing the invention

[0010] In the following, embodiments of the present invention will be described clearly and in detail so that a person skilled in the art can easily practice the present invention. For convenience of explanation, similar components are referred to using the same or similar reference numbers.

[0011] The modules in the drawings or detailed description below may be connected to components other than those shown in the drawings or described in the detailed description. Connections between modules or components may be direct or indirect. Connections between modules or components may be communication connections or physical connections.

[0012] FIG. 1 is a block diagram showing a memory test device according to an embodiment of the present invention. Referring to FIG. 1, a memory test device (100) according to an embodiment of the present invention is shown. The memory test device (100) may be a device for testing the function of a memory (10). The memory test device (100) may communicate with the memory (10) to test the function of the memory (10).

[0013] The memory test device (100) may be implemented in hardware, software, or a combination thereof. For example, the memory test device (100) may be an automatic test equipment that tests the function of the memory (10). Alternatively, the memory test device (100) may be a simulation program that tests the function of the memory (10).

[0014] The memory (10) may be a semiconductor memory device configured to store data. For example, the memory (10) may be a volatile memory such as Dynamic Random Access Memory (DRAM). The memory (10) may be implemented in hardware, software, or a combination thereof. For example, the memory (10) may be a memory device connected to an automated test device. Alternatively, the memory (10) may be a simulation-only file generated based on memory design information.

[0015] According to an embodiment of the present invention, a memory test device (100) can test the function of a memory (10) under various test conditions. The test conditions may include the type of memory (10), standard specifications applied to the memory (10), the content of a test operation to be performed in the memory (10), the range of memory cells among the memory cells of the memory (10) to perform the test operation, and protocol information used for communication with the memory (10).

[0016] For example, the type of memory (10) may be a type according to the target for which the memory is used, such as a computer, a mobile device, and a graphics processing unit. The standard specifications applied to the memory (10) may be specifications applied according to the type of device, such as DDR4 (Double Data Rate 4th generation) or DDR5 (Double Data Rate 5th generation) for computers, LPDDR4 (Low Power DDR 4th generation) or LPDDR5 (Low Power DDR 5th generation) for mobile devices, and GDDR6 (Graphics DDR 6th generation) for graphics processing units.

[0017] The memory test device (100) may be modified to perform different tests on the memory (10). For example, at least a part of the memory test device (100) may be modified to test different functions of the memory (10), to test functions in different ranges of memory cells of the memory (10), to test a memory (10) that has been supplemented or replaced by reflecting previous test results, or to test a memory different from the memory (10). In this case, modifying or replacing at least a part of the memory test device (100) may require a significant amount of time and effort. Accordingly, a memory test device having a structure that is easy to reuse in accordance with changes in test conditions may be required.

[0018] FIG. 2 is a block diagram exemplarily embodying the memory test device of FIG. 1. Referring to FIG. 2, a block diagram exemplarily embodying a memory test device (100) having a structure that is easy to reuse is shown. The memory test device (100) may include a user interface (110), a processor (120), a request module (130), and a vector (140).

[0019] The user interface (110) can output a setting signal (SET) to the processor (120). The setting signal (SET) can point to the memory (10) to be tested. The user interface (110) can receive setting information from the user. The user interface (110) can generate a setting signal (SET) based on the received setting information.

[0020] The processor (120) can receive a set signal (SET) from the user interface (110). The processor (120) can output a request signal (RQ) to the request module (130). The request signal (RQ) may be a signal requesting a test operation of the memory (10). The processor (120) can receive a feedback signal (FB) from the request module (130). The feedback signal (FB) may be a signal indicating that the memory (10) has performed a test operation. That is, the processor (120) may be a module that calculates or schedules the test operation to be performed in the memory (10).

[0021] The request module (130) can receive a request signal (RQ) from the processor (120). The request module (130) can communicate with the memory (10) so that the memory (10) performs a test operation. The request module (130) can output a feedback signal (FB) to the processor (120). That is, the request module (130) may be a module that tests the memory (10) based on the request signal (RQ).

[0022] The vector (140) can record communication between the memory (10) and the request module (130). For example, the vector (140) can record information corresponding to a test operation output from the request module (130) to the memory (10). For example, if the test operation is a read command, the vector (140) can record read data corresponding to the read command output from the memory (10) to the request module (130).

[0023] The memory (10) can perform a test operation based on communication with the request module (130). For example, if the test operation is a read command, the memory (10) can output read data corresponding to the read command to the request module (130). For example, if the test operation is a write command, the memory (10) can store write data corresponding to the write command.

[0024] In an exemplary embodiment, the request module (130) may output a feedback signal (FB) to the processor (120) indicating that the memory has performed a test operation corresponding to the communication, based on communication with the memory (10). Based on the feedback signal (FB), the processor (120) may calculate information corresponding to another test operation appropriate for the memory (10) to perform next, and output another request signal (not shown) corresponding to the calculated information to the request module (130).

[0025] According to an embodiment of the present invention, a memory test device (100) may include configurations that are highly relevant to the memory (10) and configurations that are less relevant. For example, if the type or specifications of the memory (10) are changed, the request module (130) that is highly relevant to the memory (10) may require many modifications. The user interface (110), processor (120), and vector (140) that are less relevant to the memory (10) may require few modifications or may be reused without modification. Since the configurations that are less relevant can be reused for testing other memories with or without few modifications, a memory test device having a structure that is easy to reuse may be provided.

[0026] FIG. 3 is a block diagram that exemplarily embodies the user interface of FIG. 2. Referring to FIG. 3, a block diagram exemplarily embodies the user interface (110) is shown. The user interface (110) may include a setting module (111) and a graphical user interface (112). The user interface (110) may output a setting signal (SET) pointing to a memory to be tested to a processor (120).

[0027] The setting module (111) can set test conditions and generate a setting signal (SET). The setting module (111) can output the setting signal (SET) to the processor (120). In an exemplary embodiment, the setting module (111) can generate a setting signal (SET) including setting information indicating a specification according to the type of memory (10), setting information indicating a range of memory cells among a plurality of memory cells of the memory (10) on which a test operation is to be performed, and setting information indicating a format in which a vector (140) stores information corresponding to communication (e.g., an automatic test equipment dedicated file format or a simulation dedicated file format).

[0028] The graphical user interface (112) may be a module that connects the user and the setting module (111) through graphics. For example, the graphical user interface (112) may graphically represent the setting information of the setting module (111) and output it to the user. The user may refer to the graphically represented setting information to add new setting information to the setting module (111) or modify existing setting information.

[0029] FIG. 4 is a block diagram exemplarily embodying the processor of FIG. 2. Referring to FIG. 4, a block diagram exemplarily embodying the processor (120) is shown. The processor (120) may include a mode module (121), a state module (122), a gap inserter (123), an address controller (124), a request generator (125), and a request executor (126). The processor (120) may receive a set signal (SET) from a user interface (110). The processor (120) may output a request signal (RQ) to a request module (130). The processor (120) may receive a feedback signal (FB) from the request module (130).

[0030] The mode module (121) may be a module that determines the mode of the test operation. The mode of the test operation may include information specifying the test operation. For example, the mode of the test operation may indicate the size of the data corresponding to the test operation, the power consumed in memory, and the processing speed of the commands corresponding to the test operation in memory.

[0031] The state module (122) may be a module that determines the state information of the memory. The state of the memory may change after performing a test operation. The operations that can be performed by the memory may vary depending on the state. For example, if the memory is a DRAM to which the DDR4 standard applies, the memory in the Idle state may perform a refresh operation or an activation operation. The memory that has performed the activation operation may become active. The memory in the active state may perform a read operation or a write operation. At this time, the memory in the Idle state may not be able to perform a read operation without a separate activation operation.

[0032] In an exemplary embodiment, the state module (122) can determine the state of the memory based on a feedback signal (FB). For example, the state module (122) can receive a feedback signal (FB) indicating that an activation operation has been performed and determine the state of the memory to be active. The request generator (125) can generate a request signal (RQ) corresponding to a read operation based on the state determined to be active by the state module (122).

[0033] In an exemplary embodiment, the state module (122) can determine the state of the memory independently of the feedback signal (FB). For example, the memory may be in a power-off state before performing a test. The state module (122) can determine the state of the memory to be in a power-off state independently of the feedback signal (FB). The request generator (125) can generate a request signal (RQ) corresponding to a power-on operation based on the power-off state determined by the state module (122).

[0034] The gap inserter (123) can calculate the time interval between each of the commands corresponding to the test operation. For example, the test operation may include a first write command and a second write command. The gap inserter (123) can calculate the time interval between the first write command and the second write command.

[0035] The address controller (124) can determine the address of a memory cell to perform a test operation. More specifically, the memory may include a plurality of memory cells each configured to store data. The address controller (124) can determine an address pointing to the location of at least one memory cell among the plurality of memory cells of the memory to perform a test operation.

[0036] The request generator (125) can generate a request signal (RQ) based on information generated from the mode module (121), the state module (122), the gap inserter (123), and the address controller (124). More specifically, the request generator (125) can generate a request signal (RQ) based on the mode of the test operation determined by the mode module (121), the state information of the memory managed by the state module (122), the time interval between each of the commands corresponding to the test operation calculated by the gap inserter (123), and the address of the memory cell to perform the test operation determined by the address controller (124).

[0037] The request executor (126) can output the request signal (RQ) generated by the request generator (125) to the request module (130).

[0038] FIG. 5 is a block diagram exemplarily embodying the request module of FIG. 2. Referring to FIG. 5, a block diagram exemplarily embodying the request module (130) is shown. The request module (130) may include a gap module (131), an address module (132), a command table (133), an action module (134), and protocol information. The protocol information may be information representing a communication protocol used for communication between the request module (130) and the memory (10). The request module (130) may receive a request signal (RQ) from the processor (120). The request module (130) may communicate with the memory (10) based on the request signal (RQ). The request module (130) may output a feedback signal (FB) to the processor (120) based on communication with the memory (10).

[0039] The gap module (131) can store the calculated time interval between each of the commands corresponding to the test operation based on the request signal (RQ). The address module (132) can store the determined address of at least one memory cell among the plurality of memory cells of the memory (10) to perform the test operation based on the request signal (RQ).

[0040] The command table (133) can store commands for memory according to standard specifications applied to the memory (10). The commands stored in the command table (133) may include commands corresponding to test operations. For example, the command table (133) can store commands performed in memory such as calibration, refresh, precharge, activate, write, and read.

[0041] The action module (134) can generate data corresponding to a test action based on a request signal (RQ). For example, the action module (134) can generate data corresponding to a test action based on the size information of the data included in the request signal (RQ).

[0042] In an exemplary embodiment, the action module (134) can communicate with the memory (10) to perform a test operation based on the time interval stored in the gap module (131), the address stored in the address module (132), commands corresponding to the test operation stored in the command table (133), protocol information, and data generated by the action module (134).

[0043] The action module (134) may include a DQ action module, a DQS action module, and a DM action module. The DQ action module may generate a data signal corresponding to a test action. The DQS action module may generate a data strobe signal that controls the transmission of the data signal. The DM action module may generate a data mask signal that masks the data signal. The action module (134) may output data corresponding to a test action to the memory (10) based on the data signal, the data strobe signal, and the data mask signal.

[0044] According to an embodiment of the present invention, the request module (130) may be a configuration highly related to the memory (10). When the type or specifications of the memory (10) are changed, the request module (130) may require many modifications. At this time, since the request module (130) has sub-configurations clearly distinguished according to function, such as the gap module (131), address module (132), command table (133), action module (134), and protocol information, modifications according to changes in test conditions may be easy.

[0045] FIG. 6 is a block diagram that exemplarily embodies the vector of FIG. 2. Referring to FIG. 6, a block diagram exemplarily embodies the vector (140) is shown. The vector (140) may include a container (141) and a file generator (142). The vector (140) may record communication between the request module (130) and the memory (10).

[0046] The container (141) can record communication between the request module (130) and the memory (10). For example, it can record data corresponding to a request for a test operation output from the request module (130) to the memory (10). Alternatively, it can record read data corresponding to a read command output from the memory (10) to the request module (130).

[0047] The file generator (142) can generate a file corresponding to the communication recorded in the container (141) according to the format. For example, the file generator (142) can generate a file corresponding to the communication recorded in the container (141) in a simulation-only file format (SIM). Alternatively, the file generator (142) can generate a file corresponding to the communication recorded in the container (141) in an automatic test equipment-only file format (ATE).

[0048] In an exemplary embodiment, the file generator (142) can be connected to a user interface (e.g., the user interface of FIG. 3) and can determine whether the format of the file to be generated is a simulation-only file format (SIM) or an automated test equipment-only file format (ATE) based on the format set in the user interface.

[0049] FIG. 7 is a block diagram that exemplarily embodies the memory of FIG. 2. Referring to FIG. 7, a block diagram exemplarily embodies the memory (10) is shown. The memory (10) may include a memory cell array (11), an ECC (Error Correcting Code) module (12), and a test device interface (13). The memory (10) may perform a test operation based on communication with a request module (130).

[0050] The memory cell array (11) may include a plurality of memory cells (MC). Each of the plurality of memory cells (MC) may be configured to perform at least a part of a test operation based on communication with the request module (130). For example, a memory cell (MC) may store write data according to a write command corresponding to the test operation. Alternatively, a memory cell (MC) may output read data according to a read command corresponding to the test operation.

[0051] The ECC module (12) can correct errors that occur based on at least part of the test operation performed in the memory cell array (11). For example, if the command corresponding to the test operation is a write command, the ECC module (12) can output error-corrected encoded write data to the memory cell array (11). If the command corresponding to the test operation is a read command, the ECC module (12) can perform error-corrected decoding on the read data received from the memory cell array (11).

[0052] The test device interface (13) can be connected to the request module (130). The test device interface (13) may include protocol information used for communication with the request module (130). The test device interface (13) can be connected to a plurality of memory cells (MC) of the memory cell array (11) through the ECC module (12).

[0053] According to an embodiment of the present invention, the memory (10) may include a configuration that changes according to a change in test conditions and a configuration that does not change (or has a small portion that changes). For example, if the type of memory (10) changes, the protocol information changes, so the test device interface (13) may be required to be supplemented with new protocol information. On the other hand, the memory cell array (11) and the ECC module (12) may be reused when testing a memory of the same capacity of a different type.

[0054] FIG. 8 is a flowchart showing the operation method of a memory test device according to an embodiment of the present invention. Referring to FIG. 8, the operation method of a memory test device according to an embodiment of the present invention is illustrated. In step S110, the memory test device can set test conditions. For example, the memory test device can set specifications according to the type of memory to be tested, a range of memory cells among a plurality of memory cells of the memory for which a test operation is to be performed, and a format for storing information corresponding to communication between the memory test device and the memory.

[0055] In step S121, the memory test device may calculate information corresponding to a test operation to be performed in a memory that meets the test conditions set in step S111, and generate a request signal including the calculated information. In an exemplary embodiment, the information corresponding to the test operation may include a mode of the test operation, memory state information, a time interval between each of the commands corresponding to the test operation, and the address of the memory cell to be performed on the test operation.

[0056] In step S122, the memory test device can communicate with the memory to have the memory perform a test operation based on the request signal generated in step S121.

[0057] In step S131, the memory test device may record communication with the memory. For example, the memory test device may record data corresponding to a request for a test operation output to the memory. In an exemplary embodiment, step S131 may be performed in parallel with step S122.

[0058] In step S132, the memory test device may generate a feedback signal based on the communication in step S122. The feedback signal may be a signal indicating that the memory has performed a test operation.

[0059] FIG. 9 is a flowchart illustrating an exemplary method of operation of a memory test device according to an embodiment of the present invention. Referring to FIG. 9, an exemplary method of operation of a memory test device according to an embodiment of the present invention is illustrated. In step S210, the memory test device can set test conditions.

[0060] In step S220, the memory test device may calculate information corresponding to the first test operation and generate a first request signal including the calculated information. Based on the first request signal, the memory test device may perform first communication with the memory so that the memory performs the first test operation.

[0061] In step S230, the memory test device can record a first communication and generate a first feedback signal indicating that the memory has performed a first test operation based on the first communication.

[0062] In step S240, the memory test device may calculate information corresponding to a second test operation based on a first feedback signal and generate a second request signal including the calculated information. Based on the second request signal, the memory test device may perform second communication with the memory so that the memory performs a second test operation.

[0063] In an exemplary embodiment, the memory test device can calculate information corresponding to a second test operation based on the state of the memory that has performed a first test operation. For example, the memory to be tested may perform a first operation in a first state and become a second state. The memory may perform a second operation in a second state. The memory test device can perform a first communication to cause the memory to perform the first operation. Based on the first communication, the memory test device can change the state information of the memory from the first state to the second state and prepare a second communication for the second operation to be performed in the memory.

[0064] In step S250, the memory test device can record the second communication and generate a second feedback signal indicating that the memory has performed a second test operation based on the second communication.

[0065] As described above, with reference to FIGS. 2 through 7, the structure of a memory test device according to an embodiment of the present invention is illustrated. In an exemplary embodiment, at least a portion of the memory test device may be implemented in software. As the components of the memory test device are classified by function, a memory test device with improved readability of source code expressed in software may be provided.

[0066] In an exemplary embodiment, the configurations of the memory test device may be implemented based on Unified Modeling Language (UML). When the memory to be tested changes, the memory test device may be supplemented through forward-engineering, which modifies the source code through modifications at the modeling level, or through reverse-engineering, which modifies the modeling through modifications at the source code level, while maintaining the structure of the memory test device and the sub-configurations of the memory test device illustrated in FIGS. 2 to 7.

[0067] The above description describes specific embodiments for implementing the present invention. The present invention will include not only the embodiments described above, but also embodiments that can be simply modified or easily modified. Furthermore, the present invention will include technologies that can be easily modified and implemented using the embodiments. Accordingly, the scope of the present invention should not be limited to the embodiments described above, but should be defined by the claims set forth below as well as equivalents to the claims of this invention.

Claims

Claim 1 A user interface configured to output a setting signal pointing to a memory to be tested; a processor configured to activate the memory in response to the state information of the memory indicating an idle state, calculate first information corresponding to a first operation to be performed on the activated memory based on the setting signal, and output a first request signal including the calculated first information; a request module configured to perform first communication with the memory based on the first request signal so that the memory performs the first operation; and a vector configured to record the first communication between the memory and the request module, wherein the memory is a Dynamic Random Access Memory (DRAM); and the request module includes: an action module that performs the first communication with the DRAM; and a command table that stores a plurality of commands corresponding to calibration, refresh, precharge, activation, write, and read, and the action module includes: a DQ action module configured to generate a data signal corresponding to the first operation; and a DQS action module configured to generate a data strobe signal that controls the transmission of the data signal. A memory test device comprising a DM action module configured to generate a data mask signal that masks the data signal. Claim 2 A memory test device according to claim 1, wherein the request module is further configured to output a first feedback signal to the processor indicating that the memory has performed the first operation based on the first communication, and the processor is further configured to calculate second information corresponding to a second operation to be performed in the memory based on the first feedback signal, and to output a second request signal including the calculated second information to the request module. Claim 3 In claim 2, the request module is further configured to perform second communication with the memory based on the second request signal so that the memory performs the second operation, and the vector is further configured to record the second communication between the memory and the request module. Claim 4 A memory test device according to claim 1, wherein the user interface comprises: a setting module configured to generate a setting signal including: first setting information indicating a specification of the memory; second setting information indicating a range of memory cells among a plurality of memory cells of the memory to which the first operation is to be performed; and third setting information indicating a format in which the vector stores information corresponding to the first communication; and a graphical user interface configured to graphically display the first to third setting information of the setting module. Claim 5 In claim 1, the request module is further configured to output a first feedback signal to the processor indicating that the memory has performed the first operation based on the first communication, and the processor comprises: a mode module configured to determine the mode of the first operation, which indicates the size of data corresponding to the first operation, power consumed in the memory, and the processing speed of commands corresponding to the first operation in the memory; a state module configured to determine the state information of the memory; a gap inserter configured to calculate the time interval between each of the commands corresponding to the first operation; an address controller configured to determine the address of at least one memory cell among a plurality of memory cells of the memory to perform the first operation; and a request generator configured to generate the first request signal based on the first information. A memory test device comprising a request executor configured to output the generated first request signal to the request module, wherein the first information includes the determined mode of the first operation, the determined state information, the calculated time interval between each of the commands corresponding to the first operation, and the determined address of the at least one memory cell to perform the first operation. Claim 6 In claim 5, the request module comprises: a gap module configured to store the calculated time interval between each of the commands corresponding to the first operation based on the first request signal; an address module configured to store the determined address of at least one memory cell to perform the first operation based on the first request signal; and a memory test device further comprising protocol information used for the first communication. Claim 7 delete Claim 8 In claim 1, the vector comprises: a container configured to record the first communication; and a file generator configured to generate a file corresponding to the first communication recorded in the container in a first format or a second format, a memory test device. Claim 9 In claim 1, the memory comprises: a plurality of memory cells each configured to perform at least a portion of the first operation based on the first communication; an ECC (Error Correcting Code) module configured to correct an error that occurs based on the at least portion of the first operation performed; and a memory test device comprising a test device interface connected to the plurality of memory cells through the ECC module, the test device including protocol information used in the first communication. Claim 10 A method of operation of a memory test device comprising: a step of setting test conditions; a step of activating a DRAM (Dynamic Random Access Memory) in response to state information of the DRAM corresponding to the test conditions indicating an idle state; a step of calculating information corresponding to an operation to be performed on the activated DRAM by referring to a command table and generating a request signal including the calculated information, wherein the request signal includes a data signal corresponding to the operation to be performed, a data strobe signal controlling the transmission of the data signal, and a data mask signal masking the data signal, and the command table stores a plurality of commands corresponding to calibration, refresh, precharge, activation, write, and read; a step of communicating with the DRAM so that the DRAM performs the operation based on the request signal; and a step of recording the communication.

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