Display device

Abstract

A display device according to one embodiment comprises a substrate including a first display area, a second display area, and a non-display area; a plurality of first signal wires extending in a first direction and disposed in the first display area; a plurality of second signal wires extending from the non-display area in the first direction and disposed in the second display area; a plurality of connecting wires each connected to the plurality of first signal wires and extending to the non-display area via the first display area and the second display area; and a test circuit portion disposed in the non-display area, wherein at least some of the plurality of connecting wires and at least some of the plurality of second signal wires are electrically connected to the test circuit portion.

Description

Technology Field

[0001] The present disclosure relates to a display device, and more specifically, to a display device capable of identifying defects across an entire display area. Background Technology

[0002] A display device is a device that displays images and includes display panels such as light-emitting display panels or liquid crystal display panels. A light-emitting diode display (OLED display) is a type of self-emissive display device. A light-emitting display includes a light-emitting layer interposed between an anode and a cathode. When the two electrodes each inject electrons and holes into the light-emitting layer, excitons are generated through the combination of electrons and holes, and light is emitted as these excitons fall from the excited state to the ground state.

[0003] Meanwhile, a display device using a Chip on Plastic (COP) or Chip on Glass (COG) method, which directly attaches a Driving Integrated Circuit to a substrate, includes a chip mounting area where the Driving Integrated Circuit is bonded. The chip mounting area may include a plurality of output pads formed to be electrically connected to the output bumps of the Driving Integrated Circuit and a plurality of input pads formed to be electrically connected to the input bumps of the Driving Integrated Circuit to supply signals from the outside to the Driving Integrated Circuit.

[0004] In addition, the driving integrated circuit can perform a defect inspection of pixels according to the manufacturing process of the display panel of the display device. The defect inspection of pixels is performed by applying a test signal to the display panel without mounting the driving integrated circuit in the chip mounting area, thereby checking the resistance, capacitance, or driving status of the display panel. The problem to be solved

[0005] The embodiments are intended to provide a display device that checks for defects across the entire display area. means of solving the problem

[0006] A display device according to one embodiment comprises a substrate including a first display area, a second display area, and a non-display area; a plurality of first signal wires extending in a first direction and disposed in the first display area; a plurality of second signal wires extending from the non-display area in the first direction and disposed in the second display area; a plurality of connecting wires each connected to the plurality of first signal wires and extending to the non-display area via the first display area and the second display area; and a test circuit portion disposed in the non-display area, wherein at least some of the plurality of connecting wires and at least some of the plurality of second signal wires are electrically connected to the test circuit portion.

[0007] The plurality of first signal wires includes a first-1 sub-signal wire connected to a first pixel emitting a first color, a first-2 sub-signal wire connected to a second pixel emitting a second color, and a first-3 sub-signal wire connected to a third pixel emitting a third color, and the plurality of second signal wires include a second-1 sub-signal wire connected to a first pixel emitting a first color, a second-2 sub-signal wire connected to a second pixel emitting a second color, and a second-3 sub-signal wire connected to a third pixel emitting a third color, wherein in the first display area, a first signal wire unit having the first-1 sub-signal wire, the first-2 sub-signal wire, the first-3 sub-signal wire, and the first-2 sub-signal wire is repeatedly arranged, and in the second display area, a second signal wire unit having the second-1 sub-signal wire, the second-2 sub-signal wire, the second-3 sub-signal wire, and the second-2 sub-signal wire is repeatedly arranged. It is possible.

[0008] A sub-signal wiring of any one of the first signal wiring units and a sub-signal wiring of any one of the second signal wiring units can be connected to the test circuit.

[0009] One of the first-2 sub-signal wirings included in the first signal wiring unit and one of the second-2 sub-signal wirings included in the second signal wiring unit can be connected to the test circuit.

[0010] The first-1 sub-signal wiring of the first signal wiring unit and the second-1 sub-signal wiring of the second signal wiring unit can be connected to the test circuit.

[0011] The first-third sub-signal wiring of the first signal wiring unit and the second-third sub-signal wiring of the second signal wiring unit can be connected to the test circuit.

[0012] The two first-2 sub-signal wires included in the first signal wiring unit and the two second-2 sub-signal wires included in the second signal wiring unit can be connected to the test circuit.

[0013] The first-1 sub-signal wiring and the first-3 sub-signal wiring included in the first signal wiring unit, and the second-1 sub-signal wiring and the second-3 sub-signal wiring included in the second signal wiring unit can be connected to the test circuit.

[0014] Any one of the plurality of sub-signal wires included in at least two of the first signal wiring units and any one of the plurality of sub-signal wires included in at least two of the second signal wiring units may be connected to the test circuit.

[0015] The above multiple connecting wires may have different lengths.

[0016] The plurality of connecting wires mentioned above may be spaced apart from each other within the first display area and the second display area and may not intersect each other.

[0017] Each of the plurality of connection wires includes a first sub-connection wire extending along a second direction perpendicular to the first direction, and a second sub-connection wire extending along the first direction and connected to the first sub-connection wire, and the first sub-connection wire may overlap with the plurality of second signal wires.

[0018] A display device according to one embodiment comprises a substrate including a first display area, a second display area, a third display area, and a non-display area; a plurality of first signal wires extending in a first direction and disposed in the first display area; a plurality of second signal wires extending from the non-display area in the first direction and disposed in the second display area; a plurality of third signal wires extending from the non-display area in the first direction and disposed in the third display area; a plurality of connection wires each connected to the plurality of first signal wires and extending to the non-display area via the first display area and the second display area; and a test circuit portion disposed in the non-display area, wherein at least some of the plurality of connection wires, at least some of the plurality of second signal wires, and at least some of the plurality of third signal wires may be electrically connected to the test circuit portion.

[0019] The above plurality of connecting wires may overlap with the first display area and the second display area, and be spaced apart from the third display area.

[0020] The plurality of first signal lines include a first-1 sub-signal line connected to a first pixel emitting a first color, a first-2 sub-signal line connected to a second pixel emitting a second color, and a first-3 sub-signal line connected to a third pixel emitting a third color; the plurality of second signal lines include a second-1 sub-signal line connected to a first pixel emitting a first color, a second-2 sub-signal line connected to a second pixel emitting a second color, and a second-3 sub-signal line connected to a third pixel emitting a third color; the plurality of third signal lines include a third-1 sub-signal line connected to a first pixel emitting a first color, a third-2 sub-signal line connected to a second pixel emitting a second color, and a third-3 sub-signal line connected to a third pixel emitting a third color; and in the first display area, the first-1 sub-signal line, the first-2 sub-signal line, the first-3 sub-signal line, and the first-2 sub- A first signal wiring unit having signal wiring arranged thereon may be repeatedly arranged, and in the second display area, a second signal wiring unit having the second-1 sub-signal wiring, the second-2 sub-signal wiring, the second-3 sub-signal wiring, and the second-2 sub-signal wiring arranged thereon may be repeatedly arranged, and in the third display area, a third signal wiring unit having the third-1 sub-signal wiring, the third-2 sub-signal wiring, the third-3 sub-signal wiring, and the third-2 sub-signal wiring arranged thereon may be repeatedly arranged.

[0021] A sub-signal wiring of any one of the first signal wiring units, a sub-signal wiring of any one of the second signal wiring units, and a sub-signal wiring of any one of the third signal wiring units can be connected to the test circuit.

[0022] Multiple pixels electrically connected to the above test circuit can emit light of the same color.

[0023] Two first-2 sub-signal wires included in the first signal wiring unit, two second-2 sub-signal wires included in the second signal wiring unit, and two third-2 sub-signal wires included in the third signal wiring unit can be connected to the test circuit.

[0024] The first-1 sub-signal wiring and the first-3 sub-signal wiring included in the first signal wiring unit, the second-1 sub-signal wiring and the second-3 sub-signal wiring included in the second signal wiring unit, and the third-1 sub-signal wiring and the third-3 sub-signal wiring included in the third signal wiring unit can be connected to the test circuit.

[0025] Any one of the plurality of sub-signal wires included in at least two of the first signal wiring units, any one of the plurality of sub-signal wires included in at least two of the second signal wiring units, and any one of the plurality of sub-signal wires included in at least two of the third signal wiring units may be connected to the test circuit. Effects of the invention

[0026] According to the embodiments, a display device can be provided that performs a defect inspection across the entire display area. Brief explanation of the drawing

[0027] FIG. 1 is a schematic plan view of a display device according to one embodiment. Figure 2 is a schematic diagram showing the chip mounting area in Figure 1. Figure 3 is a diagram distinguishing areas according to the arrangement of signal wiring. Figures 4 to 11 are drawings showing signal wiring arranged in a display area and a non-display area, respectively. FIG. 12 is a diagram distinguishing regions according to the arrangement of signal wiring within a display device according to one embodiment. Figures 13 to 15 are schematic diagrams illustrating the arrangement of signal wiring placed in a display area and a non-display area. Specific details for implementing the invention

[0028] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0029] To clearly explain the present invention, parts unrelated to the explanation have been omitted, and the same reference numerals are used for identical or similar components throughout the specification.

[0030] Furthermore, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and thus the present invention is not necessarily limited to what is illustrated. Thicknesses have been enlarged in the drawings to clearly represent various layers and regions. Additionally, for convenience of explanation, the thickness of some layers and regions has been exaggerated in the drawings.

[0031] Furthermore, when a part such as a layer, membrane, region, or plate is said to be "on" or "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in between. Also, being "on" or "on" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "on" in the direction opposite to gravity.

[0032] Furthermore, throughout the specification, when a part is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0033] Additionally, throughout the specification, "planar" means when the subject part is viewed from above, and "cross-sectional" means when the cross-section obtained by vertically cutting the subject part is viewed from the side.

[0034] Hereinafter, a display device according to one embodiment will be described with reference to FIGS. 1 to 3. FIG. 1 is a schematic plan view of a display device according to one embodiment, FIG. 2 is a schematic drawing showing a chip mounting area in FIG. 1, and FIG. 3 is a drawing distinguishing display areas according to the arrangement of signal wiring.

[0035] Referring to FIG. 1, the display device may include a display area (DA) and a non-display area (PA), and the non-display area (PA) may be defined along the border of the display area (DA).

[0036] Multiple pixels (PX) may be arranged within a display area (DA). Each pixel (PX) includes a light-emitting element and a pixel circuit connected thereto. Each pixel (PX) emits, for example, red, green, blue, or white light, and may include, as an example, an organic light-emitting diode.

[0037] The display device may include a plurality of signal lines and a pad portion. The plurality of signal lines may include a scan line (SL) extended in a second direction (DR2), a data line (DL) extended in a first direction (DR1), and a driving voltage line (PL), etc.

[0038] The scan drive unit (20) is located on the left and right sides of the display area (DA) and generates and transmits a scan signal to each pixel (PX) through a scan line (SL). A pixel (PX) can receive scan signals together from two scan drive units (20) located on the left and right sides.

[0039] A plurality of terminals (P1, P2, P3) may be located at one end of the substrate (SUB) that overlaps with the non-display area (PA). The plurality of terminals (P1, P2, P3) may be exposed without being covered by an insulating layer and may be electrically connected to a flexible printed circuit board (not shown).

[0040] The first terminal (P1) can transmit a driving voltage (ELVDD) to the driving voltage supply wiring (60). The second terminal (P2) can receive a vertical synchronization signal, a horizontal synchronization signal, and / or a clock signal, and transmit a control signal to control the driving of the scan drive unit (20). Additionally, the third terminal (P3) can transmit a common voltage (ELVSS) to each of the common voltage supply wirings (70).

[0041] The driving voltage supply wiring (60) is positioned on the non-display area (PA). For example, the driving voltage supply wiring (60) may be positioned between the chip mounting area (ICA) and the display area (DA). The driving voltage supply wiring (60) provides a driving voltage (ELVDD) to the pixels (PX). The driving voltage supply wiring (60) is positioned in a second direction (DR2) and may be connected to a plurality of driving voltage lines (PL) extending in a first direction (DR1).

[0042] The common voltage supply wiring (70) is placed on the non-display area (PA). The common voltage supply wiring (70) may have a shape that surrounds the substrate (SUB). The common voltage supply wiring (70) delivers a common voltage (ELVSS) to one electrode (e.g., cathode) of the light-emitting element containing the pixel (PX).

[0043] A non-display area (PA) according to one embodiment may include a chip mounting area (ICA) to which a driving integrated circuit is bonded. The chip mounting area (ICA) may have a driving integrated circuit mounted thereon for driving a plurality of data lines (DL) to display an image on a plurality of pixels (PX). Although the present specification has illustrated and described a chip mounting area (ICA) electrically connected to the data lines (DL), it is not limited thereto, and the driving integrated circuit may be provided to overlap with all of the first to third terminals (P1, P2, P3).

[0044] A driving integrated circuit (not shown) can be mounted in a chip mounting area (ICA) after a test process for multiple pixels (PX). This driving integrated circuit converts digital input data input from a flexible circuit board attached to a substrate (SUB) into an analog data signal and supplies the converted data signal to multiple data lines (DL).

[0045] As shown in FIG. 2, an input pad portion (IP) and an output pad portion (OP) on which a driving integrated circuit is mounted can be formed in the chip mounting area (ICA).

[0046] Referring to FIG. 1 and FIG. 2, the chip mounting area (ICA) may include an output pad section (OP), an input pad section (IP), and a test circuit section (TP). The chip mounting area (ICA) may further include a probe pad (PP) located on the outer edge. The probe pad (PP) can supply various test signals provided during the test process to the test circuit section (TP) through a test signal line.

[0047] The driving integrated circuit can be mounted in the chip mounting area (ICA) after the test process. Although not illustrated, the driving integrated circuit may include a plurality of input bumps and a plurality of output bumps.

[0048] The input pad section (IP) may include a plurality of input pads electrically connected to a plurality of input bumps formed on the driving integrated circuit. The output pad section (OP) may be electrically connected to a plurality of output bumps formed on the driving integrated circuit. The output pad section (OP) may be electrically connected to a plurality of data lines (DL) formed on the display area (DA).

[0049] The test circuit section (TP) may include a plurality of transistors. The plurality of transistors may be electrically connected to at least some of the plurality of data lines (DL) formed in the display area (DA). The plurality of data lines (DL) connected to the test circuit section (TP) will be described in more detail with reference to FIG. 4 and below.

[0050] Meanwhile, although not illustrated in this specification, a bending portion may be located between the chip mounting area (ICA) and the display area (DA). When the non-display area (PA) is bent, the substrate (SUB) may be bent relative to the bending portion, and a part of the substrate (SUB) may be located on the back surface of the substrate (SUB).

[0051] Hereinafter, the display area (DA) will be examined in more detail with reference to FIG. 3. Referring to FIG. 3, the display area (DA) may include a first display area (DAa) and a second display area (DAb). Based on the center of the display area (DA), the second display area (DAb) may be located in the middle of the display area (DA), and the first display area (DAa) may be located on both sides of the second display area (DAb). The width of the second display area (DAb) and the width of the first display area (DAa) may be substantially the same, but are not limited thereto. Depending on the embodiment, the width of the first display area (DAa) and the width of the second display area (DAb) may differ.

[0052] The first display area (DAa) may include a plurality of first signal wirings, and the second display area (DAb) may include a plurality of second signal wirings. This will be explained below with reference to FIG. 4.

[0053] Below, we will examine the signal wiring arranged in the display area and non-display area in more detail with reference to FIG. 4. FIG. 4 is a diagram showing the signal wiring arranged in the display area and non-display area.

[0054] Referring to FIG. 4, a plurality of pixels (PX) may be arranged along a first direction (DR1) and a second direction (DR2) in a first display area (DAa) and a second display area (DAb). According to one embodiment, based on the n-th row, a first pixel (PX1), a second pixel (PX2), a third pixel (PX3), and a second pixel (PX2) may be repeatedly arranged along the second direction (DR2). Additionally, in the n+1-th row, a third pixel (PX3), a second pixel (PX2), a first pixel (PX1), and a second pixel (PX2) may be repeatedly arranged. The first pixel (PX1) is a pixel that emits a first color, the second pixel (PX2) is a pixel that emits a second color, and the third pixel (PX3) is a pixel that emits a third color. The first color may be red, the second color may be green, and the third color may be blue.

[0055] A plurality of first signal wires (DLa) extending along a first direction (DR1) may be arranged in a first display area (DAa). A plurality of first signal wires (DLa) may be arranged along a second direction (DR2).

[0056] A plurality of first signal wires (DLa) may include a first-1 sub-signal wire (DLa-1) connected to a first pixel (PX1) emitting a first color based on the n-th row, a first-2 sub-signal wire (DLa-2) connected to a second pixel (PX2) emitting a second color, and a first-3 sub-signal wire (DLa-3) connected to a third pixel (PX3) emitting a third color.

[0057] In the first display area (DAa), the first-1 sub-signal wiring (DLa-1), the first-2 sub-signal wiring (DLa-2), the first-3 sub-signal wiring (DLa-3), and the first-2 sub-signal wiring (DLa-2) may be repeatedly arranged. The first-1 sub-signal wiring (DLa-1), the first-2 sub-signal wiring (DLa-2), the first-3 sub-signal wiring (DLa-3), and the first-2 sub-signal wiring (DLa-2) may form a single first signal wiring unit (SU1). A plurality of first signal wiring units (SU1) may be repeatedly arranged in the first display area (DAa).

[0058] A plurality of second signal wires (DLb) extending along the first direction (DR1) may be arranged in the second display area (DAb). A plurality of second signal wires (DLb) may be arranged along the second direction (DR2).

[0059] A plurality of second signal wires (DLb) may include a second-1 sub-signal wire (DLb-1) connected to a first pixel (PX1) emitting a first color based on the n-th row, a second-2 sub-signal wire (DLb-2) connected to a second pixel (PX2) emitting a second color, and a second-3 sub-signal wire (DLb-3) connected to a third pixel (PX3) emitting a third color.

[0060] In the second display area (DAb), the second-1 sub-signal wiring (DLb-1), the second-2 sub-signal wiring (DLb-2), the second-3 sub-signal wiring (DLb-3), and the second-2 sub-signal wiring (DLb-2) may be repeatedly arranged. The second-1 sub-signal wiring (DLb-1), the second-2 sub-signal wiring (DLb-2), the second-3 sub-signal wiring (DLb-3), and the second-2 sub-signal wiring (DLb-2) may form a single second signal wiring unit (SU2). A plurality of second signal wiring units (SU2) may be repeatedly arranged in the second display area (DAb).

[0061] Additionally, according to one embodiment, a connecting wire (CL) may be disposed in the first display area (DAa) and the second display area (DAb). The connecting wire (CL) may extend from the second display area (DAb) to the first display area (DAa).

[0062] According to one embodiment, a first signal wire (DLa) may be connected to a connection wire (CL). The connection wire (CL) may include a first sub-connection wire (CLa) extending along a second direction (DR2), and a second sub-connection wire (CLb) connected to the first sub-connection wire (CLa) and extending along a first direction (DR1). The first sub-connection wire (CLa) may cross a first display area (DAa) and a second display area (DAb). The first sub-connection wire (CLa) may overlap with the first signal wire (DLa) and the second signal wire (DLb). The first sub-connection wire (CLa) may overlap with the first signal wire (DLa) and the second signal wire (DLb) while being insulated from signal wires that are not electrically connected. The second sub-connection wire (CLb) may be located in the second display area (DAb) and may not overlap with other signal wires.

[0063] More specifically, the connecting wire (CL) may include a first connecting wire (CL1) connected to a first-1 sub-signal wire (DLa-1), a second connecting wire (CL2) connected to a first-2 sub-signal wire (DLa-2), and a third connecting wire (CL3) connected to a first-3 sub-signal wire (DLa-3).

[0064] The first connecting wire (CL1) may include a first-1 sub-connecting wire (CLa1) connected to a first-1 sub-signal wire (DLa-1) and a first-2 sub-connecting wire (CLb1) connected to the first-1 sub-connecting wire (CLa1). The second connecting wire (CL2) may include a second-1 sub-connecting wire (CLa2) connected to a first-2 sub-signal wire (DLa-2) and a second-2 sub-connecting wire (CLb2) connected to the second-1 sub-connecting wire (CLa2). The third connecting wire (CL3) may include a third-1 sub-connecting wire (CLa3) connected to a first-3 sub-signal wire (DLa-3) and a third-2 sub-connecting wire (CLb3) connected to the third-1 sub-connecting wire (CLa3).

[0065] Multiple connecting wires (CL) may have different lengths from each other. The first connecting wire (CL1), the second connecting wire (CL2), and the third connecting wire (CL3) may have different lengths from each other. Additionally, multiple first connecting wires (CL1) may have different lengths from each other, multiple second connecting wires (CL2) may have different lengths from each other, and multiple third connecting wires (CL3) may have different lengths from each other.

[0066] Multiple connecting wires (CL) may be spaced apart from each other and may not overlap. Multiple connecting wires (CL) may be spaced apart from each other within the first display area (DAa) and the second display area (DAb) and may not overlap each other.

[0067] Based on FIG. 4, in the non-display area (PA), the second signal wiring (DLb) and the connection wiring (CL) may be arranged alternately. Based on the left side, the second-1 sub-signal wiring (DLb-1), the second connection wiring (CL2), the second-2 sub-signal wiring (DLb-2), the third connection wiring (CL3), the second-3 sub-signal wiring (DLb-3), the second connection wiring (CL2), the second-2 sub-signal wiring (DLb-2), and the first connection wiring (CL1) may be arranged repeatedly.

[0068] An output pad section (OP), a test circuit section (TP), and an input pad section (IP) may be located in the non-display area (PA). The output pad section (OP) and the input pad section (IP) may be electrically connected to the entire first signal wiring (DLa) and second signal wiring (DLb).

[0069] In a peripheral area (PA) according to one embodiment, a test circuit unit (TP) for performing an inspection of a plurality of pixels (PX) placed in a first display area (DAa) and a second display area (DAb) may be located. The test circuit unit (TP) may inspect whether there is a short circuit in the first signal wiring (DLa) and the second signal wiring (DLb). The test circuit unit (TP) may include a test gate wiring (Tg) and a test voltage wiring (Tv).

[0070] The test circuit section (TP) may include a first test transistor (T1) electrically connected to a test gate wire (Tg), a test voltage wire (Tv), at least one connection wire (CL), and a first signal wire (DLa). Additionally, the test circuit section (TP) may include a second test transistor (T2) connected to a test gate wire (Tg), a test voltage wire (Tv), and at least one second signal wire (DLb).

[0071] The test voltage wiring (Tv) may be positioned to receive a test voltage. While testing the display panel, the test voltage wiring (Tv) may receive the test voltage, and through the test voltage, it may be possible to verify whether the signal wiring connected to the test circuit (TP) is functioning normally. Conversely, while the display panel is not being tested, the test voltage wiring (Tv) may not receive the test voltage. The test voltage wiring (Tv) may be extended along a second direction (DR2). This is merely one embodiment, and the shape of the test voltage wiring (Tv) may vary depending on the design.

[0072] The test gate wiring (Tg) can be commonly connected to the gates of the first test transistor (T1) and the gates of the second test transistors (T2). The first test transistor (T1) and the second test transistor (T2) may be thin-film test transistors used to verify whether the signal wiring of the display area (DA) operates normally during the process of manufacturing the display panel. When testing the display panel, a plurality of test gate signals may be applied to the test gate wiring (Tg) to turn on the first test transistor (T1) and the second test transistor (T2).

[0073] Below, we examine the signal wires and connection wires among the multiple signal wires and connection wires that are electrically connected to the test circuit section (TP).

[0074] According to one embodiment, any one of the sub-signal wires of a first signal wiring unit (SU1) may be connected to a test circuit unit (TP). According to one embodiment, a first-second sub-signal wire (DLa-2) included in the first signal wiring unit (SU1) may be connected to a test circuit unit (TP). A second connecting wire (CL2) electrically connected to the first-second sub-signal wire (DLa-2) may be connected to a test circuit unit (TP).

[0075] Additionally, any one of the sub-signal wirings of the second signal wiring unit (SU2) may be connected to the test circuit section (TP). According to one embodiment, one second-2 sub-signal wiring (DLb-2) included in the second signal wiring unit (SU2) may be connected to the test circuit section (TP).

[0076] In the display area (DAa, DAb), one sub-signal wire for every four sub-signal wires along the second direction (DR2) can be connected to the test circuit section (TP). At this time, multiple pixels connected to the test circuit section (TP) can emit the same light, and for example, may be a second pixel (PX2) that emits light representing a second color.

[0077] According to one embodiment, the test circuit (TP) is electrically connected to signal wiring located in a first display area (DAa) and signal wiring located in a second display area (DAb), so as to test whether each signal wiring is defective. Since the test circuit (TP) according to one embodiment can test for defects across the entire display area, it is possible to provide a display device with improved reliability.

[0078] Hereinafter, a display device according to one embodiment will be described with reference to FIGS. 5 to 11. FIGS. 5, 6, 7, 8, 9, 10, and 11 are schematic diagrams showing the arrangement of signal wiring for a portion of the display area and non-display area. Descriptions of components identical to those described above will be omitted.

[0079] Referring to Fig. 5, According to one embodiment, any one of the sub-signal wires of a first signal wiring unit (SU1) may be connected to a test circuit unit (TP). According to one embodiment, a first-1 sub-signal wire (DLa-1) included in the first signal wiring unit (SU1) may be connected to a test circuit unit (TP). A first connection wire (CL1) electrically connected to the first-1 sub-signal wire (DLa-1) may be connected to a test circuit unit (TP).

[0080] Additionally, any one of the sub-signal wirings of the second signal wiring unit (SU2) may be connected to the test circuit section (TP). According to one embodiment, one second-1 sub-signal wiring (DLb-1) included in the second signal wiring unit (SU2) may be connected to the test circuit section (TP).

[0081] According to one embodiment, one sub-signal wire for every four sub-signal wires along the second direction (DR2) in the display area (DAa, DAb) may be connected to the test circuit section (TP).

[0082] Referring to the following Fig. 6, According to one embodiment, any one of the sub-signal wires of a first signal wiring unit (SU1) may be connected to a test circuit unit (TP). According to one embodiment, one first-third sub-signal wire (DLa-3) included in the first signal wiring unit (SU1) may be connected to a test circuit unit (TP). A third connection wire (CL3) electrically connected to the first-third sub-signal wire (DLa-3) may be connected to a test circuit unit (TP).

[0083] Additionally, any one of the sub-signal wirings of the second signal wiring unit (SU2) may be connected to the test circuit section (TP). According to one embodiment, one second-third sub-signal wiring (DLb-3) included in the second signal wiring unit (SU2) may be connected to the test circuit section (TP).

[0084] According to one embodiment, one sub-signal wire for every four sub-signal wires along the second direction (DR2) in the display area (DAa, DAb) may be connected to the test circuit section (TP).

[0085] Referring to the following Fig. 7,According to one embodiment, any one of the multiple sub-signal wires included in at least two first signal wiring units (SU1) may be connected to a test circuit unit (TP). According to one embodiment, one first-2 sub-signal wire (DLa-2) among eight sub-signal wires included in two first signal wiring units (SU1) may be connected to a test circuit unit (TP). A second connecting wire (CL2) connected to the first-2 sub-signal wire (DLa-2) may be connected to a test circuit unit (TP).

[0086] In addition, according to one embodiment, any one of the multiple sub-signal wires included in at least two second signal wiring units (SU2) may be connected to a test circuit unit (TP). According to one embodiment, one of the eight sub-signal wires included in two second signal wiring units (SU2) may be connected to a test circuit unit (TP).

[0087] According to the embodiment illustrated in FIG. 7, for every eight sub-signal wires arranged along the second direction (DR2) in the display area (DAa, DAb), one sub-signal wire may be connected to the test circuit section (TP). At this time, a plurality of pixels connected to the test circuit section (TP) may emit light that exhibits the same color. For example, the plurality of pixels may be a second pixel (PX2).

[0088] Referring to the following Fig. 8,According to one embodiment, any one of the multiple sub-signal wires included in at least two first signal wiring units (SU1) may be connected to a test circuit unit (TP). According to one embodiment, one of the eight sub-signal wires included in two first signal wiring units (SU1) may be connected to a test circuit unit (TP). A first connection wire (CL1) connected to the first sub-signal wire (DLa-1) may be connected to a test circuit unit (TP).

[0089] In addition, according to one embodiment, any one of the multiple sub-signal wires included in at least two second signal wiring units (SU2) may be connected to a test circuit unit (TP). According to one embodiment, one of the eight sub-signal wires included in two second signal wiring units (SU2) may be connected to a test circuit unit (TP).

[0090] According to the embodiment illustrated in FIG. 8, for every eight sub-signal wires arranged along the second direction (DR2) in the display area (DAa, DAb), one sub-signal wire can be connected to the test circuit section (TP).

[0091] Referring to the following Fig. 9, According to one embodiment, any one of the multiple sub-signal wires included in at least two first signal wiring units (SU1) may be connected to a test circuit unit (TP). According to one embodiment, one of the eight sub-signal wires included in two first signal wiring units (SU1), specifically a first-third sub-signal wire (DLa-3), may be connected to a test circuit unit (TP). A third connection wire (CL3) connected to the first-third sub-signal wire (DLa-3) may be connected to a test circuit unit (TP).

[0092] In addition, according to one embodiment, any one of the multiple sub-signal wires included in at least two second signal wiring units (SU2) may be connected to a test circuit unit (TP). According to one embodiment, one second-third sub-signal wire (DLb-3) among the eight sub-signal wires included in two second signal wiring units (SU2) may be connected to a test circuit unit (TP).

[0093] According to the embodiment illustrated in FIG. 9, for every eight sub-signal wires arranged along the second direction (DR2) in the display area (DAa, DAb), one sub-signal wire can be connected to the test circuit section (TP).

[0094] Referring to the following Fig. 10, According to one embodiment, at least two sub-signal wires of one first signal wiring unit (SU1) may be connected to a test circuit unit (TP). According to one embodiment, two first-second sub-signal wires (DLa-2) included in the first signal wiring unit (SU1) may be connected to a test circuit unit (TP). A second connecting wire (CL2) electrically connected to each of the first-second sub-signal wires (DLa-2) may be connected to a test circuit unit (TP).

[0095] In addition, at least two sub-signal wires of one second signal wiring unit (SU2) may be connected to a test circuit section (TP). According to one embodiment, two second-2 sub-signal wires (DLb-2) included in the second signal wiring unit (SU2) may be connected to a test circuit section (TP).

[0096] According to one embodiment, one sub-signal wiring for every two sub-signal wirings along the second direction (DR2) in the display area (DAa, DAb) may be connected to the test circuit section (TP). At this time, a plurality of pixels connected to the test circuit section (TP) may emit light that exhibits the same color. For example, the plurality of pixels may be a second pixel (PX2).

[0097] Referring to the following Fig. 11, According to one embodiment, at least two sub-signal wires of one first signal wiring unit (SU1) may be connected to a test circuit unit (TP). According to one embodiment, each of the first-1 sub-signal wire (DLa-1) and the first-3 sub-signal wire (DLa-3) included in the first signal wiring unit (SU1) may be connected to a test circuit unit (TP). A first connection wire (CL1) connected to the first-1 sub-signal wire (DLa-1) and a third connection wire (CL3) connected to the first-3 sub-signal wire (DLa-3) may be connected to a test circuit unit (TP).

[0098] In addition, at least two sub-signal wires of one second signal wiring unit (SU2) may be connected to a test circuit section (TP). According to one embodiment, each of the second-1 sub-signal wire (DLb-1) and the second-3 sub-signal wire (DLb-3) included in the second signal wiring unit (SU2) may be connected to a test circuit section (TP).

[0099] According to one embodiment, one sub-signal wiring for each of the two sub-signal wirings along the second direction (DR2) can be connected to the test circuit section (TP).

[0100] Hereinafter, a display device according to one embodiment will be examined with reference to FIGS. 12 and FIGS. 13. FIGS. 12 is a schematic plan view of a display device according to one embodiment, in which areas are distinguished according to the arrangement of wiring, and FIGS. 13 is a schematic diagram showing the arrangement of signal wiring placed in a display area and a non-display area. Descriptions of components identical to those described above will be omitted.

[0101] Referring to FIG. 12, the display area (DA) may include a first display area (DAa), a second display area (DAb), and a third display area (DAc). Based on the center of the display area (DA), the third display area (DAc) may be located in the center of the display area (DA), and the second display area (DAb) may be located on both sides of the third display area (DAc). The first display area (DAa) may be located to the right of the second display area (DAb) located on the right, and the first display area (DAa) may be located to the left of the second display area (DAb) located on the left. The widths of the first display area (DAa), the second display area (DAb), and the third display area (DAc) may vary depending on the embodiment.

[0102] As illustrated in FIG. 13, a plurality of first signal wires (DLa) and connection wires (CL) may be located in the first display area (DAa), a plurality of second signal wires (DLb) and connection wires (CL) may be located in the second display area (DAb), and a plurality of third signal wires (DLc) may be located in the third display area (DAc). This will be examined in more detail below.

[0103] In the first display area (DAa), the second display area (DAb), and the third display area (DAc), a plurality of pixels (PX) may be arranged along the first direction (DR1) and the second direction (DR2). According to one embodiment, based on the n-th row, the first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the second pixel (PX2) may be repeatedly arranged along the second direction (DR2). Additionally, in the n+1-th row, the third pixel (PX3), the second pixel (PX2), the first pixel (PX1), and the second pixel (PX2) may be repeatedly arranged. The first pixel (PX1) is a pixel that emits a first color, the second pixel (PX2) is a pixel that emits a second color, and the third pixel (PX3) is a pixel that emits a third color. The first color may be red, the second color may be green, and the third color may be blue.

[0104] A plurality of first signal wires (DLa) extending along a first direction (DR1) may be arranged in a first display area (DAa). A plurality of first signal wires (DLa) may be arranged along a second direction (DR2).

[0105] A plurality of first signal wires (DLa) may include a first-1 sub-signal wire (DLa-1) connected to a first pixel (PX1) emitting a first color based on the n-th row, a first-2 sub-signal wire (DLa-2) connected to a second pixel (PX2) emitting a second color, and a first-3 sub-signal wire (DLa-3) connected to a third pixel (PX3) emitting a third color.

[0106] A plurality of second signal wires (DLb) extending along the first direction (DR1) may be arranged in the second display area (DAb). A plurality of second signal wires (DLb) may be arranged along the second direction (DR2).

[0107] A plurality of second signal wires (DLb) may include a second-1 sub-signal wire (DLb-1) connected to a first pixel (PX1) emitting a first color based on the n-th row, a second-2 sub-signal wire (DLb-2) connected to a second pixel (PX2) emitting a second color, and a second-3 sub-signal wire (DLb-3) connected to a third pixel (PX3) emitting a third color.

[0108] Additionally, according to one embodiment, a connecting wire (CL) may be disposed in a first display area (DAa) and a second display area (DAb). The connecting wire (CL) may extend to the first display area (DAa) across the second display area (DAb). The connecting wire (CL) may extend from a non-display area (PA), pass through the second display area (DAb), and be connected to a plurality of first signal wires (DLa) disposed in the first display area (DAa). The connecting wire (CL) may overlap with the first display area (DAa) and the second display area (DAb) and be spaced apart from the third display area (DAc). The connecting wire (CL) may not overlap with the third display area (DAc).

[0109] In the third display area (DAc), a plurality of third signal wires (DLc) extending along the first direction (DR1) may be arranged. A plurality of third signal wires (DLc) may be arranged along the second direction (DR2).

[0110] A plurality of third signal wires (DLc) may include a third-1 sub-signal wire (DLc-1) connected to a first pixel (PX1) emitting a first color based on the n-th row, a third-2 sub-signal wire (DLc-2) connected to a second pixel (PX2) emitting a second color, and a third-3 sub-signal wire (DLc-3) connected to a third pixel (PX3) emitting a third color.

[0111] The 3-1 sub-signal wiring (DLc-1), the 3-2 sub-signal wiring (DLc-2), the 3-3 sub-signal wiring (DLc-3), and the 3-2 sub-signal wiring (DLc-2) can form a single 3rd signal wiring unit (SU3). Multiple 3rd signal wiring units (SU3) may be repeatedly arranged in the 3rd display area (DAc).

[0112] Below, we examine the signal wires and connection wires among the multiple signal wires and connection wires that are electrically connected to the test circuit section (TP).

[0113] According to one embodiment, any one of the sub-signal wires of a first signal wiring unit (SU1) may be connected to a test circuit unit (TP). According to one embodiment, a first-second sub-signal wire (DLa-2) included in the first signal wiring unit (SU1) may be connected to a test circuit unit (TP). A second connecting wire (CL2) electrically connected to the first-second sub-signal wire (DLa-2) may be connected to a test circuit unit (TP).

[0114] Additionally, any one of the sub-signal wirings of the second signal wiring unit (SU2) may be connected to the test circuit section (TP). According to one embodiment, one second-2 sub-signal wiring (DLb-2) included in the second signal wiring unit (SU2) may be connected to the test circuit section (TP).

[0115] Additionally, any one of the sub-signal wirings of the third signal wiring unit (SU3) may be connected to the test circuit section (TP). According to one embodiment, one third-2 sub-signal wiring (DLc-2) included in the third signal wiring unit (SU3) may be connected to the test circuit section (TP).

[0116] According to one embodiment, one sub-signal wire for every four sub-signal wires along the second direction (DR2) in the display area (DAa, DAb, DAc) may be connected to the test circuit section (TP). At this time, a plurality of pixels connected to the test circuit section (TP) may emit the same light, and, for example, may be a second pixel (PX2) that emits light representing a second color.

[0117] Although the present specification illustrates and describes an embodiment in which the first-2 sub-signal wiring (DLa-2), the second-2 sub-signal wiring (DLb-2), and the third-2 sub-signal wiring (DLc-2) connected to the second pixel (PX2) are connected to the test circuit section (TP), it is not limited thereto, and it is of course possible that the sub-signal wirings connected to the first pixel (PX1) based on the n-th row are connected to the test circuit section (TP), or the sub-signal wirings connected to the third pixel (PX3) are connected to the test circuit section (TP).

[0118] According to one embodiment, the test circuit (TP) is electrically connected to signal wiring located in a first display area (DAa), a second display area (DAb), and a third display area (DAc), so as to test whether each signal wiring is defective. Since the test circuit (TP) according to one embodiment can test for defects across the entire display area, it is possible to provide a display device with improved reliability.

[0119] Hereinafter, a display device according to one embodiment will be examined with reference to FIGS. 14 and 15. FIGS. 14 and FIGS. 15 are schematic diagrams illustrating the arrangement of signal wiring in a display area and a non-display area, respectively. Descriptions of components identical to those described above will be omitted.

[0120] Referring to FIG. 14, according to one embodiment, any one of the multiple sub-signal wires included in at least two first signal wiring units (SU1) may be connected to a test circuit unit (TP). According to one embodiment, one first-2 sub-signal wire (DLa-2) among the eight sub-signal wires included in two first signal wiring units (SU1) may be connected to a test circuit unit (TP). A second connecting wire (CL2) connected to the first-2 sub-signal wire (DLa-2) may be connected to a test circuit unit (TP).

[0121] In addition, according to one embodiment, any one of the multiple sub-signal wires included in at least two second signal wiring units (SU2) may be connected to a test circuit unit (TP). According to one embodiment, one of the eight sub-signal wires included in two second signal wiring units (SU2) may be connected to a test circuit unit (TP).

[0122] In addition, according to one embodiment, any one of the multiple sub-signal wires included in at least two third signal wiring units (SU3) may be connected to a test circuit unit (TP). According to one embodiment, one third-2 sub-signal wire (DLc-2) among the eight sub-signal wires included in two third signal wiring units (SU3) may be connected to a test circuit unit (TP).

[0123] According to the embodiment illustrated in FIG. 14, for every eight sub-signal wires arranged along the second direction (DR2) in the display area (DAa, DAb, DAc), one sub-signal wire may be connected to the test circuit section (TP). At this time, a plurality of pixels connected to the test circuit section (TP) may emit light that exhibits the same color. For example, the plurality of pixels may be a second pixel (PX2).

[0124] Although the present specification illustrates and describes an embodiment in which the first-2 sub-signal wiring (DLa-2), the second-2 sub-signal wiring (DLb-2), and the third-2 sub-signal wiring (DLc-2) connected to the second pixel (PX2) are connected to the test circuit section (TP), it is not limited thereto, and it is of course possible that the sub-signal wirings connected to the first pixel (PX1) based on the n-th row are connected to the test circuit section (TP), or the sub-signal wirings connected to the third pixel (PX3) are connected to the test circuit section (TP).

[0125] Referring to FIG. 15, according to one embodiment, at least two sub-signal wires of one first signal wiring unit (SU1) may be connected to a test circuit section (TP). According to one embodiment, two first-second sub-signal wires (DLa-2) included in the first signal wiring unit (SU1) may be connected to a test circuit section (TP). A second connecting wire (CL2) electrically connected to each of the first-second sub-signal wires (DLa-2) may be connected to a test circuit section (TP).

[0126] In addition, at least two sub-signal wires of one second signal wiring unit (SU2) may be connected to a test circuit section (TP). According to one embodiment, two second-2 sub-signal wires (DLb-2) included in the second signal wiring unit (SU2) may be connected to a test circuit section (TP).

[0127] In addition, at least two sub-signal wires of one third signal wiring unit (SU3) may be connected to a test circuit section (TP). According to one embodiment, two third-2 sub-signal wires (DLc-2) included in the third signal wiring unit (SU3) may be connected to a test circuit section (TP).

[0128] According to one embodiment, one sub-signal wiring for every two sub-signal wirings along the second direction (DR2) in the display area (DAa, DAb, DAc) may be connected to the test circuit section (TP). At this time, a plurality of pixels connected to the test circuit section (TP) may emit light that exhibits the same color. For example, the plurality of pixels may be a second pixel (PX2).

[0129] Although the present specification illustrates and describes an embodiment in which the first-2 sub-signal wiring (DLa-2), the second-2 sub-signal wiring (DLb-2), and the third-2 sub-signal wiring (DLc-2) connected to the second pixel (PX2) are connected to the test circuit section (TP), it is not limited thereto, and it is of course possible that the sub-signal wirings connected to the first pixel (PX1) based on the n-th row are connected to the test circuit section (TP), or the sub-signal wirings connected to the third pixel (PX3) are connected to the test circuit section (TP).

[0130] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention. Explanation of the symbols

[0131] DAa: First display area DAb: Second display area DAc: Third display area PA: Non-display area DLa: 1st signal wiring DLb: 2nd signal wiring DLc: Third signal wiring CL: Connection wiring TP: Test circuit section

Claims

Claim 1 A display device comprising a substrate including a first display area, a second display area adjacent to the first display area, and a non-display area; a plurality of first signal wires extending in a first direction and disposed in the first display area; a plurality of second signal wires extending from the non-display area in the first direction and disposed in the second display area; a plurality of connection wires each connected to the plurality of first signal wires and extending to the non-display area via the first display area and the second display area; and an output pad portion, a test circuit portion, and an input pad portion disposed in the non-display area, wherein at least some of the plurality of connection wires and at least some of the plurality of second signal wires are electrically connected to the test circuit portion, and the plurality of connection wires overlap with the first display area and the second display area, and the output pad portion, the test circuit portion, and the input pad portion are arranged in order along the first direction. Claim 2 In claim 1, the plurality of first signal wirings includes a first-1 sub-signal wiring connected to a first pixel emitting a first color, a first-2 sub-signal wiring connected to a second pixel emitting a second color, and a first-3 sub-signal wiring connected to a third pixel emitting a third color, and the plurality of second signal wirings includes a second-1 sub-signal wiring connected to a first pixel emitting a first color, a second-2 sub-signal wiring connected to a second pixel emitting a second color, and a second-3 sub-signal wiring connected to a third pixel emitting a third color, and in the first display area, a first signal wiring unit having the first-1 sub-signal wiring, the first-2 sub-signal wiring, the first-3 sub-signal wiring, and the first-2 sub-signal wiring is repeatedly arranged, and in the second display area, the second-1 sub-signal wiring, the second-2 sub-signal wiring, the second-3 sub-signal wiring, and the second signal wiring having the second-2 sub-signal wiring are arranged A display device in which units are repeatedly arranged. Claim 3 A display device according to paragraph 2, wherein any one of the plurality of sub-signal wires included in the first signal wiring unit and any one of the plurality of sub-signal wires included in the second signal wiring unit are connected to the test circuit. Claim 4 In paragraph 3, a display device in which one of the first-2 sub-signal wirings included in the first signal wiring unit and one of the second-2 sub-signal wirings included in the second signal wiring unit are connected to the test circuit. Claim 5 A display device in which the first-1 sub-signal wiring of the first signal wiring unit and the second-1 sub-signal wiring of the second signal wiring unit are connected to the test circuit section in paragraph 3. Claim 6 A display device in which the first-3 sub-signal wiring of the first signal wiring unit and the second-3 sub-signal wiring of the second signal wiring unit are connected to the test circuit section in paragraph 3. Claim 7 A display device in which, in paragraph 2, two first-2 sub-signal wires included in the first signal wiring unit and two second-2 sub-signal wires included in the second signal wiring unit are connected to the test circuit. Claim 8 A display device in which the first-1 sub-signal wiring and the first-3 sub-signal wiring included in the first signal wiring unit, and the second-1 sub-signal wiring and the second-3 sub-signal wiring included in the second signal wiring unit are connected to the test circuit unit. Claim 9 A display device according to paragraph 2, wherein any one of a plurality of sub-signal wires included in at least two first signal wiring units and any one of a plurality of sub-signal wires included in at least two second signal wiring units are connected to the test circuit. Claim 10 In claim 1, the plurality of connecting wires are a display device having mutually different lengths. Claim 11 In claim 10, the plurality of connecting wires are spaced apart from each other and do not intersect within the first display area and the second display area. Claim 12 In claim 10, each of the plurality of connecting wires includes a first sub-connecting wire extending along a second direction perpendicular to the first direction, and a second sub-connecting wire extending along the first direction and connected to the first sub-connecting wire, and the first sub-connecting wire overlaps with the plurality of second signal wires. Claim 13 A display device comprising a substrate including a first display area, a second display area, a third display area, and a non-display area; a plurality of first signal wires extending in a first direction and disposed in the first display area; a plurality of second signal wires extending from the non-display area in the first direction and disposed in the second display area; a plurality of third signal wires extending from the non-display area in the first direction and disposed in the third display area; a plurality of connection wires each connected to the plurality of first signal wires and extending to the non-display area via the first display area and the second display area; and a test circuit portion disposed in the non-display area, wherein at least some of the plurality of connection wires, at least some of the plurality of second signal wires, and at least some of the plurality of third signal wires are electrically connected to the test circuit portion. Claim 14 In paragraph 13, the plurality of connecting wires overlap with the first display area and the second display area, and are spaced apart from the third display area. Claim 15 In claim 13, the plurality of first signal wires comprises a first-1 sub-signal wire connected to a first pixel emitting a first color, a first-2 sub-signal wire connected to a second pixel emitting a second color, and a first-3 sub-signal wire connected to a third pixel emitting a third color; the plurality of second signal wires comprises a second-1 sub-signal wire connected to a first pixel emitting a first color, a second-2 sub-signal wire connected to a second pixel emitting a second color, and a second-3 sub-signal wire connected to a third pixel emitting a third color; the plurality of third signal wires comprises a third-1 sub-signal wire connected to a first pixel emitting a first color, a third-2 sub-signal wire connected to a second pixel emitting a second color, and a third-3 sub-signal wire connected to a third pixel emitting a third color; and in the first display area, the first-1 sub-signal wire, the first-2 sub-signal wire, the first-3 sub-signal wire, and A display device in which a first signal wiring unit having the first-2 sub-signal wiring is repeatedly arranged, in the second display area, the second-1 sub-signal wiring, the second-2 sub-signal wiring, the second-3 sub-signal wiring, and a second signal wiring unit having the second-2 sub-signal wiring are repeatedly arranged, and in the third display area, the third-1 sub-signal wiring, the third-2 sub-signal wiring, the third-3 sub-signal wiring, and a third signal wiring unit having the third-2 sub-signal wiring are repeatedly arranged. Claim 16 A display device according to claim 15, wherein a sub-signal wiring of any one of the first signal wiring units, a sub-signal wiring of any one of the second signal wiring units, and a sub-signal wiring of any one of the third signal wiring units are connected to the test circuit. Claim 17 In paragraph 16, a display device in which a plurality of pixels electrically connected to the test circuit emit light of the same color. Claim 18 A display device in which, in claim 15, two first-2 sub-signal wires included in the first signal wiring unit, two second-2 sub-signal wires included in the second signal wiring unit, and two third-2 sub-signal wires included in the third signal wiring unit are connected to the test circuit. Claim 19 A display device in which, in claim 15, the first-1 sub-signal wiring and the first-3 sub-signal wiring included in the first signal wiring unit, the second-1 sub-signal wiring and the second-3 sub-signal wiring included in the second signal wiring unit, and the third-1 sub-signal wiring and the third-3 sub-signal wiring included in the third signal wiring unit are connected to the test circuit unit. Claim 20 A display device according to claim 15, wherein any one of a plurality of sub-signal wires included in at least two first signal wiring units, any one of a plurality of sub-signal wires included in at least two second signal wiring units, and any one of a plurality of sub-signal wires included in at least two third signal wiring units are connected to the test circuit.

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