Chip integration into a host wafer cavity using lateral dielectric material bonding

Abstract

The electronic assembly includes a back capping layer, and the host wafer has a back surface bonded to the top surface of the back capping layer, excluding cavities within the wafer formed over regions of the back capping layer, and the cavities have side surfaces of the wafer. The chiplets have back surfaces directly bonded to at least a portion of regions of the top surface of the back capping layer. A lateral dielectric material between the side surfaces of the chiplets and the side surfaces of the cavities mechanically and chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.

Description

Technology Field

[0001] The present disclosure relates to a host wafer having a circuit portion and at least one chip (or chiplet) inside, as in cases where the wafer and the chip are provided separately, and which is laterally bonded to the sidewalls of at least one cavity of the wafer using a dielectric material. Background Technology

[0002] Electronic assemblies or hybrid circuits include microelectronic circuits that are manufactured separately and assembled together to form a single component that can itself be encapsulated within an electronic circuit package. Assembling separately manufactured microelectronic circuits enables, for example, testing all separately manufactured microelectronic circuits prior to assembly, which consequently enables an improved manufacturing yield of the final component. This capability is particularly important when some of the separately manufactured microelectronic circuits are difficult and / or costly to manufacture. Assembling separately manufactured microelectronic circuits also enables the combination of microelectronic circuits that utilize different materials and different material processes into a single final component. This capability can lead to higher circuit performance.

[0003] There is a need for electronic assemblies using a host wafer that possesses pre-fabricated interconnects and integrated circuits, such as passive components connected to wafer-level microelectronic active chiplets (i.e., having transistors) integrated into the wafer-through cavity of the host wafer. This need may apply, for example, to assemblies for microwave or other radio frequency (RF) integrated circuits that separate the fabrication of active circuits (e.g., the fabrication of transistors) from the fabrication of passive circuits (e.g., the fabrication of interconnects, resistors, and capacitors). Meeting this need will enable much faster fabrication of circuits at lower costs and allow active circuit technologies to be extended to circuits without burdening costs and cycle times. Brief explanation of the drawing

[0004] FIG. 1a is a schematic top view of a host wafer having cavities for integrating substrate-in-chiplets into wafer cavities of a host wafer using a lateral dielectric material. FIG. 1b is a schematic top view of chiplets for integrating substrate-in-chiplets into wafer cavities of a host wafer using a lateral dielectric material. FIG. 2 is a schematic cross-sectional view of a device in which a substrate-in-chiplet is integrated into the wafer cavities of a host wafer using a lateral dielectric material. FIGS. 3a through 3f are flowcharts illustrating a process for manufacturing a device that integrates a substrate-in-chiplet into wafer cavities of a host wafer using a lateral dielectric material. FIGS. 4a to 4c are drawings illustrating two processes for forming the device of FIG. 3c. Throughout this description, elements appearing in the drawings are assigned three- or four-digit reference designators, where two least significant digits are specific to the element and one or two most significant digits may be the drawing number where the element is first introduced or manufactured. Any element not described with the drawings may be presumed to have the same characteristics and functions as a previously described or subsequently described element having the same reference designator. Specific details for implementing the invention

[0005] Description of the device

[0006] The following describes improved wafers, dies, chips, and their manufacturing techniques for electronic assemblies that integrate in-substrate chips (e.g., chiplets) into wafer cavities of a host wafer using lateral dielectric materials. The host wafer may have pre-fabricated interconnects and integrated circuits, such as passive components connected to chiplet-level microelectronic transistor chips integrated into the wafer's through-wafer cavity. This allows for the formation of assemblies for integrated circuit devices in which the chips contain active circuits from at least one semiconductor technology and the wafer contains passive (or active) circuits from another semiconductor technology (often a cheaper and larger-scale technology). Using a low-cost, large-diameter integration platform for chips containing active devices enables much faster manufacturing of assembled circuits at a larger scale and lower cost.

[0007] An electronic assembled circuit can integrate one type of component onto a carrier wafer having a different type of component. An electronic assembled circuit can integrate chiplets containing high-performance integrated circuits, such as Gallium Nitride (GaN) radio frequency (RF) integrated circuits (ICs), into host wafers containing other integrated circuits, such as silicon-based integrated circuits, in a manner that is inexpensive, has high manufacturing yield, and short manufacturing cycles. High-performance RF ICs, chips (or chiplets), may have III-V type transistors or other types of transistors and passive components, and can be integrated into the host wafer along with resistors, inductors, capacitors, and matching networks, as well as active devices from other semiconductor technologies. For example, RF ICs may be a type of semiconductor technology that is integrated along with resistors, inductors, capacitors, matching networks, and active devices from other semiconductor technologies that are part of the host wafer. A chiplet may be a chip comprising the circuits, materials, and / or devices mentioned above in this paragraph. A chiplet may also be a chip or small chip having active microelectronic (i.e., transistor) devices, CMOS devices, microwave IC devices, and / or radio frequency (RF) IC devices. A chiplet may also be a chip or small chip having SAW, BAW, or other acoustic wave devices. A chiplet may have a footprint or top surface area of ​​less than half, 1 / 3, 1 / 5, or 1 / 5 of a computer processor chip (e.g., 8086, P3, P4, etc.).

[0008] FIG. 1a is a schematic top view (100) of a host wafer (110) having cavities (120) for incorporating substrate-in-chilets into wafer cavities (120) of a host wafer (110) using a lateral dielectric material. The host wafer (110) has a rear surface (112) and a front surface (114) as shown in FIG. 2. The host wafer (110) and / or each cavity (120) has lateral surfaces (116), such as vertical or sidewall surfaces between the rear surface (112) and the front surface (114). There may be three, four, or more lateral surfaces (116). Typically, there are four lateral surfaces.

[0009] The wafer (110) may be or may include silicon, silicon germanium, silicon on insulator, gallium arsenide, indium phosphide, aluminum nitride, diamond, silicon carbide, quartz, or alumina (e.g., as a mixture of materials or as layers of materials). If the wafer includes only interconnects and passive components, it may be a dielectric such as glass, quartz, alumina, or other ceramics. The host wafer (110) may have layers of one or more of these materials in the form of oxide materials, crystalline materials, polycrystalline materials, and / or amorphous materials. The wafer (110) may include at least one of resistors, capacitors, inductors, through-substrate vias, dielectric layers, and metal layers (e.g., signal traces or signal planes). The wafer (110) may include at least one layer of silicon, silicon carbide (SiC), quartz, or other semiconductor wafer materials.

[0010] The wafer (110) may include regions to be diced into integrated circuits, each integrated circuit having passive integrated components (e.g., signal traces, interconnects and conductive vias, resistors, inductors and / or capacitors), a single transistor and / or multiple transistors. Silicon is an advantageous choice for the wafer (110) because silicon is less expensive than other materials; and / or utilizes known microelectronic manufacturing processes and scaling and manufacturing capabilities.

[0011] FIG. 1b is a schematic top view (102) of chiplets (130) for incorporating substrate-in-chiplets into wafer cavities (120) of a host wafer (110) using a lateral dielectric material. The chiplets (130) have a front surface (132) (e.g., a front surface) and a back surface (134) (e.g., a back surface) as shown in FIG. 2. Each chiplet (130) has lateral surfaces (136), such as vertical or sidewall surfaces between the front surface (132) and the back surface (134). There may be three, four, or more lateral surfaces (136). Sometimes, there are four lateral surfaces. The number of lateral surfaces (136) of each chiplet (130) may be equal to the number of surfaces (116).

[0012] The chiplets (130) may be or include silicon, silicon germanium, silicon-on-insulator, gallium arsenide, indium phosphide, aluminum nitride, quartz, alumina, gallium nitride, silicon carbide (e.g., as a mixture of materials or as layers of materials). The chiplets (130) may have layers of one or more of these materials in the form of oxide materials, crystalline materials, polycrystalline materials, and / or amorphous materials. There may be different types of chiplets (130) or electrical components manufactured separately from each other. The chiplets (130) may include GaN, InP, or GaAs or any other electrical component known in the industry and may be manufactured on a substrate such as Si, SiGe, InP, GaAs, SiC, alumina, or diamond, or any other substrate known in the industry.

[0013] The chiplets (130) or types of chiplets (130) may include RF switches, transmit and / or receive circuits; power switches, amplifiers, and circuits such as those using GaAs, InP, GaN; and / or transistors such as Si CMOS transistors. These may have electrical components that are smaller and more expensive than the wafer (110). There may be hundreds, thousands, or hundreds of thousands of chiplets (130) embedded in a single wafer (110). The wafer (110) may have more passive components, cheaper components, and routing (e.g., traces, conductive vias, and interconnections) than the chiplets (130). The wafer (110) may be manufactured using microelectronic manufacturing technologies or processes different from those used to manufacture the chiplets (130).

[0014] The chiplets (130) and the wafer (110) may be made of different materials. For example, the wafer (110) may be a silicon wafer, whereas the chiplets (130) may be type III nitride material component chips. Each of the chiplets (130) may be passive integrated components (e.g., signal traces, interconnects and conductive vias, resistors, inductors and / or capacitors), a single transistor and / or multiple transistors, or may include them.

[0015] Each of the chiplets (130) includes at least one of interconnects and transistor circuits for contacting pads on the front surface (132) of the chiplets (130). The chiplets (130) may be high-quality pre-manufactured active device chiplets that are integrated into the wafer (110) via pick-and-place assembly on a temporary wafer having an adhesive laminate or simply on an adhesive laminate (340) (see FIG. 3b).

[0016] FIG. 2 is a schematic cross-sectional view of a device (200) in which a substrate-in-chiplet (130) is integrated into wafer cavities (120) of a host wafer (110) using a lateral dielectric material (360). The device (200) may include the devices of FIG. 1a and FIG. 1b.

[0017] The device (200) may be an electronic assembly having a rear capping layer (370) having a top surface (372) and a rear surface (374). The device (200) has a host wafer (110) having a rear surface (112) and a front surface (114), wherein the rear surface (112) of the wafer is bonded to the top surface (372) of the rear capping layer (370), except for cavities (120) within the wafer (110) formed on a plurality of regions (376) of the top surface (372). The cavities may extend from the rear surface (112) through the wafer to the front surface (114). The cavities have side surfaces (116). The rear surface (112) of the wafer may be directly attached to and touch the top surface (372). The bond between the rear surface (112) and the top surface (372) may be a covalent bond, a chemical bond, or an atomic bond.

[0018] The chiplets (130) or a plurality of chips have a back surface (134) and a front surface (132), wherein the back surfaces (134) of the chiplets (130) are directly bonded to at least a portion (378) of a plurality of regions (376) of the top surface (372) of the back capping layer. The portion (378) may be a footprint of the chiplet (130) on the top surface (372) within the cavity (120). The gap (350) between the side surfaces (116 and 136) may be the difference between the region (376) and the portion (378). The back surface (134) is directly attached to and may touch the top surface (372). The bond between the back surface (134) and the top surface (372) may be a covalent bond, a chemical bond, or an atomic bond.

[0019] The cavities (120) may be substrate-through holes or substrate-through holes etched into the wafer in regions (376). Chiplets (130) may be embedded within the wafer (110) in the substrate holes or in the cavities (120).

[0020] The lateral dielectric material (360) extends between the lateral surfaces (136) of the chiplets (130) and the lateral surfaces (116) of the wafer or cavity. The lateral dielectric material (360) can mechanically and chemically bond the lateral surfaces (136) of the chiplets (130) to the lateral surfaces (116) of the wafer. The lateral dielectric material (360) can form mechanical and / or chemical bonds to the lateral surfaces (136) and to the lateral surfaces (116). In some cases, the lateral dielectric material (360) is a molded material, and the bond is a mechanical and chemical bond.

[0021] The dielectric material (360) is not a metal and is an electrical insulator. The dielectric material (360) may be a material that is not conductive, is not a semiconductor, is plastic, is not an alloy, or is a biomaterial, or may include such. The material (360) may be an epoxy. It may be an epoxy having silica particles. It may be an epoxy having SiO2 particles.

[0022] The material (360) may have dielectric properties such that charges do not flow through the material when placed in an electric field. The charges are shifted slightly from their average balanced positions, which causes dielectric polarization that causes positive charges to flow in the direction of the magnetic field and negative charges to shift in the opposite direction of the magnetic field. This phenomenon generates an internal electric field, which consequently reduces the overall electric field within the dielectric material.

[0023] In some cases, the material (360) may not have a current flowing through it when a voltage is applied. However, certain changes occur at the atomic scale. When a voltage is applied across a dielectric material, it becomes polarized. Since atoms consist of positively charged nuclei and negatively charged electrons, polarization is the effect of shifting the electrons slightly toward the positive voltage. They do not move far enough to generate a current flow through the material—the shift is subtle but has a very significant effect. When the voltage source is removed from the material, the material returns to its original non-polarized state, or remains in a polarized state if the molecular bonding within the material is weak. Dielectric materials can be insulators but can be easily polarized.

[0024] In some cases, the dielectric material (360) has a thermal expansion coefficient between or equal to the thermal expansion coefficient of the wafer (110) and the thermal expansion coefficient of the chiplets (130).

[0025] A lateral dielectric material (360) is disposed in the gaps (350) between the lateral surface (136) of each chiplet (130) and the lateral surface (116) of the corresponding wafer cavity disposed in each chiplet (130). The gap (350) has a width (gw) between 1 / 5 and 10 times the thickness (tw) of the wafer (110) or the chiplets (130).

[0026] The wafer thickness (tw) may be between 20 and 200 microns. The thickness may be between 50 and 125 μm. The thickness may be 75 μm. The thickness of one, many, or all of the chiplets may be the same as the wafer thickness.

[0027] The thickness of the back capping layer may be between 3 and 300 microns. The thickness may be between 5 and 100 microns. The thickness may be between 10 and 50 microns. The thickness may be 15 μm.

[0028] Each chiplet (130) has between three and six sides. Chiplets may have four sides. The sides may have a straight, curved, or wavy profile when viewed from the top. Cavities (120) may have the same number of sides as the sides of the chiplets (130) and sides corresponding to their shapes.

[0029] The back capping layer (370) may be a high-thermal-conductivity back metallized layer, which improves heat transfer from the chiplets (130) to the wafer (110). The layer (370) may be a thermal plane that improves heat conduction away from the chiplets by increasing heat conduction from the chiplets (130) to the layer (370) and / or the wafer (110). The layer (370) may be a material in direct contact with the chiplets (130) to increase heat conduction between the material of the chiplets (130) and the material of the layer (370). In some cases, the back capping layer (370) has a thermal expansion coefficient between or equal to the thermal expansion coefficient of the wafer (110) and the thermal expansion coefficient of the chiplets (130).

[0030] The interconnects (510) may be formed directly on the lateral dielectric material (360) and may connect the electrical (e.g., power, ground, and / or signal) contacts (138) of the chiplets (130) to the contacts (118) of the wafer (110). The interconnects (510) may include direct interconnect routing or traces formed directly on the lateral dielectric material (e.g., without any dielectric / air gap) and extending from the chiplets to the wafer electrical routing. The interconnect routing may include low-loss, high-performance DC, RF, and mm-wave routing from the chiplets (130) directly above the lateral dielectric material to the wafer electrical routing. The interconnects (510) may be directly on the material (360) by being bonded to and / or directly attached thereto (e.g., touching) the top surface of the lateral dielectric material (360).

[0031] In some cases, the wafer (110) comprises an electronic integrated circuit (not shown), at least one integrated circuit contact (118) (e.g., a contact pad) formed on a front wafer surface (114), and at least one wafer-through-cavity (120) having a side surface (116) that combines a rear surface (112) with the front surface (114). In some cases, a chiplet (130) is held in the wafer-through-cavity (120) by a lateral dielectric material (360) that attaches at least one side surface (116) of the wafer-through-cavity (120) to at least one side surface (136) of the chiplet (130). In some cases, the lateral dielectric material (360) fills the gap (350) of the cavity and thus attaches most of the lateral surfaces (136) of the chiplet (130) to the lateral surface (116) of the wafer-through cavity (120); however, the material (360) does not attach the back surface (134) of the chiplet (130) to the top surface (372) of the layer (370).

[0032] A passivation layer (not shown) may be arranged over most of the front surface (114) of the wafer (110). Conductive vias (e.g., TWVs) arranged through the passivation layer connect active and / or passive circuits of the wafer (110) to contacts (118) (e.g., contact pads) on the front surface (114). The wafer (110) may be a silicon wafer or a substrate, which enables the utilization of known production processes and manufacturability for large wafer diameters.

[0033] The wafer (110) may contain any integrated circuit (active or passive) made by a selected manufacturing process; for example, a CMOS manufacturing process. In some cases, the thickness of one or more integrated circuit layers may be only a part of the thickness (tw) of the wafer (110), for example (for example, between 1 / 10 and 1 / 1000 of the thickness of the wafer (110); for example, 50 nm if the wafer is 50 μm thick). In some cases, the thickness of the wafer (110) may be reduced after manufacturing the integrated circuits of the wafer and, for example, before etching the wafer-through cavity (120) or after filling the gap (350) with a lateral dielectric material (360).

[0034] The chiplet (130) may include one or more transistors (not shown) whose terminals are connected to at least one integrated circuit contact (138) (e.g., contact pad) by, for example, conductive vias (not shown). The chiplet (130) may include a substrate and integrated circuit layers formed on the top of the substrate, the thickness of which is, for example, only a part of the thickness of the substrate (e.g., between 1 / 10 and 1 / 1000 of the thickness of the substrate). In some cases, the total thickness of the chiplet (130) is smaller than the total thickness of the host wafer (110). In some cases, the lateral dielectric material (360) contacts the lateral surface (136) of the chiplet (130) along most of its height (starting near the top surface of the chiplet (130) and covering at least 50% of the height). Preferably, the lateral dielectric material (360) essentially contacts all of the lateral surfaces (136) of the chiplet (130). Preferably, the lateral dielectric material (360) completely fills the gap (350) up to a level essentially equal in height to the front surface (114) of the maximum host wafer (110).

[0035] In some cases, the measuring dielectric material (360) holds the chiplet (130) so that the chiplet front (132) is at the same height as the front surface (114). "At the same height" can be understood to mean that the two surfaces are in the same plane or have a small or negligible height difference relative to each other. The two surfaces may be at the same height due to a process (see FIG. 3a through 3f) in which the material (360) permanently attaches the chiplet (130) to the side surfaces (116) through the wafer through cavity (120) while, for example, both the chiplet front (132) and the front surface (114) are temporarily attached to the adhesive laminate (340), according to a process as illustrated herein. The front surface (132) and the front surface (114) may be at the same height due to polishing or CMP of these surfaces, for example, after removing the temporary adhesive laminate (340).

[0036] In some cases, the layer (370) has a continuous flat surface and a constant thickness (te), for example, when both the back surfaces (112) of the chiplets and the back surface (134) of the wafer are at the same vertical plane level. In other cases, the layer (370) has a non-flat surface and a non-constant thickness, for example, when the back surfaces (112) of the chiplets and / or the back surface (134) of the wafer have varying heights and are not flat. In one case, the thickness of the layer (370) varies between the chiplets and the wafer, having a specific thickness for the wafer and a different thickness for one or more chips. In other words, some of the wafer and chiplets have different thicknesses. In this case, some of the chiplets may have thicknesses different from other chiplets.

[0037] A host wafer (110) can be diced vertically along the perimeter (386) of the wafer around at least one chiplet in order to form a chip having at least one chiplet and an area of ​​the wafer surrounding at least one chiplet, in dicing lines (shown as vertical bars in FIG. 2).

[0038] Explanation of methods

[0039] FIGS. 3a through 3f are flowcharts illustrating the process of steps (301-306) for manufacturing a device (200) that integrates a substrate-in-chiplet into wafer cavities of a host wafer using a lateral dielectric material. The process may form the device (200) using the devices of FIGS. 1a and 2b. The process begins with the device (311) and ends with the device (200). The process may be a method for forming or assembling an electronic assembly or device. The process may be a lateral chiplet dielectric bonding process. The flowcharts of FIGS. 3a through 3f illustrate only the major process steps. Various conventional process steps (e.g., surface preparation, chemical mechanical processing (CMP), cleaning, inspection, deposition, photolithography, baking, annealing, monitoring, testing, etc.) may be performed before, between, after, or during the steps illustrated in FIGS. 3a through 3f.

[0040] FIG. 3a illustrates a step (301) for forming a device (311) comprising a host wafer (110) bonded to an adhesive laminate (340). The step (301) includes forming cavities (120) penetrating the host wafer (110) having a rear surface (112) and a front surface (114), wherein the cavities have side surfaces (116). The step of forming the cavities (120) may include etching substrate-through holes in the rear surface (112) of the wafer.

[0041] Then, step (301) includes the step of bonding the front surface (114) of the wafer to the top surface (342) of the adhesive laminate (340) having the top surface (342) and the bottom surface (344) so ​​that the cavities (120) are placed over a plurality of regions (376) of the top surface (342) of the adhesive laminate. The bonding step in step (301) may include the step of directly attaching the front surface (114) of the wafer to the top surface (342) so that the front surface (114) is bonded to and touches the top surface (342), excluding the cavities (120) or regions (376). The bond between the front surface (114) and the top surface (342) may be a covalent bond, a chemical bond, or an atomic bond. In some cases, the cavities (120) may be formed after the wafer (110) is bonded to the laminate (340).

[0042] The laminate (340) may include at least one of an adhesive, an epoxy, a sacrificial layer on a wafer, a water-soluble adhesive, a solvent-soluble adhesive, a UV-release adhesive, or a heat-release adhesive.

[0043] Step (301) may include the step of placing a host wafer (110) having substrate-through holes (120) to form a device (311), for example, on a laminate (340) or stacking a laminate (340) on the surface of the wafer (110). The holes (120) may have at least one side (e.g., may be circular) and up to an infinite number of sides, but preferably may have four sides. The wafer thickness (tw) may be 10 to 2,000 microns, but preferably may be 75 μm.

[0044] FIG. 3b illustrates a step (302) for forming a device (312) comprising chiplets (130) bonded to an upper surface (342) within cavities (120). The step (302) may include bonding the front surface (132) of a plurality of chiplets (130) having a rear surface (134) and a front surface (132) to a portion (378) of a plurality of regions (376) of the upper surface (342) of an adhesive laminate (340). The bonding step in step (302) may include directly attaching the front surfaces (132) of the chiplets (130) to portions (378) of the regions (376) so that the front surface (132) is bonded to and touches the upper surface (342) within the cavities (120). The bond between the front surface (132) and the top surface (342) can be a covalent bond, a chemical bond, or an atomic bond.

[0045] The chiplets (130) typically have four sides, but may have sides between zero and an infinite number of sides, and these sides are then flipped over onto an adhesive laminate material (340) to align with the substrate-through holes (120) of the device (311) and bonded into the holes (e.g., flip-chip bonding). The chiplets (130) may have a thickness (tw) equal to the thickness (tw) of the wafer (110), or be thicker or thinner than this.

[0046] The joining step in step (302) may include the step of pick-and-place assembling a high-end pre-manufactured chiplet (130) into cavities (120) of the top surface (342) of the adhesive laminate (340).

[0047] Each chiplet (130) may include at least one of interconnects to an active device circuit and contact pads on the front surface of the chiplet. Each chiplet (130) may be a pre-manufactured transistor chiplet.

[0048] FIG. 3c illustrates a step (303) for forming a device (313) comprising a lateral dielectric material (360) molded between a wafer (110) and chiplets (130) within cavities (120). The step (303) may include molding the lateral dielectric material (360) between the lateral surfaces (236) of the chiplets (130) and the lateral surfaces (116) of the wafer (110) within cavities (120). The lateral dielectric material (360) may mechanically and chemically bond the lateral surfaces (136) of the chiplets (130) to the lateral surfaces (116) of the wafer. The lateral dielectric material (360) may fill the gaps (150) between the chiplets (130) and the wafer (110). The lateral dielectric material (360) can completely fill the gap width (gw) and thickness (tw) of the gaps (150).

[0049] The molding step in step (303) may include the step of directly attaching the material (360) to the side surfaces (136) of the chiplets (130), the top surface (342) of the adhesive (340), and the side surfaces (116) of the wafer (110) so that the material (360) touches the side surfaces (136), the top surface (342), and the side surfaces (116). The bond between the material (360), the side surfaces (136), the top surface (342), and the side surfaces (116) may be a covalent bond, a chemical bond, or an atomic bond. It may be an adhesive bond formed by forming pressure of the material (360) into the gaps (350).

[0050] Step (303) may involve performing a lateral chip bonding process to bond the chiplets (130) to the wafer (110) of the device (312) (e.g., see FIG. 4a through 4c for details). The aspect ratio, as defined by the ratio of the thickness (tw) of the wafer (or chip) to the width (gw) of the gap (150) (e.g., the minimum distance between the vertical side of the chip (236) and the side of the through-hole (116)), may be about 100:1, but typically will be 10:1. In some cases, the thickness (tw) is 1000 μm and the width (gw) is 10 μm.

[0051] FIGS. 4a and 4b are flowcharts illustrating two processes for the step (303) of forming the device (313) of FIG. 3, also illustrated in FIG. 4c. The processes of FIGS. 4a and 4b can form the device (313) by molding a lateral dielectric material (360) into the gaps (350). The flowcharts of FIGS. 4a through 4c illustrate only the major process steps. Various conventional process steps (e.g., surface preparation, chemical mechanical processing (CMP), cleaning, inspection, deposition, photolithography, baking, annealing, monitoring, testing, etc.) may be performed before, between, after, or during the steps illustrated in FIGS. 4a through 4c.

[0052] FIG. 4a illustrates a step (401) for forming a device (411) comprising a bump (480) of a lateral dielectric material (360) printed on the back surface (134) of a chiplet or the back surface (112) of a wafer. The step (401) may include using a printing process to print the bump (480) of the lateral dielectric material (360) into the gap (350) between the side surfaces (116) of the wafer (110) and the side surfaces (136) of the chiplets using a permanent screen, such as using a wafer having a cavity as a screen to be printed by a printer.

[0053] Step (401) may include a screen-printing process, where 484 may be a squeegee that spreads balls (480) of the bonding material over surfaces (134 and 112) and into gaps (350) as shown in FIG. 4c. Thus, FIG. 4a is a step of the process prior to FIG. 4c in which the bumps (480) of the adhesive are no longer present.

[0054] Step (401) may include the step of using a printer (482) having a printhead (484) that prints bumps (480) of the material (360) on the rear surface and within the gaps (350).

[0055] FIG. 4b includes a step (402) for forming a device (412) comprising a bump (480) of a lateral dielectric material (360) that is pressed onto the back surface (134) of the device (411). The step (402) may include using a molding process to mold the bump (480) of the lateral dielectric material (360) into the gap (350) between the side surfaces (116) of the wafer (110) and the side surfaces (136) of the chiplets using vacuum and pressure. The molding step may be performed using a liquid compression molding technique such as liquid composite molding (LCM).

[0056] The printing step in 401 and / or the molding step in 402 may use a squeegee or a squeegee process to print bumps (480) into gaps (350) or to mold bumps (480).

[0057] After step (401) or step (402), FIG. 4c illustrates step (403) for forming the device (313) of FIG. 3c. Step (401) or step (402) may include the step of mechanically and chemically bonding bumps (480) between the side surfaces (236) of chiplets (130) and the side surfaces (116) of the wafer (110) within cavities (120) to form a lateral dielectric material (360). Step (403) may include the step of heating and / or curing the molding of step (401) or step (402).

[0058] After step (303), FIG. 3d illustrates a step (304) for forming a device (314) comprising a back capping (370) that encapsulates the back surface (134) of the chiplets, the back surface (112) of the wafer (110), and the top surface of the lateral dielectric material (360). Step (304) may include encapsulating the back surface (134), the back surface (112), and the top surface of the lateral dielectric material (360) into a back capping layer (370) having a top surface (372) and a back surface (374) such that regions of the cavities (120) are placed over regions (376) of the top surface (372) of the back capping layer (370). As illustrated, the portions (376) and regions (378) may be aligned vertically with respect to the laminate (340) and the layer (370).

[0059] The encapsulation step in step (304) may include the step of directly attaching the upper surfaces of the rear surface (134), rear surface (112), and lateral dielectric material (360) to the rear capping layer (370) so that the layer (370) touches the upper surfaces of the rear surface (134), rear surface (112), and lateral dielectric material (360). The encapsulation step in step (304) may include the step of embedding chiplets (130) in the wafer (110) in holes or cavities (120).

[0060] The encapsulation step in step (304) may include encapsulating the reconfigured wafer / panel device (313) in a metal version of a layer (370) acting as a thermal plane having a thickness (te) of about 5-25 microns, and bringing it into direct contact with the back surface (134) and front surface (114) of the chips (130) and wafer (110).

[0061] The back capping layer (370) may be a high-thermal-conductivity back metallized layer, which improves heat transfer from the chiplets, for example, to the wafers. This may form a "thermal plane" for conducting heat away from the chiplets. The back capping layer (370) may have a thermal expansion coefficient greater than the thermal expansion coefficients of the wafers and chiplets. The back capping layer (370) may have a thermal expansion coefficient between the thermal expansion coefficient of the wafer and the thermal expansion coefficient of the chiplets.

[0062] FIG. 3e illustrates a step (305) of forming a device (315) that does not include an adhesive laminate (340) but includes a layer (370) on the chiplets (130), on the wafer (110), and on the lateral dielectric material (360). FIG. 3e illustrates a device (314) that is inverted and does not have the laminate (340), and the step (305) may include a step of removing or separating the adhesive laminate (340) from the surfaces of the chiplets (130), the wafer (110), and the lateral dielectric material (360) using a bath, liquid, and / or heat. The step (305) may be removing the adhesive laminate (340) from the device (314).

[0063] Then, since the chiplet (130) is attached inside the cavity (120) by the material (360), the chiplet (130) is maintained inside the cavity (120) at a position relative to the wafer (110) when attached to the laminate (340).

[0064] The chiplets (130) and the exposed bottom surfaces of the wafer may be polished, for example, by chemical mechanical polishing (CMP) after the laminate (340) is removed. In other cases, they are not polished. The exposed surfaces (132) may be surfaces having electrical components, which are subsequently interconnected with conductors (510) added in FIG. 3f. In some cases, the chiplets (130) may be arranged such that the surface manufactured as a side surface is aligned and maintained parallel to the front surface of the wafer (110). This capability may be used to increase the number of component chiplets (130) embedded in the wafer (110), and / or when the side surface of the chiplet (130) maintained parallel to the front surface of the wafer (110) has a specific function. This may be, for example, when the chiplet (130) is a semiconductor laser chip and its side surface is a laser-emitting side.

[0065] FIG. 3f illustrates a step (306) for forming a device (316) comprising interconnects (510) that connect the contact portions (118) of chiplets to the contact portions (138) of a wafer. The step (306) may include forming the interconnects (510) directly on a lateral dielectric material (360) and connecting the contact portions of the chiplets to the contact portions of the wafer. The interconnects (510) may be formed by electroplating a pattern of interconnects (510) through a photoresist and then dissolving the photoresist. The interconnects (510) may be formed by attaching a mask over the pattern of interconnects (510) and etching non-patterned portions of a conductive material, such as metal.

[0066] Advantageously, interconnects (510) can be formed on contacts of chiplets (130) or wafers (110) without the cost, processing, or material height of using solder or contact bumps.

[0067] The step of forming in step (306) may include the step of directly attaching the interconnects (510) to the material (360) so that the interconnects (510) touch the top surface of the material (360). The step of forming in step (306) may include the step of forming routes or traces of the interconnects (510) directly from the contact portions (138) of the chiplets (130) directly onto the lateral dielectric material (360) (e.g., coupled thereto, directly attached thereto, touching thereto, and / or having no air gap between the interconnect and the dielectric), and directly to the wafer electrical routing or contact portions (118).

[0068] A host wafer (110) can be diced vertically along the perimeter (386) of the wafer around at least one chiplet in order to form a chip having at least one chiplet and an area of ​​the wafer surrounding at least one chiplet at dicing lines (shown as vertical bars in FIG. 3).

[0069] FIGS. 2 and 3f may illustrate a method in which an interconnect structure (510) is placed directly on top of a dielectric bonding material (360) between chiplets (130) and a wafer (110).

[0070] Advantageously, the use of the lateral mechanical-chemical chiplet bonding and / or dielectric (360) in step (303) is: (1) inexpensive by using materials such as the dielectric (360) and the low-cost processes of step (303); and (2) volume expansion is possible by making it possible to easily change the size and number of chiplets (130), for example. Advantageously, the use of the lateral mechanical-chemical chiplet bonding and / or dielectric (360) in step (303) mitigates the thermal expansion coefficient mismatch between the silicon wafer frame (110) and the chiplets (130) by the dielectric (360), for example, having a thermal expansion coefficient close to or between the wafer (110) and the chiplets (130). Advantageously, step (303) lateral mechanical-chemical chiplet coupling and / or the use of a dielectric (360) enables: (1) direct interconnect routing from the chiplets (130) to the wafer (110) electrical routing (e.g., without a dielectric / air gap); and (2) low-loss high-performance DC, RF, and mm-wave signal transmission between the chiplets (130) and the wafer (110) electrical routing, wherein (1) and (2) may use interconnects (510) between contacts of the wafer (110) and the chiplets (130) that can be formed on the surface of the dielectric (360).

[0071] Advantageously, the use of the lateral mechanical-chemical chiplet coupling and / or dielectric (360) in step (303) reduces noise and frequency variations in the interconnect routing from the chiplets (130) to the wafer (110) electrical routing compared to using a semiconductor or conductive material instead of the dielectric (360). Advantageously, the use of the lateral mechanical-chemical chiplet coupling and / or dielectric (360) in step (303) reduces the capacitance of high-frequency signals and has lower signal loss in the interconnect routing from the chiplets (130) to the wafer (110) electrical routing compared to using a semiconductor or conductive material instead of the dielectric (360). Advantageously, the use of the lateral mechanical-chemical chiplet bonding and / or dielectric (360) in step (303) reduces the cost of materials and processing for forming the lateral bonding material between the chiplets (130) and the wafer (110) compared to using a semiconductor or conductive material instead of the dielectric (360).

[0072] In addition to these advantages, the lateral mechanical-chemical dielectric bonding process is enhanced by the use of a back capping layer (370) and / or the advantages of steps (304-304) providing: a layer (370) that may be a "thermal plane" for the device (200) from the chiplets (130) and high-thermal-conductivity back metallization (370) of the reconfigured wafer (314 or 200) to improve heat transfer to the wafer (110).

[0073] According to the process (301-306), multiple electronic assemblies may be manufactured simultaneously, in which case multiple component chiplets (130) are provided and attached to multiple predetermined locations (e.g., regions (378)) on the laminate (340). The chiplets (130) may actually comprise multiple identical or distinct component chips, each of which has its front surface (132) temporarily attached to predetermined locations on the top surface (342). In some cases, the various component chips may have different thicknesses subject to the constraint that they are not thicker than the wafer (110).

[0074] The chiplets (130) are preferably pre-tested to verify their functionality. As a result, the yield of the final device (200) or the diced devices is significantly improved compared to the integration of component chips where the functionality of the component chips is not verified until after integration.

[0075] Embedding a chiplet (130) (including a single chip or multiple component chips, etc.) in a cavity (120) filled with a dielectric (360) enables a desirable increase in the dissipation of any chip-generated heat into the wafer (110) during use of the chiplet. The increased dissipation significantly advantageously limits any change in the size of the chiplet due to temperature changes and enables any mechanical deformation resulting from such size changes to be advantageously maintained at an appropriate level. Another advantage is that the dielectric (360) can be resilient and flexible to better absorb size changes. This heat dissipation is improved by connecting the bottom of the chiplet (130) to a metal back capping layer (370), such as a metal plate, formed on a portion of the bottom surface of the wafer (110). As illustrated in FIG. 3, a metal back capping layer (370) (e.g., gold) can be formed on the bottom of the chiplet (130) and the wafer (110). Doing this improves the thermal conductivity and interface between the chiplet (130), the material (360), and the wafer (110), thereby further increasing the desirable discharge of any chip-generated heat from the chiplet to the layer (370) during use of the chiplet.

[0076] Advantageously, by making it possible for different electrical components of the chiplets (130) to be manufactured separately from each other and from the wafer (110), all of these electronic components of the chiplets (130) and the wafer (110) can be tested separately before assembling them. If one of the components of a specific electrical component chiplet (130) or the wafer (110) has a poor manufacturing yield, it is possible to spend time and money separately to improve the manufacturing yield of the electrical component separately in order to produce a finished product device (200) or its die having the chiplets (130) together in the cavities of the wafer (110). For example, if the electrical components of a specific type of chiplet (130) have a poor manufacturing yield, it is possible to separately spend time and money to improve the manufacturing yield of the electrical component chiplet type without spending time and money to improve the components of other types of chiplets (130) or wafers (110) in order to produce a finished product device (200) or a die thereof having chiplets (130) and wafers (110).

[0077] Additionally, since the embodiments enable different electrical components of the chiplets (130) to be manufactured separately from each other and from the wafer (110), all component types of the chiplets (130) and the wafer (110) do not need to be exposed to manufacturing steps of all different electrical components of the chiplets (130) that could potentially damage other chiplets (130) or damage the wafer (110).

[0078] Accordingly, the embodiments can reduce manufacturing costs by using smaller component chips in chiplets (130) made of new, expensive materials having more general features, combined with integrated circuits of wafers (110) and / or other chiplets (130) made of cheaper general materials having more general features.

[0079] According to the embodiments, the chiplets (130) may include GaN, InP, or GaAs electrical components and may be fabricated on a substrate such as Si, SiGe, InP, GaAs, alumina, or diamond. In some cases, the electrical components or integrated circuits of the host wafer (110) may include metal routing and passive components fabricated at the wafer scale. In some cases, the interconnections (510) may be made using conductors made of thin films, thick-plated interconnects, multilayers, etc. The interconnections may be made, for example, using back-end steps of the manufacturing process.

[0080] Examples

[0081] Examples of the technology described herein include an electronic assembly, the electronic assembly comprising: a back capping layer having a top surface and a back surface; a wafer having a front surface and a back surface—the back surface of the wafer is bonded to the top surface of the back capping layer except for cavities within the wafer formed over a plurality of regions of the top surface of the back capping layer, the cavities having side surfaces—; a plurality of chiplets having a back surface and a front surface—the back surfaces of the chiplets are directly bonded to at least a portion of the plurality of regions of the top surface of the back capping layer—; a lateral dielectric material between the side surfaces of the chiplets and the side surfaces of the cavities—the lateral dielectric material bonds the side surfaces of the chiplets to the side surfaces of the wafer—; and direct interconnects of a conductive material leading directly from the plurality of chiplets onto the lateral dielectric material and to the wafer electrical routing of the wafer.

[0082] Examples include: the back surface of the wafer, excluding cavities, being directly attached to and touching the top surface of the back capping layer, and the back surfaces of the chiplets being directly attached to and touching multiple regions of the top surface of the back capping layer.

[0083] Examples include a lateral dielectric material being placed in the gap between the lateral surfaces of the chiplets and the lateral surfaces of the wafer, wherein the gap has a width between 1 / 5 and 10 times the thickness of the wafer or chiplets.

[0084] Examples include the back capping layer being a high-thermal-conductivity back metallized layer that improves heat transfer from chiplets to wafers.

[0085] Examples include the lateral dielectric material layer having a thermal expansion coefficient between the thermal expansion coefficient of the wafer and the thermal expansion coefficient of the chiplets.

[0086] Examples include the lateral dielectric material being a molded material and the bonding being a mechano-chemical bond.

[0087] Examples include the wafer comprising at least one of resistors, capacitors, inductors, through-substrate vias, dielectric layers, and metal layers; the wafer comprising at least one layer of silicon, silicon carbide (SiC), quartz, or other semiconductor wafer material; each chiplet comprising a transistor circuit, direct interconnects to contact pads on the front surface of the chiplet; and each chiplet comprising one of high-end pre-manufactured transistor chiplets or integrated into the wafer using pick-and-place assembly on a temporary wafer.

[0088] Examples include direct interconnects connecting the contacts of chiplets to the contacts of a wafer.

[0089] Examples include dicing the wafer vertically along the perimeter of the wafer around at least one chiplet to form a chip having at least one chiplet and an area of ​​the wafer surrounding the at least one chiplet.

[0090] Examples include a rear capping layer being a single integrated layer that is directly attached to a plurality of chiplets.

[0091] Examples include direct interconnects that are radio frequency (RF) interconnects connecting multiple chiplets to transmit RF signals between multiple chiplets.

[0092] Examples of the technology described herein include a method for assembling an electronic assembly, the method for assembling an electronic assembly comprising: forming cavities penetrating a wafer having a front surface and a rear surface - the cavities have side surfaces of the wafer -; bonding the front surface of the wafer to the top surface of an adhesive laminate having a top surface and a bottom surface such that the cavities are positioned over a plurality of regions of the top surface of an adhesive laminate; bonding the front surface of a plurality of chiplets having a back surface and a front surface to a portion of a plurality of regions of the top surface of the adhesive laminate; molding a lateral dielectric material between the side surfaces of the chiplets and the side surfaces of the cavities - the lateral dielectric material mechanically and chemically bonds the side surfaces of the chiplets to the side surfaces of the cavities -; encapsulating the back surface of the plurality of chiplets, the lateral dielectric material, and the rear surface of the wafer on the top surface of a back capping layer having a top surface and a rear surface - the back capping layer is a single integrated layer directly attached to the plurality of chiplets -; and removing the adhesive laminate.

[0093] Examples include the step of bonding the front surface of a wafer to the top surface of an adhesive laminate, which includes the step of directly attaching the front surface of the wafer to the top surface of the adhesive laminate excluding cavities; the step of bonding the front surface of a plurality of chiplets to a portion of a plurality of regions, which includes the step of directly attaching the front surface of the chiplets to a plurality of regions of the top surface of the adhesive laminate; and the step of encapsulating the back surface of the chiplets, the lateral dielectric material, and the wafer rear surface of the wafer on the top surface of a back capping layer, which includes the step of directly attaching the back surface of the chiplets, the lateral dielectric material, and the wafer rear surface of the wafer to the top surface of the back capping layer.

[0094] Examples include the step of forming cavities, which includes etching through-holes in the substrate on the front or rear surface of the wafer, and the step of encapsulating, which includes embedding chiplets in the through-holes in the wafer.

[0095] Examples include a step of molding a lateral dielectric material comprising one of the steps of: printing the lateral dielectric material into the gaps between the side surfaces of the chiplets and the side surfaces of the wafer using a permanent screen; or molding the lateral dielectric material into the gaps between the side surfaces of the chiplets and the side surfaces of the wafer using vacuum and pressure.

[0096] Examples include the step of bonding the front surfaces of a plurality of chiplets to a portion of a plurality of regions, which includes the step of pick-and-place assembly of pre-fabricated transistor chiplets on the top surface of an adhesive laminate.

[0097] Examples further include the step of directly forming a plurality of interconnects on a lateral dielectric material and connecting the contact portions of the chiplets to the contact portions of the wafer.

[0098] Examples include further including the step of forming interconnects directly from a plurality of chiplets onto a lateral dielectric material and directly via wafer electrical routing after removing the adhesive laminate.

[0099] Examples further include the step of vertically dicing the perimeter of the wafer around the chiplets to form a chip having at least one chiplet and an area of ​​the wafer surrounding the at least one chiplet.

[0100] Examples include a molding step occurring after the front surfaces of a plurality of chiplets are joined; an encapsulation step occurring after the molding step; and a removal step occurring after the encapsulation step.

[0101] Examples of the technology described herein include a method for assembling an electronic assembly, the method for assembling an electronic assembly comprising: a step of bonding a front surface of a wafer having cavities having a front surface, a rear surface, and side surfaces of the wafer to a top surface of an adhesive laminate having a top surface and a bottom surface such that cavities are disposed over a plurality of regions of the top surface of the adhesive laminate; a step of bonding a front surface of a plurality of chiplets having a rear surface and a front surface to a portion of a plurality of regions of the top surface of the adhesive laminate; a step of molding a lateral dielectric material between the side surfaces of the chiplets and the side surfaces of the cavities, wherein the lateral dielectric material bonds the side surfaces of the chiplets to the side surfaces of the cavities; and a step of forming direct interconnects of a conductive material directly from the chiplets onto the lateral dielectric material and into the wafer electrical routing of the wafer.

[0102] Examples further include the step of encapsulating the back surface of the chiplets, the lateral dielectric material, and the back surface of the wafer on the top surface of a back capping layer having a top surface and a back surface; and the step of removing the adhesive laminate.

[0103] Examples include the step of bonding the front surface of a wafer to the top surface of an adhesive laminate, which includes the step of directly attaching the front surface of the wafer to the top surface of the adhesive laminate excluding cavities; the step of bonding the front surface of a plurality of chiplets to a portion of a plurality of regions, which includes the step of directly attaching the front surface of the chiplets to a plurality of regions of the top surface of the adhesive laminate; and the step of encapsulating the back surface of the chiplets, the lateral dielectric material, and the wafer rear surface of the wafer on the top surface of a back capping layer, which includes the step of directly attaching the back surface of the chiplets, the lateral dielectric material, and the wafer rear surface of the wafer to the top surface of the back capping layer.

[0104] Examples include a step of molding a lateral dielectric material comprising one of the steps of: printing the lateral dielectric material into the gaps between the side surfaces of the chiplets and the side surfaces of the wafer using a permanent screen; or molding the lateral dielectric material into the gaps between the side surfaces of the chiplets and the side surfaces of the wafer using vacuum and pressure.

[0105] Examples include the step of bonding the front surfaces of a plurality of chiplets to a portion of a plurality of regions, which includes the step of pick-and-place assembly of pre-fabricated transistor chiplets on the top surface of an adhesive laminate.

[0106] Examples further include the step of vertically dicing the perimeter of the wafer around the chiplets to form a chip having at least one chiplet and an area of ​​the wafer surrounding the at least one chiplet.

[0107] Examples include direct interconnects that are radio frequency (RF) interconnects connecting multiple chiplets to transmit RF signals between multiple chiplets.

[0108] Examples include a molding step occurring after the front surfaces of a plurality of chiplets are joined; and a forming step occurring after the molding step.

[0109] Closing comment

[0110] Throughout this description, the illustrated embodiments and examples should be regarded as examples rather than limitations to the disclosed or claimed devices and procedures. While many of the examples presented herein may involve specific combinations of method actions or system elements, it should be understood that such actions or such elements may be combined in different ways to achieve the same purposes. With respect to flowcharts, additional or fewer steps may be performed, and steps as illustrated may be combined or further subdivided to achieve the methods described herein. Actions, embodiments, and features discussed in relation to only one embodiment are not intended to be excluded from similar roles in other embodiments.

[0111] As used herein, "plural" means two or more. As used herein, a "set" of items may include one or more of these items. As used herein, regardless of whether they are used in the signature description or claims, the terms "comprising," "comprising," "carrying," "having," "containing," "accompanying," and similar terms should be understood as open-ended, that is, meaning that they include without limitation. With respect to the claims, only the transition phrases "consisting of" and "essentially consisting of" are closed or semi-closed transition phrases. The use of ordinal terms such as "first," "second," "third," etc., in claims to define claim elements does not, in itself, imply any priority, priority, or order of the actions of the methods relative to another, or the chronological order in which the actions of the methods are performed, but is used merely as labels to distinguish one claim element having a specific name from another element having the same name (but for the use of ordinal terms) in order to distinguish claim elements. As used herein, "and / or" means that the listed items are alternatives, but the alternatives also include any combination of the listed items.

Claims

Claim 1 An electronic assembly comprising: a back capping layer having an upper surface and a back surface; a wafer having a front surface and a back surface, wherein the back surface of the wafer is coupled to the upper surface of the back capping layer except for cavities formed within the wafer over a plurality of regions of the upper surface of the back capping layer, the cavities having side surfaces; a plurality of chiplets having a back surface and a front surface, wherein the back surface of the chiplets is directly coupled to at least some of the plurality of regions of the upper surface of the back capping layer; a side dielectric material disposed between the side surfaces of the chiplets and the side surfaces of the cavities and coupling the side surfaces of the chiplets and the side surfaces of the cavities; and a direct interconnect of a conductive material formed directly on the side dielectric material from the plurality of chiplets and connected to the wafer wiring routing of the wafer, wherein the wafer comprises at least one layer of a semiconductor wafer material, and the semiconductor wafer material comprises a passive integrated device and an active microelectronic device. Claim 2 An electronic assembly according to claim 1, wherein the back surface of the wafer is directly attached to and contacts the flat and continuous upper surface of the back capping layer, excluding the cavities, and the back surface of the chiplets is directly attached to and contacts the plurality of regions of the flat and continuous upper surface of the back capping layer. Claim 3 An electronic assembly according to claim 1, wherein the lateral dielectric material is disposed in the gap between the lateral surfaces of the chiplets and the lateral surfaces of the wafer, and the width of the gap is 1 / 5 to 10 times the thickness of the wafer or the chiplets. Claim 4 An electronic assembly according to claim 1, wherein the back capping layer is a high thermal conductivity back metallized layer that improves heat transfer from the chiplets to the wafer, and the back capping layer acts as a thermal plane having a thickness of 3 μm to 100 μm. Claim 5 An electronic assembly according to claim 1, wherein the lateral dielectric material is a molded material, and the bond between the lateral surfaces of the chiplets and the lateral surfaces of the cavities is a mechanical-chemical bond. Claim 6 An electronic assembly according to claim 1, wherein the direct interconnect is formed directly on the lateral dielectric material and further comprises a plurality of interconnects connecting the contact portions of the chiplets to the contact portions of the wafer. Claim 7 An electronic assembly according to claim 1, wherein a chip is formed by dicing vertically along the perimeter of a wafer around at least one chiplet to include the at least one chiplet and the region of the wafer surrounding it. Claim 8 An electronic assembly according to claim 1, wherein the rear capping layer is a single integrated layer directly attached to the plurality of chiplets. Claim 9 An electronic assembly comprising: a back capping layer having an upper surface and a back surface; a wafer having a front surface and a back surface, wherein the back surface of the wafer is coupled to the upper surface of the back capping layer except for cavities formed on a plurality of regions of the upper surface of the back capping layer, said cavities having side surfaces; a plurality of chiplets having a back surface and a front surface, wherein the back surface of the chiplets is directly coupled to at least some of the plurality of regions of the upper surface of the back capping layer; a side dielectric material disposed between the side surfaces of the chiplets and the side surfaces of the cavities and coupling the side surfaces of the chiplets and the side surfaces of the cavities; and a direct interconnect of a conductive material formed directly on the side dielectric material from the plurality of chiplets and connected to the wafer wiring routing of the wafer, wherein the coefficient of thermal expansion of the side dielectric material layer is between the coefficient of thermal expansion of the wafer and the chiplets. Claim 10 As an electronic assembly, a back capping layer having an upper surface and a back surface; a wafer having a front surface and a back surface, wherein the back surface of the wafer is coupled to the upper surface of the back capping layer except for cavities formed on a plurality of regions of the upper surface of the back capping layer, said cavities having side surfaces; a plurality of chiplets having a back surface and a front surface, said chiplets having a back surface and a front surface, said chiplets having a back surface and a portion of the plurality of regions of the upper surface of the back capping layer directly coupled to at least some of said regions; a side dielectric material disposed between the side surfaces of said chiplets and the side surfaces of said cavities, and coupling the side surfaces of said chiplets and the side surfaces of said cavities; An electronic assembly comprising a plurality of chiplets, a direct interconnect of a conductive material formed directly on the lateral dielectric material and connected to the wafer wiring routing of the wafer, wherein the wafer comprises at least one of a resistor, a capacitor, an inductor, a through-substrate via (TSV), a dielectric layer, and a metal layer, wherein the wafer comprises at least one layer of silicon, silicon carbide (SiC), quartz, or other semiconductor wafer material, and wherein each chiplet comprises a transistor circuit and is interconnected to a contact pad on the front surface, or each chiplet is a high-end pre-manufactured transistor chiplet, or is integrated into the wafer using pick-and-place assembly on a temporary wafer. Claim 11 An electronic assembly comprising: a back capping layer having an upper surface and a back surface; a wafer having a front surface and a back surface, wherein the back surface of the wafer is coupled to the upper surface of the back capping layer except for cavities formed on a plurality of regions of the upper surface of the back capping layer, said cavities having side surfaces; a plurality of chiplets having a back surface and a front surface, wherein the back surface of the chiplets is directly coupled to at least some of the plurality of regions of the upper surface of the back capping layer; a side dielectric material disposed between the side surfaces of the chiplets and the side surfaces of the cavities and coupling the side surfaces of the chiplets and the side surfaces of the cavities; and a direct interconnect of a conductive material formed directly on the side dielectric material from the plurality of chiplets and connected to the wafer wiring routing of the wafer, said direct interconnect including radio frequency (RF) interconnects for connecting the plurality of chiplets and transmitting RF signals between the plurality of chiplets. Claim 12 An electronic assembly comprising: a back capping layer having an upper surface and a back surface; a wafer having a front surface and a back surface, wherein the back surface of the wafer is coupled to the upper surface of the back capping layer except for cavities formed on a plurality of regions of the upper surface of the back capping layer, said cavities having side surfaces; a plurality of chiplets having a back surface and a front surface, wherein the back surface of the chiplets is directly coupled to at least some of the plurality of regions of the upper surface of the back capping layer; and a side dielectric material disposed between the side surfaces of the chiplets and the side surfaces of the cavities, and coupling the side surfaces of the chiplets and the side surfaces of the cavities, wherein a semiconductor material on the back surface of the wafer is directly attached to the upper surface of the back capping layer. Claim 13 An electronic assembly according to claim 12, wherein the back surface of the wafer is directly attached to and contacts the upper surface of the back capping layer, excluding the cavities, and the back surface of the chiplets is directly attached to and contacts the plurality of regions of the upper surface of the back capping layer. Claim 14 An electronic assembly according to claim 12, wherein the lateral dielectric material is disposed in the gap between the lateral surfaces of the chiplets and the lateral surfaces of the wafer, and the width of the gap is 1 / 5 to 10 times the thickness of the wafer or the chiplets. Claim 15 An electronic assembly according to claim 12, wherein the back capping layer is a high thermal conductivity back metallized layer that improves heat transfer from the chiplets to the wafer. Claim 16 An electronic assembly according to claim 12, wherein the coefficient of thermal expansion of the lateral dielectric material layer is between the coefficients of thermal expansion of the wafer and the chiplet. Claim 17 An electronic assembly according to claim 12, wherein the lateral dielectric material is a molded material, and the bond between the lateral surface of the chiplets and the lateral surface of the wafer is a mechanical-chemical bond. Claim 18 An electronic assembly according to claim 12, wherein the wafer comprises at least one of a resistor, a capacitor, an inductor, a through-substrate via (TSV), a dielectric layer, and a metal layer, and the wafer comprises at least one layer of silicon, silicon carbide (SiC), quartz, or other semiconductor wafer material, and each chiplet comprises a transistor circuit and is interconnected to a contact pad on the front surface of the chiplet, and each chiplet is a high-end pre-manufactured transistor chiplet or is integrated into the wafer using pick-and-place assembly on a temporary wafer. Claim 19 An electronic assembly according to claim 12, wherein the electronic assembly comprises one of: a plurality of interconnects formed directly on the side dielectric material to connect the contact portion of the chiplet to the contact portion of the wafer; or a direct interconnect routing formed directly from the chiplet to the side dielectric material to the wafer wiring routing. Claim 20 An electronic assembly according to claim 19, wherein the plurality of interconnects or the direct interconnect routing comprises RF interconnects for connecting a plurality of chiplets and transmitting RF signals between the plurality of chiplets. Claim 21 An electronic assembly according to claim 12, wherein a chip is formed by dicing vertically along the perimeter of a wafer around at least one chiplet to include the at least one chiplet and the region of the wafer surrounding it. Claim 22 In claim 12, the electronic assembly, wherein the rear capping layer is a single integrated layer directly attached to the plurality of chiplets. Claim 23 An electronic assembly comprising: a back capping layer having an upper surface and a back surface; a wafer having a front surface and a back surface, wherein the back surface of the wafer is coupled to the upper surface of the back capping layer except for cavities formed on a plurality of regions of the upper surface of the back capping layer, said cavities having side surfaces; a plurality of chiplets having a back surface and a front surface, wherein the back surface of the chiplets is directly coupled to at least some of the plurality of regions of the upper surface of the back capping layer; a side dielectric material disposed between the side surfaces of the chiplets and the side surfaces of the cavities and coupling the side surfaces of the chiplets and the side surfaces of the cavities; a direct interconnect of a conductive material formed directly on the side dielectric material from the plurality of chiplets and connected to the wafer wiring routing of the wafer; and an electronic assembly configured such that the perimeter of the wafer and the back capping layer around the chiplets is vertically diced to form chips comprising at least one chiplet and a region of the wafer surrounding it. Claim 24 An electronic assembly according to claim 23, wherein the back capping layer comprises a metal back capping layer, the back surface of the wafer is directly attached to and contacts the upper surface of the metal back capping layer excluding the cavities, and the back surface of the chiplets is directly attached to and contacts the plurality of regions of the upper surface of the back capping layer. Claim 25 delete Claim 26 delete Claim 27 delete Claim 28 delete

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