Barrier free tungsten liner in contact plugs and the method forming the same

Abstract

The method includes the steps of forming a dielectric layer over a conductive feature and etching the dielectric layer to form an opening. The conductive feature is exposed through the opening. The method further includes the steps of forming a tungsten liner within the opening—the tungsten liner in contact with the sidewall of the dielectric layer—, depositing a tungsten layer to fill the opening, and flattening the tungsten layer. Parts of the tungsten liner and the tungsten layer within the opening form a contact plug.

Description

Technology Field

[0001] [Priority Claims and Cross-references]

[0002] This application claims the benefit of U.S. provisional application No. 63 / 497,478 filed on April 21, 2023, titled “Barrier Free W-liner for Low-R and Low-Cost Plug,” which is incorporated herein by reference.

[0003] The present invention relates to a barrier-free tungsten liner in a contact plug and a method for forming the same. Background Technology

[0004] In the manufacture of integrated circuits, source / drain contact plugs are used to connect to the source and drain regions of a transistor. Source / drain contact plugs are typically connected to source / drain silicide regions. The formation of source / drain contact plugs includes the steps of forming a contact opening within the interlayer dielectric, depositing a metal layer extending into the contact opening, and then performing an annealing process to react the metal layer with the silicon / germanium in the source / drain regions. Subsequently, source / drain contact plugs are formed within the remaining contact opening. Additionally, a gate contact plug is formed to connect to the gate of the transistor. Brief explanation of the drawing

[0005] The aspects of the present disclosure are best understood from the following detailed description with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not depicted proportionally. In practice, the dimensions of various features may be increased or decreased at will for the sake of clarity of discussion. FIGS. 1-7, 8a, 8b, 9-22, 23a, 23b, 23c, and 24 illustrate intermediate stages in the formation of a FinFET (Fin Field-Effect Transistor) according to some embodiments. FIGS. 25 and 26 illustrate top views of some structures that can adopt a contact plug according to an embodiment of the present disclosure. FIG. 27 illustrates an exemplary distribution profile of fluorine and boron according to some embodiments. FIG. 28 illustrates a process flow for forming a FinFET according to some embodiments. Specific details for implementing the invention

[0006] The following description provides a number of different embodiments or examples for implementing different features of the present disclosure. For the sake of brevity, specific embodiments of components and arrangements are disclosed below. Of course, this is merely illustrative and is not intended to be limiting. For example, in the following description, the formation of the first feature on or above the second feature may include an embodiment in which the first and second features are formed and in direct contact, or an embodiment in which an additional feature may be formed between the first and second features so that the first and second features do not come into direct contact. Additionally, reference numerals and / or letters may be repeated in various embodiments of the present disclosure. Such repetition is for brevity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations being discussed.

[0007] Additionally, spatial terms such as "placed below," "under," "lower," "placed above," and "upper" may be used herein for convenience of description to indicate the relationship of a feature to one element or another, as exemplified in the drawings. Spatial terms are intended to include different orientations of the device in use or operation regarding the orientation depicted in the drawings. The device may be oriented differently (rotated 90 degrees or oriented differently), and accordingly, the spatial descriptors used herein may be interpreted in the same way.

[0008] Transistors and contact plugs are provided according to a number of embodiments. Corresponding forming processes are also provided. According to some embodiments, the contact plug comprises tungsten liners and additional tungsten layers on top of the tungsten liners. The tungsten liners may be formed using Physical Vapor Deposition (PVD). By adopting tungsten liners, contact resistance may be reduced and is lower than the contact resistance of a contact plug adopting Ti / TiN liners. Seams may also be reduced or eliminated. Several variations of some embodiments are discussed. In various drawings and exemplary embodiments, similar reference numerals are used to denote similar elements. According to some embodiments, the formation of a Fin Field-Effect Transistor (FinFET) is used as an example to illustrate the concept of the present disclosure. Planar transistors and Gate-All-Around (GAA) transistors

[0009] Other types of transistors, such as CFETs (Complementary Field-Effect Transistors) and corresponding contact plugs, may also adopt the concept of the present disclosure.

[0010] FIGS. 1-7, 8a, 8b, 9-22, 23a, 23b, 23c, and 24 illustrate intermediate stages in the formation of a FinFET (Fin Field-Effect Transistor) according to some embodiments. The process illustrated in these figures is also schematically reflected in the process flow (200) illustrated in FIG. 28.

[0011] In FIG. 1, a substrate (20) is provided. The substrate (20) may be a semiconductor substrate, such as a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate, which can be doped (e.g., with a p-type or n-type dopant). The semiconductor substrate (20) may be part of a wafer (10), such as a silicon wafer. Generally, the SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as a multi-layer or gradient substrate, may also be used.

[0012] In some embodiments, the semiconductor material of the semiconductor substrate (20) may include silicon; germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof.

[0013] Referring further to FIG. 1, a well region (22) is formed within the substrate (20). Each process is exemplified by a process (202) in a process flow (200) as illustrated in FIG. 28. According to some embodiments of the present disclosure, the well region (22) is an n-type well region formed by injecting an n-type impurity, which may be phosphorus, arsenic, antimony, etc., into the substrate (20). According to other embodiments of the present disclosure, the well region (22) is a p-type well region formed by injecting a p-type impurity, which may be boron, indium, etc., into the substrate (20). The obtained well region (22) may extend to the upper surface of the substrate (20). The concentration of n-type or p-type impurities is 10 18 cm -3 Below, for example, about 10 17 cm -3 to about 10 18 cm -3 It can be a range.

[0014] Referring to FIG. 2, isolation regions (24) are formed so as to extend from the upper surface of the substrate (20) to the substrate (20). The isolation regions (24) are alternatively referred to as Shallow Trench Isolation (STI) regions below. Each process is exemplified by a process (204) in a process flow (200) as illustrated in FIG. 28. The portion of the substrate (20) between adjacent STI regions (24) is referred to as a semiconductor strip (26). To form the STI regions (24), a pad oxide layer (28) and a hard mask layer (30) are formed on the semiconductor substrate (20) and subsequently patterned. The pad oxide layer (28) may be a thin film formed of silicon oxide. According to some embodiments, the pad oxide layer (28) is formed in a thermal oxidation process, and the upper surface of the semiconductor substrate (20) is oxidized. The pad oxide layer (28) functions as an adhesive layer between the semiconductor substrate (20) and the hard mask layer (30). The pad oxide layer (28) can function as an etch stop layer for etching the hard mask layer (30).

[0015] According to some embodiments, the hard mask layer (30) is formed of silicon nitride, for example, using Low-Pressure Chemical Vapor Deposition (LPCVD). According to other embodiments of the present disclosure, the hard mask layer (30) is formed by thermal nitridation of silicon or Plasma Enhanced Chemical Vapor Deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer (30) and then patterned. Subsequently, the hard mask layer (30) is patterned using the patterned photoresist as an etching mask to form the hard mask (30) as shown in FIG. 2.

[0016] Subsequently, the patterned hard mask layer (30) is used as an etching mask to etch the pad oxide layer (28) and the substrate (20), and the resulting trench in the substrate (20) is filled with dielectric material(s). A planarization process, such as a Chemical Mechanical Polish (CMP) process or a mechanical polishing process, is performed to remove excess dielectric material, and the remaining portion of the dielectric material(s) is an STI region (24). The STI region (24) may include a liner dielectric (not shown), which may be a thermal oxide formed through thermal oxidation of the surface layer of the substrate (20). The liner dielectric may be, for example, a silicon oxide layer, a silicon nitride layer, etc. formed using Atomic Layer Deposition (ALD), High-Density Plasma Chemical Vapor Deposition (HDPCVD), or Chemical Vapor Deposition (CVD). The STI region (24) may include a dielectric material on the liner oxide, and the dielectric material may be formed using FCVD (Flowable Chemical Vapor Deposition), spin-on coating, etc. The dielectric material on the liner dielectric may include silicon oxide according to some embodiments.

[0017] The upper surface of the hard mask (30) and the upper surface of the STI region may be substantially at the same level. The semiconductor strip (26) is located between adjacent STI regions (24). According to some embodiments, the semiconductor strip (26) is part of the original substrate (20), and accordingly, the material of the semiconductor strip (26) is the same as the material of the substrate (20). According to alternative embodiments of the present disclosure, the semiconductor strip (26) is an alternative strip formed by etching the portion of the substrate (20) between the STI regions (24) to form a recess and performing epitaxy to regrow a different semiconductor material in the recess. Thus, the semiconductor strip (26) is formed of a semiconductor material different from the material of the substrate (20). According to some embodiments, the semiconductor strip (26) is formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material.

[0018] Referring to FIG. 3, the STI region (24) is recessed so that the upper portion of the semiconductor strip (26) protrudes higher than the upper surface (24T) of the remainder of the STI region (24) to form a protruding pin (36). Each process is exemplified by a process (206) in a process flow (200) as illustrated in FIG. 28. Etching may be performed using a dry etching process in which HF3 and NH3 are used, for example, as etching gases. Plasma may be generated during the etching process. Argon may also be included. According to alternative embodiments of the present disclosure, the recessing of the STI region (24) is performed using a wet etching process. Etching chemicals may include, for example, HF.

[0019] In the embodiments illustrated above, the pin may be patterned by any suitable method. For example, the pin may be patterned using one or more photolithography processes including double patterning or multi-patterning processes. Generally, double patterning or multi-patterning processes combine photolithography and self-alignment processes, and accordingly, a pattern with a smaller pitch than that can be obtained using, for example, a single direct photolithography process may be produced. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the sacrificial layer patterned using a self-alignment process. Subsequently, the sacrificial layer is removed, and the remaining spacers or mandrels may be used to pattern the pin.

[0020] Referring to FIG. 4, a dummy gate stack (38) is formed on the upper surfaces and sidewalls of the (protruding) pin (36). Each process is exemplified by a process (208) in the process flow (200) as illustrated in FIG. 28. The dummy gate stack (38) may include a dummy dielectric (40) and a dummy gate electrode (42) on the dummy gate dielectric (40). The dummy gate electrode (42) may be formed using, for example, polysilicon, or other materials may be used. Each dummy gate stack (38) may include one (or a plurality) hard mask layers (44) on the dummy gate electrode (42). The hard mask layers (44) may be formed of silicon nitride, silicon oxide, silicon carbon-nitride, or a multilayer thereof. The dummy gate stack (38) may cross over one or a plurality of protruding pins (36) and / or STI regions (24). The dummy gate stack (38) may have a length direction perpendicular to the length direction of the protruding pin (36).

[0021] Next, a gate spacer (46) is formed on the sidewall of the dummy gate stack (38). Each process is also illustrated as a process (208) in the process flow (200) as illustrated in FIG. 28. According to some embodiments, the gate spacer (46) is formed of a dielectric material(s) such as silicon nitride, silicon carbide-nitride, etc., and may have a single-layer structure or a multi-layer structure including multiple dielectric layers.

[0022] Next, an etching process is performed to etch a portion of the protruding pins (36) that are not covered by the dummy gate stack (38) and gate spacer (46) that form the structure illustrated in FIG. 5. Each process is exemplified by a process (210) in a process flow (200) as illustrated in FIG. 28. The recessing may be anisotropic, so that some of the pins (36) located directly beneath the dummy gate stack (38) and gate spacers (46) are protected and not etched. According to some embodiments, the upper surface of the recessed semiconductor strip (26) may be lower than the upper surface (24T) of the STI region (24). The spaces left by the etched protruding pins (36) are referred to as recesses (50). The recesses (50) include portions located between adjacent gate stacks (38). A portion of the lower part of the recesses (50) is located between adjacent STI regions (24).

[0023] Next, an epitaxy region (source / drain region) (54) is formed by selectively growing a semiconductor material within the recess (50) that forms the structure in FIG. 6. Each process is exemplified by a process (212) in the process flow (200) as illustrated in FIG. 28. The source / drain region(s) may be referred to as source or drain individually or collectively depending on the context. Depending on whether the obtained FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities may be doped in-situ during the proceeding of epitaxy. For example, when the obtained FinFET is a p-type FinFET, SiGeB (silicon germanium boron), SiB (silicon boron), etc. may be grown. Conversely, when the obtained FinFET is an n-type FinFET, SiP (silicon phosphorous), SiCP (silicon carbon phosphorous), etc. may be grown. According to alternative embodiments of the present disclosure, the epitaxy region (54) comprises a III-V compound semiconductor such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multiple layers thereof. After the recess (50) is filled into the epitaxy region (54), further epitaxy growth of the epitaxy region (54) may cause the epitaxy region (54) to expand horizontally so that a facet may be formed. Further growth of the epitaxy region (54) may also cause adjacent epitaxy regions (54) to merge with each other. A void (air gap) (56) may be created.

[0024] After the epitaxy step, p-type impurities or n-type impurities may be further injected into the epitaxy region (54) to form source and drain regions indicated by reference numeral 54. According to alternative embodiments of the present disclosure, when the epitaxy region (54) is in situ-doped with p-type impurities or n-type impurities during epitaxy, the injection process is omitted.

[0025] FIG. 7 shows a perspective view of the structure after the formation of the Contact Etch Stop Layer (CESL) (58) and the Inter-Layer Dielectric (ILD) (60). Each process is exemplified by a process (214) in the process flow (200) as illustrated in FIG. 28. The CESL (58) can be formed from silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. The ILD (60) may include a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or other film deposition methods. The ILD (60) may be formed from a dielectric material including silicon oxide, PSG (Phospho-Silicate Glass), BSG (Boro-Silicate Glass), BPSG (Boron-Doped Phospho-Silicate Glass), etc. A flattening process, such as a CMP process or a mechanical polishing process, can be performed to make the upper surfaces of the ILD (60), dummy gate stack (38), and gate spacer (46) level with each other.

[0026] After the structure illustrated in FIG. 7 is formed, the dummy gate stack (38) is replaced with an alternative gate stack, as illustrated in the process of FIG. 8a, FIG. 8b. In FIG. 8b, the upper surface (24T) of the STI region (24) is illustrated, and the semiconductor pin (36) protrudes higher than the upper surface (24T).

[0027] To form a replacement gate, the hard mask layer (44), dummy gate electrode (42), and dummy gate dielectric (40) as shown in FIG. 7 are removed, and an opening (62) as shown in FIG. 8a is formed. Each process is exemplified by a process (216) in a process flow (200) as shown in FIG. 28. The upper surface and side wall of the protrusion (36) are each exposed to the opening (62).

[0028] FIG. 8b illustrates a vertical cross-section (8B-8B) as illustrated in FIG. 8a. Subsequently, an alternate gate stack (64) is formed as illustrated in FIG. 9. Each process is exemplified by a process (218) in a process flow (200) as illustrated in FIG. 28. The gate stack (64) includes a gate dielectric (70) and a gate electrode (72). The gate dielectric (70) may include an interfacial layer (IL) (66) and a high-k dielectric layer (68). The IL (66) may include an oxide layer, such as a silicon oxide layer, formed on the exposed surface of the protruding pin (36) through a thermal oxidation, chemical oxidation process, or film deposition process of the protruding pin (36). The high-k dielectric layer (68) includes a high-k dielectric material such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, silicon nitride, etc. The dielectric constant (k value) of the high k dielectric material may be higher than 3.9 and higher than about 7.0. According to some embodiments, the high k dielectric layer (68) is formed using ALD or CVD.

[0029] Referring further to FIG. 9, a gate electrode (72) is formed on a gate dielectric (70). The gate electrode (72) may include a diffusion barrier layer (capping layer) (74) and one or more work function layers (76) on the diffusion barrier layer (74). The diffusion barrier layer (74) may be formed of titanium nitride that can be doped with silicon (or may not be doped). Titanium nitride, when doped with silicon, is sometimes referred to as titanium silicon nitride (Ti-Si-N, or TSN). The work function layer (76) determines the work function of the gate electrode and comprises at least one layer or a plurality of layers formed of different materials. A specific material of the work function layer may be selected depending on whether the individual FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work function layer (76) may comprise a TaN layer and a TiAl (titanium aluminum) layer on top of the TaN layer. For example, when the FinFET is a p-type FinFET, the work function layer (76) may comprise a TaN layer, a TiN layer on top of the TaN layer, and a TiAl layer on top of the TiN layer. After the formation of the capping layer (74) and the work function layer (76), another TiN A blocking layer (78) that can be a layer is formed. The blocking layer (78) can be formed using CVD.

[0030] Next, a metal-filled region (80) is formed and has a lower surface that is in physical contact with the upper surface of the blocking layer. The formation of the metal-filled region (80) can be achieved through CVD, ALD, PVD (Physical Vapor Deposition), etc., and the metal-filled region (80) may be formed of or include cobalt, tungsten, alloys thereof, or other metals or metal alloys.

[0031] Next, planarization, such as a Chemical Mechanical Polish (CMP) process or a mechanical polishing process, is performed so that the upper surface of the gate stack (64) is flush with the upper surface of the ILD (60). In a subsequent process, the gate stack (64) is etched back to form a recess between the gate spacers (46) on both sides. Next, as shown in FIG. 10, a hard mask (82) as shown in FIG. 10 is formed over the alternate gate stack (64). According to some embodiments, the formation of the hard mask (82) includes a deposition process for forming a dielectric to fill the recess, followed by a planarization process to remove excess dielectric material over the gate spacers (46) and the ILD (60). The hard mask (82) may be formed of, for example, silicon nitride or other similar dielectric material.

[0032] FIG. 11 illustrates the formation of a lower source / drain contact plug (84) and a silicide region (86). Each process is exemplified by a process (220) in a process flow (200) as illustrated in FIG. 28. According to some embodiments, the formation process includes the steps of etching an ILD (60) and a CESL (58) to form a contact opening, depositing a metal layer (such as a titanium layer or a cobalt layer) extending into the contact opening, and performing an annealing process so that a lower portion of the metal layer reacts with the source / drain region (54) to form a silicide region (86). The remaining sidewall portions of the metal layer may be removed or left unremoved.

[0033] Subsequently, a source / drain contact plug (84) is formed to contact the source / drain silicide region (86). Accordingly, a FinFET (100) is formed. According to some embodiments, the source / drain contact plug (84) may be formed of tungsten. The formation process may include the step of forming a tungsten liner and the step of forming an additional tungsten layer on the tungsten liner. The formation process may be identical to the formation of the contact plug (98), and the structure, material, and formation process are identical to those described with reference to FIGS. 14 through 22. According to alternative embodiments, the source / drain contact plug (84) may comprise cobalt, tungsten, other applicable metals, or alloys thereof. Planarization, such as a mechanical polishing process or a CMP process, is performed so that the upper surface of the contact plug (84) is flush with the upper surface of the ILD (60).

[0034] FIG. 12 illustrates the formation of an etch stop layer (ESL) (90) and a dielectric layer (92) (which may also be an ILD) on an ESL (90). Each process is exemplified by a process (222) in a process flow (200) as illustrated in FIG. 28. The ESL (90) may be formed of or include aluminum oxide, aluminum nitride, silicon oxynitride, silicon carbon nitride, silicon carbon oxide, etc., or a combination thereof. The dielectric layer (92) may be silicon dioxide, low-k dielectric material, silicon oxynitride, PSG, BSG, BPSG, USG, FSG, SiOC, or include the same, and the ESL (90) and the dielectric layer (92) may be formed using spin-on coating, CVD, ALD, LPCVD, PECVD, etc.

[0035] FIG. 13 illustrates the formation of source / drain contact openings (94) and gate contact openings (96) by etching to expose contact plugs (84) and gate electrodes (72), respectively. Each process is exemplified by a process (224) in a process flow (200) as illustrated in FIG. 28. The dielectric layer (92) and ESL (90) may be etched, for example, using photolithography and one or more etching processes. The etching process may include a dry etching process using reactive ion etch (RIE), neutral beam etch (NBE), inductively coupled plasma (ICP) etch, capacitively coupled plasma (ICP) etch, ion beam etch (IBE), etc., or a combination thereof. The etching process can be anisotropic. The width (W1) of the gate contact opening (96) and the width (W2) of the source / drain contact opening (94) can be in the range of about 50 Å to about 1,000 Å.

[0036] FIGS. 14 through 18 illustrate cross-sectional views of intermediate stages in the formation of a gate contact plug (98A) according to some embodiments. In the illustrated cross-sectional views, the formation of the gate contact plug (98A) (see also FIG. 23a and FIG. 23b) is illustrated as an example. The formation process may also be used to form other contact plugs, including but not limited to source / drain contact plugs, gate contact plugs and contact plugs over source / drain contact plugs, butted contact plugs, etc. For example, when the gate contact opening (96) is filled to form the gate contact plug (98A), the source / drain contact opening (94) may be simultaneously filled in the same process with the same material to form the source / drain contact plug (98B) ( FIG. 23a).

[0037] FIG. 14 illustrates a cross-sectional view, and the region (102) in FIG. 13 is illustrated in the cross-sectional view. The gate electrode (72) is exposed to the gate contact opening (96). Next, referring to FIG. 15, a tungsten liner (104) is formed. Each process is exemplified by the process (226) in the process flow (200) as illustrated in FIG. 28. There may be no metal cap, such as a titanium cap, formed on the gate electrode (72). Thus, the tungsten liner (104) is in physical contact with the upper surface of the gate electrode (72) and in contact with dielectric materials such as a hard mask (82), ESL (90), and ILD (92). According to some embodiments in which the gate spacers (46) are exposed to the gate contact opening (96), the tungsten liner (104) is also in physical contact with the gate spacers (46).

[0038] The deposition of the tungsten liner (104) can be performed using PVD in a PVD chamber. According to some embodiments, in the PVD chamber, a tungsten target is placed on the wafer (10), and the distance between the tungsten target and the wafer (10) may be in the range of about 10 mm to about 1,000 mm. The tungsten target may be substantially pure tungsten, and the tungsten purity is, for example, 5N5 (greater than about 99.9995%).

[0039] During the PVD process for forming the tungsten liner (104), the wafer temperature of the wafer (10) may be in the range between room temperature (e.g., about 21°C) and about 500°C. The source power may be DC power or RF power, which may be in the range of about 100 watts to about 50,000 watts. When RF power is used, the frequency of the RF power may be in the range of about 2 MHz to about 60 MHz. The bias power (plasma power) may be in the range of about 0 watts to about 2,000 watts. According to some embodiments, sputtering may be performed using a gas such as Ar, Kr, or a combination thereof. The gas flow may be in the range of about 1 sccm to about 5,000 sccm. The PVD chamber pressure may be in the range of about 0.1 Torr to about 500 Torr. Pull-in or pull-out ion direction control can be adopted.

[0040] According to some embodiments, the tungsten liner (104) is formed using a tungsten target via PVD, and elements such as boron, chlorine, and fluorine are not present in the tungsten target and PVD chamber, and the resulting tungsten liner (104) may not contain elements such as boron, chlorine, and fluorine when formed.

[0041] The tungsten liner (104) is more advantageous than other types of liners, such as the Ti / TiN liner (including a Ti layer and a TiN layer on top of the Ti layer). For example, the tungsten liner (104) is smoother with a smaller surface roughness than the Ti / TiN liner. The roughness of the liner can be transferred to the subsequently deposited tungsten layer and can cause seams [voids]. Since the tungsten liner (104) has a smaller roughness, the subsequently deposited tungsten layer also has a smooth surface and is less likely to have seams. By adopting the tungsten liner, if seams are always created, the seams will be narrower.

[0042] Using PVD to form the tungsten liner (104) may result in low coverage issues. FIG. 17 illustrates some exemplary thicknesses of the tungsten liner (104). The thickness values ​​indicate that the sidewall portions of the tungsten liner (104) are thinner than the upper and lower portions. The sidewall of the dielectric material facing the gate contact opening (96) may not be completely covered by the tungsten liner (104).

[0043] Referring to FIG. 16, a nucleation layer (106) is deposited to completely cover the sidewalls of the dielectric material. Each process is exemplified by a process (228) in a process flow (200) as illustrated in FIG. 28. The nucleation layer (106) is also a tungsten layer and can be deposited using ALD, CVD, etc. Additionally, to form a nucleation layer (106) with better coverage, the temperature for depositing the nucleation layer (106) may be lower than the deposition temperature of the bulk tungsten layer (108) to reduce the deposition rate.

[0044] According to some embodiments, the nucleation layer (106) is a fluorine-containing tungsten layer formed using a fluorine-containing tungsten precursor. According to some embodiments, the fluorine-containing tungsten precursor comprises tungsten hexafluoride (WF6) or other applicable precursors. The precursor further comprises a reducing agent such as diborane (B2H6), hydrogen (H2), a silicon-containing precursor such as silane, or a combination thereof. Formation may be performed via (thermal) ALD. The ALD process may comprise a plurality of cycles, each comprising pulsing the fluorine-containing tungsten precursor, turning off the conduction of the fluorine-containing tungsten precursor, pulsing the reducing agent, and turning off the conduction of the reducing agent.

[0045] According to some embodiments, since the tungsten precursor contains fluorine, the resulting nucleation layer (106) (in a filmed state) may contain fluorine. When the reducing agent contains boron, the resulting nucleation layer (106) may also contain filmed boron. When the reducing agent contains a silicon-containing precursor such as silane, the resulting tungsten liner (104) may also contain filmed silicon.

[0046] According to some embodiments, the nucleation layer (106) is a fluorine-free tungsten layer formed using a fluorine-free tungsten precursor. According to some embodiments, the fluorine-free tungsten precursor is tungsten hexafluoride (WCl5) or tungsten pentachloride (W2Cl5). 10 Tungsten pentachloride is a solid at room temperature and is converted into a gaseous phase when used. The precursor further includes a reducing agent such as hydrogen (H2), a silicon-containing precursor such as silane, etc.

[0047] The formation of the fluorine-free nucleation layer (106) can be performed via (thermal) ALD, while other processes such as CVD may be used. When the ALD process is adopted, the ALD process may include multiple cycles comprising, respectively, pulsing a fluorine-free tungsten precursor, turning off the conduction of the fluorine-free tungsten precursor, pulsing a reducing agent, and turning off the conduction of the reducing agent. When the CVD process is adopted, the fluorine-free tungsten precursor and the reducing agent are simultaneously conducted into their respective CVD chambers to form the nucleation layer (106). The CVD process may also be a plasma-free thermal process.

[0048] In the formation of the nucleation layer (106), to ensure that the nucleation layer is formed with complete coverage on the sidewalls of the dielectric material, the temperature of each wafer is lower than, for example, the temperature for forming the bulk tungsten layer (10) subsequently formed. The temperature may also be higher, equal to, or lower than the wafer temperature during the PVD process for forming the tungsten liner (104).

[0049] During the ALD process for forming a fluorine-free nucleation layer (106), the wafer temperature of the wafer (10) may be in the range of about 300°C to about 500°C. The source power may be in the range of about 0 watts (if the ALD or CVD process is a thermal process) to about 5,000 watts. The plasma may be generated via ICP, CCP, microwaves, etc. The plasma (if used) may be remote plasma or direct plasma. Additionally, the plasma may be filtered or not filtered to remove ions and leave radicals of the process gas.

[0050] According to another alternative embodiment, during the formation of the fluorine-free nucleation layer ((106)), the chamber pressure may be in the range of about 1 Torr to about 100 Torr. The gas flow rate may be in the range of about 1 sccm to about 10,000 sccm. The tungsten-containing gas may have a flow rate percentage (in the process gas) in the range of about 0.01% to about 100%.

[0051] According to some embodiments, since the nucleation layer (106) contains fluorine, the resulting tungsten liner (104) (in a filmed state) may contain fluorine. However, the percentage of fluorine atoms may be low. When the reducing agent contains a silicon-containing precursor such as silane, the resulting tungsten liner (104) may also contain filmed silicon.

[0052] According to some embodiments, there may or may not be a vacuum break between the tungsten liner (104) and the formation of the nucleation layer (106) (independent of the process gases for forming the nucleation layer (106)). The formation of the nucleation layer (106) and the subsequent formation of the bulk tungsten layer (108) (Fig. 17) may be performed on the same vacuum platform within different vacuum chambers, without a vacuum break between them.

[0053] FIG. 17 illustrates the deposition of a bulk tungsten layer (108) according to some embodiments. Each process is exemplified by a process (230) in a process flow (200) as illustrated in FIG. 28. According to some embodiments, the deposition of the bulk tungsten layer (108) is performed using a thermal CVD process (in which plasma may not be generated). The deposition of the bulk tungsten layer (108) may be performed using WF6 and H2 as process gases. According to some embodiments, in the formation of the nucleation layer (106), the precursor flow is appropriately provided to ensure full coverage. Thus, the transition from the formation of the nucleation layer (106) to the formation of the bulk tungsten layer (108) can be achieved by increasing the temperature of the wafer, while other process conditions such as the precursor flow rate, chamber pressure, etc., may remain unchanged.

[0054] According to some embodiments, the film of the bulk tungsten layer (108) is formed with a hydrogen flow rate in the range of about 1,000 sccm to about 7,000 sccm and a WF6 flow rate in the range of about 50 sccm to about 450 sccm. The pressure in the individual chamber may be in the range of about 10 Torr to about 300 Torr.

[0055] According to some embodiments, the bulk tungsten layer (108) and the tungsten liner (104) may be distinguishable from each other. For example, when Transmission Electron Microscopy (TEM) is used, images of the bulk tungsten layer (108) and the tungsten liner (104) may be distinguishable from each other by different gray levels and different patterns such as dark / light patterns. Additionally, the nucleation layer (106) may be more amorphous than the bulk tungsten layer (108) and the tungsten liner (104) due to lower film formation, and thus may be distinguishable from the bulk tungsten layer (108) and the tungsten liner (104).

[0056] As described above, as a result of forming the tungsten liner (104), the tungsten liner (104) has a smooth upper surface (Fig. 15) having a smaller roughness than the Ti / TiN liner when, for example, a Ti / TiN liner is used. Accordingly, the nucleation layer (106) and the bulk tungsten layer (108) are also smoother with a smaller roughness. Consequently, when the air gap (110) is formed, it will be narrower than the air gap created when the Ti / TiN liner is used. The air gap (110) can also be eliminated due to the use of the tungsten liner. The reduction in the air gap results in an increase in the volume of tungsten. Therefore, replacing the Ti / TiN liner with a tungsten liner also reduces the contact resistance of the resulting contact plug.

[0057] Some of the exemplary dimensions are shown in FIG. 17. The upper portion of the tungsten layers (104 / 106 / 108) may have an overall upper thickness (T1) in the range of about 30 Å to about 2,000 Å, and the lower portion of the tungsten layers (104 / 106 / 108) may have an overall lower thickness (T2) in the range of about 10 Å to about 1,000 Å. The particle size of the upper portion of the tungsten layers may be in the range of about 30 Å to about 2,000 Å. The particle size of the lower portion of the tungsten layers may be smaller than the particle size of the upper portion of the tungsten layers and may be in the range of about 30 Å to about 1,000 Å.

[0058] The tungsten liner (104) has an upper thickness (T) in the range of about 30 Å to about 100 Å. 104T It can have ). The sidewall thickness (T) of the tungsten liner (104). 104SW ) is the upper thickness (T 104T It is smaller than ) (therefore, coverage issues may occur), and can be in the range of about 5 Å to about 30 Å. Bottom thickness (T 104B ) may be in the range of about 10 Å to about 100 Å. The conformal tungsten nucleation layer (106) may have an upper thickness (T) in the range of about 0 Å (if not formed) to about 30 Å. 106T ), sidewall thickness (T 106SW ), and lower thickness (T 106B ) may have. The bulk tungsten layer (108) has an upper thickness (T) in the range of about 30 Å to about 2,000 Å. 108T ), sidewall thickness (T 108SW ), and lower thickness (T 108B Can have ).

[0059] FIG. 18 illustrates a flattening process that removes excess portions of the tungsten liner (104), nucleation layer (106), and bulk tungsten layer (108) above the ILD (92). Each process is exemplified by a process (232) in the process flow (200) as illustrated in FIG. 28. Thus, a gate contact plug (98A) is formed. In the same process for forming the gate contact plug (98A), a source / drain contact plug (98B) (Fig. 23a) may also be formed.

[0060] FIG. 27 illustrates exemplary distribution profiles of fluorine and boron when B2H6 is used to form a nucleation layer (106) and WF6 is used to form a bulk tungsten layer (108), according to some embodiments. Boron has a peak atomic percentage (and concentration) in the nucleation layer (106), and the atomic percentage (and concentration) of boron gradually decreases in the direction of entering the tungsten liner (104) and the bulk tungsten layer (108). Additionally, fluorine has a peak atomic percentage (and concentration) in the bulk tungsten layer (108), and the atomic percentage (and concentration) of fluorine gradually decreases in the direction of entering the nucleation layer (106) and the tungsten liner (104). When silane is used to form the nucleation layer (106), the silane may also have a profile similar to that of boron and may have a peak concentration in the nucleation layer (106).

[0061] FIGS. 19 through 22 illustrate the formation of a contact plug using a tungsten liner according to an alternative embodiment. Unless explicitly indicated otherwise, the material, structure, and formation process of the component in these embodiments are essentially the same as the similar component indicated by similar reference numerals in FIGS. 14 through 18 in the embodiments described above. Accordingly, details regarding the material, structure, and formation process of the component illustrated in FIGS. 19 through 22 can be identified in the discussion of the embodiments described above.

[0062] The initial processes of these embodiments are essentially the same as those shown in FIGS. 1 through 13. Next, as shown in FIG. 19, a tungsten liner (104) is formed. The formation process is essentially the same as that discussed with reference to FIG. 15 and is therefore not repeated here.

[0063] Referring to FIG. 20, a hydrogen treatment process (112) is performed to treat the tungsten liner (104) without forming a nucleation layer (106). Each process is exemplified by a process (229) in a process flow (200) as illustrated in FIG. 28. Because the tungsten liner (104) is not sufficiently conformal, some surfaces of dielectric materials, such as the mask (72), ESL (90), and ILD (92), may not be covered by the tungsten liner (104). The hydrogen treatment process (112) can create dangling bonds on the exposed dielectric material and can improve the nucleation of tungsten for the subsequent formation of a bulk tungsten layer (108).

[0064] Hydrogen treatment can be performed using a process gas containing hydrogen (H2), while an inert gas such as Ar can be added to H2. The chamber pressure can be in the range of about 1 mTorr to about 50,000 mTorr. The gas flow rate can be in the range of about 1 sccm to about 10,000 sccm. The percentage of hydrogen flow in the process gas can be in the range of about 0.1% to about 100%.

[0065] The treatment may include a thermal process (with the plasma turned off) and / or a plasma treatment process, wherein the wafer (10) may be heated and / or the plasma may be turned on. When plasma treatment is adopted, the wafer temperature may be in the range between room temperature (e.g., about 21°C) and about 500°C. When thermal treatment is adopted, the wafer temperature may be in the range of about 150°C to about 500°C. The plasma power (when plasma is adopted) may be lower than about 5,000 watts and may be in the range of about 50 watts to about 5,000 watts. The plasma may be generated via ICP, CCP, microwaves, etc. The plasma may be remote plasma or direct plasma. Additionally, the plasma may be filtered or not filtered to remove ions and leave radicals (including hydrogen radicals) for treatment.

[0066] The hydrogen treatment process (112) is performed before the deposition of the bulk tungsten layer (108). There may or may not be a vacuum break between the formation of the tungsten liner (104) and the subsequent deposition of the bulk tungsten layer (108) (Fig. 17). According to some embodiments, the hydrogen treatment process (112) may be performed in the same chamber [and in the same vacuum environment (without a vacuum break)] to deposit the bulk tungsten layer (108) (Fig. 17) so that the dangling bonds generated by the hydrogen treatment do not recombine due to exposure to air until the deposition of the bulk tungsten layer (108). According to alternative embodiments, the hydrogen treatment process (112) may be performed in a PVD chamber [and in the same vacuum environment (without a vacuum break)] to deposit the tungsten liner (104). According to another alternative embodiment, two hydrogen treatment processes (112) are performed, one hydrogen treatment process is performed in a PVD chamber, and another hydrogen treatment process is performed in the same chamber [and in the same vacuum environment (without a vacuum break)] to form a bulk tungsten layer (108) (Fig. 17).

[0067] FIG. 21 illustrates the formation of a bulk tungsten layer (108). The formation process is essentially the same as that discussed with reference to FIG. 17 and is therefore not repeated here. FIG. 22 illustrates a flattening process that forms a gate contact plug (98A). In the same process for forming the gate contact plug (98A), a source / drain contact plug (98B) is also formed, as shown in FIG. 23a.

[0068] FIG. 23b shows a perspective view of the structure shown in FIG. 23a, in which a gate contact plug (98A) and a source / drain contact plug (98B) are shown. FIG. 23c shows an alternative embodiment in which a butted contact plug (98C) is formed. The process for forming the butted contact plug (98C) is essentially the same as that shown in FIG. 14 through 22 and includes the formation of a tungsten liner. Details are not repeated herein. The tungsten liner (104) and the nucleation layer (106) will have contours along the sidewalls and bottom of the butted contact plug (98C).

[0069] FIG. 24 illustrates the formation of an upper structure comprising an ESL (114), an ILD (116), and a contact plug (118). The material, structure, and formation process may be essentially the same as the ESL (90), ILD (92), and contact plug (98), respectively, and are not repeated here.

[0070] A contact plug employing a tungsten liner can be applied to all contact plugs within an integrated circuit, including but not limited to source / drain contact plugs, gate contact plugs, upper contact plugs above source / drain contact plugs and gate contact plugs, butted contact plugs, etc. FIG. 25 illustrates a schematic top view of a logic circuit. An active region (which may be a semiconductor region for semiconductor pins, semiconductor nanostructures, etc.) (36) and a gate stack (64) are illustrated. A plurality of contact plugs (120) and upper-level contact plugs that may represent contact plugs (98 and 118) as described above are illustrated. FIG. 26 illustrates a schematic top view of a Static Random-Access Memory (SRAM) circuit. The contact plugs, vias, etc. in the illustrated top view can all be formed using embodiments of the present disclosure and are represented as 120.

[0071] Tungsten contact plugs may have two phases, an alpha phase and a beta phase. The corresponding tungsten are referred to as α-phase tungsten (α-W) and β-phase tungsten (β-W), respectively. The resistivity of β-W is much higher than that of α-W (sometimes six times higher). Experimental results have revealed that adopting the embodiments of the present disclosure increases the likelihood of forming α-phase tungsten. For example, when Ti / TiN is used to form the liners of a contact plug, 20 percent of the tungsten in the contact plug is α-phase tungsten. For comparison, when tungsten is used to form the liner of a contact plug, 100 percent of the tungsten in the contact plug is α-phase tungsten.

[0072] The embodiments of the present disclosure have several beneficial features. A contact plug formed according to an embodiment of the present disclosure has no barrier. By adopting a tungsten liner, the core within the contact plug is reduced or eliminated. This causes the volume of tungsten to increase. Additionally, more contact plugs having α-phase tungsten can be formed, which also results in a reduction of the contact plug.

[0073] According to some embodiments, the method comprises: forming a dielectric layer over a conductive feature; etching the dielectric layer to form an opening—the conductive feature is exposed through the opening—; forming a tungsten liner within the opening—the tungsten liner is in contact with the sidewall of the dielectric layer—; depositing a tungsten layer to fill the opening; and flattening the tungsten layer—parts of the tungsten layer and the tungsten liner within the opening form a contact plug. In an embodiment, the step of depositing the tungsten layer comprises depositing a tungsten nucleating layer on the tungsten liner; and depositing a bulk tungsten layer on the tungsten nucleating layer. In an embodiment, the step of depositing the tungsten nucleating layer is performed using a precursor comprising tungsten chloride. In an embodiment, the step of forming the tungsten nucleation layer is performed using a precursor containing tungsten fluoride.

[0074] In an embodiment, the step of forming the bulk tungsten layer is performed using a precursor comprising tungsten fluoride. In an embodiment, the step of forming the tungsten layer comprises: performing a hydrogen treatment process on the tungsten liner using hydrogen (H2) as a process gas; and forming a bulk tungsten layer on the tungsten liner. In an embodiment, the hydrogen treatment process includes a heat treatment process. In an embodiment, the hydrogen treatment process includes a plasma treatment process. In an embodiment, the tungsten liner and the tungsten layer do not contain titanium. In an embodiment, the contact plug includes a source / drain contact plug. In an embodiment, the contact plug includes a gate contact plug. In an embodiment, the tungsten liner comprises substantially pure tungsten.

[0075] According to some embodiments, the method comprises: forming a gate stack on a semiconductor region; forming a source / drain region on a side of the gate stack; depositing a contact etching stop layer on the source / drain region; depositing an interlayer dielectric on the contact etching stop layer; etching the interlayer dielectric and the contact etching stop layer to form a source / drain contact opening; forming a dielectric hard mask on the gate stack; etching the dielectric hard mask to form a gate contact opening; and forming a contact plug in one of the source / drain contact opening and the gate contact opening, wherein the step of forming the contact plug comprises depositing a tungsten liner via physical vapor deposition; and depositing a bulk tungsten layer on the tungsten liner via chemical vapor deposition.

[0076] In an embodiment, the tungsten liner is deposited substantially as a pure tungsten layer. In an embodiment, the method further comprises the step of performing a hydrogen treatment process on the tungsten liner between the step of depositing the tungsten liner and the step of depositing the bulk tungsten layer. In an embodiment, the method further comprises the step of depositing a nucleation layer on the tungsten liner using a fluorine-containing process gas, and the bulk tungsten layer is deposited on the nucleation layer. In an embodiment, the method further comprises the step of depositing a nucleation layer on the tungsten liner using a chlorine-containing process gas, and the bulk tungsten layer is deposited on the nucleation layer.

[0077] According to some embodiments, the method comprises the steps of forming a transistor, comprising the steps of forming a gate stack on a semiconductor region and forming a source / drain region adjacent to the gate region; and forming a contact plug within a dielectric layer, wherein the contact plug is on one of the gate stack and the source / drain region and is electrically coupled thereto, the entire contact plug is formed of tungsten, and the contact plug is in physical contact with the dielectric layer. In an embodiment, the method comprises the steps of depositing a first tungsten layer; depositing a second tungsten layer on the first tungsten layer; and depositing a third tungsten layer on the second tungsten layer, wherein the first tungsten layer, the second tungsten layer, and the third tungsten layer are deposited using different deposition methods. In an embodiment, the step of forming the contact plug comprises the step of depositing a first tungsten layer; The method includes the step of performing a processing process on the first tungsten layer using a process gas containing hydrogen (H2); and the step of forming a second tungsten layer on the first tungsten layer.

[0078] According to some embodiments, the structure comprises: a semiconductor region; a transistor—the transistor comprises a gate stack on the semiconductor region; and a source / drain region adjacent to the gate stack—; a dielectric layer on the gate stack and the source / drain region; and a tungsten-containing conductive layer, wherein the tungsten-containing conductive layer comprises: a lower portion within the dielectric layer—the lower portion is on the gate stack and in contact with the gate stack, and the lower portion has a first particle size—; and an upper portion on the dielectric layer and coupled to the lower portion—the upper portion extends laterally beyond the edge of the lower portion, and the upper portion has a second particle size larger than the first particle size. In an embodiment, the entirety of the upper portion and the lower portion is formed of tungsten, and the tungsten-containing conductive layer comprises a plurality of tungsten layers. In an embodiment, the first particle size is within a first range of about 10 Å to about 1,000 Å, and the second particle size is within a second range of about 30 Å to about 2,000 Å.

[0079] The foregoing describes an overview of the features of several embodiments to enable those skilled in the art to better understand the details of this disclosure. Those skilled in the art should recognize that this disclosure can be readily used as a basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same advantages as the embodiments disclosed herein. Furthermore, those skilled in the art should recognize that such equivalents do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications may be made without departing from the spirit and scope of this disclosure.

[0080] [Example 1]

[0081] As a method,

[0082] A step of forming a dielectric layer on a conductive feature;

[0083] A step of etching the dielectric layer to form an opening - the conductive feature is exposed through the opening - ;

[0084] Step of forming a tungsten liner within the opening - the tungsten liner is in contact with the sidewall of the dielectric layer - ;

[0085] A step of forming a tungsten layer to fill the above opening; and

[0086] Step of flattening the tungsten layer - portions of the tungsten layer and the tungsten liner within the opening form a contact plug -

[0087] A method including

[0088] [Example 2]

[0089] In Example 1,

[0090] The step of forming the above tungsten layer is,

[0091] A step of forming a tungsten nucleation layer on the above tungsten liner; and

[0092] Step of forming a bulk tungsten layer on the above tungsten nucleation layer

[0093] A method that includes

[0094] [Example 3]

[0095] In Example 2,

[0096] A method in which the step of forming the tungsten nucleation layer is performed using a precursor containing tungsten chloride.

[0097] [Example 4]

[0098] In Example 2,

[0099] A method in which the step of forming the tungsten nucleation layer is performed using a precursor containing tungsten fluoride.

[0100] [Example 5]

[0101] In Example 2,

[0102] A method in which the step of forming the bulk tungsten layer is performed using a precursor containing tungsten fluoride.

[0103] [Example 6]

[0104] In Example 1,

[0105] The step of forming the above tungsten layer is,

[0106] A step of performing a hydrogen treatment process on the tungsten liner using hydrogen (H2) as a process gas; and

[0107] Step of forming a bulk tungsten layer on the above tungsten liner

[0108] A method that includes

[0109] [Example 7]

[0110] In Example 5,

[0111] A method in which the above hydrogen treatment process includes a heat treatment process.

[0112] [Example 8]

[0113] In Example 5,

[0114] A method in which the above hydrogen treatment process includes a plasma treatment process.

[0115] [Example 9]

[0116] In Example 1,

[0117] A method in which the tungsten liner and the tungsten layer are free of titanium.

[0118] [Example 10]

[0119] In Example 1,

[0120] A method in which the above contact plug includes a source / drain contact plug.

[0121] [Example 11]

[0122] In Example 1,

[0123] A method in which the above contact plug includes a gate contact plug.

[0124] [Example 12]

[0125] In Example 1,

[0126] A method in which the above tungsten liner substantially comprises pure tungsten.

[0127] [Example 13]

[0128] As a method,

[0129] A step of forming a gate stack on a semiconductor region;

[0130] A step of forming a source / drain region on the side of the gate stack;

[0131] A step of forming a contact etching stop layer on the above source / drain region;

[0132] A step of forming an interlayer dielectric film on the above contact etching stop layer;

[0133] A step of etching the interlayer dielectric and the contact etching stop layer to form a source / drain contact opening;

[0134] A step of forming a dielectric hard mask on the gate stack above;

[0135] A step of etching the dielectric hard mask to form a gate contact opening; and

[0136] A step of forming a contact plug in one of the source / drain contact opening and the gate contact opening.

[0137] Includes,

[0138] The step of forming the above contact plug is,

[0139] A step of forming a tungsten liner film through physical vapor deposition; and

[0140] Step of forming a bulk tungsten layer on the tungsten liner through chemical vapor deposition

[0141] A method that includes

[0142] [Example 14]

[0143] In Example 13,

[0144] A method in which the above tungsten liner is formed substantially as a pure tungsten layer.

[0145] [Example 15]

[0146] In Example 13,

[0147] A method comprising further including the step of performing a hydrogen treatment process on the tungsten liner between the step of forming the tungsten liner and the step of forming the bulk tungsten layer.

[0148] [Example 16]

[0149] In Example 13,

[0150] A method further comprising the step of forming a nucleation layer on the tungsten liner using a fluorine-containing process gas, wherein the bulk tungsten layer is formed on the nucleation layer.

[0151] [Example 17]

[0152] In Example 13,

[0153] A method further comprising the step of forming a nucleation layer on the tungsten liner using a chlorine-containing process gas, wherein the bulk tungsten layer is formed on the nucleation layer.

[0154] [Example 18]

[0155] As a structure,

[0156] Semiconductor area;

[0157] Transistor - The above transistor is,

[0158] A gate stack on the semiconductor region above; and

[0159] Source / drain region adjacent to the above gate stack

[0160] Includes - ;

[0161] The above gate stack and the dielectric layer above the source / drain region; and

[0162] Tungsten-containing conductive layer

[0163] Includes,

[0164] The above tungsten-containing conductive layer is,

[0165] A lower portion within the above dielectric layer - said lower portion is above the gate stack and in contact with the gate stack, and said lower portion has a first particle size - ; and

[0166] An upper portion situated on the dielectric layer and coupled to the lower portion - the upper portion extends laterally beyond the edge of the lower portion, and the upper portion has a second particle size larger than the first particle size -

[0167] A structure that includes

[0168] [Example 19]

[0169] In Example 18,

[0170] A structure in which the entire upper portion and the lower portion are formed of tungsten, and the tungsten-containing conductive layer comprises a plurality of tungsten layers.

[0171] [Example 20]

[0172] In Example 18,

[0173] A structure in which the first particle size is within a first range of about 10 Å to about 1,000 Å, and the second particle size is within a second range of about 30 Å to about 2,000 Å.

Claims

Claim 1 A method comprising: forming a dielectric layer on a conductive feature on a substrate; etching the dielectric layer to form an opening, wherein the conductive feature is exposed through the opening; forming a tungsten liner within the opening, wherein the tungsten liner is in contact with the sidewall of the dielectric layer and the upper surface of the conductive feature; depositing a tungsten layer to fill the opening; and flattening the tungsten layer, wherein portions of the tungsten layer and the tungsten liner within the opening form a contact plug. Claim 2 A method according to claim 1, wherein the step of forming the tungsten layer comprises: forming a tungsten nucleation layer on the tungsten liner; and forming a bulk tungsten layer on the tungsten nucleation layer. Claim 3 A method according to claim 1, wherein the step of forming the tungsten layer comprises: a step of performing a hydrogen treatment process on the tungsten liner using hydrogen (H2) as a process gas; and a step of forming a bulk tungsten layer on the tungsten liner. Claim 4 A method according to claim 1, wherein the tungsten liner and the tungsten layer are free of titanium. Claim 5 A method according to claim 1, wherein the contact plug comprises a source / drain contact plug. Claim 6 A method according to claim 1, wherein the contact plug comprises a gate contact plug. Claim 7 A method according to claim 1, wherein the tungsten liner comprises pure tungsten. Claim 8 A method comprising: forming a gate stack on a semiconductor region; forming a source / drain region on a side of the gate stack; depositing a contact etching stop layer on the source / drain region; depositing an interlayer dielectric on the contact etching stop layer; etching the interlayer dielectric and the contact etching stop layer to form a source / drain contact opening; forming a dielectric hard mask on the gate stack; etching the dielectric hard mask to form a gate contact opening; and forming a contact plug in one of the source / drain contact opening and the gate contact opening, wherein the step of forming the contact plug comprises depositing a tungsten liner via physical vapor deposition—the tungsten liner contacts the upper surface of a conductive feature in one of the source / drain contact opening and the gate contact opening—; A method comprising the step of forming a bulk tungsten layer on the tungsten liner through chemical vapor deposition. Claim 9 A structure comprising: a semiconductor region; a transistor - the transistor comprises: a gate stack on the semiconductor region; and a source / drain region adjacent to the gate stack -; a dielectric layer on the gate stack and the source / drain region; and a tungsten-containing conductive layer, wherein the tungsten-containing conductive layer comprises: a lower portion within the dielectric layer - the lower portion is on the upper surface of the gate electrode of the gate stack and is in contact with the upper surface of the gate electrode, and the lower portion has a first particle size -; and an upper portion on the dielectric layer and coupled to the lower portion - the upper portion extends laterally beyond the edge of the lower portion, and the upper portion has a second particle size larger than the first particle size -. Claim 10 A structure according to claim 9, wherein the entire upper portion and the lower portion are formed of tungsten, and the tungsten-containing conductive layer comprises a plurality of tungsten layers.

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