System for Semiconductor Alignment Based on Dual Side Images

Abstract

The present disclosure relates to a dual side image-based semiconductor alignment system, wherein the positional relationship between a test pin and a ball is determined from different side images of a DUT and a socket, a Y coordinate and a Z coordinate are determined based on a first image, and an X coordinate is determined and the Y coordinate is corrected based on a second image, thereby generating position coordinates and movement control signals for aligning a test pin and a ball.

Description

Technology Field

[0001] The present disclosure relates to a semiconductor alignment system based on dual side images. Background Technology

[0002] Semiconductor test devices are essential equipment for ensuring the quality and reliability of chips manufactured in the semiconductor industry. Semiconductor test devices apply various electrical signals and patterns to a chip to be tested (e.g., referred to as a DUT (Device Under Test)), and measure and analyze the response to inspect for functional and electrical defects of the chip.

[0003] To perform tests on high-bandwidth memory such as HBM, the test socket and the HBM serving as the DUT must be combined before the test. For a successful test, the test pins of the socket and the balls of the HBM must be precisely aligned when the socket and the HBM are combined.

[0004] Conventional alignment systems can utilize mechanical alignment systems on the test side without the use of vision systems. However, mechanical alignment systems may or may not be accurate due to tolerances inherent in the mechanical system. Furthermore, conventional vision alignment systems often require utilizing space for vision systems and alignment correction mechanisms within the test-side area where space is limited. Moreover, these systems frequently require continuous runtime adjustments of the device during testing, affecting the handling time and runtime speed of the test procedure. Prior art literature

[0005] U.S. Patent Publication, US 11,867,749 B2 (January 9, 2024) The problem to be solved

[0006] These conventional methods have issues such as inaccuracy due to tolerances in the mechanical system, the need to utilize space for the vision system and alignment correction mechanism, and the impact on the handling time and runtime speed of the test procedure as the vision alignment system requires continuous runtime adjustment of the device.

[0007] The embodiments of the present disclosure aim to provide a semiconductor alignment system and a method of operation thereof for solving various problems, including the problems mentioned above.

[0008] However, these tasks are exemplary and do not limit the scope of the present disclosure. means of solving the problem

[0009] According to one aspect of the present disclosure, a semiconductor alignment system is provided, comprising: a stage; a socket including a plurality of test pins disposed on the stage to face a plurality of balls of a Device Under Test (DUT); an image sensing unit that captures the DUT and the socket to acquire a plurality of images representing the plurality of test pins and the plurality of balls; an image processing unit that calculates values ​​of position coordinates of the stage for aligning the plurality of test pins and the plurality of balls based on the plurality of images and generates a movement control signal representing the position coordinates; and a stage driving unit that moves the stage based on the movement control signal.

[0010] According to the present embodiment, the image sensing unit may include a reflective portion disposed on the sides of the socket; and a shooting unit that captures the reflective portion and acquires a plurality of reflective images representing the plurality of test pins and the plurality of balls generated in the reflective portion as the plurality of images.

[0011] According to the present embodiment, the reflector includes a first reflector panel disposed on a first side of the socket; and a second reflector panel disposed on a second side of the socket, and the imaging unit may include a first camera that photographs the first reflector panel to acquire a first reflector image showing at least one first test pin of the plurality of test pins and at least one first ball of the plurality of balls formed on the first reflector panel; and a second camera that photographs the second reflector panel to acquire a second reflector image showing at least one second test pin of the plurality of test pins and at least one second ball of the plurality of balls formed on the second reflector panel.

[0012] According to the present embodiment, the image processing unit sets a focus value corresponding to the position of the reference test pin so as to fix the focus based on the position of the reference test pin located closest to the image sensing unit among the plurality of test pins, and the image sensing unit can set the focus in response to the focus value.

[0013] According to the present embodiment, the image processing unit can reduce the resolution of the plurality of images to obtain a plurality of resized images with reduced resolution, and calculate the values ​​of the position coordinates based on the plurality of resized images.

[0014] According to the present embodiment, the image processing unit detects at least one ball of the DUT from each of the plurality of images using an artificial intelligence model, generates location information for at least one ball of the DUT for each of the plurality of images, calculates the spatial position difference values ​​between the position of the test pin and the ball based on the location information of the plurality of images, and calculates the values ​​of the position coordinates of the stage based on the spatial position difference values.

[0015] According to the present embodiment, the position information may include the number and identification information of detection areas corresponding to the detected balls, the location of the detection areas, the size of the detection areas, a focus value corresponding to an area containing the detected balls, and the angle difference of the DUT with respect to the socket.

[0016] According to the present embodiment, the image processing unit can post-process the position information based on the angle of the DUT tilted with respect to the stage.

[0017] According to the present embodiment, the image processing unit calculates values ​​of fine position coordinates of the stage for finely aligning the plurality of test pins and the plurality of balls using the detection result of the artificial intelligence model and the position information of the plurality of images, and generates a fine movement control signal representing the fine position coordinates, the stage driving unit moves the stage based on the fine movement control signal, and the image sensing unit provides the image processing unit with a plurality of captured images that capture the plurality of test pins and the plurality of balls in response to the capture control of the image processing unit.

[0018] According to one aspect of the present disclosure, a method of operating a semiconductor alignment system is provided, comprising: acquiring a first image representing at least one first test pin disposed on a first side of a socket and at least one first ball disposed on a first side of a Device Under Test (DUT); inferring first position information for the at least one first ball in the first image using an artificial intelligence model; moving a stage based on the first position information to align the at least one first test pin and the at least one first ball; acquiring a second image representing at least one second test pin disposed on a second side of the socket and at least one second ball disposed on a second side of the DUT; inferring second position information for the at least one second ball in the second image using the artificial intelligence model; and moving the stage based on the second position information to align the at least one second test pin and the at least one second ball.

[0019] Other aspects, features, and advantages other than those described above will become clear from the following specific details, claims, and drawings for implementing the invention.

[0020] In addition, these general and specific aspects may be implemented using a system, method, computer program, or any combination of a system, method, or computer program. Effects of the invention

[0021] According to an exemplary embodiment of the present disclosure, there is an effect of providing an optimal test performance environment and inducing the derivation of accurate test results.

[0022] Of course, the scope of the present disclosure is not limited by these effects. Brief explanation of the drawing

[0023] FIG. 1 is a block diagram of a semiconductor alignment system according to an exemplary embodiment of the present disclosure. FIG. 2 is a perspective view of a semiconductor alignment system according to an exemplary embodiment of the present disclosure. FIG. 3 is a drawing for explaining a method of acquiring images and video according to an exemplary embodiment of the present disclosure. FIGS. 4 and FIGS. 5 are drawings for explaining a method of adjusting the position of a stage according to an exemplary embodiment of the present disclosure. FIG. 6 is a drawing for explaining a method for calculating position coordinate values ​​of a stage according to an exemplary embodiment of the present disclosure. FIG. 7 is a drawing illustrating a method for aligning a socket and a DUT of a semiconductor alignment system according to an exemplary embodiment of the present disclosure. FIG. 8 is a flowchart illustrating a method of operation of a semiconductor alignment system according to an exemplary embodiment of the present disclosure. Specific details for implementing the invention

[0024] Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be modified and implemented in various forms. Accordingly, actual implementations are not limited to the specific embodiments disclosed, and the scope of this specification includes modifications, equivalents, or substitutions included in the technical concept described by the embodiments.

[0025] Terms such as "first" or "second" may be used to describe various components, but these terms should be interpreted solely for the purpose of distinguishing one component from another. For example, the first component may be named the second component, and similarly, the second component may be named the first component.

[0026] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0027] In the following embodiments, terms such as "comprising" or "having" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0028] In the following embodiments, when a part such as a layer, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of another part, but also cases where another region, component, etc. is interposed in between.

[0029] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and therefore the present disclosure is not necessarily limited to what is depicted.

[0030] Where an embodiment can be implemented differently, a specific sequence of operations may be performed differently from the order described. For example, two steps described consecutively may be performed substantially simultaneously or proceed in the reverse order of the description.

[0031] In this specification, “A and / or B” indicates the case where it is A, B, or both A and B. Additionally, phrases such as “at least one of A and B,” “at least one of A or B,” “at least one of A, B and C,” and “at least one of A, B, or C” may each include any one of the items listed together in the corresponding phrase, or all possible combinations thereof. For example, “at least one of A and B” indicates the case where it is A, B, or both A and B.

[0032] In the following embodiments, when layers, regions, components, etc. are described as being connected, this includes cases where the layers, regions, components are directly connected, or / or cases where other layers, regions, components are interposed between the layers, regions, components to form an indirect connection. For example, when layers, regions, components, etc. are described as being electrically connected in this specification, it indicates cases where the layers, regions, components, etc. are directly electrically connected, and / or cases where other layers, regions, components, etc. are interposed between them to form an indirect electrical connection.

[0033] The x-axis, y-axis, and z-axis are not limited to the three axes of an orthogonal coordinate system but can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0034] The advantages and features of the present disclosure and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure is complete and to fully inform those skilled in the art of the scope of the present disclosure, and the present disclosure is defined only by the scope of the claims.

[0035] The terms used in this disclosure are for describing the embodiments and are not intended to limit this disclosure. In this disclosure, the singular form may include the plural form unless specifically stated otherwise in the text. The terms “comprises” and / or “comprising” used in this disclosure do not exclude the presence or addition of one or more other components in addition to the components mentioned. Throughout the disclosure, the same reference numerals refer to the same components, and “and / or” may include each of the mentioned components and all combinations of one or more. Although terms such as “first,” “second,” etc., are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of this disclosure.

[0036] The word "exemplary" is used in this disclosure to mean "used as an example or illustration." Any embodiment described as "exemplary" in this disclosure should not be interpreted as being preferred or having an advantage over other embodiments.

[0037] Embodiments of the present disclosure may be described in terms of a function or a block performing a function.

[0038] The term “module” in this disclosure may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit, for example. A “module” may be a component formed integrally or a minimum unit of a component or part thereof that performs one or more functions. For example, according to one embodiment, a “module” may be implemented in the form of an application-specific integrated circuit (ASIC).

[0039] The term “part” in this disclosure refers to a software or hardware component, such as an FPGA or ASIC, and the “part” performs certain roles. However, the “part” is not limited to software or hardware. The “part” may be configured to reside in an addressable storage medium or configured to operate one or more processors. For example, the “part” may include components such as software components, object-oriented software components, class components, and task components, as well as processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided within the components and “parts” may be combined into a smaller number of components and “parts” or further separated into additional components and “parts.” Furthermore, the components and “parts” may be implemented to operate one or more CPUs within a device or secure multimedia card. Additionally, "~part" may include one or more processors.

[0040] Embodiments of the present disclosure may be implemented using at least one software program running on at least one hardware device and may perform network management functions to control elements.

[0041] Spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used to facilitate the description of the relationship between one component and other components as illustrated in the drawings. Spatially relative terms should be understood as encompassing different orientations of components during use or operation, in addition to the orientations depicted in the drawings. For example, if a component depicted in a drawing is inverted, a component described as "below" or "beneath" of another component may be placed "above" of that component. Therefore, the exemplary term "below" may encompass both the lower and upper directions. Components may also be oriented in other directions, and accordingly, spatially relative terms may be interpreted according to the orientation.

[0042] Unless otherwise defined, all terms used in this disclosure (including technical and scientific terms) may be used in a meaning commonly understood by those skilled in the art to which this disclosure pertains. Additionally, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise.

[0043] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0044] FIG. 1 is a block diagram of a semiconductor alignment system (100) according to an exemplary embodiment of the present disclosure.

[0045] Referring to FIG. 1, the semiconductor alignment system (100) may include a stage (110), a socket (120), an image sensing unit (130), and an image processing unit (140), etc.

[0046] The stage (110) can accommodate or support components of the semiconductor alignment system (100). For example, a socket (120), an image sensing unit (130), and an image processing unit (140), etc., may be placed on or connected to the stage (110).

[0047] A socket (120) may be placed on a stage (110). The socket (120) may be coupled with a Device Under Test (DUT). The DUT may be a semiconductor device capable of receiving various electrical signals and pattern data, and may output or store data. For example, a memory device such as High Bandwidth Memory (HBM) may be the DUT. As a DUT, the HBM may include a substrate, a silicon interposer, a plurality of dies, a plurality of Through Silicon Via (TSVs), a plurality of microbumps, and a plurality of balls. The socket (120) may include and be equipped with a plurality of test pins (121), and the plurality of test pins (121) may be placed on the stage (110) to face the plurality of balls of the HBM.

[0048] The image sensing unit (130) can capture the DUT and the socket (120) to obtain multiple images showing the plurality of test pins (121) and the plurality of balls of the HBM.

[0049] In one embodiment, the image sensing unit (130) may include a reflection unit (131) and a shooting unit (133). The reflection unit (131) may be disposed on the sides of the socket (120). For example, the reflection unit (131) may include at least one test pin and at least one ball of the HBM and may reflect an image formed on the reflection unit (131). The shooting unit (133) may photograph the reflection unit (131) to obtain a plurality of reflection images representing a plurality of test pins and a plurality of balls generated (e.g. formed) on the reflection unit (131).

[0050] The image processing unit (140) can control various operations of the semiconductor alignment system (100) overall. The image processing unit (140) (e.g., an application processor) can access memory (150) and execute one or more instructions. The image processing unit (140) may be implemented as a computer or a similar device according to hardware, software, or a combination thereof. In terms of hardware, the image processing unit (140) may be provided in the form of an electronic circuit that processes electrical signals to perform control functions, and in terms of software, it may be provided in the form of a program that drives the hardware image processing unit (140).

[0051] The image processing unit (140) can calculate the values ​​of the position coordinates of the stage (110) for aligning the plurality of test pins (121) and the plurality of balls based on the plurality of images, and generate a movement control signal representing the position coordinates.

[0052] In one embodiment, the image processing unit (140) may include a preprocessing unit (141), a postprocessing unit (143), and an artificial intelligence (hereinafter, AI) engine (145). The preprocessing unit (141) may preprocess an image and / or stream of images provided by the image sensing unit (130). The postprocessing unit (143) may postprocess the processing results of the AI ​​engine (145), etc. The AI ​​engine (145) may infer a result desired by the user using artificial intelligence on the preprocessed image, or learn from the preprocessed image. Functions related to artificial intelligence according to the present disclosure may be operated through the AI ​​engine (145) and memory (150) of the image processing unit (140).

[0053] The image processing unit (140) can execute one or more instructions stored in memory (150). The image processing unit (140) may be composed of one or more image processing units (140). In this case, the one or more image processing units (140) may be a general-purpose image processing unit (140) such as a CPU, AP, DSP (Digital Signal Processor), a graphics-dedicated image processing unit (140) such as a GPU, VPU (Vision Processing Unit), or an artificial intelligence-dedicated image processing unit (140) such as an NPU. The one or more image processing units (140) control input data to be processed according to predefined operation rules or artificial intelligence models stored in memory (150). Alternatively, if the one or more image processing units (140) are artificial intelligence-dedicated image processing units (140), the artificial intelligence-dedicated image processing units (140) may be designed with a hardware structure specialized for processing a specific artificial intelligence model.

[0054] The predefined operating rules or artificial intelligence models are characterized by being created through learning. Here, being created through learning means that a predefined operating rules or artificial intelligence models configured to perform desired characteristics (or objectives) are created by a basic artificial intelligence model being trained using multiple learning data by a learning algorithm. Such learning may be performed on the device itself where the artificial intelligence according to the present disclosure is executed, or it may be performed through a separate server and / or system. Examples of learning algorithms include supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but are not limited to the examples described above.

[0055] An artificial intelligence model may be composed of multiple neural network layers. Each of the multiple neural network layers has multiple weight values ​​and performs neural network operations through operations between the results of previous layers and the multiple weights. The multiple weights possessed by the multiple neural network layers can be optimized based on the learning results of the artificial intelligence model. For example, the multiple weights may be updated so that the loss value or cost value obtained by the artificial intelligence model during the learning process is reduced or minimized. Artificial neural networks may include deep neural networks (DNNs), such as Convolutional Neural Networks (CNNs), Deep Neural Networks (DNNs), Recurrent Neural Networks (RNNs), Restricted Boltzmann Machines (RBMs), Deep Belief Networks (DBNs), Bidirectional Recurrent Deep Neural Networks (BRDNNs), or Deep Q-Networks, but are not limited to the examples mentioned above.

[0056] According to an exemplary embodiment of the present disclosure, the image processing unit (140) can implement artificial intelligence. Artificial intelligence refers to a machine learning method based on an artificial neural network that mimics human biological neurons to enable a machine to learn. The methodology of artificial intelligence can be classified according to the learning method into supervised learning, where input data and output data are provided together as training data and the solution (output data) to the problem (input data) is determined; unsupervised learning, where only input data is provided without output data and the solution (output data) to the problem (input data) is not determined; and reinforcement learning, where a reward is given from an external environment whenever an action is taken in the current state, and learning proceeds in a direction that maximizes such reward. In addition, artificial intelligence methodologies can be classified according to the architecture, which is the structure of the learning model. The architectures of widely used deep learning technologies can be classified into Convolutional Neural Networks (CNN), Recurrent Neural Networks (RNN), Transformers, and Generative Adversarial Networks (GAN).

[0057] The device and system may include an artificial intelligence model. The artificial intelligence model may be a single model or may be implemented as multiple models. The artificial intelligence model may be composed of a neural network (or artificial neural network) and may include statistical learning algorithms that mimic biological neurons in machine learning and cognitive science. A neural network may refer to a model that possesses problem-solving capabilities by having artificial neurons (nodes) that form a network through synaptic connections and change the strength of synaptic connections through learning. The neurons of a neural network may include combinations of weights or biases. A neural network may include one or more layers composed of one or more neurons or nodes. For example, the device may include an input layer, a hidden layer, and an output layer. The neural network constituting the device can infer a result (output) to be predicted from an arbitrary input by changing the weights of the neurons through learning.

[0058] The image processing unit (140) can generate a neural network, train or learn a neural network, perform operations based on received input data, generate an information signal based on the results of the operation, or retrain the neural network. The neural network models may include, but are not limited to, various types of models such as Convolutional Neural Networks (CNN), Region with Convolutional Neural Networks (R-CNN), Region Proposal Networks (RPN), Recurrent Neural Networks (RNN), Stacking-based Deep Neural Networks (S-DNN), State-Space Dynamic Neural Networks (S-SDNN), Deconvolution Networks, Deep Belief Networks (DBN), Restructured Boltzmann Machines (RBM), Fully Convolutional Networks, Long Short-Term Memory Networks (LSTM), and Classification Networks, such as GoogleNet, AlexNet, and VGG Network. The image processing unit (140) can perform operations on one or more images according to the neural network models. It may include a processing unit (140). For example, the neural network may include a deep neural network.

[0059] Neural networks include CNN (Convolutional Neural Network), RNN (Recurrent Neural Network), perceptron, multilayer perceptron, FF (Feed Forward), RBF (Radial Basis Network), DFF (Deep Feed Forward), LSTM (Long Short Term Memory), GRU (Gated Recurrent Unit), AE (Auto Encoder), VAE (Variational Auto) Encoder), DAE (Denoising Auto Encoder), SAE (Sparse Auto Encoder), MC (Markov Chain), HN (Hopfield Network), BM (Boltzmann Machine), RBM (Restricted Boltzmann Machine), DBN (Depp Belief Network), DCN (Deep Convolutional Network), DN (Deconvolutional Network), DCIGN (Deep Convolutional Inverse Graphics Network), GAN (Generative Adversarial Network), LSM (Liquid State Machine), ELM (Extreme Learning Machine), ESN (Echo It will be understood by a person skilled in the art that any neural network may be included, but is not limited to, State Network, Deep Residual Network, Differential Neural Computer, Neural Turning Machine, Capsule Network, Kohonen Network, and Attention Network.

[0060] According to an exemplary embodiment of the present disclosure, the image processing unit (140) includes a Convolutional Neural Network (CNN) such as GoogleNet, AlexNet, VGG Network, Region with Convolutional Neural Network (R-CNN), Region Proposal Network (RPN), Recurrent Neural Network (RNN), Stacking-based Deep Neural Network (S-DNN), State-Space Dynamic Neural Network (S-SDNN), Deconvolution Network, Deep Belief Network (DBN), Restructured Boltzmann Machine (RBM), Fully Convolutional Network, Long Short-Term Memory Network (LSTM), Classification Network, Generative Modeling, eXplainable AI, Continual AI, Representation Learning, AI for Material Design, BERT, SP-BERT, MRC / QA, Text Analysis, Dialog System, GPT-3, GPT-4 for natural language processing, Visual Analytics, Visual Understanding, Video Synthesis for vision processing, Anomaly Detection, Prediction, Time-Series for ResNet data intelligence Various artificial intelligence structures and algorithms, such as forecasting, optimization, recommendation, and data creation, may be used, but are not limited thereto.

[0061] The memory (150) can store data for a program that reproduces a model or algorithm for controlling the operation of components within the device, and can be implemented as at least one image processing unit (140) that performs the aforementioned operation using the data stored in the memory (150). Here, the memory (150) and the image processing unit (140) can each be implemented as separate chips. In addition, the memory (150) and the image processing unit (140) can be implemented as a single chip. The memory (150) can store data supporting various functions of the device and a program for the operation of the image processing unit (140), and can store input / output data, and can store a plurality of application programs (or applications) running on the device, data for the operation of the device, commands, and one or more instructions. At least some of these application programs can be downloaded from an external server via wireless communication. The memory (150) and the image processing unit (140) can each be implemented as separate chips. Additionally, the memory (150) and the image processing unit (140) may be implemented as a single chip.

[0062] The memory (150) may include at least one type of storage medium among flash memory type, hard disk type, SSD type (Solid State Disk type), SSD type (Silicon Disk Drive type), multimedia card micro type, card type memory (e.g., SD or XD memory, etc.), RAM (random access memory; RAM), SRAM (static random access memory), ROM (read-only memory; ROM), EEPROM (electrically erasable programmable read-only memory), PROM (programmable read-only memory), magnetic memory, magnetic disk, and optical disk. Additionally, the memory (150) may be a database that is separated from the device but connected via wired or wireless connection.

[0063] The memory (150) can temporarily store data and can provide the stored data to the image processing unit (140) under the control of the image processing unit (140). The database can store various data sets.

[0064] The stage drive unit (160) can move the stage (110) based on a movement control signal. For example, the stage drive unit (160) can move the stage (110) linearly forward, backward, left, and right on a two-dimensional plane. For example, the stage drive unit (160) can move the stage (110) linearly up and down in a three-dimensional space.

[0065] FIG. 2 is a perspective view of a semiconductor alignment system (200) according to an exemplary embodiment of the present disclosure.

[0066] Referring to FIGS. 1 and 2, the semiconductor alignment system (200) may correspond to the semiconductor alignment system (100). The DUT (20) may be, for example, an HBM. The DUT (20) may be positioned to face a socket (not shown in FIG. 2) placed on the stage (210). That is, the socket may be located below the DUT (20).

[0067] In one embodiment, the reflector (131) of the semiconductor alignment system (100) may include a plurality of reflector panels. Referring to FIG. 2, for example, the semiconductor alignment system (200) may include first and second reflector panels (231, 233) disposed on a stage (210). Each of the first and second reflector panels (231, 233) may be disposed on the side of the socket (120) and the DUT (20). For example, the first reflector panel (231) may be disposed at a position spaced apart from the first side of the socket (120) and the DUT (20) in the Z-axis direction. The second reflector panel (233) may be disposed at a position spaced apart from the second side of the socket (120) and the DUT (20) in the X-axis direction. In an exemplary embodiment, the reflector panels may be implemented as planar mirrors, but are not limited thereto.

[0068] In one embodiment, the imaging unit (133) of the semiconductor alignment system (100) may include a plurality of cameras. Referring to FIG. 2, for example, the semiconductor alignment system (200) may include first and second cameras (232, 234) disposed on a stage (210). For example, the first camera (232) may be disposed alongside the first reflective panel (231) in the Z-axis direction. The first camera (232) may photograph the first reflective panel (231) to obtain a first reflected image showing at least one first test pin of the plurality of test pins and at least one first ball of the plurality of balls formed on the first reflective panel (231). The second camera (234) may be disposed alongside the second reflective panel (233) in the X-axis direction. The second camera (234) can photograph the second reflective panel (233) to obtain a second reflective image showing at least one second test pin of the plurality of test pins and at least one second ball of the plurality of balls formed on the second reflective panel (233).

[0069] A camera system comprising first and second reflective panels (231, 233) and first and second cameras (232, 234) in a semiconductor alignment system (200) may be dependent on and fixed to a stage (210). The object to be aligned is a test pin of a socket connected to a bumper and / or ball of an HBM. The HBM may be tilted rather than moving in a straight line. The semiconductor alignment system (200) can align the test pins of the socket with the bumpers and balls of the HBM by fine-tuning the stage (210). Due to the structural characteristics of the stage (210), the object to be aligned may be obtained through an image and / or video reflected on the reflective panel. The position of the test pin in the reflected image and / or video may be assumed to be fixed. The test pin connected to the HBM can be aligned by moving the stage (210).

[0070] A semiconductor alignment system (200) according to one embodiment includes two reflective panels and two cameras, but the present disclosure is not limited to the aforementioned embodiment. A semiconductor alignment system (200) according to another embodiment includes four reflective panels and four cameras, and each reflective panel and each camera may be spaced apart from one side of the socket and DUT (20). In this case, a reflective image may be acquired by each of the four cameras, and a total of four reflective images may be used.

[0071] The semiconductor alignment system (200) of the present disclosure performs precise alignment between a device and a socket (or contactor) in a test handler environment, controls and corrects the driving of a stage through camera-based vision feedback, calculates position deviations through multiple vision paths, and performs position and attitude correction in three dimensions based on the said values. The semiconductor alignment system (200) of the present disclosure is based on a mirror reflection image (oblique view) or the front and side placement of dual cameras, and can utilize inference and alignment logic through a pipeline that utilizes AI-based object detection and focus values ​​and resizes the resolution from high resolution to low resolution (e.g., 2448×2048 to 640×640). The semiconductor alignment system (200) of the present disclosure can provide a control sequence that calculates the position difference value between the test pin of the socket and the ball of the HBM as the position change coordinate of the stage (210), along with coarse or preliminary, location, and fine or precise adjustment procedures.

[0072] The semiconductor alignment system (200) of the present disclosure can increase contact reliability by calculating the positional error between the ball of the HBM and the pin of the socket through camera and sensor-based vision feedback and precisely controlling the stage drive unit (160). In addition, the semiconductor alignment system (200) of the present disclosure calculates the coordinates of the stage (210) for aligning the ball of the HBM and the pin of the socket through observation at multiple viewpoints, and the position and orientation in three dimensions (e.g., It can have a closed-loop structure called ) correction.

[0073] The semiconductor alignment system (200) of the present disclosure may include a deep learning-based image processing pipeline that detects AI objects through a planar mirror and an auxiliary dual camera and 15° angled shooting, resizes the resolution from high resolution to low resolution, and utilizes focus values. Additionally, the semiconductor alignment system (200) of the present disclosure may be optimized for high-pitch and high-precision environments by integrating the aforementioned three-stage adjustment procedure (e.g., preliminary, positioning, precision) algorithm and HBM-specific control logic with ±5 μm precision.

[0074] FIG. 3 is a drawing for explaining a method of acquiring images and video according to an exemplary embodiment of the present disclosure.

[0075] Referring to FIGS. 2 and 3, the ball (31) of the HBM, the stage (310), the test pin (321), the reflection panel (331), and the camera (333) shown in FIG. 3 are exemplary side views of the semiconductor alignment system (200) of FIG. 2 based on the YZ plane. A socket placed on the stage (310) may be coupled with the HBM, and the test pin (321) and the ball (31) may be in contact or connected. Images representing the test pin (321) of the socket and the ball (31) of the HBM may be formed on the reflection panel (331). The camera (330) may capture the reflection image formed on the reflection panel (331). The object to be obtained through the reflection image may be the test pin (321) and the ball (31). The resolution of the reflection image may be high, for example, 2448×2048. The camera (330) can provide a stream of multiple reflection images (IMGS1) to the preprocessing unit (341). For example, the camera (330) can transmit the stream of multiple reflection images (IMGS1) to the preprocessing unit (341) at approximately 20 fps using Giga Ethernet, etc. The preprocessing unit (341) can reduce the resolution of the stream of multiple reflection images (IMGS1) for AI inference to obtain a stream of multiple resized images (IMGS2) with reduced resolution, and provide the stream of multiple resized images (IMGS2) to the AI ​​engine (345). The resolution of the resized images may be low resolution, for example, 640×640. The AI ​​engine (345) can infer the values ​​of the position coordinates of the stage (310) based on the stream of multiple resized images (IMGS2).

[0076] FIGS. 4 and FIGS. 5 are drawings for explaining a method of adjusting the position of a stage (410) according to an exemplary embodiment of the present disclosure.

[0077] Referring to FIGS. 1 and 4, the preprocessing unit (141) of the image processing unit (140) sets a focus value corresponding to the position of the reference test pin (421a) to fix the focus based on the position of the reference test pin (421a) located closest to the plane mirror (431) of the image sensing unit (130) among the plurality of test pins (421), and the camera (433) of the image sensing unit (130) can set the focus on the focus area (FA1) in response to the focus value. That is, the camera (433) can fix and set the focus on the first test pin placed closest to it.

[0078] The balls (32) placed on the substrate (31) of the HBM (30) and the test pins (421) of the socket (420) are reflected by the flat mirror (431), and the camera (433) can acquire an image (PIC1) by capturing the image formed on the flat mirror (431). The image processing unit (140) can calculate the position coordinates of the stage (410) so that the number and position results of the balls (32) of the HBM (30) are the same as the object detection result (OBDET) in the image (PIC1). The stage drive unit (160) can move the stage (410) in a straight line in the X-axis and / or Y-axis direction according to the position coordinates of the stage (410) calculated through the image processing unit (140), and the alignment position of the stage (410) can be fixed after it has been moved until the balls (32) of the HBM (30) and the test pins (421) of the socket (420) are aligned, as in the object detection result (OBDET).

[0079] Referring to FIG. 2, the camera (433) may be the first camera (232) (or the second camera (234)), and if the camera (433) is the first camera (232), the X and Y coordinates of the stage (410) may be determined, and similarly as shown in FIG. 4, the Z coordinate of the stage (410) for aligning the balls (32) and test pins (421) may be determined using an image acquired by the second camera (234), and additionally, the Y coordinate may be corrected. In this way, the position coordinates of the stage (410) are calculated sequentially, and the position of the stage (410) may be finally determined.

[0080] Meanwhile, the substrate (31) of the HBM (30) may be tilted relative to the stage (410) and socket (420), and the post-processing unit (143) can correct position information by considering the degree of tilt of the HBM (30) relative to the stage (410) and socket (420) in the image (PIC1).

[0081] Referring to FIG. 5, the image processing unit (140) can finally determine the position of the stage (110) based on the first and second images (FPIC1, SPIC2) obtained from each of the first and second cameras (232, 234) as described above with reference to FIG. 2 and FIG. 4. For example, with reference to FIG. 2, the first image (FPIC1) may be an image obtained by the first camera (232), and the second image (SPIC2) may be an image obtained by the second camera (233). However, the present disclosure is not limited to the examples described above.

[0082] The image processing unit (140) can infer location information (LOINFO1, LOINFO2) from each of the first and second images (FPIC1, SPIC2) using an artificial intelligence model. Each location information may include, for example, the left, top, width, and height of the detected box, the number and identification number of the boxes, the ball detection area focus value, and the angle difference. The image processing unit (140) can apply the aforementioned values ​​of the location information (LOINFO1, LOINFO2) to an algorithm (ALGM) that determines the position to which the stage (110) moves, and can calculate the location coordinate values ​​of the stage (110) calculated through the said algorithm (ALGM).

[0083] The stage drive unit (160) can move the stage (110) to a position (STGLO) corresponding to the calculated position coordinate values ​​of the stage (110).

[0084] FIG. 6 is a drawing for explaining a method for calculating position coordinate values ​​of a stage according to an exemplary embodiment of the present disclosure.

[0085] Referring to FIG. 6, for example, images (611, 612) resized to a low resolution of 640×640 (640 unit pixels each for the width and height) may be provided to AI engines (621, 622). The AI ​​engines (621, 622) may detect at least one ball of the HBM from the resized images (611, 612) using an artificial intelligence model. The AI ​​engines (621, 622) may generate location information for at least one ball of the HBM for each of the plurality of images. For example, the AI ​​engines (621, 622) may detect location information (631, 632) from the resized images (611, 612). Each location information may include the number and identification information of detection areas corresponding to the detected balls, the location of the detection areas, the size of the detection areas, a focus value corresponding to the area containing the detected balls, and the angle difference of the HBM with respect to the socket.

[0086] AI engines (621, 622) and / or post-processing unit (640) can calculate the spatial position difference values ​​of the test pin and the ball based on the position information of a plurality of images, and calculate the values ​​of the position coordinates of the stage (110) based on the spatial position difference values.

[0087] FIG. 7 is a drawing illustrating a method for aligning a socket and a DUT of a semiconductor alignment system according to an exemplary embodiment of the present disclosure.

[0088] Referring to FIG. 7, in step S100, a front camera stream may be provided. The front camera stream is, for example, a stream of reflected images captured by the first camera (232) with reference to FIG. 2, provided to the image processing unit (140).

[0089] In step S110, image processing may be performed. For example, the image processing unit (140) may detect a ball based on a first image of the first camera (232) and calculate position coordinate values ​​of the stage (110) for aligning the test pin and the ball.

[0090] If the test pin and ball are not aligned in the first image currently received, a stage control operation may be performed in step S120. For example, the stage (110) may be moved by the stage drive unit (160) according to the calculated position coordinate values ​​of the stage (110) (e.g., X coordinate value and Y coordinate value), and the Z-axis may be maintained by an angle. After step S120, the first image capture operation continues, and steps S100 and S110 may be performed.

[0091] In step S130, the image processing unit (140) can infer position information from the front camera. The position information is as described above with reference to FIG. 5. The position information can be used to calculate the stage position coordinate values ​​in step S110.

[0092] If the test pin and the ball are aligned in the first image currently received, a side camera stream may be provided in step S200. The side camera stream is, for example with reference to FIG. 2, a stream of reflected images captured by the second camera (234) is provided to the image processing unit (140).

[0093] In step S210, image processing may be performed. For example, the image processing unit (140) may detect a ball based on a second image of the second camera (234) and calculate position coordinate values ​​of the stage (110) for aligning the test pin and the ball.

[0094] If the test pin and ball are not aligned in the currently received second image, a stage control operation may be performed in step S220, and after step S220, a second image capture operation continues, and steps S200 and S210 may be performed.

[0095] In step S230, the image processing unit (140) can infer position information from the side camera. The position information is as described above with reference to FIG. 5. The position information can be used to calculate the stage position coordinate values ​​in step S210.

[0096] In one embodiment, at each of steps S110 and S210, the image processing unit (140) can post-process the position information based on the angle of the HBM tilted with respect to the stage (110).

[0097] In one embodiment, the image processing unit (140) can calculate values ​​of fine position coordinates of the stage for finely aligning the plurality of test pins and the plurality of balls using the detection result of the artificial intelligence model and the position information of the plurality of images, and generate a fine movement control signal representing the fine position coordinates. Then, the stage driving unit (160) can move the stage based on the fine movement control signal. And, the image sensing unit (130) can provide the image processing unit (140) with a plurality of captured images that capture the plurality of test pins and the plurality of balls in response to the capture control of the image processing unit (140).

[0098] Referring to FIG. 7, for example, in step S300, the image processing unit (140) can perform fine-tuning from the AI ​​inference result of the AI ​​engine and / or image information using a final alignment algorithm. If fine-tuning is completed, alignment for testing a DUT, such as an HBM, is completed.

[0099] If further fine-tuning is required, a control action to move the stage (110) is performed in step S300, and the X coordinate value, Y coordinate value, and / or Z coordinate value of the stage (110) may be changed. When fine-tuning is completed, front camera capture (e.g., see step S100) and side camera capture (e.g., see step S200) may be performed in step S320, fine-tuning may be retried, and step S300 may be performed.

[0100] FIG. 8 is a flowchart illustrating a method of operation of a semiconductor alignment system according to an exemplary embodiment of the present disclosure.

[0101] Referring to FIG. 8, in step S1000, the semiconductor alignment system (100) of the present disclosure may acquire a first image showing at least one first test pin disposed on the first side of the socket (120) and at least one first ball disposed on the first side of the DUT (e.g., HBM). Referring to FIG. 2 and FIG. 3, for example, a camera (333) corresponding to the first camera (232) may acquire a reflected image through a reflective panel (331).

[0102] In step S1100, the semiconductor alignment system (100) of the present disclosure can infer first position information for the at least one first ball in the first image using an artificial intelligence model. For example, with reference to FIGS. 3 to 7, an AI engine (145) can infer position information of the first test pin and the first ball using the first image.

[0103] In step S1200, the semiconductor alignment system (100) of the present disclosure may move the stage (110) based on the first position information to align at least one first test pin and at least one first ball. Referring to FIGS. 4 through 7, for example, an AI engine (145) may infer and calculate the position coordinates of the stage (110) based on the position information of the first test pin and the first ball. The post-processing unit (143) may provide a movement control signal corresponding to the position coordinates of the stage (110) to be moved to the stage driving unit (160), and the stage driving unit (160) may move the stage (110).

[0104] In step S1300, the semiconductor alignment system (100) of the present disclosure may acquire a second image showing at least one second test pin disposed on the second side of the socket (120) and at least one second ball disposed on the second side of the DUT (e.g., HBM). For example, with reference to FIG. 2, a second camera (234) may acquire a reflected image through a second reflective panel (233) similar to as described above with reference to FIG. 3.

[0105] In step S1400, the semiconductor alignment system (100) of the present disclosure can infer second position information for the at least one second ball in the second image using an artificial intelligence model. An embodiment of step S1400 is the same as the embodiment described above with reference to FIGS. 4 to 7.

[0106] In step S1500, the semiconductor alignment system (100) of the present disclosure may move the stage (110) based on the second position information to align at least one second test pin and at least one second ball. An embodiment of step S1500 is the same as the embodiment described above with reference to FIGS. 4 to 7.

[0107] As described above, the present disclosure can optimize test results in high-pitch and high-precision environments and improve test performance.

[0108] Although the present disclosure has been described with reference to embodiments illustrated in the drawings, this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0109] 100: Semiconductor alignment system 110: Stage 120: Socket 121: Multiple test pins 130: Image sensing unit 131: Reflective part 133: Filming Department 140: Image processing unit 141: Preprocessing section 143: Post-processing section 145: AI Engine 150: Memory 160: Stage drive unit

Claims

Claim 1 A semiconductor alignment system comprising: a stage; a socket including a plurality of test pins disposed on the stage to face a plurality of balls of a DUT; an image sensing unit comprising a first reflective panel and a second reflective panel disposed respectively on a first side and a second side of the socket, and a first camera and a second camera disposed respectively alongside the first reflective panel and the second reflective panel to acquire a first image and a second image respectively by capturing the test pin and the ball formed on each reflective panel, wherein the first camera and the second camera capture the DUT and the socket from different sides and acquire a plurality of images including the first image and the second image; an image processing unit that calculates position coordinates of the stage for aligning the test pin and the ball by determining the X coordinate and Y coordinate of the stage based on the first image and the Z coordinate of the stage based on the second image respectively and further correcting the Y coordinate, and generates a movement control signal representing the position coordinates; and a stage driving unit that moves the stage based on the movement control signal. Claim 2 delete Claim 3 A semiconductor alignment system according to claim 1, wherein the first camera and the second camera are fixed to the stage, and the image processing unit sets the position of the test pin in the plurality of images as a fixed reference position and calculates the position coordinates of the stage based on the relative position of the ball with respect to the fixed reference position. Claim 4 A semiconductor alignment system according to claim 1, wherein the image processing unit detects at least one ball of the DUT from each of the plurality of images using an artificial intelligence model, generates position information for the detected ball for each of the plurality of images, calculates a spatial position difference value between the position of the test pin and the position of the ball based on the position information generated for each of the plurality of images, and calculates the position coordinates of the stage based on the spatial position difference value. Claim 5 A semiconductor alignment system according to claim 1, wherein the image processing unit detects at least one ball of the DUT from each of the plurality of images using an artificial intelligence model, generates position information for the detected ball for each of the plurality of images, and the position information includes the number and identification information of detection areas corresponding to the detected ball, the position of the detection area, the size of the detection area, a focus value corresponding to an area including the detected balls, and the angle difference of the DUT with respect to the socket. Claim 6 A semiconductor alignment system according to claim 1, wherein the image processing unit generates position information for a ball of the DUT from the plurality of images, post-processes the position information based on the angle of the DUT tilted with respect to the stage, and calculates a spatial position difference value between the position of the test pin and the position of the ball based on the post-processed position information. Claim 7 A semiconductor alignment system according to claim 1, wherein the image processing unit reduces the resolution of the plurality of images to obtain a plurality of resized images, detects at least one ball of the DUT from each of the plurality of resized images using an artificial intelligence model, and calculates the position coordinates of the stage based on the detection results for the plurality of resized images. Claim 8 A semiconductor alignment system according to claim 1, wherein each of the first reflective panel and the second reflective panel is a flat mirror that reflects the test pin and the ball, and either the first camera or the second camera is called a reference camera, and the reflective panel captured by the reference camera is called a reference reflective panel, wherein the image processing unit sets a focus value corresponding to the position of the reference test pin to fix the focus of the reference camera based on the position of the reference test pin located closest to the reference reflective panel among the plurality of test pins, and the reference camera sets a focus in a focus area corresponding to the reference test pin in response to the focus value. Claim 9 A semiconductor alignment system according to claim 1, wherein the image processing unit detects at least one ball of the DUT from each of the plurality of images using an artificial intelligence model, generates position information for the detected ball for each of the plurality of images, calculates fine position coordinates of the stage for fine alignment using the ball detection result and the position information generated for each of the plurality of images, generates a fine movement control signal representing the fine position coordinates, the stage driving unit moves the stage based on the fine movement control signal, and the image sensing unit provides the image processing unit with a plurality of captured images capturing the test pin and the ball in response to the capture control of the image processing unit. Claim 10 A semiconductor alignment system according to claim 1, wherein the image processing unit detects at least one ball of the DUT from each of the plurality of images using an artificial intelligence model, generates position information for the detected ball for each of the plurality of images, calculates fine position coordinates of the stage for fine alignment using the ball detection result and the position information generated for each of the plurality of images, generates a fine movement control signal representing the fine position coordinates, receives image information based on a captured image acquired by the image sensing unit in response to the capture control of the image processing unit, performs fine adjustment for the fine alignment from the ball detection result and the image information using a final alignment algorithm, and if the fine adjustment is not completed, recalculates the fine position coordinates and regenerates the fine movement control signal.

Images