Cache for storing coherent and non-coherent data

Abstract

The present invention advantageously provides a system cache and a method for storing coherent data and non-coherent data in a system cache. A transaction is received from a source in the system, the transaction includes at least a memory address, the source has a location within a coherent domain or a non-coherent domain of the system, the coherent domain includes shareable data, and the non-coherent domain includes non-shareable data. It is determined whether the memory address is stored in a cache line, and when it is not determined that the memory address is stored in a cache line, a status bit of the allocated cache line is set to indicate whether the shareable data or non-shareable data is stored in the allocated cache line based on the source location, thereby allocating the cache line to the transaction and processing the transaction.

Description

Background Technology

[0001] The present invention relates to a data processing system. More specifically, the present invention relates to a cache for a data processing system.

[0002] A data processing system may include a system-on-chip (SoC) having various components connected by one or more interconnects. Generally, certain components, such as processors like central processing units (CPUs) and CPU clusters, and accelerators like graphics processing units (GPUs) and GPU clusters, process data, while other components, such as memory controllers, input / output (I / O) controllers, and network interface controllers, transmit data to and receive data from the data processing components. These data provisioning components may be connected to on-chip or off-chip memory, data buses, wired or wireless networks, etc. The interconnects provide a network infrastructure through which data transactions between the components are transmitted. The data processing system may be divided into coherent domains and non-coherent domains.

[0003] A cache storing coherent data resides within the coherent domain of a data processing system and is coupled to (or resides within) a coherent interconnect. The coherent interconnect generates appropriate snoops and management transactions to maintain data consistency without additional software management by various components or agents. Any agent using this cache must also reside within the coherent domain. The coherent cache does not store data from the non-coherent domain.

[0004] Similarly, a cache storing non-coherent data resides within the non-coherent domain of a data processing system. Compared to a coherent cache, a non-coherent cache is typically located closer to memory controllers, is larger, and has higher latency. Any agent using such a cache must maintain data consistency using additional software management to ensure that dirty data becomes visible to other agents within the non-coherent domain. A non-coherent cache does not store data from the coherent domain. Prior art literature

[65535] (Patent Document 0001) US 20190317897 A1 Brief explanation of the drawing

[0005] FIG. 1a depicts a block diagram of a system having a coherent domain according to one embodiment of the present invention. FIG. 1b depicts a block diagram of the system described in FIG. 1a using protocol node nomenclature according to one embodiment of the present invention. FIG. 2 depicts a block diagram of a system having coherent and non-coherent domains according to one embodiment of the present invention. FIG. 3 depicts a partitioned memory cache according to one embodiment of the present invention. FIG. 4 depicts a cache line and a parsed memory address according to one embodiment of the present invention. FIG. 5a depicts an authorized cache state variation table according to one embodiment of the present invention. FIGS. 5b through 5e depict predicted and permitted state change tables according to embodiments of the present invention. FIG. 6 depicts a flowchart illustrating the functionality associated with storing coherent data and non-coherent data in a system cache according to an embodiment of the present invention. Specific details for implementing the invention

[0006] Embodiments of the present invention will now be described with reference to the drawings, wherein similar reference numbers refer to similar parts throughout.

[0007] Embodiments of the present invention advantageously provide a single cache that stores both coherent data and non-coherent data by tracking which cache lines store shareable data from coherent domains and which cache lines store non-shareable data from non-coherent domains. Cache lines are dynamically allocated as shareable (i.e., coherent) or non-shareable (i.e., non-coherent), which advantageously expands the caching resources available to coherent and non-coherent domains.

[0008] In addition to identifying and storing shareable and non-shareable data from coherent and non-coherent domains, respectively, the cache advantageously functions as an eviction cache for the coherent domain by caching shareable clean evictions, and enables dirty shareable cache lines to be transferred back to the coherent domain without writing cache line data to memory. The cache is located closer to off-chip memory, which reduces average latencies compared to memory and reduces off-chip memory traffic, while moving away from the coherent domain, where area and latency are optimal. Additionally, the cache can be maximally occupied when cache usage is in a mode with bursts of activity in each domain.

[0009] In one embodiment, a method for storing coherent data and non-coherent data in a system cache comprises: receiving a transaction from a source in a system—wherein the transaction includes at least a memory address, the source has a location within a coherent domain or a non-coherent domain of the system, the coherent domain includes shareable data, and the non-coherent domain includes non-shareable data—; determining whether the memory address is stored in a cache line; and when it is not determined that the memory address is stored in a cache line, assigning a cache line to the transaction, including setting a status bit of the assigned cache line to indicate whether shareable data is stored in the assigned cache line or non-shareable data is stored in the assigned cache line based on the source location; and processing the transaction.

[0010] FIG. 1a depicts a block diagram of a system (10) having a coherent domain according to one embodiment of the present invention.

[0011] The system (10) includes one or more processors such as a CPU complex (120), one or more accelerators such as a GPU complex (130), one or more I / O master or manager devices such as I / O coherent agents (140), and a coherent interconnect (110) coupled to one or more dynamic memory controllers (DMCs) such as a DMC complex (150). The DMC complex (150) is coupled to memory (154). In this embodiment, the CPU complex (120) is coupled to the coherent interconnection (110) via the AMBA 5 CHI connection (101), the GPU complex (130) is coupled to the coherent interconnection (110) via the ACE5-LiteDVM connection (102), the I / O coherent agents (140) are coupled to the coherent interconnection (110) via the ACE5-Lite connections (103), and the DMC complex (150) is coupled to the coherent interconnection (110) via the ACE5-Lite connection (104), and other connection protocols may also be used.

[0012] AMBA 5 CHI refers to the Arm AMBA (Advanced Microcontroller Bus Architecture) 5 CHI (Coherent Hub Interface) architecture, ACE5 refers to the Arm AMBA ACE (AXI Coherency Extension) 5 architecture, AXI5 refers to the Arm AXI (Advanced eXtensible Interface) 5 architecture, and ACE5-LiteDVM refers to the Arm AMBA ACE5-Lite DVM (Distributed Virtual Memory) architecture.

[0013] The coherent interconnection unit (110) is a communication system that transmits data between the CPU complex (120), the GPU complex (130), the I / O coherent agents (130), the DMC complex (150) (and memory (154)), as well as other components (not shown). The coherent interconnection unit (110) employs a coherent bus protocol that ensures all requesters, namely processors, accelerators, manager devices, agents, etc., see the same view of memory. Certain components of the system (10) may be classified as, associated with, or represented by a specific type of interconnection protocol node, as discussed in more detail in relation to FIG. 1b. The coherent interconnection unit (110) may also include one or more system caches and snoop filters to store data that is evicted or hidden from the requesters.

[0014] Generally, the coherent interconnection part (110) is, Especially among themIt may include a shared or hierarchical bus, a crossbar switch, a packet-based serialized network-on-chip (NoC), etc. In one embodiment, the coherent interconnection (110) has a crossbar topology that provides an ordered network with low latency and may be particularly suitable for a small-sized interconnection having a small number of protocol nodes, switches, and wire counts. In another embodiment, the coherent interconnection (110) has a ring topology that balances wiring efficiency with latency that increases linearly with the number of protocol nodes and may be particularly suitable for a medium-sized interconnection. In a further embodiment, the coherent interconnection (110) has a mesh topology that has more wires to provide greater bandwidth, is modular, and is easily scalable by adding more rows and columns of switches or routers and may be particularly suitable for a large-sized interconnection.

[0015] In many embodiments, the coherent interconnect (110) is a coherent mesh network comprising a plurality of switch or router logic modules (routers) arranged in a two-dimensional rectangular mesh topology, such as, for example, the Arm CoreLink coherent mesh network CMN-700. In this example, the switches or routers are intersections (i.e., XPs). Each XP can connect to up to four neighboring XPs using mesh ports and can connect to one or two components (devices) using device ports. Additionally, each XP can support four CHI channels to transmit data from a source device to a destination or target device.

[0016] In these embodiments, the coherent interconnect (110) may have an architecture comprising three layers: an upper protocol layer, an intermediate network layer, and a lower link layer. The protocol layer generates and processes requests and responses at protocol nodes, defines allowed cache state variations at protocol nodes including caches, defines transaction flows for each request type, and manages protocol-level flow control. The network layer packetizes protocol messages, determines source and target node identifiers (IDs) required to route the packet through the coherent interconnect (110) to the required destination, and adds them to the packet. The link layer provides flow control between components and manages link channels to provide deadlock-free switching across the coherent interconnect (110).

[0017] The CPU complex (120) includes a plurality of CPUs arranged in a cluster. In many embodiments, each CPU includes a plurality of cores, each core includes one or two caches, and each CPU may include a cache shared by cores, such as, for example, Arm Cortex A, R, and M series processors. Additionally, the CPU complex (120) may include a cache shared by CPUs and a local interconnect. Generally, the CPUs in the CPU complex (120) execute computer programs or modules, such as an operating system, application software, and other software modules, stored in memory, such as memory (154), to perform various functions for the system (10), such as, for example, control, computation, input / output. The CPUs of the CPU complex (120) initiate data requests to the coherent interconnect (110) via the AMBA 5 CHI connection (101).

[0018] The GPU complex (130) includes a plurality of GPUs arranged in a cluster. In many embodiments, each GPU includes a plurality of processors or a plurality of cores having a plurality of cores, and each processor or core may include a cache, and each GPU may include a cache shared by processors or cores, such as, for example, Arm Mali series graphics processing units. Additionally, the GPU complex (130) may include a cache shared among the GPUs and a local interconnect. Generally, the GPUs are optimized to perform one or more specific functions, such as performing graphics processing of images and / or multimedia data, processing of digital signal data, processing of artificial neural network data, etc. The GPUs of the GPU complex (130) initiate data requests to the coherent interconnect (110) via the ACE5-LiteDVM connection (102).

[0019] I / O coherent agents (140) are I / O manager devices that initiate data requests for the coherent interconnection unit (110) through ACE5-Lite connections (103).

[0020] The DMC complex (150) includes one or more DMCs arranged in a cluster, such as, for example, an Arm CoreLink dynamic memory controller DMC-620. Each DMC includes a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), logic circuits, etc., and is configured to provide access to memory (154) through a coherent interconnect (110). Memory (154) may include various non-transient computer-readable media that can be accessed by other components of the system (10), such as a CPU complex (120), a GPU complex (130), an I / O coherent agent (140), etc. For example, memory (154) may store data and instructions for execution by CPUs of the CPU complex (120), etc. The DMCs of the DMC complex (150) receive data requests from the coherent interconnection unit (110) through the ACE5-Lite connection (104).

[0021] In various embodiments, the memory (154) may include volatile and non-volatile media, non-removable media and / or removable media. For example, the memory (154) may include random access memory (RAM), dynamic RAM (DRAM), double data rate (DRAM) DRAM or synchronous DRAM (SDRAM), static RAM (SRAM), read-only memory (ROM), flash memory, and / or any combination of any other type of non-transient computer-readable media. In many embodiments, the DMCs of the DMC complex (150) provide data transfers to and from high-density DDR3 or DDR4 DRAM memory.

[0022] FIG. 1b depicts a block diagram of a system (10) using protocol node naming conventions according to one embodiment of the present invention.

[0023] A requester is represented as a Request Node (RN), which is a protocol node that generates protocol transactions for the coherent interconnect (110), such as memory reads and writes, I / O data transfers, etc. The RN-F protocol node represents a "full" coherent requester, and the RN-I protocol node represents an "I / O" coherent requester. Since the CPUs of the CPU complex (120) are full coherent requesters, the RN-Fs (122) represent the CPUs of the CPU complex (120). Similarly, since the GPUs of the GPU complex (130) are full coherent requesters, the RN-Fs (132) represent the GPUs of the GPU complex (130). Each RN-I is associated with an I / O coherent agent (140) connected to the coherent interconnect (110) and includes a microprocessor, microcontroller, ASIC, FPGA, logic circuit, etc., to provide related functionality. In some embodiments, the RN-Is may use the same hardware. Since the I / O coherent agents (140) are I / O coherent requesters, the RN-Is (111) are associated with the I / O coherent agents (140).

[0024] In this embodiment, the coherent interconnection unit (110) includes several completers, each comprising a microprocessor, microcontroller, ASIC, FPGA, logic circuit, etc., to provide the relevant functionality. Each completer is associated with a Home Node (HN), which is a protocol node that receives protocol transactions from RNs, and can receive protocol transactions from Slave Nodes or Subordinate Nodes (SN), as described below. Similar to RNs, an HN-F protocol node represents a fully coherent completer, and an HN-I protocol node represents an I / O coherent completer.

[0025] In many embodiments, each HN-F (112) manages a portion of the address space for memory (154). Each HN-F may include a system-level cache and a snoop traffic filter and operates as a Point-of-Coherency (PoC) and Point-of-Serialization (PoS) for requests sent from RN-Fs and RN-Is to the HN-F. To avoid collisions when multiple RNs attempt to access the same memory address in memory (154), the HN-Fs (112) operate serially as a PoS, processing read requests, write requests, etc.

[0026] A fully coherent slave or dependent device may be represented as an SN-F node, which is a protocol node that receives and completes requests from HN-Fs. Since the memory controllers (150) are fully coherent dependent devices, the SN-Fs (152) represent the memory controllers (150). In many embodiments, each HN-F (112) is associated with an SN-F (152), and each SN-F (152) is represented by one or more HN-Fs (112).

[0027] FIG. 2 depicts a block diagram of a system (100) having a coherent domain and a non-coherent domain according to one embodiment of the present invention.

[0028] The system (100) includes a coherent domain and a non-coherent domain. The coherent domain includes a coherent interconnect (110), a CPU complex (120), a GPU complex (130), I / O coherent agents (140), a partitioned memory cache (160), a DMC complex (150), and memory (154). The non-coherent domain includes a non-coherent interconnect (115), non-coherent agents (170) (i.e., manager devices) and peripherals (180) (i.e., dependent devices), as well as a partitioned memory cache (160), a DMC complex (150), and memory (154). Several components, namely the partitioned memory cache (160), the DMC complex (150), and memory (154), provide services to both domains and reside within them. Each non-interfering agent (170) uses software management to ensure that dirty data becomes visible to other agents within the non-interfering domain.

[0029] In this embodiment, the CPU complex (120) is coupled to the coherent interconnection (110) via the AMBA 5 CHI connection (101), the GPU complex (130) is coupled to the coherent interconnection (110) via the ACE5-LiteDVM connection (102), I / O coherent agents (140) are coupled to the coherent interconnection (110) via the ACE5-Lite connections (103), non-coherent agents (170) are coupled to the non-coherent interconnection (115) via the ACE5-Lite connections (107), the coherent interconnection (110) is coupled to the non-coherent interconnection (115) via the ACE5-Lite connection (104), and the non-coherent interconnection (115) is partitioned memory via the ACE5-Lite connection (105). The partitioned memory cache (160) is coupled to the cache (160), and the partitioned memory cache (160) is coupled to the DMC complex (150) via the AXI5 connection (106), and other connection protocols may also be used.

[0030] The non-coherent interconnect (115) is a communication system that transmits data between the coherent interconnect (110) (i.e., CPU complex (120), GPU complex (130), and I / O coherent agents (140)), non-coherent agents (170), DMC complex (150) (i.e., memory (154)), and peripherals (180). In many embodiments, the non-coherent interconnect (115) is a packetized network-on-chip (NoC), such as the Arm CoreLink network interconnect NI-700, which includes a manager and dependent interfaces. The dependent interfaces receive requests from manager devices, such as the coherent interconnect (110) and non-coherent agents (170), and the manager interfaces transmit the requests to dependent devices, such as the partitioned memory cache (160) and peripherals (180).

[0031] FIG. 3 depicts a partitioned memory cache (160) according to one embodiment of the present invention.

[0032] Generally, the partitioned memory cache (160) intercepts and processes requests intended for the DMC complex (150) and memory (154), forwards the requests appropriately to the DMC complex (150), and stores copies of the requested data for future use. In addition to identifying and storing shareable and non-shareable data from coherent and non-coherent domains, respectively, the partitioned memory cache (160) advantageously functions as an ejection cache for the coherent domain by caching shareable clean ejections, and enables dirty shareable cache lines to be transferred back to the coherent domain without writing cache line data to memory (154), as is discussed in more detail below.

[0033] The partitioned memory cache (160) includes a cache controller (162), I / O interfaces (164), and a cache memory (166). The cache controller (162) is coupled to the I / O interfaces (164) and the cache memory (166), and the I / O interfaces (164) are also coupled to the cache memory (166). In various embodiments, the partitioned memory cache (160) may be referred to as a system cache, an LLC (last level cache), etc. The cache controller (162) includes a microprocessor, a microcontroller, an ASIC, an FPGA, logic circuits, etc., and is configured to manage cache memory (166) and I / O interfaces (164), to process incoming requests from CPU complex (120), GPU complex (130), I / O coherent agents (140), and non-coherent agents (170) (and to send responses to them), and to send outgoing requests to the DMC complex (150) (and to process responses from them). Generally, these requests are intended read transactions and write transactions for the DMC complex (150) and memory (154). Read and write transactions always include memory addresses, and write transactions include data to be written to memory (154).

[0034] The I / O interfaces (164) include suitable circuitry to support communication of these transactions through the ACE5-Lite connection (105) and the AXI5 connection (106). As previously mentioned, other communication protocols may also be used.

[0035] The cache memory (166) includes DRAM, embedded DRAM, SRAM, etc., and is configured to store a plurality of cache lines (200). Data is stored in the cache lines (200) based on transaction memory addresses and cache mapping methods. Generally, a cache line is a unit of data transfer between a partitioned memory cache (160), a DMC controller (150), and memory (154). Each cache line (200) includes a tag field (210), a state field (220), and a data field (230). The size of each cache line (200) is typically indicated by the size of the data field (230), such as, for example, 32 bytes, 64 bytes, etc. The tag field (210) stores a part of the memory address (i.e., "tag") where the data is stored in memory (154), the state field (220) stores a plurality of bits characterizing the data, and the data field (230) stores the data at that memory address. More specifically, the data field (230) stores a sequence of bytes starting at that memory address (e.g., 32 bytes, 64 bytes, etc.). After system start, restart, reset, etc., all cache lines (200) in the cache memory (166) are cleared and made available for allocation by the cache controller (162).

[0036] In many embodiments, cache lines (200) are stored as a sequence of rows within the cache memory (166). In other embodiments, each cache line is an architectural construct, and the fields of each cache line (200) are stored in different parts of the cache memory (166), namely, tag fields (210) are stored in one part of the cache memory (166), state fields (220) are stored together with the tag fields (210) or in another part of the cache memory (166), and data fields (230) are stored in an additional part of the cache memory (166), and an indexing scheme may be used to link the cache line fields to each other. In these embodiments, the same type of memory may be used to store the cache line fields, or alternatively, different types of memory may be used to store the tag fields (210), state fields (220), and data fields (230). For example, tag fields (210) and state fields (220) can be stored in SRAM to increase performance during tag matching, while data fields (230) can be stored in eDRAM.

[0037] Generally, the partitioned memory cache (160) may be a direct mapping cache, an N-way set associative cache, or a fully associative cache. A direct mapping cache maps each memory address to a specific cache line (200); in other words, a direct mapping cache maps multiple memory addresses to a single cache line (200). An N-way set associative cache maps each memory address to a cache line within a specific set of N cache lines (200); in other words, an N-way set associative cache maps multiple memory addresses to each set of N cache lines (200). A fully associative cache allows each memory address to be mapped to any cache line (200).

[0038] In one example, a direct mapping cache has a capacity of 32 KB, a 32 B cache line size, and 1,024 cache lines (200) (i.e., 32 KB / 32 bytes per cache line). In another example, a 4-way set associative cache has a capacity of 32 KB (i.e., total data storage), a 32 byte cache line size (i.e., data field size), and 4 cache lines per set (i.e., ways). This 4-way set associative cache example has 256 sets (200) of 4 cache lines (240) (i.e., 32 KB / (4 - 32 B) = 256 sets). In an additional example, a fully associative cache has a capacity of 32 KB, a 32 B cache line size, and 1,024 cache lines (200) (i.e., 32 KB / 32 bytes per cache line).

[0039] FIG. 4 depicts a cache line (200) and a parsed memory address (300) according to one embodiment of the present invention.

[0040] The status field (220) includes an invalid bit (221) indicating whether invalid data or valid data is stored in the cache line (200), a status bit (222) indicating whether shareable data or non-shareable data is stored in the cache line (200), and a dirty bit (223) indicating whether dirty data or clean data is stored in the cache line (200). For example, the cache controller (162) may set the invalid bit (221) to 1 to indicate invalid data and set it to 0 to indicate valid data (or vice versa), and may set the dirty bit (223) to 1 to indicate dirty data and set it to 0 to indicate clean data (or vice versa). Since a source located in an interfering domain stores shareable data in a partitioned memory cache (160) and a source located in a non-interfering domain stores non-shareable data in a partitioned memory cache (160), the cache controller (162) sets a status bit (222) based on the location of the source. The cache controller (162) can set the status bit (222) to 1 to indicate shareable data and to 0 to indicate non-shareable data (or vice versa).

[0041] Generally, the state field (220) defines the state of the cache line (200), and the cache controller (162) sets or determines the state of the cache line (200) based on the values ​​of the invalid bit (221), the state bit (222), and the dirty bit (223). In many embodiments, the cache line (200) may have a number of different states including invalid (e.g., state "Invalid"), non-shareable clean (e.g., state "NshC"), non-shareable dirty (e.g., state "NshD"), shareable clean (e.g., state "ShC"), and shareable dirty (e.g., state "ShD"). For example, the cache controller (162) has a specific cache line (200) having a state of invalid when the invalid bit (221) is set to 1 (regardless of the values ​​of the status bit (222) and the dirty bit (223), having a state of NshC when the invalid bit (221) is set to 0, the status bit (222) is set to 0, and the dirty bit (223) is set to 0, having a state of NshD when the invalid bit (221) is set to 0, the status bit (222) is set to 0, and the dirty bit (223) is set to 1, having a state of ShC when the invalid bit (221) is set to 0, the status bit (222) is set to 1, and the dirty bit (223) is set to 0, and the invalid bit (221) is set to 0, the status bit (222) is set to 1, and the dirty bit (223) When set to 1, it is set or determined to have the state ShD.

[0042] After a transaction is received from a source within an interfering or non-interfering domain in a partitioned memory cache (160), the cache controller (162) determines whether the memory address of the transaction is stored in one of the cache lines (200). If the memory address and associated data are stored in one of the cache lines (200), the transaction is processed. If the memory address and associated data are not stored in one of the cache lines (200), a cache line is assigned to the transaction, and then the transaction is processed.

[0043] The cache controller (162) determines which cache line (200) can store transaction data by parsing the transaction memory address and applying a cache mapping method.

[0044] In the case of a direct mapping cache, the memory address (300) can be parsed into a tag (310), an index (320), and an offset (330). The tag (310) is a part of the memory address (300) stored in the tag field (210) of the cache line (200). In the case of a direct mapping cache, the index (320) identifies a specific cache line (200) where transaction data can be stored. The offset (330) identifies a byte within the data field (230) of the cache line (200).

[0045] In the case of an N-way set associative cache, the memory address (300) can be parsed into a tag (310), an index (320), and an offset (330). The tag (310) is a part of the memory address (300) stored in the tag field (210) of the cache line (200). In the case of an N-way set associative cache, the index (320) identifies a specific set (240) of cache lines (200) where transaction data can be stored. The offset (330) identifies a byte within the data field (230) of the cache line (200).

[0046] In the case of a fully associative cache, the memory address (300) can be parsed into a tag (310) and an offset (330); and since all cache lines (200) are available for allocation, the index (320) is not used. The offset (330) identifies a byte within the data field (230) of the cache line (200).

[0047] In many embodiments, the system (100) has a 32-bit physical memory address space (i.e., 2 32 It has physical memory addresses, and each 32-bit memory address identifies a byte stored in memory (154).

[0048] In the direct mapping cache example, 5 bits of the memory address identify a byte within the data field (230) (i.e., log2(32) = 5 bits), and 10 bits of the memory address identify a cache line (200) (i.e., log2(1024) = 10 bits), so the size of the tag field (210) is 17 bits (i.e., 32 - 10 - 5 = 17 bits), and each tag field (210) stores 17 most significant bits (MSBs) of the memory address. In this example, the size of the tag (310) is 17 bits, the size of the index (320) is 10 bits, and the size of the offset (330) is 5 bits.

[0049] In the 4-way set associative cache example, 5 bits of the memory address identify a byte within the data field (230) (i.e., log2(32) = 5 bits), and 8 bits of the memory address identify a set (i.e., log2(256) = 8 bits), so the size of the tag field (210) is 19 bits (i.e., 32 - 8 - 5 = 19 bits), and each tag field (210) stores 19 most significant bits (MSB) of the memory address. In this example, the size of the tag (310) is 19 bits, the size of the index (320) is 8 bits, and the size of the offset (330) is 5 bits.

[0050] In the fully associative cache example, 5 bits of the memory address identify the byte within the data field (230) (i.e., log2 (32) = 5 bits), so the size of the tag field (210) is 27 bits (i.e., 32 - 5 = 27 bits), and each tag field (210) stores the 27 most significant bits (MSB) of the memory address. In this example, the size of the tag (310) is 27 bits, and the size of the offset (330) is 5 bits.

[0051] In other words, the cache controller (162) determines the tag (310) based on the transaction memory address for all three types of cache mapping methods.

[0052] In the case of a direct mapping cache, the cache controller (162) also determines an index (320) based on a transaction memory address, identifies a cache line (200) where transaction data may be stored based on the index (320), and then compares a tag stored in a tag field (210) within the identified cache line (200) with a tag (310). If the cache controller (162) determines that the tag (310) matches a tag stored in the tag field (210), the transaction is processed based on the status field (220). A cache "hit" is generated when the invalid bit (221) is set to valid (e.g., 0), and a cache "miss" is generated when the invalid bit (221) is set to invalid (e.g., 1). When the cache controller (162) determines that the tag (310) does not match the tag stored in the tag field (210) (i.e., cache "miss"), the identified cache line (200) is assigned to a transaction, and the transaction is subsequently processed. If valid data is stored within the assigned cache line (200), the data within the assigned cache line (200) can be evicted from the cache memory (166) according to the transaction.

[0053] In the case of an N-way set associative cache, the cache controller (162) determines an index (320) based on a transaction memory address, identifies a set (240) in which transaction data may be stored based on the index (320), and then searches for cache lines (200) of the identified set (240) for tags stored in tag fields (210) that match the tag (310). When the cache controller (162) determines that a specific cache line (200) within the identified set (240) has a tag stored in a tag field (210) that matches the tag (310), the transaction is processed based on the status field (220). A cache "hit" is generated when the invalid bit (221) is set to valid (e.g., 0), and a cache "miss" is generated when the invalid bit (221) is set to invalid (e.g., 1). When the cache controller (162) determines that none of the cache lines (200) in the identified set (240) have a tag stored in the tag field (210) that matches the tag (310) (i.e., cache "miss"), the cache line (200) in the identified set (240) is assigned to a transaction, and the transaction is subsequently processed. If valid data is stored in the assigned cache line (200), the data in the assigned cache line (200) can be evicted from the cache memory (166) according to the transaction.

[0054] In a fully associative cache example, the cache controller (162) searches all cache lines (200) for a tag stored in the tag field (210) that matches the tag (310). When the cache controller (162) determines that a particular cache line (200) has a tag (310) that matches the tag stored in the tag field (210), the transaction is processed based on the status field (220). A cache "hit" is generated when the invalid bit (221) is set to valid (e.g., 0), and a cache "miss" is generated when the invalid bit (221) is set to invalid (e.g., 1). When the cache controller (162) determines that none of the cache lines (200) have a tag (310) that matches the tag stored in the tag field (210) (i.e., a cache "miss"), the cache line (200) is assigned to a transaction, and the transaction is subsequently processed. If valid data is stored within an allocated cache line (200), the data within the allocated cache line (200) can be ejected from the cache memory (166) according to the transaction.

[0055] In other words, the cache controller (162) searches for one or more cache lines (200) for tags stored in the tag field (210) that match the tag (310) for all three types of cache mapping methods.

[0056] More specifically, when the cache controller (162) determines that a memory address is not stored in the cache line (200), the cache controller (162) assigns the cache line (200) to a transaction, which includes setting the status bit (222) of the assigned cache line (200) to indicate whether shareable data is stored in the assigned cache line (200) or non-shareable data is stored in the assigned cache line (200) based on the source location. The cache controller (162) also stores a tag (310) in the tag field (210) of the assigned cache line (200) and then processes the transaction.

[0057] When a cache line (200) is allocated for a transaction, the cache controller (162) processes read and write transactions differently. As discussed above, the partitioned memory cache (160) receives transactions from sources in both the coherent domain and the non-coherent domain through the non-coherent interconnect (115) and the connection (105).

[0058] In the case of a read transaction, the cache controller (162) is, Especially among them, A read transaction containing a memory address and related information is transmitted to a DMC complex (150) via a connection (106) for processing. The related information includes, for example, the length or exact number of data transfers within the read transaction, the size of each data transfer or the number of bytes within it, etc. The DMC complex (150) queries the memory (154) and returns the read data to a partitioned memory cache (160) via the connection (106). The cache controller (162) stores the read data in a data field (230) of an allocated cache line (200), sets an invalid bit (221) to indicate valid data, and sets a dirty bit (223) to indicate clean data. Typically, the read data fills the data field (230) of the cache line (200). Next, the cache controller (162) transmits the read transaction response, which includes the read data, to the non-interfering interconnect (115) via the connection (105) to transmit it back to the source.

[0059] Write transactions may include write-through transactions and also write-back transactions. In the case of a write-through transaction, the cache controller (162) stores the write data in the cache memory (166) and simultaneously transmits the write data to the DMC complex (150) and memory (154). In the case of a write-back transaction, the cache controller (162) initially stores the write data in the cache memory (166) and, after a delay, transmits the write data to the DMC complex (150) and memory (154). For example, the cache controller (162) may delay transmitting the write data to the DMC complex (150) and memory (154) until the cache line (200) where the write data is stored is evicted from the cache memory (166).

[0060] In the case of a write-through transaction, the cache controller (162) stores write data in the data field (230) of the allocated cache line (200), sets an invalid bit (221) to indicate valid data, and sets a dirty bit (223) to indicate clean data. Generally, the write data can fill the data field (230) of the cache line (200). The cache controller (162) then, Especially among them, A write-through transaction containing a memory address, write data, and related information is transmitted to a DMC complex (150) via a connection (106) for processing. The related information includes, for example, the length or exact number of data transmissions within the write transaction, the size of each data transmission, or the number of bytes within it. The DMC complex (150) transmits the write-through transaction to memory (154) and then transmits the write-through transaction response to a partitioned memory cache (160) via the connection (106). Subsequently, the cache controller (162) transmits the write-through transaction response to a non-coherent interconnect (115) to transmit it back to the source.

[0061] In the case of a write-back transaction, the cache controller (162) stores write data within the data field (230) of the allocated cache line (200), sets an invalid bit (221) to indicate valid data, and sets a dirty bit (223) to indicate dirty data because the data stored in the cache memory (166) is different from the data stored in the memory (154) for this memory address. Generally, the write data can fill the data field (230) of the cache line (200). After a delay, the cache controller (162) changes the dirty bit (223) to indicate clean data, and then Especially among them, A write-through transaction containing a memory address, write data, and related information is transmitted to a DMC complex (150) via a connection (106) for processing. The related information includes, for example, the length or exact number of data transmissions within the write transaction, the size of each data transmission, or the number of bytes within it. The DMC complex (150) transmits a write-back transaction to memory (154) and transmits a write-back transaction response to a partitioned memory cache (160) via a connection (106). Subsequently, the cache controller (162) transmits the write-back transaction response to a non-coherent interconnect (115) to transmit it back to the source.

[0062] When the cache controller (162) determines that a memory address is stored in a cache line (200) (i.e., the identified cache line (200)), the cache controller (162) determines the state of the cache line (200) based on the state field (220). Further processing of the transaction depends on the source location as well as the state of the identified cache line (200), as indicated by the values ​​of the invalid bit (221), the state bit (222), and the dirty bit (223). As described above, in many embodiments, each cache line (200) in the cache memory (166) may have an invalid state (i.e., when the invalid bit indicates invalid data), may have an NshC state (i.e., when the invalid bit indicates valid data, the status bit indicates non-shareable data, and the dirty bit indicates clean data), may have an NshD state (i.e., when the invalid bit indicates valid data, the status bit indicates non-shareable data, and the dirty bit indicates dirty data), may have an ShC state (i.e., when the invalid bit indicates valid data, the status bit indicates shareable data, and the dirty bit indicates clean data), or may have an ShD state (i.e., when the invalid bit indicates valid data, the status bit indicates shareable data, and the dirty bit indicates dirty data).

[0063] When the state of the identified cache line (200) is invalid and the source location is in an interfering or non-interfering domain, the cache controller (162) assigns the identified cache line (200) to a transaction and then processes the transaction, as described above.

[0064] When the state of the identified cache line (200) is NshC state, NshD state, ShC state, or ShD state and the source location is in an interfering domain, the transaction is processed. In other words, the source within the interfering domain can "hit" in a shareable or non-shareable cache line (200).

[0065] When the state of the identified cache line (200) is NshC state, NshD state, or ShD state and the source location is in the non-interfering domain, the transaction is processed. In other words, the source within the non-interfering domain may "hit" in the shareable and dirty cache line (200), but may not "hit" in the shareable and clean cache line (200). When the state of the identified cache line (200) is ShD state, after the transaction is processed, the cache controller (162) changes the state of the identified cache line (200) to NshD state by setting the state bit (222) to indicate non-shareable data.

[0066] When a transaction is a cache maintenance operation, the transaction is processed.

[0067] When a transaction is a write-through or write-back transaction representing a clean eviction from a cache within an interfering domain, after the identified cache line (200) is assigned to the transaction and the status bit (222) is set to indicate shareable data, the cache controller (162) prevents the identified cache line (200) from being accessed by a source location within an interfering domain regardless of the value of the dirty bit (223). In other words, a source within an interfering domain may not be "hit" on the shareable and dirty cache line (200) representing a clean eviction from an interfering domain.

[0068] When the transaction is a read transaction, and the state of the identified cache line (200) is the ShD state, and the source is located in the coherent domain, processing the transaction includes setting the dirty bit (233) to indicate clean data, but does not include writing the identified cache line (200) to a memory address.

[0069] In one embodiment, the interface to the partitioned memory cache (160) is an ACE5-Lite interface, the connection (105) is an ACE5-Lite connection, and the connection (106) is an AXI5 connection. The following description explains the advantageous features of the partitioned memory cache (160) described above in the context of this embodiment.

[0070] The "Memory_Cache_Support" attribute can be used to indicate whether the interface supports a partitioned memory cache (160). When set to "true," additional transactions for the partitioned memory cache (160) are supported, and when set to "false," additional transactions for the partitioned memory cache (160) are not supported. Table 1 shows the compatibility between the manager interface and the dependent interface according to the values ​​of the "Memory_Cache_Support" attribute.

[0071] [Table 1]

[0072]

[0073] If the administrator supports partitioned memory cache transactions but does not support linked dependencies, alternative requests may be issued as presented in Table 2.

[0074] [Table 2]

[0075]

[0076] Transactions on read channels may include ReadClean transactions and ReadShared transactions.

[0077] A ReadClean transaction is a full cache line shareable read, where data may be allocated to the upstream cache, the transaction must be cache line size and regular, and the read data must be clean.

[0078] A ReadShared transaction is a full cache line shareable read, where the data may be allocated to the upstream cache, the transaction must be cache line size and regular, and the read data can be clean or dirty. If the data is dirty, the cache line must be allocated to the upstream, and the response for every beat of the read data must be OKAYDIRTY instead of OKAY.

[0079] Transactions on write channels may include WriteNoSnoopFull transactions, WriteBackFull transactions, and WriteEvictFull transactions.

[0080] A WriteNoSnoopFull transaction is a non-shareable write to an entire cache line, where the data is dirty and not allocated upstream. The write must be the size of the cache line and regular. All write strobes must be asserted. An upstream cache may issue a WriteNoSnoopFull transaction when evicting a non-shareable dirty cache line or when streaming write data of the size of the cache line. When a downstream cache receives a WriteNoSnoopFull request, it may allocate the cache line, knowing that the cache line will not be allocated upstream and that the entire cache line will be received without any missing bytes.

[0081] A WriteBackFull transaction may be used when a shareable dirty cache line is evicted from the cache. This transaction enables the partitioned memory cache (160) to allocate the cache line as shareable dirty. Writes must be cache line size and regular. All write strobes must be asserted.

[0082] A WriteEvictFull transaction may be used when a shareable clean cache line is evicted from the cache. This transaction allows a downstream cache to allocate the cache line as a shareable clean. Writes must be cache line size and regular. All write strobes must be asserted. A shareable clean cache line must not be exposed to any non-shareable sources or agents because the cache line may stale within the cache of a coherent domain. For the same reason, data from a WriteEvictFull transaction must not update memory (154).

[0083] Regarding read signaling, Table 3 presents several acceptable operations. ReadShared and ReadClean also require the "Shareable_Transactions" parameter to be true.

[0084] [Table 3]

[0085]

[0086] When the Memory_Cache_Support attribute is true, RRESP includes an OKAYDIRTY response as shown in Table 4.

[0087] [Table 4]

[0088]

[0089] Regarding write signaling, Table 5 presents several acceptable behaviors. WriteBackFull and WriteEvictFull transactions also require the Shareable_Transactions parameter to be true.

[0090] [Table 5]

[0091]

[0092] FIG. 5a depicts a table of permitted cache state variations (400) according to one embodiment of the present invention. The table (400) illustrates permitted state variations that may occur without an incoming transaction hitting on a cache line.

[0093] FIGS. 5b through 5e depict a table of predicted and permitted state changes (410) according to embodiments of the present invention. The table (410) illustrates predicted and permitted state changes in response to incoming transactions.

[0094] FIG. 6 depicts a flowchart (500) representing functionality associated with storing coherent data and non-coherent data in a system cache according to embodiments of the present invention.

[0095] In 510, a transaction is received from a source within the system (100) in a partitioned memory cache (160). The transaction includes at least a memory address. The source has a location within a coherent domain or a non-coherent domain of the system (100), the coherent domain contains shareable data and the non-coherent domain contains non-shareable data.

[0096] At 520, it is determined whether the memory address is stored in the cache line. If it is not determined that the memory address is stored in the cache line, the flow proceeds to 530, and if it is determined that the memory address is stored in the cache line, the flow proceeds to 550.

[0097] At 530, a cache line is assigned to a transaction, including setting the status bit of the assigned cache line to indicate whether the assigned cache line contains shareable data or non-shareable data based on the source location. The flow then proceeds to 540.

[0098] At 540, the transaction is processed.

[0099] In 550, the state of a cache line is determined based on a state bit, an invalid bit, and a dirty bit, and the state includes an invalid state, a non-shareable clean state, a non-shareable dirty state, a shareable clean state, and a shareable dirty state. The invalid bit indicates whether invalid data or valid data is stored in the cache line, and the dirty bit indicates whether dirty data or clean data is stored in the cache line. The flow then proceeds to 540, where the transaction is processed based on the state of the cache line and the source location.

[0100] The embodiments described in this specification are combinable.

[0101] In one embodiment, a method for storing coherent data and non-coherent data in a system cache comprises: receiving a transaction from a source in a system—wherein the transaction includes at least a memory address, the source has a location within a coherent domain or a non-coherent domain of the system, the coherent domain includes shareable data, and the non-coherent domain includes non-shareable data—; determining whether the memory address is stored in a cache line; and when it is not determined that the memory address is stored in a cache line, assigning a cache line to the transaction, including setting a status bit of the assigned cache line to indicate whether shareable data is stored in the assigned cache line or non-shareable data is stored in the assigned cache line based on the source location; and processing the transaction.

[0102] In another embodiment of the present method, the step of determining whether a memory address is stored in a cache line includes the step of determining a tag based on the memory address and the step of searching one or more cache lines for a matching tag, and the step of assigning a cache line to a transaction includes the step of storing a tag in a cache line.

[0103] In another embodiment of the present method, when the transaction is a read transaction, the step of allocating a cache line includes the step of transmitting a read request to a memory controller, the step of receiving a read response from the memory controller including read data, and the step of storing the read data in a cache line; and when the transaction is a write transaction including write data, the step of allocating a cache line includes the step of storing the write data in a cache line.

[0104] In another embodiment of the present method, the step of assigning a cache line to a transaction includes the step of setting an invalid bit of the cache line to indicate whether invalid data or valid data is stored in the cache line, and the step of setting a dirty bit of the cache line to indicate whether dirty data or clean data is stored in the cache line.

[0105] In another embodiment of the method, the method further comprises the step of determining the state of a cache line based on a state bit, an invalid bit, and a dirty bit when it is determined that a memory address is stored in a cache line—the state includes an invalid state, a non-shareable clean state, a non-shareable dirty state, a shareable clean state, and a shareable dirty state—and the step of processing a transaction based on the state of the cache line and the source location.

[0106] In another embodiment of the present method, an invalid state is determined when the invalid bit indicates invalid data; a non-shareable clean state is determined when the invalid bit indicates valid data, the status bit indicates non-shareable data, and the dirty bit indicates clean data; a non-shareable dirty state is determined when the invalid bit indicates valid data, the status bit indicates non-shareable data, and the dirty bit indicates dirty data; a shareable clean state is determined when the invalid bit indicates valid data, the status bit indicates shareable data, and the dirty bit indicates clean data; a shareable dirty state is determined when the invalid bit indicates valid data, the status bit indicates shareable data, and the dirty bit indicates dirty data.

[0107] In another embodiment of the method, the step of processing a transaction includes processing the transaction when the source location is in an interfering domain, and the state of the cache line is a non-shareable clean state, a non-shareable dirty state, a shareable clean state, or a shareable dirty state.

[0108] In another embodiment of the method, the step of processing a transaction includes processing the transaction when the source location is in a non-interfering domain, and when the state of the cache line is a non-shareable clean state, a non-shareable dirty state, or a shareable dirty state.

[0109] In another embodiment of the present method, when the state of a cache line is a shareable dirty state, after a transaction is processed, the state of the cache line is changed to a non-shareable dirty state.

[0110] In another embodiment of the present method, the transaction is a cache maintenance operation, and the present method further includes the step of processing the transaction when it is determined that a memory address is stored in a cache line.

[0111] In another embodiment of the method, the transaction is a clean evacuation from the coherent domain, and after the cache line is assigned to the transaction and the status bit is set to indicate shareable data, the cache line is not visible to the source having a location within the non-coherent domain.

[0112] In another embodiment of the present method, the transaction is a read transaction from a source having a location within a coherent domain, the status bit indicates shareable data, the dirty bit indicates dirty data, and the step of processing the transaction includes the step of setting the dirty bit to indicate clean data, and does not include the step of writing a cache line to a memory address.

[0113] In one embodiment, the system cache comprises: a communication interface configured to receive a transaction from a source in the system, wherein the transaction includes at least a memory address, the source has a location within a coherent domain or a non-coherent domain of the system, the coherent domain includes shareable data, and the non-coherent domain includes non-shareable data; a memory coupled to the communication interface, comprising a plurality of cache lines, wherein each cache line has a tag field, a status field, and a data field, and the status field includes an invalid bit, a status bit, and a dirty bit; and a controller coupled to the communication interface and the memory, wherein the controller is configured to assign a cache line to a transaction and process the transaction, including setting a status bit of the assigned cache line to indicate whether shareable data is stored in the assigned cache line or non-shareable data is stored in the assigned cache line based on the source location when it is not determined that the memory address is stored in the cache line.

[0114] In another embodiment of the system, determining whether a memory address is stored in a cache line includes determining a tag based on the memory address and searching one or more cache lines for a matching tag, and allocating a cache line includes storing a tag in a cache line, setting an invalid bit of a cache line to indicate whether invalid data is stored in a cache line or valid data is stored in a cache line, and setting a dirty bit of a cache line to indicate whether dirty data is stored in a cache line or clean data is stored in a cache line.

[0115] In another embodiment of the system, when the transaction is a read transaction, allocating a cache line includes transmitting a read request to a memory controller, receiving a read response from the memory controller containing read data, and storing the read data in the cache line; and when the transaction is a write transaction containing write data, allocating a cache line includes storing the write data in the cache line.

[0116] In another embodiment of the system, the controller is configured to determine the state of a cache line based on a status bit, an invalid bit, and a dirty bit when it is determined that a memory address is stored in a cache line—the state includes an invalid state, a non-shareable clean state, a non-shareable dirty state, a shareable clean state, and a shareable dirty state—and to process a transaction based on the state of the cache line and the source location. The invalid state is determined when the invalid bit indicates invalid data; the non-shareable clean state is determined when the invalid bit indicates valid data, the status bit indicates non-shareable data, and the dirty bit indicates clean data; the non-shareable dirty state is determined when the invalid bit indicates valid data, the status bit indicates non-shareable data, and the dirty bit indicates dirty data; the shareable clean state is determined when the invalid bit indicates valid data, the status bit indicates shareable data, and the dirty bit indicates clean data; the shareable dirty state is determined when the invalid bit indicates valid data, the status bit indicates shareable data, and the dirty bit indicates dirty data.

[0117] In another embodiment of the system, processing a transaction includes processing the transaction when the source location is in a coherent domain, and the state of the cache line is a non-shareable clean state, a non-shareable dirty state, a shareable clean state, or a shareable dirty state.

[0118] In another embodiment of the system, processing a transaction includes processing the transaction when the source location is in a non-interfering domain, and when the state of the cache line is a non-shareable clean state, a non-shareable dirty state, or a shareable dirty state.

[0119] In another embodiment of the system, when the state of a cache line is a shareable dirty state, after a transaction is processed, the controller is configured to change the state of the cache line to a non-shareable dirty state.

[0120] In another embodiment of the system, the transaction is a cache maintenance operation, and the controller is configured to process the transaction when it is determined that the memory address is stored in the cache line.

[0121] In another embodiment of the system, the transaction is a write transaction representing a clean eviction from the coherent domain, and after the cache line is assigned to the write transaction and the status bit is set to indicate shareable data, the controller is configured to prevent a source having a location within the non-coherent domain from accessing the cache line.

[0122] In another embodiment of the system, the transaction is a read transaction from a source having a location within a coherent domain, the status bit indicates shareable data, the dirty bit indicates dirty data, and processing the transaction includes setting the dirty bit to indicate clean data and does not include writing a cache line to a memory address.

[0123] Embodiments of the present invention are possible in many different forms, but are illustrated in the drawings and will be described in detail in specific embodiments herein. It is understood that the present invention should be considered as an example of the principles disclosed and is not intended to be limited to the specific embodiments illustrated and described. In the foregoing description, similar reference numerals may be used to describe identical, similar, or corresponding parts in some views of the drawings.

[0124] In these documents, the terms “include,” “include,” “equip,” “equip,” “have,” “have,” or any other variations thereof are intended to encompass non-exclusive inclusions, so that a process, method, article, or device comprising a list of elements may not include only these elements but may include other elements not explicitly enumerated or inherent to such process, method, article, or device. An element preceding “…include” does not exclude, without further restriction, the existence of additional identical elements in a process, method, article, or device comprising such element.

[0125] Throughout this document, references to "one embodiment," "a set of embodiments," "many embodiments," "one embodiment," "embodiment(s)," "mode(s)," or similar terms mean that a specific feature, structure, or characteristic described in relation to an embodiment is included in at least one embodiment of the present invention. Accordingly, appearances of such phrases in various places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments without limitation.

[0126] As used herein, the term "or" should be interpreted to mean any one or any combination of all or any combination. Thus, "A, B or C" means "A; B; C; A and B; A and C; B and C; any of A, B and C." Exceptions to this definition will occur only when combinations of elements, functions, steps, or actions are essentially mutually exclusive in some manner. Furthermore, grammatical conjunctions are intended to express any and all disjunctions and conjunctions of combined clauses, sentences, words, etc., unless otherwise stated or evident from the context. Accordingly, the term "or" should generally be understood to mean "and / or," etc. References to singular items should be understood to include plural items, and vice versa, unless otherwise explicitly stated or evident from the text.

[0127] Descriptions of ranges of values ​​in this specification are not limiting unless otherwise indicated, but are instead intended to refer individually to any and all values ​​within such range, and each individual value within such range is included in this specification as individually described herein. Words such as “about,” “approximately,” etc., when accompanied by numerical values, should be interpreted as indicating a deviation as understood by those skilled in the art to function satisfactorily for the intended purpose. Ranges of values ​​and / or numerical values ​​are provided in this specification merely as examples and do not constitute a limitation on the scope of the described embodiments. Any and all examples or the use of exemplary language (“e.g.,” “like,” “e.g.,” etc.) provided in this specification is intended merely to better illuminate the embodiments and does not limit the scope of the embodiments. No language in this specification should be interpreted as indicating any unclaimed element as essential to the execution of the embodiments.

[0128] For the sake of simplicity and clarity of example, reference numerals may be repeated between drawings to indicate corresponding or similar elements. Many details are described to provide an understanding of the embodiments described herein. The embodiments may be practiced without these details. In other cases, well-known methods, procedures, and components are not described in detail to avoid obscuring the described embodiments. The description should not be construed as being limited to the scope of the embodiments described herein.

[0129] Many features and advantages of the present invention are apparent from the detailed description, and thus the appended claims are intended to include all such features and advantages of the present invention that fall within the scope of the present invention. Additionally, since numerous modifications and variations will readily come to mind of those skilled in the art, it is not desirable to limit the present invention to the exact configuration and operation illustrated and described, and thus all suitable modifications and equivalents may be relied upon as falling within the scope of the present invention.

Claims

Claim 1 A method for storing coherent data and non-coherent data in a partitioned memory cache of a data processing system, comprising: receiving a transaction from a source of the data processing system in the partitioned memory cache, wherein the transaction includes at least a memory address, and the source has a location within a coherent domain or a non-coherent domain of the data processing system, wherein the coherent domain includes shareable data and the non-coherent domain includes non-shareable data; determining whether data associated with the memory address is stored in a cache line of the partitioned memory cache; and, when it is not determined that data associated with the memory address is stored in a cache line, assigning a cache line to the transaction, wherein, based on the source location, a status bit of the assigned cache line is set to indicate whether shareable data is stored in the assigned cache line or non-shareable data is stored in the assigned cache line; and processing the transaction, wherein the step of determining whether data associated with the memory address is stored in a cache line comprises determining a tag based on the memory address. A method comprising the step of searching for one or more cache lines for a matching tag; and the step of assigning the cache line to the transaction, wherein the step of storing the tag in the cache line. Claim 2 delete Claim 3 A method according to claim 1, wherein when the transaction is a read transaction, the step of allocating the cache line comprises: transmitting a read request to a memory controller of the data processing system; receiving a read response from the memory controller, including read data; and storing the read data in the cache line; and when the transaction is a write transaction including write data, the step of allocating the cache line comprises storing the write data in the cache line. Claim 4 A method according to claim 1, wherein the step of assigning the cache line to the transaction comprises: the step of setting an invalid bit of the cache line to indicate whether invalid data or valid data is stored in the cache line; and the step of setting a dirty bit of the cache line to indicate whether dirty data or clean data is stored in the cache line. Claim 5 A method according to claim 4, further comprising the step of determining the state of the cache line based on the state bit, the invalid bit, and the dirty bit when it is determined that data associated with the memory address is stored in the cache line - wherein the state includes an invalid state, a non-shareable clean state, a non-shareable dirty state, a shareable clean state, and a shareable dirty state -; and the step of processing the transaction based on the state of the cache line and the source location. Claim 6 In claim 5, the invalid state is determined when the invalid bit indicates invalid data; the non-shareable clean state is determined when the invalid bit indicates valid data, the status bit indicates non-shareable data, and the dirty bit indicates clean data; the non-shareable dirty state is determined when the invalid bit indicates valid data, the status bit indicates non-shareable data, and the dirty bit indicates dirty data; the shareable clean state is determined when the invalid bit indicates valid data, the status bit indicates shareable data, and the dirty bit indicates clean data; the shareable dirty state is determined when the invalid bit indicates valid data, the status bit indicates shareable data, and the dirty bit indicates dirty data. Claim 7 A method according to claim 5, wherein the step of processing the transaction comprises processing the transaction when the source location is the coherent domain, and the state of the cache line is the non-shareable clean state, the non-shareable dirty state, the shareable clean state, or the shareable dirty state. Claim 8 A method according to claim 5, wherein the step of processing the transaction comprises processing the transaction when the source location is the non-coherent domain, and when the state of the cache line is the non-shareable clean state, the non-shareable dirty state, or the shareable dirty state. Claim 9 A method according to claim 8, wherein when the state of the cache line is the shareable dirty state, after the transaction is processed, the state of the cache line is changed to the non-shareable dirty state. Claim 10 A method according to claim 1, wherein the transaction is a cache maintenance operation, and the method further comprises the step of processing the transaction when it is determined that data associated with the memory address is stored in a cache line. Claim 11 A method according to claim 4, wherein the transaction is a clean eviction from the coherent domain, and after the cache line is assigned to the transaction and the status bit is set to indicate shareable data, the cache line is not accessible by a source having a location within the non-coherent domain. Claim 12 A method according to claim 5, wherein the transaction is a read transaction from a source having a location within the coherent domain, the status bit indicates shareable data, the dirty bit indicates dirty data, and the step of processing the transaction includes the step of setting the dirty bit to indicate clean data, and does not include the step of writing the cache line to the memory address. Claim 13 A partitioned memory cache comprising: a communication interface configured to receive a transaction from a source of a data processing system, wherein the transaction includes at least a memory address, and the source has a location within a coherent domain or a non-coherent domain of the data processing system, wherein the coherent domain includes shareable data and the non-coherent domain includes non-shareable data; a memory coupled to the communication interface comprising a plurality of cache lines, wherein each cache line has a tag field, a status field and a data field, and the status field includes an invalid bit, a status bit and a dirty bit; and a controller coupled to the communication interface and the memory, wherein the controller determines whether data associated with the memory address is stored in a cache line of the memory; and when it is not determined that data associated with the memory address is stored in a cache line of the memory, the controller assigns a cache line to the transaction, wherein the controller sets a status bit of the assigned cache line to indicate whether shareable data is stored in the assigned cache line or non-shareable data is stored in the assigned cache line based on the source location. A partitioned memory cache configured to process the above transaction, and determining whether data associated with the memory address is stored in a cache line includes determining a tag based on the memory address; and searching one or more cache lines for a matching tag, and allocating the cache line includes storing the tag in the cache line. Claim 14 A partitioned memory cache according to claim 13, wherein allocating the cache line comprises: setting an invalid bit of the cache line to indicate whether invalid data or valid data is stored in the cache line; and setting a dirty bit of the cache line to indicate whether dirty data or clean data is stored in the cache line. Claim 15 A partitioned memory cache according to claim 14, wherein when the transaction is a read transaction, allocating the cache line comprises transmitting a read request to a memory controller; receiving a read response from the memory controller, including read data; and storing the read data in the cache line; and when the transaction is a write transaction including write data, allocating the cache line comprises storing the write data in the cache line. Claim 16 In claim 14, the controller determines the state of the cache line based on the status bit, the invalid bit, and the dirty bit when it is determined that data associated with the memory address is stored in the cache line, wherein the state includes an invalid state, a non-shareable clean state, a non-shareable dirty state, a shareable clean state, and a shareable dirty state, wherein the invalid state is determined when the invalid bit indicates invalid data, the non-shareable clean state is determined when the invalid bit indicates valid data, the status bit indicates non-shareable data, the dirty bit indicates clean data, the non-shareable dirty state is determined when the invalid bit indicates valid data, the status bit indicates non-shareable data, the dirty bit indicates dirty data, the shareable clean state is determined when the invalid bit indicates valid data, the status bit indicates shareable data, the dirty bit indicates clean data, the shareable dirty state is determined when the invalid bit indicates valid data, the status bit indicates shareable data, and the dirty bit indicates dirty data A partitioned memory cache configured to process the transaction based on the state of the cache line and the source location. Claim 17 A partitioned memory cache according to claim 16, wherein processing the transaction comprises processing the transaction when the state of the cache line is the non-shareable clean state, the non-shareable dirty state, the shareable clean state, or the shareable dirty state, where the source location is the coherent domain. Claim 18 A partitioned memory cache according to claim 16, wherein processing the transaction comprises processing the transaction when the source location is the non-coherent domain, and when the state of the cache line is the non-shareable clean state, the non-shareable dirty state, or the shareable dirty state. Claim 19 A partitioned memory cache according to claim 18, wherein, when the state of the cache line is the shareable dirty state, after the transaction is processed, the controller is configured to change the state of the cache line to the non-shareable dirty state. Claim 20 In paragraph 13, the transaction is a cache maintenance operation, and the controller is configured to process the transaction when it is determined that data associated with the memory address is stored in the cache line, a partitioned memory cache. Claim 21 In claim 14, the transaction is a write transaction representing a clean eviction from the coherent domain, and after the cache line is assigned to the write transaction and the status bit is set to indicate shareable data, the controller is configured to prevent a source having a location within the non-coherent domain from accessing the cache line, a partitioned memory cache. Claim 22 A partitioned memory cache according to claim 14, wherein the transaction is a read transaction from a source having a location within the coherent domain, the status bit indicates shareable data, the dirty bit indicates dirty data, and processing the transaction includes setting the dirty bit to indicate clean data, and does not include writing the cache line to the memory address.

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