Semiconductor package

Abstract

A semiconductor package comprises: a first semiconductor structure including a first semiconductor substrate and a lower penetration structure penetrating the first semiconductor substrate; a connection structure on the first semiconductor structure; and a second semiconductor structure disposed on the connection structure and including a second semiconductor substrate and an upper penetration structure penetrating the second semiconductor substrate, wherein the connection structure comprises: a lower bending pad on the lower penetration structure; and an upper bending pad on the lower bending pad, wherein the upper surface of the lower bending pad is a curved surface, the lower surface of the upper bending pad is a curved surface, and the upper bending pad is electrically connected to the upper penetration structure.

Description

Technology Field

[0001] The present invention relates to a semiconductor package, and more specifically to a stacked semiconductor package. Background Technology

[0002] In the semiconductor industry, the increasing demand for high capacity, thinness, and miniaturization of semiconductor packages and electronic products utilizing them has led to the rapid emergence of various related packaging technologies. One such technology is a packaging technique capable of achieving high-density chip stacking by vertically stacking multiple semiconductor chips. This technology offers the advantage of being applicable when integrating semiconductor chips with diverse functions into a smaller area compared to conventional packages consisting of a single chip.

[0003] A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. With the advancement of the electronics industry, various studies are being conducted to improve the reliability and durability of semiconductor packages. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a semiconductor package with improved reliability during the bonding process.

[0005] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A semiconductor package according to embodiments of the present invention for solving the aforementioned technical problems comprises: a first semiconductor structure including a first semiconductor substrate and a lower penetration structure penetrating the first semiconductor substrate; a connection structure on the first semiconductor structure; and a second semiconductor structure disposed on the connection structure and including a second semiconductor substrate and an upper penetration structure penetrating the second semiconductor substrate, wherein the connection structure comprises: a lower bending pad on the lower penetration structure; and an upper bending pad on the lower bending pad, wherein the upper surface of the lower bending pad is a curved surface, the lower surface of the upper bending pad is a curved surface, and the upper bending pad can be electrically connected to the upper penetration structure.

[0007] A semiconductor package according to embodiments of the present invention for solving the aforementioned technical problems comprises: a first semiconductor structure including a first semiconductor substrate and a lower penetrating structure penetrating the first semiconductor substrate;

[0008] The structure comprises a connection structure on the first semiconductor structure; and a second semiconductor structure disposed on the connection structure and including a second semiconductor substrate and an upper penetration structure penetrating the second semiconductor substrate, wherein the connection structure comprises: a lower insulating film on the first semiconductor substrate; a lower bending pad disposed on the lower insulating film and electrically connected to the lower penetration structure; and a lower connection pad disposed on the lower insulating film and spaced apart from the lower bending pad, and the level of the upper surface of the lower bending pad may be lower than the level of the upper surface of the lower connection pad.

[0009] A semiconductor package according to embodiments of the present invention for solving the aforementioned technical problems comprises: a first semiconductor structure including a first semiconductor substrate and a lower penetration structure penetrating the first semiconductor substrate; a connection structure on the first semiconductor structure; and a second semiconductor structure disposed on the connection structure and including a second semiconductor substrate and an upper penetration structure penetrating the second semiconductor substrate, wherein the connection structure comprises: a lower insulating film on the first semiconductor substrate; an intermediary film on the lower insulating film; a lower curved pad on the lower penetration structure; and an upper curved pad on the lower curved pad, wherein the upper surface of the lower curved pad is a curved surface and the lower surface of the upper curved pad is a curved surface, the upper curved pad is electrically connected to the upper penetration structure, and the level of the upper surface of the intermediary film may be lower than the level of the upper surface of the curved pad. Effects of the invention

[0010] In the semiconductor package according to the embodiments of the present invention, when the upper structure and the lower structure come into contact, the curved surfaces of the insulating film and the curved surfaces of the pad come into contact with each other, so the topology of the semiconductor structure can be relaxed. Brief explanation of the drawing

[0011] FIG. 1 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention. Figure 2 is a planar view of the upper curved pads of a semiconductor package according to Figure 1. FIG. 3 is a planar view of the lower curved pads of a semiconductor package according to FIG. 1. Figure 4 is an enlarged cross-sectional view of section Q of Figure 1. FIG. 5 is a cross-sectional view illustrating the bonding between semiconductor substrates according to embodiments of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention. FIG. 7 is a plan view illustrating a semiconductor package according to embodiments of the present invention. FIG. 8 is a plan view illustrating a semiconductor package according to embodiments of the present invention. Figure 9 is an enlarged cross-sectional view of the Qb portion of Figure 1. FIG. 10 is a cross-sectional view illustrating the bonding between semiconductor substrates according to embodiments of the present invention. FIGS. 11 to 18 are plan views for explaining a method for manufacturing a semiconductor package according to embodiments of the present invention. FIG. 19 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention. FIG. 20 is an enlarged cross-sectional view of part P of FIG. 19. FIG. 21 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention. Specific details for implementing the invention

[0012] A semiconductor package according to the concept of the present invention is described with reference to the drawings.

[0013] FIG. 1 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention. In FIG. 1, for convenience of explanation, some components are omitted or several components are merged into a single component.

[0014] A semiconductor package according to embodiments of the present invention may be a stacked package using through-hole structures. For example, semiconductor chips of the same type may be stacked on a base substrate, and the semiconductor chips may be electrically connected to each other through through-hole structures that penetrate them. The semiconductor chips may be connected to each other using their pads facing each other.

[0015] Referring to FIG. 1, a semiconductor package (1) according to embodiments of the present invention may have the form of a plate extending along a plane defined by a first direction (D1) and a second direction (D2). The first direction (D1) and the second direction (D2) may intersect each other. For example, the first direction (D1) and the second direction (D2) may be orthogonal to each other. A semiconductor package (1) according to embodiments of the present invention may include a solder ball (81), a solder layer (90), a base structure (100), a first connection structure (210), a first semiconductor structure (220), a second connection structure (310), a second semiconductor structure (320), a third connection structure (410), a third semiconductor structure (420), and a molding layer (190).

[0016] A solder ball (81) may be provided. The solder ball (81) may include a conductive material. The solder ball (81) may be electrically connected to a base structure (100), a first semiconductor structure (220), a second semiconductor structure (320), and a third semiconductor structure (420). The solder ball (81) may electrically connect the base structure (100), the first semiconductor structure (220), the second semiconductor structure (320), and the third semiconductor structure (420) to an external device (not shown).

[0017] A solder layer (90) may be provided on a solder ball (81). The solder layer (90) may include a solder insulating film (91) and a solder pad (92). The solder insulating film (91) may surround the side of the solder pad (92).

[0018] The solder insulating film (91) may include an insulating material. The solder insulating film (91) may include, for example, at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON).

[0019] The solder pad (92) may include a conductive material. The solder pad (92) may include, for example, one or more of copper (Cu), aluminum (Al) and / or nickel (Ni). The solder pad (92) may be electrically connected to the solder ball (81).

[0020] A base structure (100) may be provided on a solder layer (90). The base structure (100) may include, for example, a base substrate (101) and a base through-via (102).

[0021] The base substrate (101) may contain a circuit directly within it. For example, the base substrate (101) may be a wafer-level die made of a semiconductor such as silicon (Si). In some embodiments, the base substrate (101) may be a substrate that does not contain electronic components such as a transistor, and may be, for example, a printed circuit board (PCB).

[0022] The first connecting structure (210) may be interposed between the base substrate (101) and the first semiconductor substrate (225). The first connecting structure (210) may have a structure similar to the second connecting structure (310) described later. The base substrate (101) and the first semiconductor substrate (225) may be bonded through the first connecting structure (210). The base substrate (101) and the first semiconductor structure (220) may be electrically connected through the first connecting structure (210).

[0023] A first semiconductor structure (220) may be provided on a first connection structure (210). The first semiconductor structure (220) may include a first semiconductor substrate (225) and a plurality of lower penetration structures (221, 222, 223). The plurality of lower penetration structures (221, 222, 223) may include a first lower penetration structure (221), a second lower penetration structure (222), and a third lower penetration structure (223). The first lower penetration structure (221), the second lower penetration structure (222), and the third lower penetration structure (223) may penetrate the first semiconductor substrate (225).

[0024] The first semiconductor substrate (225), base structure (100), and solder ball (81) can be electrically connected through the first lower penetration structure (221), the second lower penetration structure (222), and the third lower penetration structure (223).

[0025] A second connection structure (310) may be provided on the first semiconductor substrate (225). The second connection structure (310) may be interposed between the first semiconductor substrate (225) and the second semiconductor substrate.

[0026] A second semiconductor structure (320) may be provided on the second connection structure (310). The second semiconductor structure (320) may have a structure similar to the first semiconductor structure (220).

[0027] A third connection structure (410) may be provided on the second semiconductor structure (320). The third connection structure (410) may have a structure similar to the first and second connection structures (210, 310).

[0028] A third semiconductor structure (420) may be provided on the third connection structure (410). The third semiconductor structure (420) may have a structure similar to the first and second semiconductor structures (220).

[0029] A fourth connection structure (510) may be provided on the third semiconductor structure (420). The fourth connection structure (510) may have a structure similar to the first, second, and third connection structures (210, 310, 410).

[0030] A fourth semiconductor structure (520) may be provided on the third connection structure (510). The fourth semiconductor structure (520) may be similar to the first semiconductor structure (220), except for the configuration corresponding to the first lower penetration structure (221), the second lower penetration structure (222), and the third lower penetration structure (223).

[0031] A molding layer (190) may be provided on a base structure (100). The molding layer (190) may be provided to surround a first connection structure (210), a first semiconductor structure (220), a second connection structure (310), a second semiconductor structure (320), a third connection structure (410), and a third semiconductor structure (420). The molding layer (190) may include an insulating material. For example, the molding layer (190) may include an epoxy molding compound (EMC).

[0033] FIG. 2 is a planar view showing the upper curved pads of a semiconductor package according to FIG. 1. FIG. 3 is a planar view showing the lower curved pads of a semiconductor package according to FIG. 1. FIG. 4 is an enlarged cross-sectional view of portion Q of FIG. 1. FIG. 5 is a cross-sectional view for explaining the bonding between semiconductor substrates according to embodiments of the present invention.

[0034] Referring to FIGS. 2, 3, and 4, a second connecting structure (310) may be interposed between a first semiconductor substrate (225) and a second semiconductor substrate (325). The second connecting structure (310) may be formed by joining an upper structure (US) and a lower structure (LS) to be described later. The second connecting structure (310) comprises a lower insulating film (317), an interlayer (318) on the lower insulating film (317), lower connecting pads (311, 312, 313, 314) on the lower insulating film (317), lower curved pads (381, 382, ​​383) on the lower insulating film (317), a bonding insulating film (319) on the interlayer (318), upper connecting pads (321, 322, 323, 324) on the lower connecting pads (311, 312, 313, 314), upper curved pads (391, 392, 393) on the lower curved pads (381, 382, ​​383), and upper connecting top pads (331, 332) on the upper connecting pads (321, 322, 323, 324). It may include upper curve top pads (333, 334, 335) on upper curve top pads (336, 337), upper curve top pads (333, 334, 335) on upper curve top pads (333, 334, 335), and upper conductive pads (351, 352, 353) on upper curve top pads (333, 334, 335).

[0035] Referring to FIG. 2, in a planar view, the bonding insulating film (319) may have the shape of a plate extending in a first direction (D1) and a second direction (D2).

[0036] The upper connecting pads (321, 322, 323, 324) may include a plurality of first upper connecting pads (321), a plurality of second upper connecting pads (322), a plurality of third upper connecting pads (323), and a plurality of fourth upper connecting pads (324).

[0037] The upper connecting top pads (331, 332, 336, 337) may include a first connecting top pad (331), a second connecting top pad (332), a third connecting top pad (336), and a fourth connecting top pad (337). The first connecting top pad to the fourth connecting top pad (331, 332, 336, 337) may be spaced apart in a first direction (D1).

[0038] The first upper connecting pads (321) may be circular. The first upper connecting pads (321) may include a conductive material. A plurality of first upper connecting pads (321) may be spaced apart in a second direction (D2). The first connecting top pad (331) may be rectangular in shape, with the length of the side in the second direction (D2) being longer than the length of the side in the first direction (D1). The first connecting top pad (331) may overlap with a plurality of first upper connecting pads (321).

[0039] The first connecting top pad (331) and the second connecting top pad (332) may be adjacent. The third connecting top pad (336) and the fourth connecting top pad (337) may be adjacent. The first upper connecting pad (321) and the second upper connecting pad (322) may be adjacent. The third upper connecting pad (323) and the fourth upper connecting pad (324) may be adjacent.

[0040] A plurality of curved upper pads (333, 334, 335) may be disposed between the second connecting upper pad (332) and the third connecting upper pad (336). A plurality of upper curved pads (391, 392, 393) may be disposed between the second upper connecting pad (322) and the third upper connecting pad (323).

[0041] A plurality of curved upper pads (333, 334, 335) may include a plurality of first curved upper pads (333), a plurality of second curved upper pads (334), and a plurality of third curved upper pads (335). A plurality of upper curved pads (391, 392, 393) may include a plurality of first upper curved pads (391), second upper curved pads (392), and third upper curved pads (393).

[0042] A plurality of first curved top pads (333) may be spaced apart in a second direction (D2). A plurality of first curved top pads (333) may include a conductive material. A plurality of first curved top pads (333) may be circular.

[0043] A plurality of first upper curved pads (391) may be spaced apart in a second direction (D2). A plurality of first upper curved pads (391) may include a conductive material. A plurality of first curved top pads (333) may be circular.

[0044] The first curve top pad (333) and the first upper curve pad (391) may be concentric circles. The diameter of the first curve top pad (333) may be larger than the diameter of the first upper curve pad (391). The first upper curve pad (391) and the first curve top pad (333) may overlap.

[0045] The second to fourth upper connecting pads (322, 323, 324) and the second to fourth connecting upper pads (332, 336, 337) may also be likewise.

[0046] Referring to FIG. 3, from a planar perspective, the lower insulating film (317) may have the shape of a plate extending in the first direction (D1) and the second direction (D2).

[0047] The lower connecting pads (311, 312, 313, 314) and lower bending pads (381, 382, ​​383) may be circular. The diameter of the lower bending pads (381, 382, ​​383) may be larger than the diameter of the lower connecting pads (311, 312, 313, 314).

[0048] The lower connecting pads (311, 312, 313, 314) may include a plurality of first lower connecting pads (311), a plurality of second lower connecting pads (312), a plurality of third lower connecting pads (313), and a plurality of fourth lower connecting pads (314). The plurality of first lower connecting pads (311) may be spaced apart in a second direction (D2). The first lower connecting pads (311) and the plurality of second lower connecting pads (312) may be adjacent.

[0049] The lower bending pads (381, 382, ​​383) may include a plurality of first lower bending pads (381), a plurality of second lower bending pads (382), and a plurality of third lower bending pads (383). The first lower bending pads (381) may be spaced apart in a second direction (D2). The first to third lower bending pads (381, 382, ​​383) may be spaced apart in a first direction (D1).

[0050] First lower bending pads (381), second lower bending pads (382), and third lower bending pads (383) may be disposed between the second lower connecting pads (312) and the third lower connecting pads (313).

[0052] Referring to FIG. 4, a lower insulating film (317) may be disposed on a first semiconductor substrate (225). The lower insulating film (317) may include an insulating material. Lower penetrating structures (221, 222, 223) penetrating the first semiconductor substrate (225) and the lower insulating film (317) may be provided. The lower penetrating structures (221, 222, 223) may include a first lower penetrating structure (221), a second lower penetrating structure (222), and a third lower penetrating structure (223) spaced apart from each other.

[0053] A first lower connecting pad (311), a second lower connecting pad (312), a third lower connecting pad (313), a fourth lower connecting pad (314), a first lower bending pad (381), a second lower bending pad (382), and a third lower bending pad (383) may be disposed on a lower insulating film (317) so as to penetrate the inclusion film (318).

[0054] The level of the upper surface of the lower bending pads (381, 382, ​​383) may be lower than the level of the upper surface of the lower connecting pads (311, 312, 313, 314).

[0055] The inclusion film (318) may include an insulating material. The inclusion film (318) may include a material different from that of the lower insulating film (317). The inclusion film (318) may include, for example, silicon nitride. The level of the upper surface of the inclusion film (318) may be lower than the level of the upper surface of the first lower connecting pad (311) and the first lower bending pad (381).

[0056] The lower surfaces of the first lower connecting pad (311), the second lower connecting pad (312), the third lower connecting pad (313), and the fourth lower connecting pad (314) can form a common surface with the upper surface of the lower insulating film (317).

[0057] A first upper connecting pad (321) may be provided on a first lower connecting pad (311). The first upper connecting pad (321) and the first lower connecting pad (311) may be electrically connected. The first upper connecting pad (321) and the first lower connecting pad (311) may include a conductive material. The first upper connecting pad (321) and the first lower connecting pad (311) may include, for example, copper. The second to fourth upper connecting pads (322, 323, 324) and the second to fourth lower connecting pads (312, 313, 314) may likewise be likewise.

[0058] A first upper bending pad (391) may be provided on a first lower bending pad (381). The first lower bending pad (381) and the first upper bending pad (391) may be electrically connected. The first lower bending pad (381) and the first upper bending pad (391) may include a conductive material. The first lower bending pad (381) and the first upper bending pad (391) may include, for example, copper. The upper surface (381_CS) of the first lower bending pad (381) may be a curved surface. The lower surface (391_CS) of the first upper bending pad (391) may be a curved surface. The curvature of the upper surface (381_CS) of the first lower bending pad (381) and the curvature of the lower surface (391_CS) of the first upper bending pad (391) may be the same. The upper surface (382_CS) of the second lower bending pad (382), the lower surface (392_CS) of the second upper bending pad (392), the upper surface (383_CS) of the third lower bending pad (383), and the lower surface (393_CS) of the third upper bending pad (393) may also be likewise.

[0059] A first connection top pad (331) may be provided on the first upper connection pad (321). The first connection top pad (331) may include a conductive material. The first connection top pad (331) may include, for example, aluminum. The first connection top pad (331) may include a material different from that of the first upper connection pad (321).

[0060] A first curved top pad (333) may be provided on the first upper curved pad (391). The first curved top pad (333) may include a conductive material. The first curved top pad (333) may include, for example, aluminum. The first curved top pad (333) may include a material different from that of the first upper curved pad (391).

[0061] The level of the upper surface of the first upper bending pad (391) may be lower than the level of the first upper connecting pad (321). The width (221w) of the first lower penetrating structure (221) may be smaller than the width (391w) of the first lower bending pad (391). The width (221w) of the first lower penetrating structure (221) may be, for example, 4 µm or less. The width (391w) of the first upper bending pad (391) may be smaller than the width (381w) of the first lower bending pad (381). The width (381w) of the first lower bending pad (381) may be smaller than the width (333w) of the first upper bending pad (333). The width (391w) of the first lower bending pad (391) may be smaller than the width (311w) of the first lower connecting pad (311). The width (333w) of the first curved top pad (333) may be smaller than the width (331w) of the first connecting top pad (331). The width (333w) of the first curved top pad (333) may be, for example, 8 µm or less. The width (311w) of the first lower connecting pad (311) may be smaller than the width (331w) of the first connecting top pad (331). The height (333h) of the first curved top pad (333) may be smaller than the height (331h) of the first connecting top pad (331). The height of the first connecting top pad (331) may be, for example, 2.5 µm or less. The level of the upper surface of the connected upper pads (331, 332, 336, 337) may be higher than the level of the upper surface of the curved upper pads (333, 334, 335).

[0062] Upper penetration structures (341, 342, 343) may be disposed on the curved uppermost pads (333, 334, 335). The upper penetration structures (341, 342, 343) may include a first upper penetration structure (341), a second upper penetration structure (342), and a third upper penetration structure (343).

[0063] A first upper penetrating structure (341) may be placed on the first curved uppermost pad (333). A first conductive pad (351) may be placed on the first curved uppermost pad (333) so as to overlap with the first upper penetrating structure (341). The same may be true for the second upper penetrating structure (342), the second conductive pad (352), the third upper penetrating structure (343), and the third conductive pad (353).

[0064] The first curved top pad (333) and the first conductive pad (351) may be spaced apart. The first conductive pad (351) may include a plurality of first conductive pads (351) spaced apart in a third direction (D3). The level of the upper surface of the upper pad of the plurality of first conductive pads (351) may be lower than the level of the upper surface of the bonding insulating film (319). The width (351w) of the first conductive pad (351) may be smaller than the width (333w) of the first curved top pad (333). The height (351h) of the first conductive pad (351) may be smaller than the height (331h) of the first connecting top pad (331). The height (351h) of the first conductive pad (351) may be smaller than the height (333h) of the first curved top pad (333).

[0065] The bonding insulating film (319) may cover the sides and top surfaces of the connected top pads (331, 332, 336, 337) and the sides of the curved top pads (333, 334, 335). The bonding insulating film (319) may include an insulating material. A second semiconductor substrate (325) may be disposed on the bonding insulating film (319).

[0066] The upper penetrating structures (341, 342, 343) can penetrate the second semiconductor substrate (325). The distance (d1) between the center of the first upper connecting pad (321) and the center of the second upper connecting pad (322) may be 30 µm or less. The distance (d2) between the center of the second upper penetrating structure (342) and the center of the third upper penetrating structure (343) may be 30 µm or less.

[0067] The topology of the semiconductor chip can be offset by the second connection structure (310) having lower bending pads (381, 382, ​​383) and upper bending pads (391, 392, 393). Referring to FIG. 5, an upper structure (US) and a lower structure (LS) are provided immediately before the second connection structure (310) is formed. The upper structure (US) may be provided on top of the lower structure (LS). For convenience of explanation, a detailed description of technical features that overlap with those previously described is omitted, and the differences are described in detail.

[0068] The lower structure (LS) may include a first semiconductor substrate (225), a lower insulating film (317) on the first semiconductor substrate (225), an interlayer (318) on the lower insulating film (317), a first curved insulating film (3192) on the interlayer (318), lower penetrating structures (221, 222, 223) penetrating the first semiconductor substrate (225) and the lower insulating film (317), lower curved pads (381, 382, ​​383) on the lower penetrating structures (221, 222, 223), and lower connecting pads (311, 312, 313, 314).

[0069] The first semiconductor substrate (225) may include a semiconductor material. For example, the first semiconductor substrate (110) may be a silicon (Si) single crystal substrate.

[0070] The first curved insulating film (3192) may include a lower flat surface (3192_FS) and a lower curved surface (3192_CS). The lower flat surface (3192_FS) and the lower curved surface (3192_CS) may be continuous without interruption.

[0071] The lower flat surface (3192_FS) may be a flat surface among the upper surfaces of the first curved insulating film (3192). The lower flat surface (3192_FS) may be co-plane with the upper surfaces of the lower connecting pads (311, 312, 313, 314). The level of the lower flat surface (3192_FS) may be higher than the lowest level of the lower curved surface (3192_CS).

[0072] The lower curved surface (3192_CS) may have a downwardly concave shape. The lower curved surface (3192_CS) may form a co-plane with the upper surfaces (381_CS, 382_CS, 383_CS) of the lower curved pads (381, 382, ​​383).

[0073] The entire lower surface of the lower connecting pads (311, 312, 313, 314) can come into contact with the lower insulating film (317).

[0074] A first lower bending pad (381) may be provided on the first lower penetration structure (221). A second lower bending pad (382) may be provided on the second lower penetration structure (222). A third lower bending pad (383) may be provided on the third lower penetration structure (223).

[0075] The upper structure (US) may include a second bending insulating film (3191), a second semiconductor substrate (325) on the second bending insulating film (3191), upper connection pads (321, 322, 323, 324) within the second bending insulating film (3191), upper connection top pads (331, 332, 336, 337) on the upper connection pads, upper bending top pads (333, 334, 335) on the upper bending pads (391, 392, 393), upper penetration structures (341, 342, 343) penetrating the second bending insulating film (3191) and the second semiconductor substrate (325), and conductive pads (351, 352, 353) on the upper bending top pads (333, 334, 335).

[0076] The second bending insulating film (3191) may include an upper flat surface (3191_FS) and an upper bending surface (3191_CS). The upper flat surface (3191_FS) and the upper bending surface (3191_CS) may be continuous without interruption. The second bending insulating film (3191) may include silicon oxide.

[0077] The upper flat surface (3191_FS) may be a flat surface among the lower surfaces of the second curved insulating film (3191). The upper flat surface (3191_FS) may be co-plane with the lower surfaces of the upper connecting pads (321, 322, 323, 324). The level of the upper flat surface (3191_FS) may be higher than the lowest level of the upper curved surface (3191_CS).

[0078] The upper curved surface (3191_CS) may have a downwardly concave shape. The upper curved surface (3191_CS) may form a co-plane with the lower surfaces (391_CS, 392_CS, 393_CS) of the upper curved pads (391, 392, 393). The curvature of the lower curved surface (3192_CS) and the curvature of the upper curved surface (3191_CS) may be the same.

[0079] The lower surface (391_CS) of the first upper curved pad (391) and the upper surface (381_CS) of the first lower curved pad (381) can be in contact. The lower surface (392_CS) of the second upper curved pad (392) and the upper surface (382_CS) of the second lower curved pad (382) can be in contact. The lower surface (392_CS) of the second upper curved pad (392) and the upper surface (382_CS) of the second lower curved pad (382) can be in contact. The lower surface (393_CS) of the third upper curved pad (393) and the upper surface (383_CS) of the third lower curved pad (383) can be in contact. The lower curved surface (3192_CS) and the upper curved surface (3191_CS) can be in contact. In this case, the second bending insulating film (3192) and the second bending insulating film (3191) can be joined together to form a single unit. The first bending insulating film (3192) and the second bending insulating film (3191) can be joined together to form a bonded insulating film (319).

[0080] As described above, the upper structure (US) and the lower structure (LS) are joined to form a connecting structure (310) that connects the first semiconductor substrate (225) and the second semiconductor substrate (325).

[0081] Since the width (333w) of the first curved top pad (333) may be smaller than the width (331w) of the first connected top pad (331), the metal density of the portion where the first curved top pad (333) is located may be smaller than the metal density of the portion where the first connected top pad (331) is located. The first lower curved pad (381) is positioned to overlap with the first curved top pad (333) having a smaller metal density, thereby reducing the topology when joining the first semiconductor structure (220) and the second semiconductor structure (320).

[0083] FIG. 6 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention.

[0084] Referring to FIG. 6, a semiconductor package (1b) is provided. In FIG. 6, for convenience of explanation, some components are omitted or several components are merged into a single component. For convenience of explanation, detailed descriptions of technical features that overlap with those previously described are omitted, and the differences are described in detail.

[0085] A semiconductor package (1b) according to embodiments of the present invention may include a solder ball (81b), a solder layer (90b), a base structure (100b), a first connection structure (210b), a first semiconductor structure (220b), a second connection structure (310b), a second semiconductor structure (320b), a third connection structure (410b), a third semiconductor structure (420b), and a molding layer (190b).

[0086] A solder layer (90b) may be provided on a solder ball (81b). The solder layer (90b) may include a solder insulating film (91b) and a solder pad (92b).

[0087] A base structure (100b) may be provided on a solder layer (90b). The base structure (100b) may include, for example, a base substrate (101b) and a base through-via (102b).

[0088] The first connecting structure (210b) may be interposed between the base substrate (101b) and the first semiconductor structure (220b). The first semiconductor structure (220b) may be provided on the first connecting structure (210b). The first semiconductor structure (220b) may include a first semiconductor substrate (225b) and a plurality of lower through-hole structures (221b, 222b, 223b, 224b). The plurality of lower through-hole structures (221b, 222b, 223b, 224b) may include a first lower through-hole structure (221b), a second lower through-hole structure (222b), a third lower through-hole structure (223b), and a fourth lower through-hole structure (224b). The first lower penetration structure (221b), the second lower penetration structure (222b), the third lower penetration structure (223b), and the fourth lower penetration structure (224b) can penetrate the first semiconductor substrate (225b).

[0089] The first semiconductor substrate (225b), base structure (100b), and solder ball (81b) can be electrically connected through the first lower penetration structure (221b), the second lower penetration structure (222b), the third lower penetration structure (223b), and the fourth lower penetration structure (224b).

[0090] The distance between the second lower penetration structure (222b) and the third lower penetration structure (223b) may be greater than the distance between the first lower penetration structure (221b) and the second lower penetration structure (222b).

[0091] A second connection structure (310b) may be provided on the first semiconductor substrate (225b). A second semiconductor structure (320b) may be provided on the second connection structure (310b). A third connection structure (410b) may be provided on the second semiconductor structure (320b). A third semiconductor structure (420b) may be provided on the third connection structure (410b). A fourth connection structure (510b) may be provided on the third semiconductor structure (420b). A fourth semiconductor structure (520b) may be provided on the fourth connection structure (510b). A molding layer (190b) may be provided on the base structure (100b).

[0093] FIG. 7 is a plan view illustrating a semiconductor package according to embodiments of the present invention. FIG. 8 is a plan view illustrating a semiconductor package according to embodiments of the present invention. FIG. 9 is an enlarged cross-sectional view of the Qb portion of FIG. 1. FIG. 10 is a cross-sectional view illustrating a bond between semiconductor substrates according to embodiments of the present invention.

[0094] Referring to FIGS. 7, 8, and 9, a second connecting structure (310b) may be interposed between a first semiconductor substrate (225b) and a second semiconductor substrate (325b). The second connecting structure (310b) may be formed by joining an upper structure (USb) and a lower structure (LSb), which will be described later.

[0095] The second connecting structure (310b) comprises a lower insulating film (317b), an interlayer (318b) on the lower insulating film (317b), lower connecting pads (311b, 312b, 313b, 314b) on the lower insulating film (317b), lower curved pads (381b, 382b, 383b) on the lower insulating film (317b), a bonding insulating film (319b) on the interlayer (318b), upper connecting pads (321b, 322b, 323b, 324b) on the lower connecting pads (311b, 312b, 313b, 314b), upper curved pads (391, 392, 393) on the lower curved pads (381b, 382b, 383b), and upper connecting pads (321b, 322b). It may include upper connecting top pads (331b, 332b, 336b, 337b) on 323b, 324b), and upper conductive pads (351b, 352b, 353b, 354b) on the upper connecting top pads (331b, 332b, 336b, 337b).

[0096] Referring to FIG. 7, in a planar view, the bonding insulating film (319b) may have the shape of a plate extending in a first direction (D1) and a second direction (D2).

[0097] The upper connecting pads (321b, 322b, 323b, 324b) may include a plurality of first upper connecting pads (321b), a plurality of second upper connecting pads (322b), a plurality of third upper connecting pads (323b), and a plurality of fourth upper connecting pads (324b).

[0098] The upper connecting top pads (331b, 332b, 336b, 337b) may include a first connecting top pad (331b), a second connecting top pad (332b), a third connecting top pad (336b), and a fourth connecting top pad (337b). The first connecting top pad to the fourth connecting top pad (331b, 332b, 336b, 337b) may be spaced apart in a first direction (D1).

[0099] The first upper connecting pads (321b) may be circular. The first upper connecting pads (321b) may include a conductive material. A plurality of first upper connecting pads (321b) may be spaced apart in the second direction (D2). The first connecting top pad (331b) may be rectangular in shape, with the length of the side in the second direction (D2) being longer than the length of the side in the first direction (D1). The first connecting top pad (331b) may overlap with a plurality of first upper connecting pads (321b). The second to fourth upper connecting pads (322b, 323b, 324b) and the second to fourth connecting top pads (332b, 336b, 337b) may also be likewise.

[0100] The first connecting top pad (331b) and the second connecting top pad (332b) may be adjacent. The third connecting top pad (336b) and the fourth connecting top pad (337b) may be adjacent. The first upper connecting pad (321b) and the second upper connecting pad (322b) may be adjacent. The third upper connecting pad (323b) and the fourth upper connecting pad (324b) may be adjacent.

[0101] The distance between the second connecting top pad (332b) and the third connecting top pad (333b) may be greater than the distance between the first connecting top pad (331b) and the second connecting top pad (332b).

[0102] Referring to FIG. 3, from a planar perspective, the lower insulating film (317b) may have the shape of a plate extending in the first direction (D1) and the second direction (D2).

[0103] The lower connecting pads (311b, 312b, 313b, 314b) and the lower bending pads (381b, 382b, 383b) may be circular. The diameter of the lower bending pads (381b, 382b, 383b) may be smaller than the diameter of the lower connecting pads (311b, 312b, 313b, 314b).

[0104] Referring to FIG. 9, a first semiconductor substrate (225b), a lower insulating film (317b) on the first semiconductor substrate (225b), and lower penetrating structures (221b, 222b, 223b, 224b) penetrating the first semiconductor substrate (225b) and the lower insulating film (317b) may be provided. The lower penetrating structures (221b, 222b, 223b, 224b) may include a first lower penetrating structure (221b), a second lower penetrating structure (222b), a third lower penetrating structure (223b), and a fourth lower penetrating structure (224b) spaced apart from each other.

[0105] A first lower connecting pad (311b), a second lower connecting pad (312b), a third lower connecting pad (313b), a fourth lower connecting pad (314b), a first lower bending pad (381b), a second lower bending pad (382b), and a third lower bending pad (383b) may be disposed on a lower insulating film (317b) so as to penetrate an inclusion film (318b).

[0106] A plurality of lower bending pads (381b, 382b, 383b) can be placed between a plurality of lower connecting pads (311b, 312b, 313b, 314b).

[0107] A first lower connecting pad (311b) may be placed on a first lower through-hole structure (221b). The first lower through-hole structure (221b) and the first lower connecting pad (311b) may overlap. A first lower connecting pad (312b) may be placed on a second lower through-hole structure (222b). The second lower through-hole structure (222b) and the first lower connecting pad (312b) may overlap. A third lower connecting pad (313b) may be placed on a third lower through-hole structure (223b). The third lower through-hole structure (223b) and the third lower connecting pad (313b) may overlap. A fourth lower connecting pad (314b) may be placed on a fourth lower through-hole structure (224b). The fourth lower through-hole structure (224b) and the fourth lower connecting pad (314b) may overlap.

[0108] A first upper connecting pad (321b) may be provided on the first lower connecting pad (311b). The second to fourth upper connecting pads (322b, 323b, 324b) and the second to fourth lower connecting pads (312b, 313b, 314b) may also be provided in the same way.

[0109] The lower surface of the first lower bending pad (381b) can come into contact with the upper surface of the lower insulating film (317b). The lower surface of the second lower bending pad (382b) can come into contact with the upper surface of the lower insulating film (317b). The lower surface of the third lower bending pad (383b) can come into contact with the upper surface of the lower insulating film (317b).

[0110] The upper surface (381b_CS) of the first lower curved pad (381b) may be a curved surface. The upper surface (382b_CS) of the second lower curved pad (382b) may be a curved surface. The upper surface (383b_CS) of the third lower curved pad (383b) may be a curved surface.

[0111] A first connection top pad (331b) may be provided on the first upper connection pad (321b). A second connection top pad (332b) may be provided on the second upper connection pad (322b). A third connection top pad (333b) may be provided on the third upper connection pad (323b). A fourth connection top pad (334b) may be provided on the fourth upper connection pad (324b). Upper penetration structures (341b, 342b, 343b, 344b) may penetrate the second semiconductor substrate (325b).

[0112] The first lower through-hole structure (221b), the first lower connecting pad (381b), and the upper connecting pad (331b) may be vertically overlapped. The second lower through-hole structure (222b), the first lower connecting pad (382b), and the upper connecting pad (332b) may be vertically overlapped. The third lower through-hole structure (223b), the first lower connecting pad (383b), and the upper connecting pad (333b) may be vertically overlapped.

[0113] Upper penetration structures (341b, 342b, 343b, 344b) may be disposed on the uppermost connection pads (331b, 332b, 333b, 334b). A first upper penetration structure (341b) may be disposed on the first uppermost connection pad (331b). A first conductive pad (351b) may be disposed on the first uppermost connection pad (333b) so as to overlap with the first upper penetration structure (341b). The same may be true for the second upper penetration structure (342b), the second conductive pad (352b), the third upper penetration structure (343b), and the third conductive pad (353b). The first uppermost connection pad (333b) and the first conductive pad (351b) may be spaced apart.

[0114] The width (221bw) of the first lower penetration structure (221b) may be smaller than the width (311bw) of the first lower connecting pad (311b). The width (381w) of the first lower bending pad (381b) may be smaller than the width (311bw) of the first lower connecting pad (311b). The width (221bw) of the first lower penetration structure (221b) may be, for example, 4 µm or less. The width (311bw) of the first lower connecting pad (311b) may be, for example, 8 µm or less. The distance (d3) between the third lower penetration structure (223b) and the fourth lower penetration structure (224b) may be, for example, 30 µm or less. The width of the first connecting top pad (331b) may be larger than the width of the first upper connecting pad (321b).

[0115] Referring to FIG. 10, an upper structure (USb) and a lower structure (LSb) are provided immediately before the second connecting structure (310b) is formed. The upper structure (USb) may be provided on top of the lower structure (LSb). For convenience of explanation, detailed descriptions of technical features that overlap with those previously described are omitted, and the differences are described in detail.

[0116] The lower structure (LSb) may include a first semiconductor substrate (225b), a lower insulating film (317b) on the first semiconductor substrate (225b), an interlayer (318b) on the lower insulating film (317b), a first curved insulating film (3192b) on the interlayer (318b), lower penetrating structures (221b, 222b, 223b, 224b) penetrating the first semiconductor substrate (225b) and the lower insulating film (317b), lower connecting pads (311b, 312b, 313b, 314b) on the lower penetrating structures (221b, 222b, 223b, 224b), and lower curved pads (381b, 382b, 383b).

[0117] The first curved insulating film (3192b) may include a lower flat surface (3192b_FS) and a lower curved surface (3192b_CS).

[0118] The lower flat surface (3192b_FS) may be a flat surface among the upper surfaces of the first curved insulating film (3192b).

[0119] The lower curved surface (3192b_CS) may have a downwardly concave shape. The lower curved surface (3192b_CS) may form a co-plane with the upper surfaces (381b_CS, 382b_CS, 383b_CS) of the lower curved pads (381b, 382b, 383b).

[0120] The lower connecting pads (311b, 312b, 313b, 314b) can come into contact with the lower penetrating structure (221b, 222b, 223b, 224b).

[0121] The upper structure (USb) comprises a second flexible insulating film (3191b), a second semiconductor substrate (325b) on the second flexible insulating film (3191b), upper connection pads (321b, 322b, 323b, 324b) within the second flexible insulating film (3191b), upper connection top pads (331b, 332b, 334b, 335b) on the upper connection pads (321b, 322b, 323b, 324b), upper penetration structures (341b, 342b, 343b, 344b) penetrating the second flexible insulating film (3191b) and the second semiconductor substrate (325b), and conductive pads (351b, 352b) on the upper connection top pads (331b, 332b, 333b, 334b). It may include 353b, 354b).

[0122] The second curved insulating film (3191b) may include an upper flat surface (3191b_FS) and an upper curved surface (3191b_CS).

[0123] The upper flat surface (3191b_FS) may be a flat surface among the lower surfaces of the second curved insulating film (3191b). The upper curved surface (3191b_CS) may have a downwardly concave shape. The curvature of the lower curved surface (3192b_CS) and the curvature of the upper curved surface (3191b_CS) may be the same. The curvature of the first lower curved pad (381b) and the curvature of the upper curved surface (3191b_CS) may be the same.

[0124] The upper surface (381b_CS) of the first lower curved pad (381b), the upper surface (382b_CS) of the second lower curved pad (382b), and the upper surface of the third lower curved pad (383b_CS) and the upper curved surface (3191b_CS) can be in contact. In this case, the first curved insulating film (3192b) and the second curved insulating film (3191b) can be joined together to form a single unit. The first curved insulating film (3192b) and the second curved insulating film (3191b) can be joined together to form a bonded insulating film (319b).

[0125] As described above, the upper structure (USb) and the lower structure (LSb) are joined to form a connecting structure (310b) that connects the first semiconductor substrate (225b) and the second semiconductor substrate (325b).

[0127] FIGS. 11 to 18 are cross-sectional views for explaining a method for manufacturing a semiconductor package according to embodiments of the present invention.

[0128] Referring to FIGS. 11 to 18, a method for manufacturing a semiconductor package having a structure similar to the lower structure (LS) of FIG. 4 is provided.

[0129] Referring to FIG. 11, a carrier substrate (700), a tape (TP) on the carrier substrate (700), a base insulating film (219) on the tape (TP), a first semiconductor substrate (225) on the base insulating film (219), preliminary upper bending pads (p291, p292, p293) in the base insulating film (219), bending top pads (233, 234, 235) on the preliminary upper bending pads (p291, p292, p293), conductive pads (251, 252, 253) on the bending top pads (233, 234, 235), and upper through-structures (221, 222, 223) are provided.

[0130] A tape (TP) can be formed between the carrier substrate (700) and the base insulating film (219). The base insulating film (219) and the preliminary upper bending pads (p291, p292, p293) can be fixed on the carrier substrate (700) by the tape (TP).

[0131] The first semiconductor substrate (225) may be formed to cover the upper surface of the upper through-structures (221, 222, 223).

[0132] Referring to FIG. 12, the first semiconductor substrate (225) can be selectively etched so that a portion of the side and the top surface of the upper through-structures (221, 222, 223) are exposed.

[0133] Referring to FIG. 13, a lower insulating film (317) may be formed on a first semiconductor substrate (225). The lower insulating film (317) may be formed to cover the upper surface of the upper through-structures (221, 222, 223). A preliminary interlayer (3181) may be formed on the lower insulating film (317). An intermediate insulating film (3183) may be formed on the preliminary interlayer (3181).

[0134] The lower insulating film (317) may be formed in a raised shape in the portion overlapping with the upper through-structures (221, 222, 223). The lower insulating film (317) may be formed in an uneven shape in the portion overlapping with the upper through-structures (221, 222, 223). A preliminary interlayer (3181) may be deposited conformally along the lower insulating film (317). An intermediate insulating film (3183) may be deposited conformally along the preliminary interlayer (3181).

[0135] Referring to FIG. 14, the intermediate insulating layer (3183), the lower insulating layer (317), and the preliminary interlayer (3181) can be removed so that only the lower insulating layer (317) and the preliminary interlayer (3181) at the same level as the upper penetrating structures (211, 222, 223) remain. In this case, the upper surface of the upper penetrating structures (221, 222, 223) may be exposed.

[0136] Referring to FIG. 15, a preliminary bending insulating film (3193) may be formed on the upper surface of the exposed upper through-structures (211, 222, 223), the lower insulating film (317), and the preliminary interlayer (3181). The preliminary bending insulating film (3193) and the upper surface of the exposed upper through-structures (211, 222, 223) may come into contact. The preliminary bending insulating film (3193) may contain a material different from that of the preliminary interlayer (3181). For example, the preliminary bending insulating film (3193) may contain SiO, and the preliminary interlayer (3181) may contain SiN.

[0137] Referring to FIG. 16, a first trench (TR1), a second trench (TR2), and a third trench (TR3) may be formed by removing a portion of the lower insulating film (317), the preliminary interlayer (3181), and the preliminary bending insulating film (3193). The first trench (TR1) may be formed on the upper surface of the first upper penetrating structure (221). The second trench (TR2) may be formed on the upper surface of the second upper penetrating structure (222). The third trench (TR3) may be formed on the upper surface of the third upper penetrating structure (223). The first trench (TR1) may be formed such that the preliminary interlayer (3181) and the preliminary bending insulating film (3193) are exposed on the sidewalls of the first trench (TR1). The same may be true for the second trench (TR2) and the third trench (TR3).

[0138] The first trench (TR1) may be formed such that the width of the first trench (TR1) is greater than the width of the first upper penetration structure (221). The second trench (TR2) may be formed such that the width of the second trench (TR2) is greater than the width of the second upper penetration structure (222). The third trench (TR3) may be formed such that the width of the third trench (TR3) is greater than the width of the third upper penetration structure (223).

[0139] Referring to FIG. 16, a preliminary pad layer (3194) may be formed. The preliminary pad layer (3194) may include a conductive material. The preliminary pad layer (3194) may be formed to fill the first trench (TR1), the second trench (TR2), and the third trench (TR3). The preliminary pad layer (3194) may be formed on a preliminary flexible insulating film (3193). The preliminary pad layer (3194) may have preliminary pad curved surfaces (3194_CS) in the portions overlapping with the trenches (TR1, TR2, TR3). The preliminary pad curved surfaces (3194_CS) may be convex upwards.

[0140] Referring to FIG. 17, the preliminary pad layer (3194) may be etched. A portion of the preliminary curved insulating film (3193) may be etched. By removing a portion of the preliminary pad layer (3194) and the preliminary curved insulating film (3193), a first curved insulating film (3192) and a lower curved surface (3192_CS) may be formed. The preliminary pad layer (3194) located at a level higher than the level of the upper surface of the preliminary pad layer (3194) may be removed, and the preliminary pad layer (3194) and the preliminary curved insulating film (3193) located at a level higher than the level of the lower curved surface (3192_CS) may be removed so that a curved insulating film (3193) including the lower curved surface (3192_CS) may be formed.

[0141] The unremoved preliminary pad layer (3194) can form lower bend pads (381, 382, ​​383). A first trench (TR1) below can be filled to form a first lower bend pad (381). A second trench (TR2) below the lower bend surface (3192_CS) can be filled to form a second lower bend pad (382). A third trench (TR3) below the lower bend surface (3192_CS) can be filled to form a third lower bend pad (383). The lower curved surface (3192_CS) may include the upper surface (381_CS) of the first lower curved pad (381), the upper surface (382_CS) of the second lower curved pad (382), and the upper surface (383_CS) of the third lower curved pad (383). Subsequently, the carrier substrate (700) and the tape (TP) may be removed.

[0143] FIG. 19 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention. FIG. 20 is an enlarged cross-sectional view of portion P of FIG. 19. For convenience of explanation, detailed descriptions of technical features that overlap with those previously described are omitted, and differences are described in detail. The same reference numerals may be provided for configurations identical to the semiconductor package according to embodiments of the present invention described above.

[0144] Referring to FIG. 19, a semiconductor package (5) is provided. The semiconductor package (5) may include a solder ball (81), a solder layer (90) on the solder ball (81), a redistribution structure (500) on the solder layer (90), a bump (BP) on the redistribution structure (500), a first semiconductor structure (220c) on the bump (BP), a first connection structure (310c) on the first semiconductor structure (220c), a second semiconductor structure (320c) on the first connection structure (310c), and a first molding film (505) on the redistribution structure (500). The width of the first semiconductor structure (220c) may be smaller than the width of the second semiconductor structure (320c).

[0145] The redistribution structure (500) may include a first redistribution layer (511), a second redistribution layer (512) on the first redistribution layer (511), and a third redistribution layer (513) on the second redistribution layer (512). The first redistribution layer (511) may include a first redistribution pattern (501) and a first redistribution insulating layer (502). The first redistribution pattern (501) may include a conductive material. The second redistribution layer (512) and the third redistribution layer (513) may be similar to the first redistribution layer (511).

[0146] The first redistribution pattern (501), the solder layer (90), and the solder ball (81) can be electrically connected. The solder layer (90), the first redistribution layer (511), the second redistribution layer (512), and the third redistribution layer (513) can be electrically connected.

[0147] The redistribution structure (500) and the first semiconductor structure (220c) can be electrically connected through a bump (BP). The bump (BP) may include a conductive material. The bump (BP) may be interposed between the redistribution structure (500) and the first semiconductor structure (220c).

[0148] The first molding film (505) may be provided to cover a surface that does not come into contact with the first semiconductor structure (220c), among the upper surface of the redistribution structure (500), the side of the first semiconductor structure (220c), the side of the second semiconductor structure (320c), the upper surface of the second semiconductor structure (320c), and the lower surface of the second semiconductor structure (320c). The first molding film (505) may include an insulating material.

[0149] Referring to FIG. 20, a semiconductor substrate (225c), lower through-structures (221c, 222c, 223c), a first connecting structure (310c) on the semiconductor substrate (225c), and a second semiconductor substrate (325c) on the first connecting structure (310c) may be provided.

[0150] The first connection structure (310c) may be interposed between the first semiconductor substrate (225c) and the second semiconductor substrate (325c). The first connecting structure (310c) comprises a lower insulating film (317c), an interlayer (318c) on the lower insulating film (317c), lower connecting pads (311c, 312c, 313c, 314c) on the lower insulating film (317c), lower curved pads (381c, 382c, 383c) on the lower insulating film (317c), a bonding insulating film (319c) on the interlayer (318c), upper connecting pads (321c, 322c, 323c, 324c) on the lower connecting pads (311c, 312c, 313c, 314c), upper curved pads (391c, 392c, 393c) on the lower curved pads (381c, 382c, 383c), and upper connecting pads (321c, It may include upper connecting top pads (331c, 332c, 336c, 337c) on upper bending pads (391c, 392c, 393c), upper bending top pads (333c, 334c, 335c) on upper bending top pads (333c, 334c, 335c), and upper conductive pads (351c, 352c, 353) on upper bending top pads (333c, 334c, 335c).

[0151] The upper surfaces (381c_CS, 382c_CS, 383c_CS) of the lower bending pads (381c, 382c, 383c) and the lower surfaces (391c_CS, 391c_CS, 393c_CS) of the upper bending pads (391c, 392c, 393c) can be in contact.

[0152] Upper penetration structures (341c, 342c, 343c) may be provided on upper bend top pads (333c, 334c, 335c). The upper penetration structures (341c, 342c, 343c) may include a first upper penetration structure (341c), a second upper penetration structure (342c), and a third upper penetration structure (343c).

[0153] A first upper penetrating structure (341c) may be disposed on the first curved uppermost pad (333c). A first conductive pad (351c) may be disposed on the first curved uppermost pad (333c) so as to overlap with the first upper penetrating structure (341c). The same may be true for the second upper penetrating structure (342c), the second conductive pad (352c), the third upper penetrating structure (343c), and the third conductive pad (353c).

[0154] The upper surface of the first upper through-hole structure (341c) may form a co-surface with the upper surface of the bonding insulating film (319c). The same may be true for the second upper through-hole structure (342c) and the third upper through-hole structure (343c).

[0156] FIG. 21 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention.

[0157] Referring to FIG. 21, the semiconductor package may include a package substrate (810). First terminals (820) electrically connected to the package substrate (810) may be provided. Through the first terminals (820), the semiconductor package may be mounted on an external device (e.g., a main board).

[0158] An interposer (830) may be provided on a package substrate (810). Second terminals (840) that electrically connect the package substrate (810) and the interposer (830) may be provided. The second terminals (840) may be provided between the package substrate (810) and the interposer (830).

[0159] A processor chip (860) may be provided on the interposer (830). For example, the processor chip (860) may be a graphics processing unit (GPU) or a central processing unit (CPU). Third terminals (850) that electrically connect the processor chip (860) and the interposer (830) may be provided. The third terminals (850) may be provided between the processor chip (860) and the interposer (830).

[0160] A semiconductor package structure (1) of FIG. 1 may be provided on an interposer (830). The semiconductor package structure (1) may be spaced apart from a processor chip (860) in a first direction (D1). Solder balls may be provided to electrically connect the semiconductor package structure (1) and the interposer (830).

[0161] A molding film (MD) surrounding an interposer (830), a processor chip (860), and a semiconductor package structure (1) may be provided on a package substrate (810).

[0162] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A semiconductor device comprising: a first semiconductor structure including a first semiconductor substrate and a lower penetration structure penetrating the first semiconductor substrate; a connection structure on the first semiconductor structure; and a second semiconductor structure disposed on the connection structure and including a second semiconductor substrate and an upper penetration structure penetrating the second semiconductor substrate, wherein the connection structure comprises: a lower bending pad on the lower penetration structure; and an upper bending pad on the lower bending pad, wherein the upper surface of the lower bending pad is a curved surface, the lower surface of the upper bending pad is a curved surface, and the upper bending pad is electrically connected to the upper penetration structure. Claim 2 A semiconductor device according to claim 1, wherein the connecting structure further comprises: a plurality of upper conductive pads in contact with the upper penetrating structure; and a curved top pad on the upper curved pad, wherein the width of the upper conductive pads is smaller than the width of the curved top pad. Claim 3 A semiconductor device according to claim 1, wherein the connecting structure further comprises an upper connecting pad spaced apart from the upper bending pad; a bending top pad on the upper bending pad; and a connecting top pad on the upper connecting pad, wherein the width of the connecting top pad is greater than the width of the bending top pad. Claim 4 A semiconductor device according to claim 1, wherein the connecting structure comprises a lower insulating film on the first semiconductor substrate; and a lower connecting pad spaced apart from the lower bending pad, wherein the entire lower surface of the lower connecting pad is in contact with the lower insulating film and the lower surface of the lower bending pad is in contact with the lower penetrating structure. Claim 5 A semiconductor device according to claim 4, wherein the level of the upper surface of the lower bending pad is lower than the level of the upper surface of the lower connecting pad. Claim 6 A semiconductor device according to claim 1, wherein the connecting structure comprises a lower insulating film on the first semiconductor substrate; and an interposition film on the lower insulating film, wherein the level of the upper surface of the interposition film is lower than the level of the upper surface of the lower bending pad. Claim 7 A semiconductor device according to claim 1, wherein the connecting structure further comprises a top bend pad on the upper bend pad, and the top bend pad comprises a material different from the upper bend pad. Claim 8 A semiconductor device in which, in claim 7, the curvature of the upper surface of the lower bending pad and the lower surface of the upper bending pad are the same. Claim 9 A semiconductor device according to claim 1, wherein the connecting structure further comprises an upper connecting pad spaced apart from the upper bending pad; a bending top pad on the upper bending pad; and a connecting top pad on the upper connecting pad, wherein the level of the upper surface of the connecting top pad is higher than the level of the upper surface of the bending top pad. Claim 10 A semiconductor device comprising: a first semiconductor structure including a first semiconductor substrate and a lower penetration structure penetrating the first semiconductor substrate; a connection structure on the first semiconductor structure; and a second semiconductor structure disposed on the connection structure and including a second semiconductor substrate and an upper penetration structure penetrating the second semiconductor substrate, wherein the connection structure comprises: a lower insulating film on the first semiconductor substrate; a lower bending pad disposed on the lower insulating film and electrically connected to the lower penetration structure; and a lower connection pad disposed on the lower insulating film and spaced apart from the lower bending pad, wherein the level of the upper surface of the lower bending pad is lower than the level of the upper surface of the lower connection pad.

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