Display driving circuit and driving method thereof

Abstract

A display driving circuit according to one embodiment includes: a memory comprising a plurality of driving information corresponding to a plurality of display mode information regarding a method of processing an image signal; a signal control unit comprising a buffer, receiving display mode information and an image signal from a host, searching for driving information corresponding to the display mode information among the plurality of driving information in the memory and writing it to the buffer, and converting the image signal into image data based on the driving information written to the buffer; and a data driving unit generating a plurality of data signals according to the image data.

Description

Technology Field

[0001] The present invention relates to a display driving circuit and a method for driving the display driving circuit. Background Technology

[0002] Display panels provide users with various visual information through images, and the colors and resolutions expressed are constantly evolving to deliver even better image quality. Display Driver Integrated Circuits (DDIs) are used to implement images on display panels. As the portability and miniaturization of electronic products increase, the driving methods of display driver circuits can also become more diverse. To drive display driver circuits in various ways, large-capacity memory is required. The problem to be solved

[0003] This invention relates to a display driving circuit capable of driving in various modes and a method for driving the display driving circuit. means of solving the problem

[0004] A display driving circuit according to one embodiment includes: a memory comprising a plurality of driving information corresponding to a plurality of display mode information regarding a method of processing an image signal; a signal control unit comprising a buffer, receiving display mode information and an image signal from a host, searching for driving information corresponding to the display mode information among the plurality of driving information in the memory and writing it to the buffer, and converting the image signal into image data based on the driving information written to the buffer; and a data driving unit generating a plurality of data signals according to the image data.

[0005] In some embodiments, the signal control unit generates a vertical synchronization signal and an internal vertical synchronization signal delayed for a predetermined period with respect to the vertical synchronization signal based on written driving information, and the data driving unit can generate a plurality of data voltages according to image data synchronized with the internal vertical synchronization signal.

[0006] In some embodiments, a predetermined period may be a period corresponding to the time required for a signal control unit to search for driving information and write it to a buffer.

[0007] In some embodiments, the signal control unit may be configured to search for one driving information corresponding to the changed mode information and write it to a buffer when the display mode information received from the host is changed.

[0008] In some embodiments, the signal control unit includes a processor including internal memory, and the processor stores driving information written to a buffer in the internal memory and can convert an image signal into image data based on the driving information stored in the internal memory.

[0009] In some embodiments, the signal control unit includes a plurality of processors, each comprising an internal memory, and the signal control unit copies driving information written to a buffer as many times as there are processors and stores it in each internal memory, and each of the plurality of processors can convert an image signal into image data based on the driving information stored in the internal memory.

[0010] In some embodiments, the signal control unit includes a processor, and the processor can convert an image signal into image data based on driving information written in a buffer.

[0011] In some embodiments, a plurality of driving information is stored in the form of a lookup table, and the buffer may be configured as SRAM (Static Random Access Memory).

[0012] In some embodiments, the lookup table may include data regarding gamma characteristics indicating a correspondence between an image signal and image data.

[0013] In some embodiments, the buffer may be a memory with a shorter access time than the memory.

[0014] A method executed by a display device according to one embodiment includes: receiving display mode information and an image signal from a host; searching for driving information corresponding to the display mode information in a memory that stores a plurality of driving information corresponding to a plurality of display mode information regarding a method of processing the image signal, and writing the driving information to a buffer; and converting the image signal into image data based on the driving information written to the buffer.

[0015] In some embodiments, the method may further include the steps of: generating a vertical synchronization signal based on written driving information; generating an internal vertical synchronization signal delayed for a predetermined period with respect to the vertical synchronization signal; and generating a plurality of data signals according to image data synchronized with the internal vertical synchronization signal.

[0016] In some embodiments, a predetermined period may be a period corresponding to the time required to perform the step of retrieving driving information and the step of writing driving information to a buffer.

[0017] In some embodiments, if the display mode information received from the host is changed, the step of retrieving driving information and writing it to a buffer may be performed.

[0018] In some embodiments, the display mode information may be changed prior to the step of generating a vertical synchronization signal.

[0019] In some embodiments, the display device may further include the step of storing driving information written to a buffer in the internal memory of a processor, and the step of the processor converting an image signal into image data based on the driving information stored in the internal memory.

[0020] In some embodiments, the display device may include the step of storing driving information written to a buffer in a plurality of internal memories of a plurality of processors, and the step of the plurality of processors converting an image signal into a plurality of image data based on the driving information stored in the plurality of internal memories.

[0021] In some embodiments, the display device may include a step of converting into image data based on driving information written in a buffer.

[0022] A display system according to one embodiment includes: a host that generates display mode information and generates an image signal according to user input or external conditions; a signal control unit that includes a buffer, receives display mode information and an image signal from the host, searches for one driving information corresponding to the display mode information and writes it to the buffer, and converts the image signal into image data using the driving information written to the buffer; a memory that includes a plurality of driving information corresponding to a plurality of display mode information regarding a method of processing the image signal; a data driving unit that generates a plurality of data signals according to the image data; and a display panel that operates in response to a plurality of data signals received from the data driving unit.

[0023] In one embodiment, the display panel is controlled by a plurality of data voltages and includes a plurality of subpixels, and the signal control unit includes a plurality of processors corresponding to the plurality of subpixels, and each of the plurality of processors includes an internal memory, and the signal control unit copies driving information written to a buffer as many times as there are processors and stores it in each of the internal memories, and each of the plurality of processors converts an image signal into image data based on the driving information stored in the internal memory. Brief explanation of the drawing

[0024] FIG. 1 is a block diagram showing a display system according to embodiments. Figure 2 is a block diagram showing the configuration of a display driving circuit. Figure 3 is a flowchart showing the operation method of the control unit. FIG. 4 is a block diagram of a signal generation unit according to one embodiment. FIG. 5 is a block diagram of a signal generation unit according to another embodiment. FIG. 6 is a block diagram of a signal generation unit according to another embodiment. FIG. 7 is a timing diagram showing the operation method of a display device according to one embodiment. FIG. 8 is a drawing for explaining a semiconductor system according to one embodiment. Specific details for implementing the invention

[0025] Embodiments of the present invention are described below with reference to the attached drawings so that those skilled in the art can easily implement them. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0026] In addition, to clearly explain the invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification have been given similar reference numerals. In the flowcharts described with reference to the drawings, various operations may be merged, certain operations may be divided, and specific operations may not be performed.

[0027] Additionally, expressions written in the singular form may be interpreted as singular or plural unless explicit expressions such as "one" or "singular" are used. Terms including ordinal numbers, such as the first, the second, etc., may be used to describe various components, but the components are not limited by these terms. These terms may be used for the purpose of distinguishing one component from another.

[0028] FIG. 1 is a block diagram showing a display system according to embodiments.

[0029] The display system (1) may include a host (10) and a display device (20).

[0030] The host (10) can perform overall control over the operation of the display device (20). The host (10) may include an application processor or a System On Chip (SOC).

[0031] The host (10) can determine an appropriate mode for driving the display device (20) based on user input or external conditions. The display device (20) may be controlled according to one of a plurality of display modes. For example, the host (10) may determine the display mode by considering frequency information of the image signal (IMS), illumination information entering the display device (20), brightness information of the display panel (25), user input, etc. The host (10) may provide the determined display mode information to the display device (20). The display mode may refer to the method by which the display panel (25) displays data. For example, the display mode may be a mode in which data is output through the display panel (25) with high luminance when there is a lot of illumination entering the display device (20) or when the user sets the brightness of the display panel (25) high. Depending on the display mode information, the method by which the display device (20) processes the image signal to generate image data may vary.

[0032] The host (10) may provide an image signal (IMS) and a command (CMD) to the display device (20). The image signal (IMS) may be a video signal for display on a display panel (25). The image signal (IMS) may include luminance information that is divided into gray levels for each pixel of the display panel (25). The image signal (IMS) may include red, green, and blue data corresponding to red, green, and blue subpixels, respectively. The image signal (IMS) may be generated by the host (10) or transmitted to the host (10) from an external source. The command (CMD) may include information regarding display mode information, vertical synchronization, horizontal synchronization, etc.

[0033] In FIG. 1, the host (10) is shown as a separate component from the display device (20), but the host (10) may be located within the display device (20).

[0034] The display device (20) may include a display driver IC (DDI) (21) and a display panel (25). The display device (20) may include an organic light-emitting display device, a liquid crystal display device, etc. Additionally, the display device (20) may include a flexible display device, a rollable display device, a curved display device, a transparent display device, a mirror display device, etc., implemented as an organic light-emitting display device, etc.

[0035] The display driving circuit (21) can control the display panel (25) according to an image signal (IMS) and a command (CMD). The display driving circuit (21) can receive an image signal (IMS) and a command (CMD) from the host (10).

[0036] The display panel (25) may include a plurality of pixels. Each pixel may include a plurality of color (red, green, and blue) subpixels.

[0037] FIG. 2 is a block diagram showing the configuration of a display driving circuit. FIG. 3 is a flowchart showing the operation method of the control unit.

[0038] The display driving circuit (21) may include a signal generating unit (200), a scan driving unit (250), and a data driving unit (270).

[0039] The scan driving unit (250) can provide a plurality of scan signals (SS) to the display panel (25) in response to the first control signal (CON1).

[0040] The data driving unit (270) can provide a plurality of data signals (GS) corresponding to image data (DATA) to the display panel (25) in response to the second control signal (CON2). For example, the data driving unit (270) can convert the image data (DATA) into a plurality of data signals corresponding to the plurality of data signals (GS). Accordingly, the data driving unit (270) can convert the image data (DATA) in the grayscale domain into a data voltage in the voltage domain.

[0041] The signal generation unit (200) may include a signal control unit (210) and a memory (230). The signal control unit (210) may include a buffer (211) and a processor (215). The processor (215) is configured to control the overall operation of the signal control unit (210).

[0042] The processor (215) can receive a command (CMD) and an image signal (IMS).

[0043] The processor (215) can generate a first control signal (CON1) and a second control signal (CON2) based on a received command (CMD) and an image signal (IMS). Specifically, the processor (215) can retrieve driving information corresponding to the command (CMD) from the memory (230). Then, the processor (215) can generate the first control signal (CON1) and the second control signal (CON2) based on the driving information. The driving information may include information related to display driving timing, such as vertical synchronization, horizontal synchronization, and data writing period. Alternatively, information regarding driving timing may be included within the command (CMD). The first control signal (CON1) may include a horizontal synchronization signal.

[0044] Additionally, the processor (215) can generate image data (DATA) based on the received command (CMD) and image signal (IMS). Specifically, the processor (215) can retrieve driving information corresponding to the command (CMD) from the memory (230). And, the processor (215) can generate image data (DATA) based on the driving information and the image signal (IMS).

[0045] The processor (215) may perform an operation of searching for driving information corresponding to a command (CMD) received from the host (10) in memory (230) for every frame. However, the embodiments are not limited thereto, and the processor (215) may perform an operation of searching for driving information corresponding to a command (CMD) received from the host (10) in memory (230) at a preset period.

[0046] Alternatively, the processor (215) may perform the operation of searching for driving information corresponding to the changed mode information from the memory (230) only when the mode information indicated by the command (CMD) received from the host (10) is changed.

[0047] For example, there may be cases where the processor (215) receives a first command (CMD) from the host (10) and then receives a second command (CMD) following the first command (CMD). At this time, if the first command (CMD) and the second command (CMD) are the same, the processor (215) may not perform the operation of searching for driving information corresponding to the received second command (CMD) from the memory (230). However, if the display mode information in the second command (CMD) is different from the display mode information in the first command (CMD), the processor (215) may perform the operation of searching for driving information corresponding to the received second command (CMD) from the memory (230). Subsequently, the processor (215) may generate a first control signal (CON1), a second control signal (CON2), and image data (DATA) based on the driving information and image signal (IMS) searched from the memory (230).

[0048] Alternatively, the processor (215) may determine that the display mode has changed by considering information regarding vertical synchronization included in a command (CMD) received from the host (10) or the frequency at which an image signal (IMS) is input from the host (10). For example, the processor (215) may calculate the frame frequency from the information regarding vertical synchronization and determine that the display mode has changed when the frame frequency changes. Similarly, the processor (215) may calculate the frame frequency from the interval between data enable (DE) signals applied when an image signal (IMS) is input and determine that the display mode has changed when the frame frequency changes. When the display mode changes, the processor (215) may perform an operation of searching for driving information corresponding to the changed mode information from the memory (230).

[0049] The processor (215) writes driving information retrieved from memory (230) into a buffer (211) and may use the driving information written in the buffer (211) to generate a first control signal (CON1), a second control signal (CON2), and image data (DATA).

[0050] Additionally, the processor (215) may generate a second control signal (CON2) and transmit it to the data driver (270) along with image data (DATA). The second control signal (CON2) may include an internal vertical synchronization signal that distinguishes frames and an internal display activation signal that determines the data writing period. The internal vertical synchronization signal may be a signal that is delayed for a predetermined period relative to a vertical synchronization signal (hereinafter referred to as the original vertical synchronization signal) that is generated based on driving information or based on information included in a command (CMD). For example, the processor (215) may generate the original vertical synchronization signal based on information related to vertical synchronization among the driving information stored in the memory (230). The processor (215) may receive mode information from the host (10) in the front porch section prior to the original vertical synchronization signal. The processor (215) may generate an internal vertical synchronization signal for controlling the data driver (270) by delaying the original vertical synchronization signal for a predetermined period. At this time, a predetermined delay period may be the period required for the processor (215) to write the driving information retrieved from memory (230) into the buffer (211).

[0051] The internal display activation signal may be a signal that is delayed for a predetermined period with respect to a display activation signal (hereinafter referred to as the original display activation signal) generated based on driving information or based on information included in a command (CMD). For example, the processor (215) may generate the original display activation signal based on information related to the data writing period among the driving information stored in the memory (230). The processor (215) may generate an internal display activation signal for controlling the data driving unit (270) by delaying the original display activation signal for a predetermined period.

[0052] The buffer (211) can receive and temporarily store driving information retrieved by the processor (215) from the memory (230). The buffer (211) may be composed of SRAM (Static Random Access Memory) or flip-flops (FF), but the embodiments are not limited thereto and various types of memory may be used.

[0053] The memory (230) may contain driving information required according to the display mode. The memory (230) may be composed of any non-volatile memory. For example, the memory (230) may be NAND Flash Memory, Vertical NAND (VNAND), NOR Flash Memory, Resistive Random Access Memory (RRAM), Phase-Change Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin Transfer Torque Random Access Memory (STT-RAM), etc.

[0054] Driving information according to the display mode may be stored in memory (230) in advance, taking into account the physical characteristics of the display panel (25). The driving information may be information that needs to be updated on a frame-by-frame basis and may be in the form of a look-up table (LUT).

[0055] For example, the lookup table may include a gamma transformation table based on a gamma value indicating gamma characteristics. The processor (215) can derive image data (DATA) corresponding to an image signal (IMS) using the gamma transformation table of the lookup table. The correlation between the image signal (IMS) and the image data (DATA) may follow a gamma curve specified according to the gamma value. Through the gamma transformation table that specifies the gamma curve according to the gamma value, the processor (215) can convert the image signal (IMS) into image data (DATA).

[0056] Since the buffer (211) can be composed of SRAM, flip-flops, etc., the time it takes for the processor (215) to access the buffer (211) to read driving information may be shorter than the time it takes for the processor (215) to access the memory (230). Since the amount of driving information that can be stored in the buffer (211) is limited, the processor (215) can store the necessary driving information from the memory (230) where the driving information is stored into the buffer (211) and use it whenever the display mode information changes.

[0057] With reference to FIG. 3, the operation method of the signal generation unit (200) will be explained in detail.

[0058] The signal control unit (210) can receive mode information (S301) from the host (10). Alternatively, the signal control unit (210) can determine mode information based on the signal received from the host (10).

[0059] The signal control unit (210) can read the memory (230) and search for a lookup table (S303) corresponding to the received mode information.

[0060] Afterwards, the signal control unit (210) can write the searched lookup table to the buffer (211) (S305).

[0061] The signal control unit (210) can control the scan drive unit (250) and the data drive unit (270) based on the lookup table stored in the buffer (211) (S307).

[0062] FIG. 4 is a block diagram of a signal generation unit according to one embodiment.

[0063] The signal generation unit (400) may include a signal control unit (410) and a memory (430).

[0064] The signal control unit (410) may include a buffer (411) and a processor (415). The processor (415) may perform an operation of converting an image signal (IMS) into image data (DATA). The processor (415) may process at least one of a plurality of data within the image signal (IMS). For example, the processor (415) may process at least one of red (R), green (G), and blue (B) data within the image signal (IMS), but the embodiments are not limited thereto.

[0065] The processor (415) may include internal memory (413).

[0066] The internal memory (413) may be composed of flip-flops, but the embodiments are not limited thereto. The processor (415) can convert an image signal (IMS) into image data (DATA) based on data stored in the internal memory (413).

[0067] The memory (430) may include lookup tables (431a, 431b, … , 431n) containing driving information according to the display mode.

[0068] The signal control unit (410) can receive mode information within a command (CMD) from the host (10). For example, the signal control unit (410) can receive mode information from the host (10) during the front porch period prior to the point in time when the original vertical synchronization signal (Vsync) was generated.

[0069] The signal control unit (410) can search for a lookup table (431k) corresponding to mode information in the memory (430). The signal control unit (410) can write the searched lookup table (431k) to the buffer (411). The time required for the signal control unit (410) to search for the lookup table (431k) and write it to the buffer (411) may be pre-set.

[0070] Afterwards, the signal control unit (410) can load the lookup table (431k) stored in the buffer (411) into the internal memory (413) in response to the original vertical synchronization signal (Vsync).

[0071] The processor (415) can convert an image signal (IMS) into image data (DATA) using a lookup table (431k) loaded in internal memory (413).

[0072] FIG. 5 is a block diagram of a signal generation unit according to another embodiment.

[0073] The signal generation unit (500) may include a signal control unit (510) and a memory (530).

[0074] The signal control unit (510) may include a buffer (511) and a plurality of processors (515). Each processor (515_1, 515_2, …, 515_n) may perform the operation of converting an image signal (IMS) into image data (DATA). For example, each processor (515_1, 515_2, …, 515_n) may process each of the red (R), green (G), and blue (B) data within the image signal (IMS), but the embodiments are not limited thereto. Each of the plurality of processors (515_1, 515_2, …, 515_n) may convert the image signal (IMS) into image data (DATA) in the same manner as the processor (415) described with reference to FIG. 4 using a corresponding lookup table.

[0075] Each processor (515_1, 515_2, …, 515_n) may include a corresponding internal memory (513_1, 513_2, …, 513_n).

[0076] The internal memory (513_1, 513_2, …, 513_n) may be composed of flip-flops, but the embodiments are not limited thereto. The processor (515_m, where m is a natural number greater than or equal to 1) can convert an image signal (IMS) into image data (DATA) based on data stored in the internal memory (513_m, where m is a natural number greater than or equal to 1).

[0077] The memory (530) may include lookup tables (531a, 531b, … , 531n) containing driving information according to the display mode.

[0078] The signal control unit (510) can receive mode information within a command (CMD) from the host (10). For example, the signal control unit (510) can receive mode information from the host (10) during the front porch period prior to the point in time when the original vertical synchronization signal (Vsync) was generated.

[0079] The signal control unit (510) can search for a lookup table (531k) corresponding to mode information in the memory (530). The signal control unit (510) can write the searched lookup table (531k) to the buffer (511). The time required for the signal control unit (510) to search for the lookup table (531k) and write it to the buffer (511) may be pre-set.

[0080] Subsequently, the signal control unit (510) can copy the lookup table (531k) stored in the buffer (511) in response to the original vertical synchronization signal (Vsync) as many times as the number of processors (515). In FIG. 5, since n processors (515_1, 515_2, …, 515_n) are shown, the signal control unit (510) can create n lookup tables (531k) by copying the lookup table (531k). Subsequently, the signal control unit (510) can load the lookup table (531k) into the internal memory (513_m) of each processor (515_m).

[0081] The processor (515_m) can convert an image signal (IMS) into image data (DATA) according to a lookup table (531k) loaded in internal memory (513_m).

[0082] FIG. 6 is a block diagram of a signal generation unit according to another embodiment.

[0083] The signal generation unit (600) may include a signal control unit (610) and a memory (630).

[0084] The signal control unit (610) may include a buffer (611) and a plurality of processors (615). The plurality of processors (615) may perform the operation of converting an image signal (IMS) into image data (DATA). For example, each processor (615_1, 615_2, …, 615_n) may process each of the red (R), green (G), and blue (B) data within the image signal (IMS), but the embodiments are not limited thereto. Each of the plurality of processors (615_1, 615_2, …, 615_n) may convert the image signal (IMS) into image data (DATA) in the same manner as the processor (415) described with reference to FIG. 4 using a corresponding lookup table.

[0085] The memory (630) may include lookup tables (631a, 631b, … , 631n) containing driving information according to the display mode.

[0086] The signal control unit (610) can receive mode information within a command (CMD) from the host (10). For example, the signal control unit (610) can receive mode information from the host (10) during the front porch period prior to the point in time when the original vertical synchronization signal (Vsync) was generated.

[0087] The signal control unit (610) can search for a lookup table (631k) corresponding to mode information in the memory (630). The signal control unit (610) can write the searched lookup table (631k) to the buffer (611). The time required for the signal control unit (610) to search for the lookup table (631k) and write it to the buffer (611) may be pre-set.

[0088] Subsequently, the signal control unit (610) can transmit the lookup table (631k) stored in the buffer (611) in response to the original vertical synchronization signal (Vsync) to each of the plurality of processors (615_1, 651_2, …, 651_n). Each of the plurality of processors (615_1, 651_2, …, 651_n) can convert the image signal (IMS) into image data (DATA) according to the received lookup table (631k).

[0089] FIG. 7 is a timing diagram showing the operation method of a display device according to one embodiment.

[0090] At t1, the processor (215) generates and outputs a pulse-shaped external vertical synchronization signal (External Vsync). In the front porch period prior to the point in time when the external vertical synchronization signal (External Vsync) is generated, the processor (215) receives mode information (Display Mode) from the host (10). Here, although it has been described that the mode information can be received from the host (10), it may also be determined by the processor (215).

[0091] The external display signal (Display active) is deactivated at time t0 and activated at t5. The activation period of the external display signal (Display active) may be the period during which data voltage is output to the display panel. In reality, the interval during which data is output to the display panel (25) is not the frame interval (1 frame) by the external vertical synchronization signal (External Vsync), but the frame interval (1'frame) by the internal vertical synchronization signal (Internal Vsync).

[0092] The processor (215) can search for any one lookup table corresponding to mode information received from the host (10) in memory (230) and write it to the buffer (211) during the period t2-t4. As shown in FIG. 7, during the period t2-t4, data (LUT_DATA) for the lookup table searched in memory (230) can be transferred to and written to the buffer (211). In FIG. 7, the section in which the searched lookup table is written to the buffer (211) is illustrated as a buffer write signal (Buffer write).

[0093] The time (t2-t4) required for the processor (215) to search the lookup table and write to the buffer (211) may be pre-set.

[0094] At t3, the processor (215) generates and outputs an internal vertical synchronization signal (internal Vsync) in the form of a pulse.

[0095] At t4, the processor (215) reads the lookup table stored in the buffer (211) in response to the internal vertical synchronization signal (Vsync). In FIG. 7, the period (t4-t6) during which the buffer (211) reads the lookup table is illustrated as a buffer read signal. During the period t4-t6, the processor (215) reads the lookup table stored in the buffer (211), copies it as many times as there are processors in the signal generation unit (200), and can deliver one lookup table to each processor. At the same time, at t3, a frame interval (1'frame) is started by the internal vertical synchronization signal (Internal Vsync).

[0096] At t6, the internal display signal (I_Display active) is activated. From t6, each processor within the signal generation unit (200) can convert the image signal (IMS) into image data (DATA) based on the lookup table received from the buffer (211). During the period when the internal display signal (Internal Display active) is activated, the data driving unit (270) can output multiple data voltages corresponding to one frame to multiple data lines.

[0097] At t7, the external vertical synchronization signal (External Vsyncn) is reactivated, and the signal generation unit (200) can repeat the operation described above.

[0098] FIG. 8 is a drawing for explaining a semiconductor system according to one embodiment.

[0099] Referring to FIG. 8, a semiconductor system (8) according to one embodiment may include a processor (80), a memory (82), a display device (84), and a peripheral device (86) that are electrically connected to a system bus (88).

[0100] The processor (80) controls the input and output of data from memory (82), a display device (84), and peripheral devices (86), and can perform image processing of video data transmitted between the devices.

[0101] The display device (84) includes a display driving circuit (840) and a display panel (842), and can store image data applied through the system bus (88) in a frame memory included within the display driving circuit (840) and then display it on the display panel (842). The display driving circuit (840) may be a display driving circuit according to embodiments of the present invention.

[0102] The peripheral device (86) may be a device that converts video or still images, such as a camera, scanner, or webcam, into electrical signals. Image data acquired through the peripheral device (86) may be stored in memory (82) or displayed in real time on a display panel (842).

[0103] The memory (82) may include volatile memory such as DRAM (Dynamic Random Access Memory) and / or non-volatile memory such as flash memory. The memory (82) may be composed of DRAM, PRAM (Phase-change Random Access Memory), MRAM (Magnetic Random Access Memory), ReRAM (Resistive Random Access Memory), FRAM (Ferroelectric Random Access Memory), NOR flash memory, NAND flash memory, and fusion flash memory (e.g., memory combining a SRAM (Static Random Access Memory) buffer, NAND flash memory, and NOR interface logic). The memory (82) may store image data acquired from a peripheral device (86) or store an image signal processed by a processor (80).

[0104] The semiconductor system (8) may be provided in a mobile electronic product such as a smartphone, but is not limited thereto, and may be provided in various types of electronic products that display images.

[0105] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

Claims

Claim 1 A display driving circuit comprising: a memory including multiple driving information corresponding to multiple display mode information regarding a method of processing an image signal, wherein the multiple driving information includes information regarding display driving timing for driving a display panel; a signal control unit including a buffer, receiving display mode information and an image signal from a host, and when the display mode information received from the host is changed, in a front porch section prior to the generation of a vertical synchronization signal for the current frame, searching for driving information corresponding to the changed display mode information from the memory, writing the searched driving information to the buffer, and converting the image signal into image data based on the driving information written to the buffer; and a data driving unit generating multiple data signals according to the image data. Claim 2 A display driving circuit according to claim 1, wherein the signal control unit generates a vertical synchronization signal and an internal vertical synchronization signal delayed for a predetermined period with respect to the vertical synchronization signal based on the written driving information, and the data driving unit generates a plurality of data voltages according to the image data synchronized with the internal vertical synchronization signal. Claim 3 A display driving circuit according to paragraph 2, wherein the predetermined period is a period corresponding to the time required for the signal control unit to search for the driving information and write it to the buffer. Claim 4 delete Claim 5 A display driving circuit according to claim 1, wherein the signal control unit includes a processor including an internal memory, the processor stores driving information written to the buffer in the internal memory, and converts the image signal into image data based on the driving information stored in the internal memory. Claim 6 A display driving circuit according to claim 1, wherein the signal control unit comprises a plurality of processors each including an internal memory, the signal control unit copies driving information written in the buffer as many times as the number of the plurality of processors and stores it in each of the internal memories, and each of the plurality of processors converts the image signal into image data based on the driving information stored in the internal memory. Claim 7 In claim 1, the signal control unit includes a processor, and the processor converts the image signal into image data based on driving information written in the buffer, a display driving circuit. Claim 8 In claim 1, the display driving circuit, wherein the buffer is a memory with a shorter access time than the memory. Claim 9 A method executed by a display device, comprising: receiving display mode information and an image signal from a host; when the display mode information received from the host is changed, in the front porch of a vertical blanking period prior to the step of generating a vertical synchronization signal for the current frame, retrieving driving information corresponding to the changed display mode information from memory - wherein the memory stores a plurality of driving information corresponding to a plurality of display mode information regarding a method of processing the image signal, and the plurality of driving information includes information regarding a display driving timing for driving a display panel included in the display device -; writing the retrieved driving information to a buffer; and converting the image signal into image data based on the driving information written to the buffer. Claim 10 A method according to claim 9, further comprising: a step of generating a vertical synchronization signal based on the driving information entered above; a step of generating an internal vertical synchronization signal delayed for a predetermined period with respect to the vertical synchronization signal; and a step of generating a plurality of data signals according to the image data synchronized with the internal vertical synchronization signal.

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