Method for manufacturing semiconductor device

Abstract

The present invention relates to a method for manufacturing a semiconductor device. A method for manufacturing a semiconductor device according to one embodiment may include the steps of forming an insulating layer, forming a barrier layer on the insulating layer, performing a nitriding process on the barrier layer, and forming a metal electrode on the barrier layer. In one embodiment, the step of performing the nitriding process may include performing a High Pressure Nitridation (HPN) process. According to the embodiments, by improving the quality of the barrier layer during the manufacturing process of the semiconductor device, the electrical characteristics of the barrier layer and the metal electrode are improved, and accordingly, the electrical characteristics of the semiconductor device may also be improved.

Description

Technology Field

[0001] The present invention relates to a method for manufacturing a semiconductor device. Background Technology

[0003] Semiconductor devices are components primarily used in electronic circuits or similar devices that utilize the electrical conductivity characteristics of semiconductors. Semiconductors can be classified into memory semiconductors and non-memory semiconductors. Memory semiconductors can be classified into volatile memory such as DRAM and SRAM, and non-volatile memory such as Mask ROM, EP ROM, EEP ROM, and flash memory.

[0004] Figure 1 shows the structure of a typical semiconductor device.

[0005] Referring to FIG. 1, the semiconductor device may include an insulating layer (12) formed on a substrate (11) having a predetermined structure and a metal electrode (14) formed on the insulating layer (12).

[0006] The metal electrode (14) may include a metal material such as Al, Cu, or W. Metal ions contained in the metal electrode (14), or oxygen or moisture, may diffuse into the insulating layer (12), causing the insulating layer (12) to become contaminated or problems such as spikes to occur. To prevent such problems, a barrier layer (13) acting as a barrier may be formed between the insulating layer (12) and the metal electrode (14) during the manufacturing process of the semiconductor device. The barrier layer (13) may include a metal material (e.g., Ti, Ta, TiN, TaN, TiOx, TaOx, W, WN, WO, etc.).

[0007] However, if a metal electrode (14) is formed on top of the barrier layer (13) after the barrier layer (13) has been formed, the conformality of the barrier layer (13) is reduced, and there is a problem that foreign substances (e.g., H2 or D2) exist inside the barrier layer (13). The degradation of electrical characteristics due to the low quality of the barrier layer (13) can also degrade the electrical characteristics of the metal electrode (14). As a result, there is a problem that the electrical characteristics of the semiconductor device are reduced. The problem to be solved

[0009] The objective of the present invention is to provide a method for manufacturing a semiconductor device that can improve the electrical characteristics of a barrier layer and a metal electrode by improving the quality of the barrier layer during the manufacturing process of the semiconductor device.

[0010] The purpose of this specification is not limited to the purposes mentioned above, and other purposes and advantages of this specification not mentioned will be more clearly understood by the embodiments of this specification described below. Furthermore, the purposes and advantages of this specification may be realized by the components and combinations thereof described in the claims. means of solving the problem

[0012] A method for manufacturing a semiconductor device according to one embodiment may include the steps of forming an insulating layer, forming a barrier layer on the insulating layer, performing a nitriding process on the barrier layer, and forming a metal electrode on the barrier layer.

[0013] In one embodiment, the step of performing the nitriding process may include the step of performing a High Pressure Nitridation (HPN) process.

[0014] In one embodiment, the HPN process may be performed in a chamber in which a reactive gas containing nitrogen is injected in an inert gas atmosphere.

[0015] In one embodiment, when the HPN process is performed, the concentration of the reactive gas in the chamber may be 5% or more.

[0016] In one embodiment, when the HPN process is performed, the internal pressure of the chamber can be maintained at 2 to 50 atmospheres.

[0017] In one embodiment, when the HPN process is performed, the internal temperature of the chamber can be maintained at 200 to 1000°C.

[0018] A method for manufacturing a semiconductor device according to one embodiment may further include the step of performing a High Pressure Anneal (HPA) process on the barrier layer.

[0019] In one embodiment, the HPA process may be performed in a chamber in which a reactive gas containing hydrogen is injected in an inert gas atmosphere.

[0020] In one embodiment, when the HPA process is performed, the concentration of the reactive gas in the chamber may be 5% or more.

[0021] In one embodiment, when the HPA process is performed, the internal pressure of the chamber can be maintained at 2 to 50 atmospheres.

[0022] In one embodiment, when the HPA process is performed, the internal temperature of the chamber can be maintained at 200 to 1000°C. Effects of the invention

[0024] According to the embodiments, by improving the quality of the barrier layer during the manufacturing process of a semiconductor device, the electrical characteristics of the barrier layer and the metal electrode are improved, and accordingly, the electrical characteristics of the semiconductor device can also be improved. Brief explanation of the drawing

[0026] Figure 1 shows the structure of a typical semiconductor device. FIGS. 2 and FIGS. 3 illustrate the manufacturing process of a semiconductor device according to one embodiment. FIGS. 4 to 8 illustrate the manufacturing process of a semiconductor device according to other embodiments. FIG. 9 is a graph showing the resistance value of a barrier layer measured when voltage is applied to a general semiconductor device and a semiconductor device according to one embodiment. FIG. 10 is a graph showing the resistance value of a metal electrode measured when a voltage is applied to a general semiconductor device and a semiconductor device according to one embodiment. Specific details for implementing the invention

[0027] The aforementioned objectives, features, and advantages are described in detail below with reference to the attached drawings, and accordingly, a person skilled in the art to which this specification pertains will be able to easily implement the embodiments of this specification. In describing this specification, detailed descriptions of known technologies related to this specification are omitted if it is determined that such descriptions would unnecessarily obscure the gist of this specification. Hereinafter, preferred embodiments of this specification will be described in detail with reference to the attached drawings. In the drawings, the same reference numerals indicate the same or similar components.

[0028] FIGS. 2 and FIGS. 3 illustrate the manufacturing process of a semiconductor device according to one embodiment.

[0029] As illustrated in FIGS. 2 and 3, according to a method for manufacturing a semiconductor device according to one embodiment, an insulating layer (22) is formed on a substrate (21), and a barrier layer (23) is formed on the insulating layer (22).

[0030] In one embodiment, the substrate (21) may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0031] In one embodiment, the insulating layer (22) may be a silicon oxide film formed through a thermal oxidation process or a silicon oxide film formed using a deposition technique.

[0032] In one embodiment, the barrier layer (23) may include a metal material (e.g., Ti, Ta, TiN, TaN, TiOx, TaOx, W, WN, WO, etc.).

[0033] When the barrier layer (23) is formed, a nitriding process is performed on the barrier layer (23) (24). By performing the nitriding process on the barrier layer (23), the content of nitrogen (N) components inside the barrier layer (23) is increased, and impurities inside the barrier layer (23) can be removed. In addition, by performing the nitriding process on the barrier layer (23), the conformality of the barrier layer (23) can be increased.

[0034] In one embodiment, the nitriding process performed on the barrier layer (23) may include a High Pressure Nitridation (HPN) process.

[0035] In one embodiment, the HPN process can be performed in a chamber in which a reactive gas containing nitrogen is injected in an inert gas atmosphere.

[0036] Examples of inert gases include N2, Ar, and He, but the types of inert gases are not limited to these.

[0037] Examples of reactive gases containing nitrogen include NH2 and NH3, but the types of reactive gases containing nitrogen are not limited to these.

[0038] In one embodiment, when the HPN process is performed, the concentration of the reactive gas containing nitrogen in the chamber may be 5% or more. For example, when the HPN process is performed, the concentration of the reactive gas containing nitrogen in the chamber may be 5% to 100%.

[0039] In one embodiment, when the HPN process is performed, the internal pressure of the chamber can be maintained at 2 to 50 atmospheres.

[0040] In one embodiment, when the HPN process is performed, the internal temperature of the chamber can be maintained at 200 to 1000°C.

[0041] When a nitriding process is performed on the barrier layer (23) as described above, the conformality of the barrier layer (23) is increased, and thus the electrical characteristics of the barrier layer (23) can be improved. In addition, when the barrier layer (23) has high conformality, the conformality of the metal electrode (24) formed on the barrier layer (23) is also increased, and thus the electrical characteristics of the metal electrode (24) can also be improved.

[0042] After the nitriding process (24) is performed on the barrier layer (23), a metal electrode (25) can be formed on the nitrided barrier layer (23).

[0043] The metal electrode (25) may be formed by a physical vapor deposition (PVD) process such as plasma sputtering or evaporation, but the method of forming the metal electrode (25) is not limited thereto. The metal electrode (25) may include a metal material such as W, Al, Ti, Ta, Co, or Cu.

[0044] Meanwhile, according to another embodiment, a High Pressure Anneal (HPA) process can be performed on the barrier layer (23).

[0045] In one embodiment, the HPA process can be performed in a chamber in which a reactive gas containing hydrogen is injected in an inert gas atmosphere.

[0046] Examples of inert gases include N2, Ar, and He, but the types of inert gases are not limited to these.

[0047] Examples of reactive gases containing hydrogen include H2 and D2, but the types of reactive gases containing hydrogen are not limited to these.

[0048] In one embodiment, when the HPA process is performed, the concentration of the reactive gas containing hydrogen in the chamber may be 5% or more. For example, when the HPN process is performed, the concentration of the reactive gas containing hydrogen in the chamber may be 5% to 100%.

[0049] In one embodiment, when the HPA process is performed, the internal pressure of the chamber can be maintained at 2 to 50 atmospheres.

[0050] In one embodiment, when the HPA process is performed, the internal temperature of the chamber can be maintained at 200 to 1000°C.

[0051] In one embodiment, an HPN process for the barrier layer (23) may be performed after the HPA process for the barrier layer (23) is performed. In another embodiment, an HPA process for the barrier layer (23) may be performed after the HPN process for the barrier layer (23) is performed.

[0052] When the HPA process and the HPN process are performed together on the barrier layer (23), the conformability of the barrier layer (23) and the conformability of the metal electrode (25) are further improved compared to when only the HPN process is performed on the barrier layer (23). Accordingly, the electrical characteristics of the barrier layer (23) and the electrical characteristics of the metal electrode (25) can be further improved.

[0053] FIGS. 4 to 8 illustrate the manufacturing process of a semiconductor device according to other embodiments.

[0054] Referring to FIG. 4, a thin film structure (TS) can be formed by alternately and repeatedly depositing sacrificial layers (112) and insulating layers (110) on a substrate (100).

[0055] In one embodiment, the substrate (100) may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0056] In one embodiment, the sacrificial layers (112) may be formed to have the same thickness. However, according to another embodiment, the lowest and highest sacrificial layers (112) among the sacrificial layers (112) may be formed thicker than the sacrificial layers (112) located between them.

[0057] In one embodiment, the insulating layers (110) may have the same thickness. In another embodiment, some of the insulating layers (110) may have different thicknesses.

[0058] In one embodiment, the sacrificial layers (112) and the insulating layer (110) may be formed using a thermal chemical vapor deposition (Thermal CVD), plasma enhanced chemical vapor deposition (Plasma enhanced CVD), physical chemical vapor deposition (PSCVD), or atomic layer deposition (ALD) process.

[0059] In one embodiment, the sacrificial layers (112) and the insulating layers (110) may comprise materials having different etch selectivity. For example, the sacrificial layers (112) may be at least one of a silicon film, a silicon oxide film, a silicon carbide film, a silicon oxynitride film, and a silicon nitride film. The insulating layers (110) may be at least one of a silicon film, a silicon oxide film, a silicon carbide film, a silicon oxynitride film, and a silicon nitride film, but may be a material different from that of the sacrificial layers (112). For example, the sacrificial layers (112) may be formed of a silicon nitride film, and the insulating layers (110) may be formed of a silicon oxide film. However, according to another embodiment, the sacrificial layers (112) may be formed of a conductive material, and the insulating layers (110) may be formed of an insulating material.

[0060] Through holes (H) that penetrate the thin film structure (TS) and expose the substrate (100) may be formed. The through holes (H) may be formed two-dimensionally on the upper surface of the thin film structure (TS) in a planar view. According to one embodiment, the through holes (H) may be arranged along a first direction (D1). However, according to another embodiment, the through holes (H) may be arranged in a zigzag pattern along the first direction (D1).

[0061] Forming through holes (H) may include forming a first mask pattern (not shown) having openings that define an area where through holes (H) are to be formed on a thin film structure (TS), and anisotropically etching the thin film structure (TS) using the first mask pattern as an etching mask. The first mask pattern may be formed of a material having selectivity for sacrificial layers (112) and insulating layers (110). By the etching process, the upper surface of the substrate (100) may be over-etched so that the upper surface of the substrate (100) may be recessed.

[0062] Next, as shown in FIG. 5, a charge storage structure (150) and a first semiconductor pattern (160) can be formed that cover the inner wall of each of the through holes (H) and expose the substrate (100).

[0063] Specifically, a charge storage structure film (not shown) and a first semiconductor film (not shown) covering the inner wall of each of the through holes (H) may be formed in sequence. The charge storage structure film and the first semiconductor film may be formed to fill a portion of each of the through holes (H). Each of the through holes (H) may not be completely filled by the charge storage structure film and the first semiconductor film.

[0064] The charge storage structure film can cover the upper surface of the substrate (100) exposed by the through holes (H). The charge storage structure film can be deposited, for example, using plasma enhanced chemical vapor deposition (PVD), physical chemical vapor deposition (PVD), or atomic layer deposition (ALD) technology.

[0065] The first semiconductor film may be formed on a charge storage structure film. According to one embodiment, the first semiconductor film may be a semiconductor material formed using one of atomic layer deposition (ALD) or chemical vapor deposition (CVD) techniques. The first semiconductor film may be, for example, a polycrystalline silicon film. According to one embodiment, the first semiconductor film may be amorphous at the time of deposition, but may be crystallized using an annealing process or the like.

[0066] After the charge storage structure film and the first semiconductor film are formed in sequence, the charge storage structure film and the first semiconductor film can be anisotropically etched to expose the substrate (100). Accordingly, the first semiconductor pattern (160) and the charge storage structure (150) can be formed on the inner wall of each of the through holes (H). That is, the charge storage structure (150) and the first semiconductor pattern (160) can be formed in a cylindrical shape having open ends. As a result of over-etching during the anisotropic etching of the first semiconductor film and the charge storage structure film, the upper surface of the substrate (100) exposed by the first semiconductor pattern (160) and the charge storage structure (150) can be recessed.

[0067] In one embodiment, the charge storage structure (150) may include a tunnel insulating layer, a charge storage layer, and a blocking insulating layer stacked sequentially between the first semiconductor pattern (160) and the thin film structure (TS). The blocking insulating layer, the charge storage layer, and the tunnel insulating layer may be sequentially deposited on the inner wall of each of the through holes (H) using plasma enhanced chemical vapor deposition (PVD), physical chemical vapor deposition (PVD), or atomic layer deposition (ALD) technology.

[0068] Next, a second semiconductor pattern (165) and a buried insulation pattern (170) can be formed to fill the remainder of each of the through holes (H).

[0069] Specifically, a second semiconductor film (not shown) and a buried insulating film (not shown) may be formed sequentially on a substrate (100) on which a charge storage structure (150) and a first semiconductor pattern (160) are formed.

[0070] The second semiconductor film may be formed with a thickness that does not completely fill each of the through holes (H). The second semiconductor film may cover the inner wall of each of the through holes (H) and may cover the upper surface of the substrate (100) exposed by the charge storage structure (150) and the first semiconductor pattern (160). The second semiconductor film may connect the substrate (100) and the first semiconductor pattern (160).

[0071] The second semiconductor film may be a semiconductor material formed using one of atomic layer deposition (ALD) or chemical vapor deposition (CVD) techniques. The second semiconductor film may be, for example, a polycrystalline silicon film. According to one embodiment, the second semiconductor film may be amorphous at the time of deposition, but may be crystallized using an annealing process or the like. The buried insulating film may be formed to completely fill the interior of each of the through holes (H). The buried insulating film may be at least one of insulating materials formed using SOG technology and a silicon oxide film.

[0072] The buried insulating film and the second semiconductor film can be flattened so that a second semiconductor pattern (165) and a buried insulating pattern (170) can be formed within each of the through holes (H). By the flattening process, the second semiconductor pattern (165) and the buried insulating pattern (170) can be formed locally within each of the through holes (H). The first and second semiconductor patterns (160, 165) can be defined as semiconductor patterns (SP).

[0073] Next, as shown in FIG. 6, a trench (T) can be formed by patterning a thin film structure (TS) to expose a substrate (100) between adjacent through holes (H).

[0074] Forming a trench (T) may include forming a second mask pattern (not shown) that defines a planar position on a thin film structure (TS) where the trench (T) is to be formed, and anisotropically etching the thin film structure (TS) using the second mask pattern as an etching mask.

[0075] A trench (T) may be formed spaced apart from the semiconductor pattern (SP) to expose the sidewalls of the sacrificial layers (112) and the insulating layers (110). In a horizontal view, the trench (T) may be formed in a line shape or a rectangle, and in terms of vertical depth, the trench (T) may be formed to expose the upper surface of the substrate (100). During the etching process, the upper surface of the substrate (100) may be over-etched so that the upper surface of the substrate (100) may be recessed.

[0076] Unlike what is illustrated, the trench (T) may have different widths depending on the distance from the substrate (100) by an anisotropic etching process. That is, the width of the lower part of the trench (T) may be narrower than the width of the upper part of the trench (T).

[0077] Next, the sacrificial layers (112) exposed by the trench (T) can be removed to form recessed regions (R) between the insulating layers (110). The recessed regions (R) can be formed by isotropically etching the sacrificial layers (112) using etching conditions that have etch selectivity for the insulating layers (110), the charge storage structure (150), the semiconductor pattern (SP), the lower insulating film (105), and the substrate (100). The sacrificial layers (112) can be completely removed by an isotropic etching process. For example, when the sacrificial layers (112) are silicon nitride films and the insulating layers (110) are silicon oxide films, the etching process can be performed using an etching solution containing phosphoric acid.

[0078] Next, as shown in the enlarged view (300) of FIG. 7, a barrier layer (200) is formed inside each recess area (R). The barrier layer (200) can be formed on the insulating layers (110) and the charge storage structure (150).

[0079] In one embodiment, the barrier layer (200) may include a metal material (e.g., Ti, Ta, TiN, TaN, TiOx, TaOx, W, WN, WO, etc.).

[0080] When the barrier layer (200) is formed, a nitriding process is performed on the barrier layer (200) (202). By performing the nitriding process on the barrier layer (200), the content of nitrogen (N) components inside the barrier layer (200) is increased, and impurities inside the barrier layer (200) can be removed. In addition, by performing the nitriding process on the barrier layer (200), the conformability of the barrier layer (200) can be increased.

[0081] In one embodiment, the nitriding process performed on the barrier layer (200) may include an HPN process.

[0082] In one embodiment, the HPN process can be performed in a chamber in which a reactive gas containing nitrogen is injected in an inert gas atmosphere.

[0083] Examples of inert gases include N2, Ar, and He, but the types of inert gases are not limited to these.

[0084] Examples of reactive gases containing nitrogen include NH2 and NH3, but the types of reactive gases containing nitrogen are not limited to these.

[0085] In one embodiment, when the HPN process is performed, the concentration of the reactive gas containing nitrogen in the chamber may be 5% or more. For example, when the HPN process is performed, the concentration of the reactive gas containing nitrogen in the chamber may be 5% to 100%.

[0086] In one embodiment, when the HPN process is performed, the internal pressure of the chamber can be maintained at 2 to 50 atmospheres.

[0087] In one embodiment, when the HPN process is performed, the internal temperature of the chamber can be maintained at 200 to 1000°C.

[0088] When a nitriding process is performed on the barrier layer (200) as described above, the conformability of the barrier layer (200) is increased, so the electrical characteristics of the barrier layer (200) can be improved. In addition, when the barrier layer (200) has high conformability, the conformability of the metal electrode (204) formed on the barrier layer (200) is also increased, so the electrical characteristics of the metal electrode (204) can also be improved.

[0089] After the nitriding process (24) is performed on the barrier layer (200), a metal electrode (204) can be formed on the nitrided barrier layer (200).

[0090] The metal electrode (204) may be formed by a PVD process such as plasma sputtering or evaporation, but the method of forming the metal electrode (204) is not limited thereto. The metal electrode (204) may include a metal material such as W, Al, Ti, Ta, Co, or Cu.

[0091] Meanwhile, according to another embodiment, an HPA process for the barrier layer (200) can be performed.

[0092] In one embodiment, the HPA process can be performed in a chamber in which a reactive gas containing hydrogen is injected in an inert gas atmosphere.

[0093] Examples of inert gases include N2, Ar, and He, but the types of inert gases are not limited to these.

[0094] Examples of reactive gases containing hydrogen include H2 and D2, but the types of reactive gases containing hydrogen are not limited to these.

[0095] In one embodiment, when the HPA process is performed, the concentration of the reactive gas containing hydrogen in the chamber may be 5% or more. For example, when the HPA process is performed, the concentration of the reactive gas containing hydrogen in the chamber may be 5% to 100%.

[0096] In one embodiment, when the HPA process is performed, the internal pressure of the chamber can be maintained at 2 to 50 atmospheres.

[0097] In one embodiment, when the HPA process is performed, the internal temperature of the chamber can be maintained at 200 to 1000°C.

[0098] In one embodiment, an HPN process for the barrier layer (200) may be performed after the HPA process for the barrier layer (200) is performed. In another embodiment, an HPA process for the barrier layer (200) may be performed after the HPN process for the barrier layer (200) is performed.

[0099] When the HPA process and the HPN process are performed together on the barrier layer (200), the conformability of the barrier layer (200) and the conformability of the metal electrode (204) are further improved compared to when only the HPN process is performed on the barrier layer (200). Accordingly, the electrical characteristics of the barrier layer (200) and the electrical characteristics of the metal electrode (204) can be further improved.

[0100] A semiconductor device like the one in Fig. 8 can be completed through this process.

[0101] FIG. 9 is a graph showing the resistance value of a barrier layer measured when voltage is applied to a general semiconductor device and a semiconductor device according to one embodiment.

[0102] In FIG. 9, M1 is a general semiconductor device as illustrated in FIG. 1, i.e., a semiconductor device in which an HPN process or an HPA process is not performed on the barrier layer (13). Also, in FIG. 9, M2 is a semiconductor device having the same structure as FIG. 3 and in which an HPN process is performed on the barrier layer (23). Also, in FIG. 9, M3 is a semiconductor device having the same structure as FIG. 3 and in which an HPA process and an HPN process are performed on the barrier layer (23).

[0103] As shown in FIG. 9, when a voltage is applied to the semiconductor device (M1), the resistance value of the barrier layer (13) is greater than the resistance value of the barrier layer (23) when a voltage is applied to the semiconductor device (M2). According to these results, it can be seen that when the HPN process is applied to the barrier layer, the conformability of the barrier layer is improved, thereby reducing the resistance of the barrier layer.

[0104] In addition, as shown in FIG. 9, when a voltage is applied to the semiconductor device (M2), the resistance value of the barrier layer (23) is greater than the resistance value of the barrier layer (23) when a voltage is applied to the semiconductor device (M3). According to these results, it can be seen that when the HPA process and the HPN process are applied together to the barrier layer, the conformability of the barrier layer is improved compared to when only the HPN process is applied to the barrier layer, thereby further reducing the resistance of the barrier layer.

[0105] FIG. 10 is a graph showing the resistance value of a metal electrode measured when a voltage is applied to a general semiconductor device and a semiconductor device according to one embodiment.

[0106] In FIG. 10, M1 is a general semiconductor device as illustrated in FIG. 1, i.e., a semiconductor device in which an HPN process or an HPA process is not performed on the barrier layer (13). Also, in FIG. 10, M2 is a semiconductor device having a structure as shown in FIG. 3 and in which an HPN process is performed on the barrier layer (23). Also, in FIG. 10, M3 is a semiconductor device having a structure as shown in FIG. 3 and in which an HPA process and an HPN process are performed on the barrier layer (23).

[0107] As shown in FIG. 10, when a voltage is applied to the semiconductor device (M1), the resistance value of the metal electrode (14) is greater than the resistance value of the metal electrode (25) when a voltage is applied to the semiconductor device (M2). According to these results, it can be seen that when the HPN process is applied to the barrier layer, the conformability of the metal electrode is improved, thereby reducing the resistance of the metal electrode.

[0108] In addition, as shown in FIG. 10, when a voltage is applied to the semiconductor device (M2), the resistance value of the metal electrode (25) is greater than the resistance value of the metal electrode (25) when a voltage is applied to the semiconductor device (M3). According to these results, it can be seen that when the HPA process and the HPN process are applied together to the barrier layer, the conformability of the metal electrode is improved compared to when only the HPN process is applied to the barrier layer, thereby further reducing the resistance of the metal electrode.

[0109] Although the present specification has been described above with reference to the illustrative drawings, the present invention is not limited by the embodiments and drawings disclosed in the present specification, and various modifications may be made by those skilled in the art. Furthermore, even if the effects according to the configuration of the present specification were not explicitly described while explaining the embodiments of the present specification above, the effects predictable by said configuration should also be acknowledged.

Claims

Claim 1 A method for manufacturing a semiconductor device comprising: a step of forming an insulating layer; a step of forming a barrier layer on the insulating layer; a step of performing a nitriding process on the barrier layer in a chamber; a step of performing an annealing process on the barrier layer on which the nitriding process has been performed in the chamber; and a step of forming a metal electrode on the barrier layer on which the annealing process has been performed, wherein the annealing process is performed in the chamber into which a reactive gas containing hydrogen is injected, and the internal pressure of the chamber is maintained at 2 to 50 atmospheres when the nitriding process or the annealing process is performed. Claim 2 A method for manufacturing a semiconductor device according to claim 1, wherein the nitriding process is performed in a chamber in which a reactive gas containing nitrogen is injected in an inert gas atmosphere. Claim 3 A method for manufacturing a semiconductor device according to claim 2, wherein the concentration of the reactive gas in the chamber is 5% or more when the nitriding process is performed. Claim 4 delete Claim 5 A method for manufacturing a semiconductor device according to claim 1, wherein the internal temperature of the chamber is maintained at 200 to 1000℃ when the nitriding process is performed. Claim 6 delete Claim 7 delete Claim 8 A method for manufacturing a semiconductor device according to claim 1, wherein the concentration of the reactive gas in the chamber is 5% or more when the annealing process is performed. Claim 9 delete Claim 10 A method for manufacturing a semiconductor device according to claim 1, wherein the internal temperature of the chamber is maintained at 200 to 1000℃ when the annealing process is performed.

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