Gate Driving Circuit and Organic Light Emitting Display using the same

Abstract

The present invention relates to a gate driving circuit capable of reducing bezel size and enabling stable driving even at low speeds, and an organic light-emitting display device using the same. The gate driving circuit of the present invention comprises a plurality of dependently connected stages, and the nth stage comprises a node control unit that controls the voltages of a first node and a second node according to a start signal or the output of a preceding stage and a first clock signal, an output unit that outputs a gate-on voltage or a gate-off voltage according to the voltages of the first and second nodes, and a stabilization unit that stabilizes the first node by the second clock signal.

Description

Technology Field

[0001] The present invention relates to a gate driving circuit capable of stable driving even at low speeds and an organic light-emitting display device using the same. Background Technology

[0002] In the information society, significant technological advancements are being made in the field of display devices to display visual information as images or videos. Among these display devices, organic light-emitting diodes (OLEDs) are gaining attention as next-generation displays because they utilize organic light-emitting diodes—self-luminous devices that emit light through the recombination of electrons and holes—to provide fast response speeds, high brightness, low driving voltage, enable ultra-thin films, and allow for the realization of free-form shapes.

[0003] An organic light-emitting display device comprises a display panel having data lines, scan lines, and a plurality of subpixels formed at the intersection of the data lines and scan lines, a gate driving circuit that supplies scan signals to the scan lines, and a data driving circuit that supplies data voltages to the data lines.

[0004] Each subpixel of the display panel is equipped with an organic light emitting diode (hereinafter referred to as 'OLED') and a pixel circuit that independently drives the organic light emitting diode.

[0005] The pixel circuit described above includes a driving thin film transistor that controls the driving current flowing through the OLED according to the gate-source voltage, a capacitor that maintains the gate-source voltage of the driving TFT constant for one frame, at least one switching thin film transistor that programs the gate-source voltage of the driving TFT in response to a gate signal, and a sensing TFT for sensing the characteristics of the driving TFT.

[0006] The gate driving circuit can be formed directly on the same substrate together with the circuit elements constituting each pixel circuit. The gate driving circuit formed directly on the substrate of the display panel together with the circuit elements constituting each pixel circuit is referred to as a "GIP (Gate In Panel) circuit."

[0007] The TFTs constituting the pixel circuit above utilize LTPS (Low Temperature Poly Silicon) TFTs with excellent on-current characteristics and Oxide Semiconductor TFTs with excellent off-current characteristics, and the TFT constituting the gate driving circuit utilizes LTPS TFTs with excellent on-current characteristics.

[0008] However, recently, in order to simplify driving and improve image quality, it has become necessary to develop technology that configures the pixel circuit entirely with oxide semiconductor TFTs having excellent off-current characteristics, and applies LTPS TFTs and oxide semiconductor TFTs to the GIP circuit to implement a narrow bezel. The problem to be solved

[0009] The purpose of the present invention is to provide a gate driving circuit capable of stable driving even during low-speed driving by continuously maintaining a low voltage at the Q node of the gate driving circuit, and an organic light-emitting display device using the same. means of solving the problem

[0010] A gate driving circuit according to one embodiment of the present invention for achieving the above-mentioned purpose comprises a plurality of dependently connected stages, and the nth stage may comprise a node control unit that controls the voltage of a first node and a second node according to a start signal or the output of a preceding stage and a first clock signal, an output unit that outputs a gate-on voltage or a gate-off voltage according to the voltages of the first and second nodes, and a stabilization unit that stabilizes the first node by a clock signal applied to the next stage.

[0011] The above stabilization unit may be configured by having a TFT in which a first electrode is connected to a clock signal supply line that supplies a clock signal of the next stage and a gate electrode is connected to the first node, and a capacitor connected between the second electrode of the TFT and the first node.

[0012] In addition, an organic gate light-emitting display device according to one embodiment of the present invention for achieving the above-mentioned purpose comprises a display panel including data lines, gate lines, and subpixels, a data driving circuit that supplies a data signal of an input image to the data lines, and a gate driving circuit that supplies a gate signal to the gate lines, wherein the gate driving circuit comprises a plurality of dependently connected stages, and the nth stage may comprise a node control unit that controls the voltage of a first node and a second node according to a start signal or the output of a preceding stage and a first clock signal, an output unit that outputs a gate-on voltage or a gate-off voltage according to the voltages of the first and second nodes, and a stabilization unit that stabilizes the first node by a clock signal applied to the next stage. Effects of the invention

[0013] The gate driving circuit according to the present invention having the above-described features and the organic light-emitting display device using the same have the following effects.

[0014] Even if a leakage current occurs in the second TFT (T12) due to gate bias stress, the gate driving circuit can be driven stably because the first node is pumped by the stabilization unit, even if the gate-on voltage is always applied to the second TFT, which applies a start signal or an output signal of the previous stage to the first node (Q), and the second TFT applies a start signal or an output signal of the previous stage to the first node (Q).

[0015] In particular, since the first node (Q) can be maintained at the gate-on voltage for a long time, the gate driving circuit can be driven stably even during low-speed driving.

[0016] In addition, since the gate driving circuit can be driven stably even at low speeds, the display quality can be improved. Brief explanation of the drawing

[0017] FIG. 1 is a drawing showing a display device according to an embodiment of the present invention. Figure 2 is a diagram schematically showing the circuit configuration of a shift register in a gate driving circuit (120). Figures 3a and 3b are schematic diagrams showing a pass gate circuit and an edge trigger circuit. Figure 4 is a diagram showing in detail the GIP circuit of the gate driving circuit according to the first comparative example. Figure 5 is a diagram showing the input and output waveforms of the circuit illustrated in Figure 4. FIG. 6 is a diagram showing in detail the GIP circuit of a gate driving circuit according to the first embodiment of the present invention. Figure 7 is a diagram showing the input and output waveforms of the circuit illustrated in Figure 6. Figure 8 is a diagram showing in detail the GIP circuit of the gate driving circuit according to the second comparative example. Figure 9 is a diagram showing the input and output waveforms of the circuit illustrated in Figure 8. FIG. 10 is a drawing showing in detail the GIP circuit of a gate driving circuit according to a second embodiment of the present invention. Figure 11 is a diagram showing the input and output waveforms of the circuit illustrated in Figure 10. Specific details for implementing the invention

[0018] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below but may be implemented in various different forms; the embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0019] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the matters shown in the drawings. Throughout the specification, the same reference numerals refer to substantially the same components. Furthermore, in describing the present invention, detailed descriptions of related prior art are omitted if it is determined that such detailed descriptions may unnecessarily obscure the essence of the present invention.

[0020] Where terms such as "comprising," "including," "having," "consisting of," etc. are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it may be interpreted as plural unless specifically stated otherwise.

[0021] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0022] In the case of a description of a positional relationship, for example, when the positional relationship between two components is described using expressions such as 'on top of,' 'above,' 'below,' or 'next to,' one or more other components may be interposed between those components where 'immediately' or 'directly' is not used.

[0023] First, second, etc., may be used to distinguish components, but the function or structure of these components is not limited by the ordinal number or component name preceding the component. Since the patent claims are described based on essential components, the ordinal number preceding the component name in the patent claims may not match the ordinal number preceding the component name in the embodiments.

[0024] The following embodiments may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or together in an associated relationship.

[0025] In the present invention, the GIP circuit of the gate driving circuit and the pixel circuit each include a plurality of transistors. The transistors can be implemented as TFTs with a Metal-Oxide-Semiconductor FET (MOSFET) structure, or as Oxide TFTs including an oxide semiconductor or LTPS TFTs including Low Temperature Poly Silicon (LTPS). Oxide TFTs can be implemented as n-type TFTs (NMOS), and LTPS TFTs can be implemented as p-type TFTs (PMOS). Both n-type TFTs (NMOS) and p-type TFTs (PMOS) can be formed in the GIP circuit of the gate driving circuit and the pixel circuit, respectively.

[0026] A MOSFET is a three-electrode device comprising a gate, source, and drain. The source is the electrode that supplies carriers to the transistor. Within a MOSFET, carriers begin to flow from the source. The drain is the electrode from which carriers exit the MOSFET. In a MOSFET, the flow of carriers is from the source to the drain. In the case of an n-type TFT (NMOS), since the carriers are electrons, the source voltage is lower than the drain voltage to allow electrons to flow from the source to the drain. In an n-type TFT (NMOS), the direction of current flows from the drain to the source. In the case of a p-type TFT (PMOS), since the carriers are holes, the source voltage is higher than the drain voltage to allow holes to flow from the source to the drain. In a p-type TFT (PMOS), current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a TFT are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the TFT. In the following description, the source and drain of the TFT will be referred to as the first and second electrodes.

[0027] The gate signal output from the GIP circuit of the gate driving circuit swings between the gate on voltage and the gate off voltage. The gate on voltage is set to a voltage higher than the threshold voltage of the TFT, and the gate off voltage is set to a voltage lower than the threshold voltage of the TFT. The TFT is turned on in response to the gate on voltage, while it is turned off in response to the gate off voltage.

[0028] Hereinafter, various embodiments of this specification will be described in detail with reference to the attached drawings. In the following embodiments, the electroluminescent display device is described primarily as an organic light-emitting display device including an organic light-emitting material. It should be noted that the technical concept of this specification is not limited to organic light-emitting display devices. For example, the present invention can be applied without significant modification to the gate driving circuit of a digital flat panel display device requiring a gate driving circuit, such as a liquid crystal display (LCD) or a quantum dot display (QD).

[0029] FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention.

[0030] A display device according to an embodiment of the present specification includes a display panel (100) and a display panel driving circuit.

[0031] The display panel (100) includes an active area (AA) that displays data of an input image. The active area (AA) is a screen in which video data of the input image is displayed. The pixel array of the active area (AA) includes a plurality of data lines (DL), a plurality of gate lines (GL) that intersect the data lines (DL), and pixels arranged in a matrix form. In addition to the matrix form, the arrangement of pixels can be formed in various ways, such as a form sharing pixels that emit the same color, a stripe form, a diamond form, etc.

[0032] Each pixel may be divided into a red subpixel, a green subpixel, and a blue subpixel for color implementation. Each pixel may also include a white subpixel. Each of the subpixels (101) includes a pixel circuit. In the case of an electroluminescent display device, the pixel circuit includes a light-emitting element, a plurality of TFTs, and a capacitor. The pixel circuit is connected to a data line (DL) and a gate line (GL). In FIG. 1, "D1~D3" indicated inside the circle are data lines, and "Gn-2~Gn" are gate lines.

[0033] Touch sensors may be placed on a display panel (100). Touch input may be sensed using separate touch sensors or through pixels. The touch sensors may be implemented as on-cell type or add-on type touch sensors placed on the screen of the display panel, or as in-cell type touch sensors embedded in a pixel array.

[0034] The driving circuit for driving the display panel (100) comprises a data driving circuit (110) and a gate driving circuit (120). The display panel driving circuit writes data of an input image to the pixels of the display panel (100) under the control of a timing controller (TCON) (130).

[0035] The display panel driving circuit can operate in a low refresh driving mode (Tlrr). The low refresh driving mode (Tlrr) can be set to reduce the power consumption of the display device when the input image is not changing for a preset number of frames after analyzing the input image. In other words, the low refresh driving mode (Tlrr) can reduce power consumption by controlling the data writing cycle of pixels to be longer by lowering the refresh rate of pixels when a still image is input for a certain period of time or longer. The low refresh driving mode (Tlrr) is not limited to when a still image is input. For example, the display panel driving circuit may operate in a low refresh driving mode when the display device operates in standby mode or when user commands or input images are not input to the display panel driving circuit for a predetermined period of time or longer.

[0036] The data driving circuit (110) converts the digital data (DATA) of the input image received from the timing controller (130) for each frame in the normal driving mode (Tnor) into a data voltage, and then supplies the data voltage to the data lines (DL). The data driving circuit (110) outputs the data voltage using a digital to analog converter (hereinafter referred to as "DAC") that converts the digital data into a gamma compensation voltage. In the low-speed driving mode, the driving frequency of the data driving unit (110) is lowered under the control of the timing controller (130).

[0037] The data driving circuit (110) outputs the data voltage of the input image for each frame period in normal driving mode (Tnor).

[0038] The data driving unit (110) outputs the data voltage of the input image during some frame periods in the low-speed driving mode (Tlrr) and does not generate output during the remaining frame periods. Therefore, in the low-speed driving mode, the driving frequency and power consumption of the data driving circuit (110) can be lower than in the normal driving mode.

[0039] The data driving circuit (110) outputs a data voltage to be supplied to the pixels of all lines of the display panel (100) within the vertical active section (VA). When the pixel array of the display panel (100) includes N*M pixels, the display panel (100) includes M data lines (DL). The data voltage can be divided into a video data voltage for display and a data voltage for sensing. The data voltage for display is the data voltage of the input image. The data voltage for sensing is a data voltage for sensing the electrical characteristics of a subpixel. The data voltage for sensing is a specific voltage that is preset regardless of the data of the input image.

[0040] A gate driving circuit (120) may be formed in a bezel area (BZ) where no image is displayed on a display panel (100). The gate driving circuit (120) outputs a gate signal under the control of a timing controller (130) to select pixels in which data voltage is charged through gate lines (GL). The gate driving circuit (120) outputs a gate signal and shifts the gate signal using one or more shift registers. The gate driving circuit (120) shifts the gate signal supplied to the gate lines at a constant shift timing to a specific gate line set within a vertical active section, and then temporarily holds the voltage of the specific gate line in response to a line control signal. Subsequently, the gate driving circuit (120) supplies a gate signal to the specific gate line and then shifts the gate pulse supplied to the remaining gate lines at a constant shift timing. Accordingly, within the vertical active section, the first and second gate signals are applied only to specific gate lines with a predetermined holding time in between, and a single gate signal is applied to the other gate lines.

[0041] The gate driving circuit (120) can have its driving frequency lowered under the control of the timing controller (130) in a low-speed driving mode. Accordingly, the driving frequency and power consumption of the gate driving circuit (120) are lower than in the normal driving mode.

[0042] The timing controller (130) receives digital video data (DATA) of an input image and a timing signal synchronized therewith from a host system. The timing signal includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock signal (DCLK), and a data enable signal (DE), etc. The host system may be any one of a TV (Television), a set-top box, a navigation system, a personal computer (PC), a home theater, a mobile device, or a wearable device. In mobile devices and wearable devices, the data driving circuit (110), the timing controller (130), the level shifter (140), etc., may be integrated into a single drive IC.

[0043] The timing controller (130) includes a low-speed drive control module that lowers the drive frequency of the display panel drive circuit (110, 120). As previously mentioned, the low-speed drive mode is not limited to still images.

[0044] The timing controller (130) can control the operation timing of the display panel driving circuit (110, 120) by multiplying the input frame frequency by i in normal driving mode to a frame frequency of input frame frequency × i (i is a positive integer greater than 0) Hz. The input frame frequency is 60Hz in the NTSC (National Television Standards Committee) system and 50Hz in the PAL (Phase-Alternating Line) system.

[0045] The timing controller (130) lowers the driving frequency of the display panel driving circuit (110, 120) in a low-speed driving mode. For example, the timing controller (130) can lower the driving frequency of the display panel driving circuit to a level of 1 Hz so that data is written to the pixels once per second. The frequency of the low-speed driving mode is not limited to 1 Hz. Therefore, the pixels of the display panel (100) can maintain an already charged data voltage without charging a new data voltage for most of the time in the low-speed driving mode.

[0046] The timing controller (130) generates a data timing control signal (DDC) for controlling the operation timing of the data driving circuit (110) and a gate timing control signal (GDC) for controlling the operation timing of the gate driving circuit (120) based on timing signals (Vsync, Hsync, DE) received from the host system.

[0047] The level shifter (140) converts the voltage of the gate timing control signal (GDC) output from the timing controller (130) into a gate on voltage and a gate off voltage and supplies them to the gate driving circuit (120). The low level voltage of the gate timing control signal (GDC) is converted into a gate low voltage (VGL), and the high level voltage of the gate timing control signal (GDC) is converted into a gate high voltage (VGH).

[0048] In the case of an n-type TFT (NMOS), the gate-on voltage may be the gate high voltage (VGH) and the gate-off voltage may be the gate low voltage (VGL). In the case of a p-type TFT (PMOS), the gate-on voltage may be the gate low voltage (VGL) and the gate-off voltage may be the gate high voltage (VGH).

[0049] The gate timing control signal (GDC) includes a gate start pulse (VST), a gate shift clock (CLK), etc. The start pulse is generated once at the beginning of each frame period and input to the gate driving circuit (120). The start pulse (VST) controls the start timing of the gate driving circuit (120) for each frame period. The clock (CLK) controls the shift timing of the gate signal output from the gate driving circuit (120).

[0050] FIG. 2 is a schematic diagram showing the circuit configuration of a shift register in a gate driving circuit (120). FIG. 3a and FIG. 3b are schematic diagrams showing a pass gate circuit and an edge trigger circuit.

[0051] The shift register of the gate driving circuit (120) includes dependently connected stages (ST(n-1) to ST(n+2)). The shift register receives a start pulse (VST) or a scan signal (Vgout(n-1) to Vgout(n+2)) or a carry signal (CAR1 to CAR4) received from the previous stage as a start pulse and generates an output (Gout(n-1)) to Gout(n+2)) in accordance with clock timing. Hereinafter, the start signal refers to the start pulse (VST) or a scan signal (Vgout(n-1) to Vgout(n+2)) or a carry signal (CAR1 to CAR4) generated from the previous stage and applied to the VST node of the next stage.

[0052] Each stage can be implemented as a pass-gate circuit as shown in Fig. 3a or an edge trigger circuit as shown in Fig. 3b.

[0053] In the pass gate circuit, a clock (CLK) is input to a pull-up transistor (Tup) that turns on / off according to the voltage of the Q node. In contrast, in the edge trigger circuit, a gate-on voltage (VGL) is supplied to a pull-up transistor (Tup) that turns on / off according to the voltage of the Q node, and a start signal (VST) and a clock (CLK) are input. A pull-down transistor (Tdn) is turned on / off according to the voltage of the QB node.

[0054] In the pass gate circuit, the Q node is floating in a pre-charged state according to the start signal. When the clock (CLK) is applied to the pull-up transistor (Tup) while the Q node is floating, the Q node voltage rises due to bootstrapping, and the voltage of the output signal (Gout(n)) changes to the gate-on voltage.

[0055] An edge trigger circuit generates an output signal (Gout(N)) with a waveform identical to the phase of the start signal because the voltage of the output signal (Gout(n)) changes with the voltage of the start signal synchronized with the edge of the clock (CLK). If the start signal waveform is changed, the waveform of the output signal is also changed accordingly. In an edge trigger circuit, the input signal overlaps with the output signal.

[0056] It is difficult for a pass gate circuit to generate an output signal in the opposite phase of the input signal. If the transistors of the pass gate circuit are implemented using p-type TFTs (PMOS), it is possible to output a gate-on voltage waveform for p-type transistors. However, when implementing a pass gate circuit with p-type transistors (PMOS), an inverter circuit is additionally required to invert the voltage at the output node in order to output a gate-on voltage waveform for an n-type TFT. If an inverter circuit is connected to the output terminal of the pass gate circuit, the area of ​​the GIP circuit increases, which consequently widens the bezel of the display device. One could consider a method of inverting the phase of the clock signal input to the pass gate circuit. However, this method cannot obtain the desired output waveform because the Q node does not bootstrap due to the clock signal inversion, and the Q node voltage does not rise.

[0057] An edge trigger circuit can generate an inverse phase output signal. For example, according to an embodiment of the present invention, the edge trigger circuit can obtain a gate-on voltage waveform of an n-type TFT without an inverter circuit by implementing the transistors of the edge trigger circuit as p-type TFTs, as shown in FIG. 4.

[0058] The gate driving circuit according to the present invention is implemented based on an edge trigger circuit.

[0059] First embodiment

[0060] Before describing the gate driving circuit according to the first embodiment of the present invention, the GIP circuit of the first comparative example is described as follows.

[0061] FIG. 4 is a diagram showing in detail the GIP circuit of the gate driving circuit according to the first comparative example, and FIG. 5 is a diagram showing the input and output waveforms of the circuit shown in FIG. 4.

[0062] The GIP circuit of the first comparative example shown in FIG. 4 is the n-th (n is a positive integer) stage circuit. The transistors shown in FIG. 4 consist of a p-type TFT (PMOS) and an n-type TFT (NMOS). Here, the p-type TFT is an LTPS TFT containing low-temperature polysilicon (LTPS), and the n-type TFT is an Oxide TFT containing an oxide semiconductor.

[0063] Referring to FIGS. 4 and FIGS. 5, the nth stage of the first comparative example includes a plurality of TFTs (T1~T4, T6~T7) and one capacitor (Cq).

[0064] The nth stage of the first comparative example comprises, as shown in FIG. 4, a first TFT (T1) in which a first electrode is connected to the input terminal of a start signal (VST) or the output terminal (Vgout(n-1)) of the previous stage, a gate electrode is connected to the supply line of a first clock signal (CLK1), and a second electrode is connected to the N node (N) to be turned on / off according to the first clock signal (CLK1) to apply the start signal (VST) or the output signal (Vgout(n-1)) of the previous stage to the N node (N); a second TFT (T2) in which a first electrode is connected to the N node (N), a gate electrode is connected to the supply line of a gate-on voltage (VGL), and a second electrode is connected to the first node (Q) to be turned on / off according to the gate-on voltage (VGL) to connect the N node (N) and the first node (Q); and a first electrode is connected to the supply line of a gate-on voltage (VGL) and a gate electrode is connected to the first node (Q). A third TFT (T3) in which a second electrode is connected to a second node (QB) and turns on / off according to the voltage of a first node (Q) to supply a gate-on voltage (VGL) to the second node (QB); a fourth TFT (T4) in which a first electrode is connected to the second node (QB), a gate electrode is connected to the first node (Q), and a second electrode is connected to a gate-off voltage (VGH) supply line to supply a gate-off voltage (VGH) to the second node (QB) by turning on / off according to the voltage of the first node (Q); a pull-up TFT (T6) in which a first electrode is connected to a gate-on voltage (VGL) supply line, a gate electrode is connected to the first node (Q), and a second electrode is connected to an output terminal (OUT) to output a gate-on voltage (VGL) to the output terminal (OUT) by turning on / off according to the voltage of the first node (Q); and a first electrode is connected to a gate-off voltage (VGH) supply line, and a second A pull-down TFT (T7) in which a gate electrode is connected to a node (QB) and a second electrode is connected to an output terminal (OUT), and which is turned on / off according to the voltage of the second node (QB) to output a gate off voltage (VGH) to the output terminal (OUT);It is configured to include a capacitor (Cq) connected between the gate electrode and the second electrode of a pull-up TFT (T6) to bootstrap the first node (Q).

[0065] Here, the first TFT (T1), second TFT (T2), fourth TFT (T4), pull-up TFT (T6), and pull-down TFT (T7) are p-type TFTs (PMOS), and the third TFT (T3) is an n-type TFT (NMOS).

[0066] The operation of the nth stage of the comparative example configured in this way is explained as follows.

[0067] In FIG. 5, the high level of the start signal (VST), each clock signal (CLK1, CLK2), and each stage output signal (Vgout(n-1), Vgout(n), Vgout(n+1)) corresponds to the gate off voltage (VGH), and the low level of the start signal (VST), each clock signal (CLK1, CLK2), and each stage output signal (Vgout(n-1), Vgout(n), Vgout(n+1)) corresponds to the gate on voltage (VGL).

[0068] As shown in FIG. 5, when the start signal (VST) or the output signal of the previous stage (Vgout(n-1)) is input at a high level, and the first clock signal (CLK1) is applied at a gate-on voltage (low level) (t1), the first node (Q) is charged to a gate-off voltage (high level) through the first and second TFTs (T1, T2).

[0069] When the first node (Q) is charged to a gate-off voltage (High Level), the third TFT (T3) is turned on, so the second node (QB) is charged to a gate-on voltage (Low Level; VGL).

[0070] Accordingly, the pull-up TFT (T6) is turned off and the pull-down TFT (T7) is turned on, and the gate-off voltage (High Level; VGH) is output as an output signal (Vgout(n)).

[0071] Then, after a period of 4H, when the start signal (VST) or the output signal of the previous stage (Vgout(n-1)) is input at a low level, and the first clock signal (CLK1) is applied again at a gate-on voltage (low level) (t2), the first node (Q) is charged to a gate-on voltage (low level) through the first and second TFTs (T1, T2).

[0072] When the first node (Q) is charged to the gate-on voltage (Low Level), the third TFT (T3) is turned off and the fourth TFT (T4) is turned on, so the second node (QB) is charged to the gate-off voltage (High Level; VGH).

[0073] Accordingly, the pull-up TFT (T6) is turned on and the pull-down TFT (T7) is turned off, and the gate-on voltage (Low Level; VGL)) is output as an output signal (Vgout(n)).

[0074] After the point in time (t2) when the first clock signal (CLK1) is applied again to the gate-on voltage (Low level), the voltage applied to the gate of the second TFT (T2) and the voltage applied to the first electrode (Source) become the same level. That is, the gate-source voltage (Vgs) of the second TFT (T2) becomes 0V.

[0075] Since the Vgs of the second TFT (T2) is 0V, the second TFT (T2) is turned off, and the first node (Q) is floated. The floating first node (Q) is bootstrapped by the capacitor (Cq) and maintains a voltage lower than the gate-on voltage (VGL).

[0076] However, since the gate-on voltage (VGL) is always applied to the gate of the second TFT (T2), leakage current occurs in the second TFT (T2) due to gate bias stress.

[0077] In this way, if leakage current occurs in the second TFT (T2), the voltage of the first node (Q) rises, and as a result, the gate driving circuit may malfunction. In particular, when driving at a low speed such as 1 Hz, the first node (Q) must maintain the gate-on voltage for a long time, so an output abnormality of the gate driving circuit occurs due to the leakage current of the second TFT (T2).

[0078] The gate driving circuit according to the first embodiment of the present invention is intended to solve the problems of the gate driving circuit of the first comparative example.

[0079] FIG. 6 is a detailed drawing of a GIP circuit of a gate driving circuit according to a first embodiment of the present invention. The GIP circuit shown in FIG. 6 is an n-th (n is a positive integer) stage circuit. The transistors shown in FIG. 6 are exemplified as p-type TFTs (PMOS) and n-type TFTs (NMOS), but are not limited thereto. Here, the p-type TFT may be an LTPS TFT including low-temperature polysilicon (LTPS), and the n-type TFT may be an Oxide TFT including an oxide semiconductor.

[0080] Figure 7 is a diagram showing the input and output waveforms of the circuit illustrated in Figure 6.

[0081] The output (Vgout) shown in FIGS. 6 and 7 may be a scan signal (SCAN) and a light emission control signal (EM).

[0082] Referring to FIGS. 6 and FIGS. 7, the nth stage of the gate driving circuit (120) according to the first embodiment of the present invention may include a plurality of TFTs (T1 to T7) and a plurality of capacitors (Cq, q1).

[0083] The nth stage may be configured to include a node control unit (11) that controls the voltages of a first node (Q) and a second node (QB) according to a start signal (VST or Vgout(n-1)) and a first clock signal (CLK1), an output unit (13) that outputs a gate-on voltage (VGL) or a gate-off voltage (VGH) according to the voltages of the first and second nodes (Q and QB), and a stabilization unit (12) that stabilizes the first node (Q) by a clock signal (CLK2).

[0084] The node control unit (11) comprises: a first TFT (T1) in which a first electrode is connected to a start signal (VST) input terminal or an output terminal of a previous stage (Vgout(n-1)), a gate electrode is connected to a first clock signal (CLK1) supply line, and a second electrode is connected to an N node (N) to be turned on / off according to the first clock signal (CLK1) to apply a start signal (VST) or an output signal of a previous stage (Vgout(n-1)) to the N node (N); and a second TFT (T2) in which a first electrode is connected to the N node (N), a gate electrode is connected to a gate-on voltage (VGL) supply line, and a second electrode is connected to a first node (Q) to be turned on / off according to the gate-on voltage (VGL) to connect the N node (N) and the first node (Q). It may be configured to include a third TFT (T3) in which a first electrode is connected to a gate-on voltage (VGL) supply line, a gate electrode is connected to a first node (Q), and a second electrode is connected to a second node (QB) and is turned on / off according to the voltage of the first node (Q) to supply a gate-on voltage (VGL) to the second node (QB); and a fourth TFT (T4) in which a first electrode is connected to the second node (QB), a gate electrode is connected to the first node (Q), and a second electrode is connected to a gate-off voltage (VGH) supply line and is turned on / off according to the voltage of the first node (Q) to supply a gate-off voltage (VGH) to the second node (QB).

[0085] The output section (13) is configured to have: a pull-up TFT (T6) in which a first electrode is connected to a gate-on voltage (VGL) supply line, a gate electrode is connected to a first node (Q), and a second electrode is connected to an output terminal (OUT) so that the gate-on voltage (VGL) is turned on / off according to the voltage of the first node (Q) and outputs the gate-on voltage (VGL) to the output terminal (OUT); a pull-down TFT (T7) in which a first electrode is connected to a gate-off voltage (VGH) supply line, a gate electrode is connected to a second node (QB), and a second electrode is connected to an output terminal (OUT) so that the gate-off voltage (VGH) is turned on / off according to the voltage of the second node (QB) and outputs the gate-off voltage (VGH) to the output terminal (OUT); and a first capacitor (Cq) connected between the gate electrode and the second electrode of the pull-up TFT (T6) to bootstrap the first node (Q).

[0086] The stabilization unit (12) may be configured to include a fifth TFT (T5) in which a first electrode is connected to a second clock signal (CLK2) supply line, a gate electrode is connected to a first node (Q), and a second electrode is connected to a first node (Q); and a second capacitor (q1) connected between the second electrode of the fifth TFT (T5) and the first node (Q).

[0087] Here, the first TFT (T1), the second TFT (T2), the fourth TFT (T4), the fifth TFT (T5), the pull-up TFT (T6), and the pull-down TFT (T7) are p-type TFTs (PMOS), and the third TFT (T3) is an n-type TFT (NMOS). That is, the first TFT (T1), the second TFT (T2), the fourth TFT (T4), the fifth TFT (T5), the pull-up TFT (T6), and the pull-down TFT (T7) are LTPS TFTs, and the third TFT (T3) is an oxide semiconductor TFT.

[0088] Also, the first to fourth TFTs (T1, T2, T3, T4) may be configured as dual TFTs, as indicated by the circle in FIG. 10. Additionally, the second clock signal (CLK2) is a clock signal input to the gate of the first TFT (T1) of the next stage (n+1).

[0089] The operation of the nth stage of the gate driving circuit according to the first embodiment of the present invention configured as described above is as follows.

[0090] In FIG. 7, the high level of the start signal (VST), each clock signal (CLK1, CLK2) and each stage output signal (Vgout(n-1), Vgout(n), Vgout(n+1)) corresponds to the gate off voltage (VGH), and the low level of the start signal (VST), each clock signal (CLK1, CLK2) and each stage output signal (Vgout(n-1), Vgout(n), Vgout(n+1)) corresponds to the gate on voltage (VGL).

[0091] The start signal (VST) and output signals (Vgout(n-1), Vgout(n), Vgout(n+1)) maintain a high level for 4 hours.

[0092] One period of each clock signal (CLK1, CLK2) has a duration of 4H, the low level of each clock signal (CLK1, CLK2) maintains a duration of 2H-1U, and the high level of each clock signal (CLK1, CLK2) maintains a duration of 2H+1U. The second clock signal (CLK2) is shifted by about 1U compared to the first clock signal (CLK1).

[0093] As illustrated in FIG. 7, when the start signal (VST) or the output signal of the previous stage (Vgout(n-1)) is input at a high level, and the first clock signal (CLK1) is applied at a gate-on voltage (low level) (t1), the first node (Q) is charged to a gate-off voltage (high level) through the first and second TFTs (T1, T2).

[0094] When the first node (Q) is charged to a gate-off voltage (High Level), the third TFT (T3) is turned on, so the second node (QB) is charged to a gate-on voltage (Low Level; VGL).

[0095] Accordingly, the pull-up TFT (T6) is turned off and the pull-down TFT (T7) is turned on, and the gate-off voltage (High Level; VGH) is output as an output signal (Vgout(n)).

[0096] Then, after a period of 4H, when the start signal (VST) or the output signal of the previous stage (Vgout(n-1)) is input at a low level, and the first clock signal (CLK1) is applied again at a gate-on voltage (low level) (t2), the first node (Q) is charged to a gate-on voltage (low level) through the first and second TFTs (T1, T2).

[0097] When the first node (Q) is charged to the gate-on voltage (Low Level), the third TFT (T3) is turned off and the fourth TFT (T4) is turned on, so the second node (QB) is charged to the gate-off voltage (High Level; VGH).

[0098] Accordingly, the pull-up TFT (T6) is turned on and the pull-down TFT (T7) is turned off, and the gate-on voltage (Low Level; VGL)) is output as an output signal (Vgout(n)).

[0099] After the point in time (t2) when the first clock signal (CLK1) is applied again to the gate-on voltage (Low level), the voltage applied to the gate of the second TFT (T2) and the voltage applied to the first electrode (Source) become the same level. That is, the gate-source voltage (Vgs) of the second TFT (T2) becomes 0V.

[0100] Since the Vgs of the second TFT (T2) is 0V, the second TFT (T2) is turned off, and the first node (Q) is floated. The floating first node (Q) is bootstrapped by the capacitor (Cq) and maintains a voltage lower than the gate-on voltage (VGL).

[0101] In this process, since the gate-on voltage (VGL) is always applied to the gate of the second TFT (T2), leakage current may occur in the second TFT (T12) due to gate bias stress.

[0102] However, the first node (Q) is not affected by the leakage current of the second TFT (T2) by the stabilization unit (12).

[0103] That is, when the first node (Q) is charged to the gate-off voltage (High Level), the fifth TFT (T5) of the stabilization unit (12) is turned off, so the second clock signal (CLK2) does not affect the first node (Q).

[0104] Conversely, when the first node (Q) is charged to the gate-on voltage (Low Level), the fifth TFT (T5) of the stabilization unit (12) is turned on. Accordingly, the second clock signal (CLK2) pumps the first node (Q) through the second capacitor (q1).

[0105] In this way, even if a leakage current occurs in the second TFT (T2) due to gate bias stress, the voltage of the first node (Q) can be continuously maintained at the gate-on voltage by the stabilization unit (12). Furthermore, since the first node (Q) can be maintained at the gate-on voltage for a long time even during low-speed driving such as 1 Hz, the gate driving circuit can be operated stably even during low-speed driving.

[0106] 2nd embodiment

[0107] Before describing the gate driving circuit according to the second embodiment of the present invention, the GIP circuit of the second comparative example is described as follows.

[0108] FIG. 8 is a diagram showing the GIP circuit of the gate driving circuit of the second comparative example in detail, and FIG. 9 is a diagram showing the input and output waveforms of the circuit shown in FIG. 8.

[0109] The GIP circuit of the second comparative example shown in FIG. 8 is the nth (n is a positive integer) stage circuit. All transistors shown in FIG. 8 are composed of p-type TFTs (PMOS). Here, the p-type TFT is an LTPS TFT including low-temperature polysilicon (LTPS).

[0110] Referring to FIGS. 8 and 9, the nth stage of the second comparative example includes a plurality of TFTs (T11~T15, T6~T7) and three capacitors (CQ, CB, CN).

[0111] The nth stage of the second comparative example, as shown in FIG. 8, comprises a first TFT (T11) in which a first electrode is connected to the input terminal of a start signal (VST) or the output terminal of the previous stage (Vgout(n-1)), a gate electrode is connected to the supply line of a first clock signal (CLK1), and a second electrode is connected to the N1 node (N1) to be turned on / off according to the first clock signal (CLK1) to apply a start signal (VST) or an output signal of the previous stage (Vgout(n-1)) to the N1 node (N1); a second TFT (T12) in which a first electrode is connected to the N1 node (N1), a gate electrode is connected to the supply line of a gate-on voltage (VGL), and a second electrode is connected to the first node (Q) to be turned on / off according to the gate-on voltage (VGL) to connect the N1 node (N1) and the first node (Q); and a first electrode is connected to the supply line of a gate-off voltage (VGH), and a start A third TFT (T13) having a gate electrode connected to the input terminal of the signal (VST) or the output terminal of the previous stage (Vgout(n-1)) and a second electrode connected to the N2 node (N2), which is turned on / off according to the start signal (VST) or the output of the previous stage (Vgout(n-1)) to supply a gate off voltage (VGH) to the N2 node (N2); a fourth TFT (T14) having a first electrode connected to the input terminal of the start signal (VST) or the output terminal of the previous stage (Vgout(n-1)), a gate electrode connected to the N2 node (N2), and a second electrode connected to the second node (QB), which is turned on / off according to the voltage of the N2 node (N2) to supply the start signal (VST) or the output of the previous stage (Vgout(n-1)) to the second node (QB); and a first electrode connected to the gate off voltage (VGH) supply line, and to the N1 node (N1 A fifth TFT (T15) that has a gate connected and a second electrode connected to a second node (QB) and turns on / off according to the voltage of the N1 node (N1) to supply a gate off voltage (VGH) to the second node (QB), and a first electrode connected to a gate on voltage (VGL) supply line,A pull-up TFT (T17) having a gate electrode connected to a first node (Q) and a second electrode connected to an output terminal (OUT), which turns on / off according to the voltage of the first node (Q) to output a gate-on voltage (VGL) to the output terminal (OUT); a pull-down TFT (T18) having a first electrode connected to a gate-off voltage (VGH) supply line, a gate electrode connected to a second node (QB), and a second electrode connected to an output terminal (OUT), which turns on / off according to the voltage of the second node (QB) to output a gate-off voltage (VGH) to the output terminal (OUT); a first capacitor (Cq) connected between the gate electrode and the second electrode of the pull-up TFT (T17) to bootstrap the first node (Q); a second capacitor (CB) connected between the gate-off voltage (VGH) supply line and the second node (QB); and a connection between the first clock signal (CLK1) input terminal and the N2 node (N2). It is configured to include a third capacitor (CN).

[0112] Here, the first to fifth TFTs (T11, T12, T13, T14, T15), the pull-up TFT (T17), and the pull-down TFT (T18) are p-type TFTs (PMOS).

[0113] The operation of the nth stage of the comparative example configured in this way is explained as follows.

[0114] In FIG. 9, the high level of the start signal (VST), each clock signal (CLK1, CLK2), and each stage output signal (Vgout(n-1), Vgout(n), Vgout(n+1)) corresponds to the gate off voltage (VGH), and the low level of the start signal (VST), each clock signal (CLK1, CLK2), and each stage output signal (Vgout(n-1), Vgout(n), Vgout(n+1)) corresponds to the gate on voltage (VGL).

[0115] As illustrated in FIG. 9, when the start signal (VST) or the output signal of the previous stage (Vgout(n-1)) is input at a high level, and the first clock signal (CLK1) is applied at a gate-on voltage (low level) (t1), the first node (Q) is charged to a gate-off voltage (high level) through the first and second TFTs (T11, T12).

[0116] When the first node (Q) is charged to a gate-off voltage (High Level), the third TFT (T13) is turned off, and since the gate-on voltage (VGL) is charged to the third capacitor (CN) in the previous frame, the fourth TFT (14) is turned on and the second node (QB) is charged to the gate-on voltage (Low level; VGL) of the first clock signal (CLK1).

[0117] Accordingly, the pull-up TFT (T17) is turned off and the pull-down TFT (T18) is turned on, and the gate-off voltage (High Level; VGH) is output as an output signal (Vgout(n)).

[0118] Then, after a period of 4H, when the start signal (VST) or the output signal of the previous stage (Vgout(n-1)) is input at a low level, and the first clock signal (CLK1) is applied again at a gate-on voltage (low level) (t2), the first node (Q) is charged to a gate-on voltage (low level) through the first and second TFTs (T11, T12).

[0119] When the first node (Q) is charged to the gate-on voltage (Low Level), the third TFT (T13) and the fifth TFT (T15) are turned on, and the fourth TFT (T14) is turned off, so the second node (QB) is charged to the gate-off voltage (High Level; VGH).

[0120] Accordingly, the pull-up TFT (T17) is turned on and the pull-down TFT (T18) is turned off, and the gate-on voltage (Low Level; VGL)) is output as an output signal (Vgout(n)).

[0121] After the point in time (t2) when the first clock signal (CLK1) is applied again to the gate-on voltage (Low level), the voltage applied to the gate of the second TFT (T12) and the voltage applied to the first electrode (Source) become the same level. That is, the gate-source voltage (Vgs) of the second TFT (T12) becomes 0V.

[0122] Since the Vgs of the second TFT (T12) is 0V, the second TFT (T12) is turned off, and the first node (Q) is floated. The floating first node (Q) is bootstrapped by the capacitor (CQ) and maintains a voltage lower than the gate-on voltage (VGL).

[0123] However, since the gate-on voltage (VGL) is always applied to the gate of the second TFT (T12), leakage current occurs in the second TFT (T12) due to gate bias stress.

[0124] In this way, if leakage current occurs in the second TFT (T12), the voltage of the first node (Q) rises, and as a result, the gate driving circuit may malfunction. In particular, when driving at a low speed such as 1 Hz, the first node (Q) must maintain the gate-on voltage for a long time, so an output abnormality of the gate driving circuit occurs due to the leakage current of the second TFT (T12).

[0125] The gate driving circuit according to the second embodiment of the present invention is intended to solve the problems of the gate driving circuit of the second comparative example.

[0126] FIG. 10 is a diagram showing in detail a GIP circuit of a gate driving circuit according to a second embodiment of the present invention. The GIP circuit shown in FIG. 10 is an n-th (n is a positive integer) stage circuit. The transistors shown in FIG. 6 are exemplified as p-type TFTs (PMOS), but are not limited thereto. Here, the p-type TFT may be an LTPS TFT including low-temperature polysilicon (LTPS).

[0127] Figure 11 is a diagram showing the input and output waveforms of the circuit illustrated in Figure 10.

[0128] The output (Vgout) shown in FIGS. 10 and 11 may be a scan signal (SCAN) and a light emission control signal (EM).

[0129] Referring to FIGS. 10 and 11, the nth stage of the gate driving circuit (120) according to the second embodiment of the present invention may include a plurality of TFTs (T11 to T18) and a plurality of capacitors (CQ, CB, CN, q1).

[0130] The nth stage may be configured to include a node control unit (11) that controls the voltages of a first node (Q) and a second node (QB) according to a start signal (VST or Vgout(n-1)) and a first clock signal (CLK1), an output unit (13) that outputs a gate-on voltage (VGL) or a gate-off voltage (VGH) according to the voltages of the first and second nodes (Q and QB), and a stabilization unit (12) that stabilizes the first node (Q) according to a clock signal (CLK2).

[0131] The node control unit (11) comprises: a first TFT (T11) in which a first electrode is connected to a start signal (VST) input terminal or an output terminal of a previous stage (Vgout(n-1)), a gate electrode is connected to a first clock signal (CLK1) supply line, and a second electrode is connected to a node N1 (N1) to be turned on / off according to the first clock signal (CLK1) to apply a start signal (VST) or an output signal of a previous stage (Vgout(n-1)) to the node N1 (N1); a second TFT (T12) in which a first electrode is connected to the node N1 (N1), a gate electrode is connected to a gate-on voltage (VGL) supply line, and a second electrode is connected to a first node (Q) to be turned on / off according to the gate-on voltage (VGL) to connect the node N1 (N1) and the first node (Q); and a first electrode is connected to a gate-off voltage (VGH) supply line, and a start signal (VST) input terminal or A third TFT (T13) having a gate electrode connected to the output terminal (Vgout(n-1)) of the previous stage and a second electrode connected to the N2 node (N2), which is turned on / off according to a start signal (VST) or the output (Vgout(n-1)) of the previous stage to supply a gate off voltage (VGH) to the N2 node (N2); a fourth TFT (T14) having a first electrode connected to the first clock signal (CLK1) supply line, a gate electrode connected to the N2 node (N2), and a second electrode connected to the second node (QB), which is turned on / off according to the voltage of the N2 node (N2) to supply the first clock signal (CLK1) to the second node (QB); and a first electrode connected to the gate off voltage (VGH) supply line, a gate connected to the N1 node (N1), and a second electrode connected to the second node (QB), which is turned on / off according to the voltage of the N1 node (N1). A fifth TFT (T15) that is turned on / off to supply a gate off voltage (VGH) to a second node (QB), a second capacitor (CB) connected between the gate off voltage (VGH) supply line and the second node (QB), andIt can be configured by providing a third capacitor (CN) connected between the first clock signal (CLK1) input terminal and the N2 node (N2).

[0132] The output section (13) may be configured to include: a pull-up TFT (T17) in which a first electrode is connected to a gate-on voltage (VGL) supply line, a gate electrode is connected to a first node (Q), and a second electrode is connected to an output terminal (OUT) to turn on / off according to the voltage of the first node (Q) and output a gate-on voltage (VGL) to the output terminal (OUT); a pull-down TFT (T18) in which a first electrode is connected to a gate-off voltage (VGH) supply line, a gate electrode is connected to a second node (QB), and a second electrode is connected to an output terminal (OUT) to turn on / off according to the voltage of the second node (QB) and output a gate-off voltage (VGH) to the output terminal (OUT); and a first capacitor (CQ) connected between the gate electrode and the second electrode of the pull-up TFT (T17) to bootstrap the first node (Q).

[0133] The stabilization unit (12) may be configured to include a sixth TFT (T16) in which a first electrode is connected to a second clock signal (CLK2) supply line, a gate electrode is connected to a first node (Q), and a second electrode is connected to a first node (Q); and a fourth capacitor (q1) connected between the second electrode of the sixth TFT (T16) and the first node (Q).

[0134] Here, the first to sixth TFTs (T11, T12, T13, T14, T15, T16), pull-up TFT (T17), and pull-down TFT (T18) are all p-type TFTs (PMOS). That is, the first to sixth TFTs (T11, T12, T13, T14, T15, T16), pull-up TFT (T17), and pull-down TFT (T18) may be LTPS TFTs.

[0135] The first to fifth TFTs (T11, T12, T13, T14, T15) can be configured as dual TFTs, as indicated by the circle in FIG. 10. And, the second clock signal (CLK2) is a clock signal input to the gate of the first TFT (T11) of the next stage (n+1).

[0136] The operation of the nth stage of the gate driving circuit according to the second embodiment of the present invention configured as described above is as follows.

[0137] In FIG. 11, the high level of the start signal (VST), each clock signal (CLK1, CLK2) and each stage output signal (Vgout(n-1), Vgout(n), Vgout(n+1)) corresponds to the gate off voltage (VGH), and the low level of the start signal (VST), each clock signal (CLK1, CLK2) and each stage output signal (Vgout(n-1), Vgout(n), Vgout(n+1)) corresponds to the gate on voltage (VGL).

[0138] The start signal (VST) and output signals (Vgout(n-1), Vgout(n), Vgout(n+1)) maintain a high level for 4 hours.

[0139] One period of each clock signal (CLK1, CLK2) has a duration of 4H, the low level of each clock signal (CLK1, CLK2) maintains a duration of 2H-1U, and the high level of each clock signal (CLK1, CLK2) maintains a duration of 2H+1U. The second clock signal (CLK2) is shifted by about 1U compared to the first clock signal (CLK1).

[0140] As illustrated in FIG. 11, when the start signal (VST) or the output signal of the previous stage (Vgout(n-1)) is input at a high level, and the first clock signal (CLK1) is applied at a gate-on voltage (low level) (t1), the first node (Q) is charged to a gate-off voltage (high level) through the first and second TFTs (T11, T12).

[0141] When the first node (Q) is charged to the gate-off voltage (High Level), the third TFT (T13) is turned off, but since the third capacitor (CN) is charging the gate-on voltage (VGL) in the previous frame, the fourth TFT (T14) is turned on, and the second node (QB) is charged to the low level (Low Level; VGL) voltage of the first clock signal.

[0142] Accordingly, the pull-up TFT (T17) is turned off and the pull-down TFT (T18) is turned on, and the gate-off voltage (High Level; VGH) is output as an output signal (Vgout(n)).

[0143] Then, after a period of 4H, when the start signal (VST) or the output signal of the previous stage (Vgout(n-1)) is input at a low level, and the first clock signal (CLK1) is applied again at a gate-on voltage (low level) (t2), the first node (Q) is charged to a gate-on voltage (low level) through the first and second TFTs (T11, T12).

[0144] When the first node (Q) is charged to the gate-on voltage (Low Level), the third TFT (T13) and the fifth TFT (T15) are turned on, and the fourth TFT (T14) is turned off, so the second node (QB) is charged to the gate-off voltage (High Level; VGH).

[0145] Accordingly, the pull-up TFT (T17) is turned on and the pull-down TFT (T18) is turned off, and the gate-on voltage (Low Level; VGL)) is output as an output signal (Vgout(n)).

[0146] After the point in time (t2) when the first clock signal (CLK1) is applied again to the gate-on voltage (Low level), the voltage applied to the gate of the second TFT (T12) and the voltage applied to the first electrode (Source) become the same level. That is, the gate-source voltage (Vgs) of the second TFT (T12) becomes 0V.

[0147] Since the Vgs of the second TFT (T12) is 0V, the second TFT (T12) is turned off, and the first node (Q) is floated. The floating first node (Q) is bootstrapped by the capacitor (CQ) and maintains a voltage lower than the gate-on voltage (VGL).

[0148] In this process, since the gate-on voltage (VGL) is always applied to the gate of the second TFT (T12), leakage current may occur in the second TFT (T12) due to gate bias stress.

[0149] However, the first node (Q) is not affected by the leakage current of the second TFT (T12) by the stabilization unit (12).

[0150] That is, when the first node (Q) is charged to the gate-off voltage (High Level), the 6th TFT (T16) of the stabilization unit (12) is turned off, so the second clock signal (CLK2) does not affect the first node (Q).

[0151] Conversely, when the first node (Q) is charged to the gate-on voltage (Low Level), the sixth TFT (T16) of the stabilization unit (12) is turned on. Accordingly, the second clock signal (CLK2) pumps the first node (Q) through the fourth capacitor (q1).

[0152] In this way, even if leakage current occurs in the second TFT (T12) due to gate bias stress, the voltage of the first node (Q) can be continuously maintained at the gate-on voltage by the stabilization unit (12). Furthermore, since the first node (Q) can be maintained at the gate-on voltage for a long time even during low-speed driving such as 1 Hz, the gate driving circuit can be operated stably even during low-speed driving.

[0153] From the above description, those skilled in the art will understand that various changes and modifications are possible within the scope of the technical concept of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0154] 11: Node control unit 12: Stabilization unit 13: Output section 100: Display panel 110: Data driving circuit 120: Gate driving circuit 130: Timing Controller 140: Level Shifter

Claims

Claim 1 A plurality of dependently connected stages, wherein the n-th stage (n is a natural number) comprises: a first TFT that is turned on / off according to a first clock signal to apply a start signal or an output signal of a previous stage to the N node; a second TFT that is turned on according to a gate-on voltage to connect the N node and the first node; a third TFT that is turned on / off according to the voltage of the first node to supply the gate-on voltage to the second node; a fourth TFT that is turned on / off according to the voltage of the first node to supply a gate-off voltage to the second node; an output unit that outputs a gate-on voltage or a gate-off voltage according to the voltages of the first and second nodes; and a fifth TFT in which a first electrode is connected to a second clock signal supply line that supplies a second clock signal and a gate electrode is connected to the first node. A gate driving circuit comprising a second capacitor connected between the second electrode of the fifth TFT and the first node, wherein even if leakage current occurs in the second TFT due to gate bias stress, the fifth TFT and the second capacitor continuously maintain the voltage of the first node as the gate-on voltage. Claim 2 delete Claim 3 In claim 1, the output portion comprises: a pull-up TFT that is turned on / off according to the voltage of the first node to output the gate-on voltage; a pull-down TFT that is turned on / off according to the voltage of the second node to output the gate-off voltage; and a gate driving circuit having a first capacitor connected between the gate electrode of the pull-up TFT and the second electrode to bootstrap the first node. Claim 4 delete Claim 5 A gate driving circuit according to claim 1, characterized in that the second clock signal is the same signal as the first clock signal applied to the node control unit of the next stage (n+1). Claim 6 In claim 3, the gate driving circuit wherein the first TFT, the second TFT, the fourth TFT, the fifth TFT, the pull-up TFT, and the pull-down TFT are low-temperature polysilicon TFTs, and the third TFT is an oxide semiconductor TFT. Claim 7 A plurality of dependently connected stages are provided, and the n-th stage (n is a natural number) comprises: a first TFT that is turned on / off according to a first clock signal to apply a start signal or an output signal of a previous stage to a node N1; a second TFT that is turned on / off according to a gate-on voltage to connect the node N1 and the first node; a third TFT that is turned on / off according to the start signal or the output signal of a previous stage to supply a gate-off voltage to a node N2; a fourth TFT that is turned on / off according to the voltage of the node N2 to supply the first clock signal to the second node; a fifth TFT that is turned on / off according to the voltage of the node N1 to supply the gate-off voltage to the second node; an output unit that outputs the gate-on voltage or the gate-off voltage according to the voltages of the first and second nodes; and a sixth TFT in which a first electrode is connected to a second clock signal supply line that supplies a second clock signal and a gate electrode is connected to the first node. A gate driving circuit having a fourth capacitor connected between the second electrode of the sixth TFT and the first node. Claim 8 A gate driving circuit according to claim 7, further comprising a second capacitor connected between a gate off voltage supply line supplying the gate off voltage and the second node, and a third capacitor connected between the first clock signal input terminal and the N2 node. Claim 9 delete Claim 10 A gate driving circuit according to claim 7, characterized in that the second clock signal is the same signal as the first clock signal applied to the node control unit of the next stage. Claim 11 A gate driving circuit according to claim 7, characterized in that the first to sixth TFTs are low-temperature polysilicon TFTs. Claim 12 A gate driving circuit according to claim 1 or 7, wherein the start signal maintains a high level for 4H, one cycle of the first and second clock signals has a period of 4H, the low level of the first and second clock signals maintains a period of 2H-1u, the high level of the first and second clock signals maintains a period of 2H+1u, and the second clock signal is shifted by about 1u compared to the first clock signal. Claim 13 delete Claim 14 delete Claim 15 delete

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