Light Emitting Display Device and Manufacturing Method Thereof

Abstract

The present invention provides a light-emitting display device comprising a display panel including a display area and a non-display area, a first reference line arranged in a first direction within the display area, a second reference line arranged in a second direction intersecting the first direction within the display area and electrically connected to the first reference line, and a second power line arranged in the first direction within the display area and arranged between at least two first reference lines.

Description

Technology Field

[0001] The present invention relates to a light-emitting display device and a method for manufacturing the same. Background Technology

[0002] As information technology advances, the market for display devices, which serve as a medium connecting users and information, is growing. Consequently, the use of display devices such as Light Emitting Display Devices (LEDs), Quantum Dot Display Devices (QDDs), and Liquid Crystal Display Devices (LCDs) is increasing.

[0003] The display devices described above include a display panel containing subpixels, a driving unit that outputs a driving signal for driving the display panel, and a power supply unit that generates power to be supplied to the display panel or the driving unit.

[0004] When driving signals, such as scan signals and data signals, are supplied to subpixels formed on a display panel, the selected subpixel transmits light or emits light directly, thereby displaying an image. The problem to be solved

[0005] The present invention resolves the problems of reduced pattern density and increased line spacing when implementing a large display panel and a narrow bezel, based on a mesh-type reference line embedded within a display area and a second power line placed between them, and minimizes the problem of second power voltage increase (EVSS Rising), thereby expressing a uniform image without differences in brightness and color coordinates depending on the position. means of solving the problem

[0006] The present invention provides a light-emitting display device comprising a display panel including a display area and a non-display area, a first reference line arranged in a first direction within the display area, a second reference line arranged in a second direction intersecting the first direction within the display area and electrically connected to the first reference line, and a second power line arranged in the first direction within the display area and arranged between at least two first reference lines.

[0007] At least one of the first reference line and the second reference line may be located on a different layer from the second power line.

[0008] The second reference line may be located on a different layer from the first reference line and the second power line.

[0009] The first reference line and the second power line can be selected as source-drain metal layers constituting a transistor included in a subpixel of the display panel.

[0010] The above second reference line may be selected as a semiconductor layer constituting a transistor included in a subpixel of the display panel.

[0011] The first reference line and the second power line may be located between the interlayer insulation layer and the planarization layer located in a layer higher than the second reference line.

[0012] The above second reference line may be located between the buffer layer and the gate insulation layer, which are located in a lower layer than the above first reference line and the above second power line.

[0013] In another aspect, the present invention provides a light-emitting display device comprising: a buffer layer located on a substrate; a lower reference line comprising a semiconductor layer located on the buffer layer and arranged horizontally within a display area defined on the substrate; at least one insulating layer located on the lower reference line; an upper reference line located on the insulating layer and arranged vertically within a display area defined on the substrate and electrically connected to the lower reference line; and a second power line located on the insulating layer and arranged vertically within a display area defined on the substrate.

[0014] The upper reference line and the second power line are located on the insulating layer but spaced apart from each other and may be composed of a source drain metal layer.

[0015] In another aspect, the present invention provides a method for manufacturing a light-emitting display device comprising the steps of: forming a buffer layer on a substrate; forming a lower reference line with a semiconductor layer positioned on the buffer layer and arranged horizontally within a display area defined on the substrate; forming at least one insulating layer on the lower reference line; patterning a first source-drain metal layer positioned on the insulating layer and arranged vertically within a display area defined on the substrate to form an upper reference line electrically connected to the lower reference line; and patterning a second source-drain metal layer positioned on the insulating layer and arranged vertically within a display area defined on the substrate to form a second power line spaced apart from the upper reference line. Effects of the invention

[0016] The present invention has the effect of providing a smooth and easy repair method in the event of a disconnection or short circuit in some lines based on a mesh-type reference line. Furthermore, the present invention can embed a second power line within the display area of ​​the display panel, thereby minimizing the problem of the second power voltage rising (EVSS Rising) when the display panel is enlarged or a narrow bezel is implemented. Additionally, even if the second power line is embeddled within the display area of ​​the display panel, the present invention can reduce pattern density and resolve the problem of increased line (wiring) spacing. Moreover, since the present invention can resolve the problems of reduced pattern density and increased line spacing, it has the effect of minimizing performance degradation issues of the display panel, such as crosstalk caused by an increase in parasitic capacitors. Furthermore, since the present invention can minimize performance degradation issues of the display panel, it has the effect of expressing a uniform image without differences in brightness and color coordinates depending on the location. In addition, the present invention can minimize the problems of reduced pattern density and increased line spacing, thereby effectively resolving the issue of reduced production yield caused by short circuits between lines and short circuits caused by foreign substances. Brief explanation of the drawing

[0017] FIG. 1 is a block diagram schematically showing a light-emitting display device, and FIG. 2 is a configuration diagram schematically showing a subpixel shown in FIG. 1. FIG. 3 is a diagram showing an example of the arrangement of a gate-in-panel type scan drive unit, and FIG. 4 and FIG. 5 are example diagrams of the configuration of a device related to a gate-in-panel type scan drive unit. FIG. 6 is an example diagram showing the shape of a display panel, and FIG. 7 is an example diagram showing the circuit configuration of a subpixel. FIG. 8 is a plan view showing a reference line and a second power line connected to three subpixels according to a first embodiment of the present invention, FIG. 9 is a plan view for comparing and explaining the arrangement structure of the first embodiment with that of an experimental example, and FIG. 10 is a plan view showing various signal lines and a second power line connected to a plurality of subpixels according to a first embodiment of the present invention. FIG. 11 is a plan view showing a reference line and a second power line connected to three subpixels according to a second embodiment of the present invention, FIG. 12 is a plan view showing various signal lines and a second power line connected to a plurality of subpixels according to a second embodiment of the present invention, FIG. 13 is a cross-sectional view showing the A1-A2 region of FIG. 12, FIG. 14 is a cross-sectional view showing the B1-B2 region of FIG. 12, and FIG. 15 is a cross-sectional view showing the C1-C2 region of FIG. 12. FIGS. 16 and 17 are drawings for explaining the line arrangement structure according to an embodiment of the present invention and the advantages thereof, and FIGS. 18 and 19 are drawings for explaining the line arrangement structure according to an experimental example and the disadvantages thereof. Specific details for implementing the invention

[0018] The display device according to the present invention may be implemented in a television, video player, personal computer (PC), home theater, automotive electrical system, smartphone, etc., but is not limited thereto. The display device according to the present invention may be implemented in a light-emitting display device (LED), a quantum dot display device (QDD), a liquid crystal display device (LCD), etc. However, for convenience of explanation, a light-emitting display device that directly emits light based on an inorganic light-emitting diode or an organic light-emitting diode is used as an example below.

[0019] FIG. 1 is a block diagram schematically showing a light-emitting display device, and FIG. 2 is a configuration diagram schematically showing a subpixel shown in FIG. 1.

[0020] As illustrated in FIGS. 1 and 2, the light-emitting display device may include an image supply unit (110), a timing control unit (120), a scan driving unit (130), a data driving unit (140), a display panel (150), and a power supply unit (180), etc.

[0021] The video supply unit (110) (set or host system) can output various driving signals along with data signals supplied from the outside or data signals stored in internal memory. The video supply unit (110) can supply data signals and various driving signals to the timing control unit (120).

[0022] The timing control unit (120) can output a gate timing control signal (GDC) for controlling the operation timing of the scan drive unit (130), a data timing control signal (DDC) for controlling the operation timing of the data drive unit (140), and various synchronization signals (Vsync, a vertical synchronization signal, Hsync, a horizontal synchronization signal). The timing control unit (120) can supply a data signal (DATA) supplied from the image supply unit (110) to the data drive unit (140) along with the data timing control signal (DDC). The timing control unit (120) may be formed in the form of an IC (Integrated Circuit) and mounted on a printed circuit board, but is not limited thereto.

[0023] The scan driver (130) can output a scan signal (or scan voltage) in response to a gate timing control signal (GDC) supplied from the timing control unit (120). The scan driver (130) can supply a scan signal to subpixels included in the display panel (150) through gate lines (GL1~GLm). The scan driver (130) may be formed in the form of an IC or formed directly on the display panel (150) in a Gate In Panel manner, but is not limited thereto.

[0024] The data driver (140) can sample and latch a data signal (DATA) in response to a data timing control signal (DDC) supplied from the timing control unit (120), and convert the digital data signal into an analog data voltage based on a gamma reference voltage and output it. The data driver (140) can supply the data voltage to subpixels included in the display panel (150) through data lines (DL1~DLn). The data driver (140) may be formed in the form of an IC and mounted on the display panel (150) or mounted on a printed circuit board, but is not limited thereto.

[0025] The power supply unit (180) can generate a first power supply of high potential and a second power supply of low potential based on an external input voltage supplied from the outside, and output them through the first power line (EVDD) and the second power line (EVSS). The power supply unit (180) can generate not only the first power supply and the second power supply, but also a voltage required for driving the scan drive unit (130) (e.g., a gate voltage including a gate high voltage and a gate low voltage) or a voltage required for driving the data drive unit (140) (a drain voltage including a drain voltage and a half-drain voltage).

[0026] The display panel (150) can display an image in response to a driving signal including a scan signal and a data voltage, a first power source, a second power source, etc. The subpixels of the display panel (150) emit light directly. The display panel (150) can be manufactured based on a substrate having rigidity or flexibility, such as glass, silicon, or polyimide. The light-emitting subpixels may consist of pixels including red, green, and blue, or pixels including red, green, blue, and white.

[0027] For example, a single subpixel (SP) may be connected to a first data line (DL1), a first gate line (GL1), a first power line (EVDD), and a second power line (EVSS), and may include a pixel circuit composed of a switching transistor, a driving transistor, a capacitor, an organic light-emitting diode, etc. Since the subpixel (SP) used in the light-emitting display device directly emits light, the circuit configuration is complex. In addition, there are various compensation circuits to compensate for the degradation of the organic light-emitting diode that emits light, as well as the driving transistor that supplies driving current to the organic light-emitting diode. Therefore, it is noted that the subpixel (SP) is simply illustrated in the form of a block.

[0028] Meanwhile, in the above description, the timing control unit (120), scan driving unit (130), and data driving unit (140) were described as being separate components. However, depending on the implementation method of the light-emitting display device, one or more of the timing control unit (120), scan driving unit (130), and data driving unit (140) may be integrated into a single IC.

[0029] FIG. 3 is a diagram showing an example of the arrangement of a gate-in-panel type scan drive unit, and FIG. 4 and FIG. 5 are example diagrams of the configuration of a device related to a gate-in-panel type scan drive unit.

[0030] As illustrated in FIG. 3, the gate-in-panel type scan drive unit (130a, 130b) is positioned in the non-display area (NA) of the display panel (150). The scan drive unit (130a, 130b) may be positioned in the left and right non-display areas (NA) of the display panel (150) as in FIG. 3(a). Additionally, the scan drive unit (130a, 130b) may be positioned in the upper and lower non-display areas (NA) of the display panel (150) as in FIG. 3(b).

[0031] Although the scan drive unit (130a, 130b) has been illustrated and described as being placed in a non-display area (NA) located on the left, right, or upper / lower side of the display area (AA), only one may be placed on the left, right, upper, or lower side.

[0032] As illustrated in FIG. 4, the gate-in-panel type scan driver (130) may include a shift register (131) and a level shifter (135). The level shifter (135) can generate clock signals (Clks) and start signals (Vst), etc., based on signals and voltages output from the timing control unit (120) and the power supply unit (180). The clock signals (Clks) can be generated in the form of K (where K is an integer greater than or equal to 2) with different phases, such as 2-phase, 4-phase, or 8-phase.

[0033] The shift register (131) operates based on signals (Clks, Vst), etc., output from the level shifter (135) and can output scan signals (Scan[1] ~ Scan[m]) that can turn on or turn off the transistor formed on the display panel. The shift register (131) can be formed in the form of a thin film on the display panel by a gate-in-panel method. Accordingly, 130a and 130b formed on the non-display area (NA) of the display panel (150) shown in FIG. 3 may correspond to the shift register (131).

[0034] As illustrated in FIGS. 4 and 5, the level shifter (135), unlike the shift register (131), may be formed independently in the form of an IC or included inside the power supply (180). However, this is only one example and is not limited thereto.

[0035] FIG. 6 is an example diagram showing the shape of a display panel, and FIG. 7 is an example diagram showing the circuit configuration of a subpixel.

[0036] As shown in FIG. 6, the display panel (150) can be implemented in various shapes such as a rectangle (or square) (a), a circle (b), an ellipse (c), and a hexagon (d). In the case of display panels (150) such as FIG. 6(b) to (d), excluding the generally widely used rectangular display panel (150) as in FIG. 6(a), they are also called irregular display panels because they have a shape different from the conventional ones (a shape different from the usual ones).

[0037] As shown in FIG. 7, the subpixel may include five switching transistors (T1 to T5), one driving transistor (DT), one storage capacitor (Cst), and one light-emitting diode (OLED). Cgv may be a compensation capacitor provided for compensation, and this may be omitted.

[0038] The first switching transistor (T1) can serve to transmit the data voltage applied through the first data line (DL1) to the first electrode of the storage capacitor (Cst) in response to the first scan signal applied through the first scan line (SCAN1).

[0039] The second switching transistor (T2) can electrically connect the gate electrode of the driving transistor (DT) and the second electrode in response to the second scan signal applied through the second scan line (SCAN2) (it can also make the DT a diode connection state for threshold voltage compensation).

[0040] The third switching transistor (T3) can serve to transmit a reference voltage (initialization voltage or compensation voltage, etc.) applied through the reference line (VREF) to the first electrode of the storage capacitor (Cst) in response to a light emission control signal (or third scan signal) applied through the light emission control line (or third scan line) (EM).

[0041] The fourth switching transistor (T4) can serve to transmit the driving current generated from the driving transistor (DT) to the anode electrode of the light-emitting diode (OLED) in response to the light-emitting control signal applied through the light-emitting control line (EM).

[0042] The storage capacitor (Cst) can store data voltage and drive the driving transistor (DT) based on the stored data voltage. The light-emitting diode (OLED) can emit light based on the driving current generated from the driving transistor (DT).

[0043] The subpixel illustrated in Fig. 7 has various advantages, such as being able to compensate the threshold voltage of the driving transistor (DT) based on the second and third switching transistors (T2, T3), and to control the light emission time of the light-emitting diode (OLED) based on the fourth switching transistor (T4).

[0044] Meanwhile, FIG. 7 illustrates an example in which all thin-film transistors included in the subpixel are of the P-type. However, the thin-film transistors included in the subpixel may all be of the N-type or may be implemented in a structure in which P-type and N-type are mixed. Additionally, FIG. 7 is illustrated and described merely to aid in understanding the planar and cross-sectional structures of various signal lines and power lines connected to the subpixel in conjunction with the following embodiments, and the present invention is not limited thereto.

[0045] FIG. 8 is a plan view showing a reference line and a second power line connected to three subpixels according to a first embodiment of the present invention, FIG. 9 is a plan view for comparing and explaining the arrangement structure of the first embodiment with that of an experimental example, and FIG. 10 is a plan view showing various signal lines and a second power line connected to a plurality of subpixels according to a first embodiment of the present invention.

[0046] As illustrated in FIG. 8, according to the first embodiment, a pixel (PIX) may be positioned within the display area (AA) of the display panel (150) in the order of a red subpixel (SPR), a green subpixel (SPG), and a blue subpixel (SPB). The order of the subpixels positioned within the pixel (PIX) is merely one example and is not limited thereto.

[0047] Additionally, within the display area (AA) of the display panel (150), a first reference line (VREF1) arranged in a first direction (vertical), a second reference line (VREF2) arranged in a second direction (horizontal), and a second power line (EVSS) arranged in the first direction may be located. The first reference line (VREF1) and the second reference line (VREF2) may be located in a mesh form.

[0048] According to the first example, the first reference line (VREF1) and the second reference line (VREF2) may be located on a different floor from the second power line (EVSS). The first reference line (VREF1) and the second reference line (VREF2) may be located on the same floor so as to be electrically connected to each other.

[0049] According to the second example, the second reference line (VREF2) may be located on a different layer from the first reference line (VREF1) and the second power line (EVSS). The second reference line (VREF2) may be electrically connected to the first reference line (VREF1), which may be an area where the two intersect.

[0050] As can be seen by comparing the experimental example of FIG. 9(a) with the first embodiment of FIG. 9(b), the present invention changes the line arrangement structure compared to the experimental example by further arranging a second reference line (VREF2) across the second direction and replacing one of the reference lines (VREF) arranged in the first direction with a second power line (EVSS).

[0051] As illustrated in FIG. 10, according to the first embodiment, the second power line (EVSS) can be positioned between each of the two first reference lines (VREF1). This can be seen by observing the left-right symmetrical arrangement of the two first reference lines (VREF1) and one second power line (EVSS) based on a virtual vertical line separating the subpixels of the first group (SP_G1) and the subpixels of the second group (SP_G2).

[0052] FIG. 10 illustrates the arrangement relationship of various signal lines (VREF1, VREF2, SCAN1, SCAN2, EM) connected to multiple subpixels and a second power line (EVSS) based on the subpixels illustrated and described in FIG. 7. According to this, two second scan lines (SCAN2), two light emission control lines (EM), and one first scan line (SCAN1) may be located between two second reference lines (VREF2). Additionally, each subpixel (SP) may be electrically connected to these signal lines (VREF1, VREF2, SCAN1, SCAN2, EM) as well as to a second power line (EVSS) arranged adjacent to them.

[0053] As described above, changing the line arrangement structure as in the first embodiment compared to the experimental example can provide various advantages, which will be discussed after explaining the second embodiment.

[0054] FIG. 11 is a plan view showing a reference line and a second power line connected to three subpixels according to a second embodiment of the present invention, FIG. 12 is a plan view showing various signal lines and a second power line connected to a plurality of subpixels according to a second embodiment of the present invention, FIG. 13 is a cross-sectional view showing the A1-A2 region of FIG. 12, FIG. 14 is a cross-sectional view showing the B1-B2 region of FIG. 12, and FIG. 15 is a cross-sectional view showing the C1-C2 region of FIG. 12.

[0055] As illustrated in FIG. 11, according to the second embodiment, a pixel (PIX) may be positioned within the display area (AA) of the display panel (150) in the order of a red subpixel (SPR), a green subpixel (SPG), and a blue subpixel (SPB). The order of the subpixels positioned within the pixel (PIX) is merely one example and is not limited thereto.

[0056] Additionally, within the display area (AA) of the display panel (150), a first reference line (VREF1) arranged in a first direction (vertical), a second reference line (VREF2) arranged in a second direction (horizontal), and a second power line (EVSS) arranged in the first direction may be located. The first reference line (VREF1) and the second reference line (VREF2) may be located in a mesh form.

[0057] The second reference line (VREF2) may be located on a lower floor (sub-floor) than the first reference line (VREF1) and the second power line (EVSS). The second reference line (VREF2) may be electrically connected to the first reference line (VREF1) through a contact hole (CH).

[0058] The first reference line (VREF1) and the second power line (EVSS) may be located on the same layer and may be formed by a source-drain metal layer that forms the source electrode and drain electrode of a transistor included in a subpixel (SP). The second reference line (VREF2) may be formed by a semiconductor layer that forms the active region of a transistor included in a subpixel (SP). Hereinafter, the explanation related thereto will be discussed in more detail with reference to FIGS. 12 to 15.

[0059] As illustrated in FIGS. 12 and 13, the first buffer layer (BUF1) may be located on a substrate (or film) (PI). The first buffer layer (BUF1) may be formed in multiple layers. The second buffer layer (BUF2) may be located on the first buffer layer (BUF1).

[0060] The semiconductor layer (ACT) may be located on the second buffer layer (BUF2). The semiconductor layer (ACT) may be a part constituting the second reference line (VREF2). Since the semiconductor layer (ACT) constituting the second reference line (VREF2) is located in a lower layer than the first reference line (VREF1), it may be named the lower reference line. The gate insulating layer (GI) may be located on the semiconductor layer (ACT). The first interlayer insulating layer (ILD1) may be located on the gate insulating layer (GI). The second interlayer insulating layer (ILD2) may be located on the first interlayer insulating layer (ILD1).

[0061] The first source drain metal layer (SD1) and the second source drain metal layer (SD2) may be located on the second interlayer insulating layer (ILD2). The first source drain metal layer (SD1) and the second source drain metal layer (SD2) may be located spaced apart from each other. The first source drain metal layer (SD1) may be a part constituting the first reference line (VREF1), and the second source drain metal layer (SD2) may be a part constituting the data line of an adjacent subpixel. Since the first source drain metal layer (SD1) constituting the first reference line (VREF1) is located in a layer higher than the second reference line (VREF2), it may be named the upper reference line.

[0062] The flattening layer (PLN) may be located on the second interlayer insulating layer (ILD2). The flattening layer (PLN) may be selected from a material capable of flattening the surface while covering the first source drain metal layer (SD1) and the second source drain metal layer (SD2).

[0063] The anode electrode layer (ANO) may be located on the planarization layer (PLN). The anode electrode layer (ANO) may be selected as the anode electrode of the organic light-emitting diode. The bank layer (BNK) may be located on the anode electrode layer (ANO). The bank layer (BNK) may serve to partition subpixels. The cathode electrode layer (CAT) may be located on the bank layer (BNK). The cathode electrode layer (CAT) may be selected as the cathode electrode of the organic light-emitting diode.

[0064] A protective layer (ALD) may be located on the cathode electrode layer (CAT). The protective layer (ALD) may be formed in the form of a dense medium by a deposition method capable of forming layers at the atomic level. Other layers, such as an organic-inorganic composite layer, may also be located on the protective layer (ALD).

[0065] As shown in FIGS. 12 to 14, a third source drain metal layer (SD3), a fourth source drain metal layer (SD4), and a fifth source drain metal layer (SD5) may be located on the second interlayer insulating layer (ILD2).

[0066] The third source drain metal layer (SD3) may be a part constituting the second power line (EVSS), and the fourth source drain metal layer (SD4) and the fifth source drain metal layer (SD5) may be parts constituting the data line of an adjacent subpixel.

[0067] As illustrated in FIGS. 12 to 15, a light-blocking layer (BSM) may be positioned on the first buffer layer (BUF1). The light-blocking layer (BSM) may serve to block the incidence of external light on the semiconductor layer (ACT) of the transistor (particularly the semiconductor layer of the driving transistor). The light-blocking layer (BSM) may be selected as a metal layer capable of reducing light absorption or transmission. The second buffer layer (BUF2) may be selected as a material capable of flattening the surface of the first buffer layer (BUF1) on which the light-blocking layer (BSM) is formed.

[0068] A semiconductor layer (ACT) constituting the active layer of a transistor may be located on the second buffer layer (BUF2). A first gate metal layer (GAT1), a second gate metal layer (GAT2), and a third gate metal layer (GAT3) may be located on the gate insulation layer (GI). The first gate metal layer (GAT1) may be a part constituting the second scan line (SCAN2). The second gate metal layer (GAT2) may be a part constituting the lower electrode (Cst_L) of a storage capacitor. The third gate metal layer (GAT3) may be a part constituting the gate electrode of a transistor.

[0069] A metal layer (TM) may be located on the first interlayer insulating layer (ILD1). The metal layer (TM) may be a part constituting the upper electrode (Cst_U) of the storage capacitor (Cst). The metal layer (TM) may be located corresponding to the second gate metal layer (GAT2) to form the storage capacitor (Cst).

[0070] A sixth source drain metal layer (SD6) and a seventh source drain metal layer (SD7) may be located on the second interlayer insulating layer (ILD2). The sixth source drain metal layer (SD6) may be a bridge portion that electrically connects a semiconductor layer (ACT) spaced apart on the second buffer layer (BUF2). The seventh source drain metal layer (SD7) may be a portion that constitutes a data line of an adjacent subpixel.

[0071] A first light-emitting layer (EL(R)) and a second light-emitting layer (EL(G)) separated by a bank layer (BNK) may be located on the anode electrode layer (ANO). The subpixel illustrated in FIG. 15 is illustrated as an example where the light-emitting region has a rhombus shape rather than a square (or rectangular) shape, but is not limited thereto.

[0072] As can be seen from the above explanation, the first reference line (VREF1) and the second reference line (VREF2) are located on different layers, but they can be electrically connected to each other by a contact hole (CH) located in the area where they intersect. In addition, the first reference line (VREF1) and the second power line (EVSS) can be located on the same layer and can be formed by a source-drain metal layer that forms the source electrode and drain electrode of a transistor included in a subpixel (SP).

[0073] FIGS. 16 and 17 are drawings for explaining the line arrangement structure according to an embodiment of the present invention and the advantages thereof, and FIGS. 18 and 19 are drawings for explaining the line arrangement structure according to an experimental example and the disadvantages thereof. For reference, the structure of FIG. 16(a) is shown in FIG. 16(b) in terms of circuitry, and the structure of FIG. 18(a) is shown in FIG. 18(b) in terms of circuitry.

[0074] As illustrated in FIGS. 16 and 17, an embodiment of the present invention may have a second power line (EVSS) disposed in a display area (AA) and a non-display area (NA) of a display panel (150). The second power line (EVSS) is disposed within the non-display area (NA) to surround all sides of the display area (AA) and is disposed within the display area (AA) to have a mesh shape.

[0075] An embodiment of the present invention can resolve the problem of an increase in the second power supply voltage (EVSS Rising) that may occur when a display panel (150) is manufactured in a specific size or shape or driven in a specific manner, by having a mesh-shaped second power line (EVSS) placed within a display area (AA). As a result, a uniform full white image can be displayed across the entire display area (AA).

[0076] However, as illustrated in FIGS. 18 and 19, the experimental example may have the second power line (EVSS) placed only in the non-display area (NA) of the display panel (150) due to the structural characteristics of the line arrangement. Since the experimental example has the second power line (EVSS) placed only in the non-display area (NA) of the display panel (150), it is difficult to resolve the problem of the second power voltage rising (EVSS Rising) when the display panel (150) is manufactured in a specific size or shape or driven in a specific manner. As a result, due to the influence of the second power voltage rising (EVSS Rising), it may be difficult to express a uniform white (Full White) image due to differences in brightness and color coordinates by location, such as the first point (A) and the second point (B) of the display area (AA). For example, the second point (B) may cause a defect (Redish) where it turns red during optical compensation.

[0077] In summary, the present invention has the effect of providing a smooth and easy repair method in the event of a disconnection or short circuit in some lines based on a mesh-type reference line. Furthermore, the present invention has the effect of minimizing the problem of the second power supply voltage rising (EVSS Rising) when the display panel is enlarged or a narrow bezel is implemented, as the second power supply line can be internalized within the display area of ​​the display panel. Additionally, even when the second power supply line is internalized within the display area of ​​the display panel, the present invention has the effect of reducing pattern density and resolving the problem of increased line (wiring) spacing. Moreover, since the present invention can resolve the problems of reduced pattern density and increased line spacing, it has the effect of minimizing performance degradation issues of the display panel, such as crosstalk caused by an increase in parasitic capacitors. Furthermore, since the present invention can minimize performance degradation issues of the display panel, it has the effect of expressing a uniform image without differences in brightness and color coordinates depending on the location. In addition, the present invention can minimize the problems of reduced pattern density and increased line spacing, thereby effectively resolving the issue of reduced production yield caused by short circuits between lines and short circuits caused by foreign substances. Explanation of the symbols

[0078] 150: Display panel NA: Non-display area AA: Display area EVSS: Second power line VREF: Reference line VREF1: First reference line VREF2: The Second Reference Line

Claims

Claim 1 A light-emitting display device comprising: a display panel including a display area and a non-display area; a first reference line arranged in a first direction within the display area; a second reference line arranged in a second direction intersecting the first direction within the display area and electrically connected to the first reference line; a transistor included in a subpixel of the display panel; and a second power line arranged in the first direction within the display area, wherein the second reference line is arranged in the same layer as the semiconductor layer of the transistor. Claim 2 A light-emitting display device according to claim 1, wherein at least one of the first reference line and the second reference line is located on a different layer from the second power line. Claim 3 In claim 1, the second reference line is a light-emitting display device located on a different layer from the first reference line and the second power line. Claim 4 A light-emitting display device according to claim 1, wherein the first reference line and the second power line are selected as source-drain metal layers constituting the transistor. Claim 5 delete Claim 6 In paragraph 4, the first reference line and the second power line are a light-emitting display device located between an interlayer insulating layer and a planarization layer located in a layer higher than the second reference line. Claim 7 In claim 1, the second reference line is a light-emitting display device located between a buffer layer and a gate insulating layer located in a lower layer than the first reference line and the second power line. Claim 8 A light-emitting display device comprising: a buffer layer located on a substrate; a lower reference line located on the buffer layer and arranged horizontally within a display area defined on the substrate; at least one insulating layer located on the lower reference line; an upper reference line located on the insulating layer and arranged vertically within a display area defined on the substrate and electrically connected to the lower reference line; and a second power line located on the insulating layer and arranged vertically within a display area defined on the substrate, wherein the lower reference line is disposed on the same layer as the semiconductor layer of a transistor located between the buffer layer and the at least one insulating layer. Claim 9 In claim 8, the upper reference line and the second power line are positioned on the insulating layer and spaced apart from each other, and the light-emitting display device is composed of a source-drain metal layer. Claim 10 A method for manufacturing a light-emitting display device comprising: a step of forming a buffer layer on a substrate; a step of forming a lower reference line in a horizontal direction within a display area defined on the substrate located on the buffer layer; a step of forming at least one insulating layer on the lower reference line; a step of patterning a first source-drain metal layer arranged in a vertical direction within a display area defined on the substrate located on the insulating layer to form an upper reference line electrically connected to the lower reference line; and a step of patterning a second source-drain metal layer arranged in a vertical direction within a display area defined on the substrate located on the insulating layer to form a second power line spaced apart from the upper reference line, wherein the lower reference line is disposed on the same layer as the semiconductor layer of a transistor located between the buffer layer and the at least one insulating layer. Claim 11 In claim 1, the second reference line is a light-emitting display device including the semiconductor layer. Claim 12 In claim 1, the second reference line is a light-emitting display device comprising the semiconductor layer located in the display area.

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