Tiling Display Device

Abstract

A tiling display device according to an embodiment of the present specification comprises: a plurality of display modules connected to each other to display divided images to form a tiling screen; and a system chip that changes the display position of the divided images based on module placement information of each display module, wherein the border regions of each display module are provided with seam patterns that can be connected to neighboring display modules, and each display module derives connection state information of the seam patterns as the module placement information.

Description

Technology Field

[0001] This specification relates to a scalable tiling display device. Background Technology

[0002] Large displays can be utilized in various fields, such as indoor and outdoor digital advertising. To meet the demand for large displays, scalable tiling display devices are being proposed. A tiling display device forms a tiling screen by connecting multiple display modules, and it has the advantage of being able to realize a desired tiling screen size by adjusting the number of connected display modules. The tiling screen is realized through the segmented images of the display modules.

[0003] The user can change the arrangement positions of the display modules constituting the tiling display device in a non-conformable manner for various purposes. In this case, the shape of the tiling screen formed by the combination of the display modules can be changed in a non-conformable manner.

[0004] However, if the positions of the split images are not adjusted in accordance with changes in the tiling screen format, the irregular screen and the split images may mismatch with each other, potentially distorting the display image of the tiling screen. The problem to be solved

[0005] Accordingly, the embodiments of the present specification provide a tiling display device capable of detecting the placement positions of display modules and automatically adjusting the positions of segmented images according to the detection result. means of solving the problem

[0006] A tiling display device according to an embodiment of the present specification comprises: a plurality of display modules connected to each other to display divided images to form a tiling screen; and a system chip that changes the display position of the divided images based on module placement information of each display module, wherein the border regions of each display module are provided with seam patterns that can be connected to neighboring display modules, and each display module derives connection state information of the seam patterns as the module placement information. Effects of the invention

[0007] This embodiment has the following effects.

[0008] This embodiment can prevent display image distortion that may occur in a heterogeneous tiling screen by detecting the placement positions of display modules and automatically adjusting the positions of divided images according to the detection result.

[0009] The effects according to this specification are not limited to those exemplified above, and a wider variety of effects are included within this specification. Brief explanation of the drawing

[0010] FIG. 1 is a schematic diagram showing a tiling display device according to an embodiment of the present specification. Figure 2 is a diagram showing the connection configuration of a work display module. Figures 3 and 4 are drawings showing a micro LED-based display panel. Figure 5 is a schematic equivalent circuit diagram of one pixel provided on a display panel. FIG. 6 is a diagram schematically showing the steps of detecting the placement positions of display modules in a tiling display device according to an embodiment of the present specification and automatically adjusting the display positions of a segmented image based on the detection results. FIG. 7 is a diagram showing the configuration of the border area of ​​a first display module for detecting the connection status with an adjacent display module. FIG. 8 is a diagram showing the configuration of the border area of ​​a second display module for detecting the connection status with an adjacent display module. FIG. 9 is a drawing showing first connection state information and second connection state information generated when the first border area of ​​the first display module shown in FIG. 7 and the second border area of ​​the second display module shown in FIG. 8 are partially connected. FIG. 10 is a diagram illustrating an example of calculating the placement coordinates of segmented images in a system chip when the misalignment between adjacent display modules is in the X-axis direction. FIG. 11 is a diagram illustrating an example of calculating the placement coordinates of segmented images in a system chip when the misalignment between adjacent display modules is in the Y-axis direction. FIG. 12 is a comparative example of the present specification showing that, despite the change in the placement positions of the display modules, the display positions of the divided images are not changed, and thus the images are displayed distortedly on the tiling screen. FIG. 13 is a diagram showing an embodiment of the present specification in which the display positions of divided images are automatically changed based on module placement information of display modules so that images are displayed normally on a tiling screen. Specific details for implementing the invention

[0011] The advantages and features of this specification and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below but may be implemented in various different forms; these embodiments are provided merely to ensure that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of the invention, and this specification is defined only by the scope of the claims.

[0012] Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of this specification are exemplary and are not limited to the details illustrated in this specification. Throughout the specification, the same reference numerals refer to the same components. Where terms such as "comprising," "having," or "consisting of" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it includes the plural unless specifically stated otherwise.

[0013] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0014] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on top of,' 'above,' 'below,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0015] "First," "second," etc., may be used to describe various components, but these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of this specification.

[0016] Hereinafter, embodiments of the present specification will be described in detail with reference to the attached drawings. In the following description, if it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the essence of the present specification, such detailed description will be omitted.

[0017] FIG. 1 is a schematic diagram showing a tiling display device according to an embodiment of the present specification. FIG. 2 is a diagram showing the connection configuration of a display module.

[0018] Referring to FIGS. 1 and 2, a tiling display device (100) according to the present embodiment includes a system chip (SET) and a plurality of display modules (CB). Each display module (CB) includes a plurality of display panels (PNL). A display module (CB) may also be referred to as a cabinet.

[0019] Display modules (CBs) can be connected to each other through an interface circuit to form a tiling screen. The total resolution of the tiling screen can be determined by the sum of the module resolutions implemented in the display modules (CBs). For example, if the tiling screen is composed of 8 display modules (CBs) having a module resolution of 960 (width) * 1080 (height), the total resolution of the tiling screen can be 3840 (width) * 2160 (height).

[0020] Display modules (CB) can be connected to each other via a first interface circuit (IF1) of a bidirectional serial communication method to execute a target operation corresponding to a control command signal input from a system chip (SET). The bidirectional first interface circuit (IF1) can be implemented as a bidirectional multi-chain interface of a feedback loop type between adjacent display modules (CB). Since individual bidirectional serial communication between display modules (CB) is enabled by the bidirectional first interface circuit (IF1), a short communication line can be secured, and the speed and reliability of high-capacity data communication through the short communication line can be improved. The bidirectional first interface circuit (IF1) can be implemented as a Dual SPI (Serial Peripheral Interface), but is not limited thereto.

[0021] Any one of the display modules (CB) can be connected to the system chip (SET) via a bidirectional first interface circuit (IF1). When a bidirectional first interface circuit (IF1) is applied between the display module (CB) and the system chip (SET), there is an advantage in that the communication speed between the display module (CB) and the system chip (SET) is increased.

[0022] The system chip (SET) can sequentially transmit image data to be divided and displayed through the display modules (CB) to the display modules (CB) through the second interface circuit (IF2). The second interface circuit (IF2) can be implemented in a V-by-One (Vx1) manner capable of high-speed and high-capacity data interfacing, but is not limited thereto.

[0023] The system chip (SET) changes the display positions of the segmented images based on module placement information received from the display modules (CB), thereby ensuring that the output image is displayed on the tiling screen without distortion even if the placement positions of the display modules are changed.

[0024] Each display module (CB) may include a plurality of display panels (PNL), panel driving circuits for driving the display panels (PNL), and a timing control unit (TCON) for controlling the operation timing of the panel driving circuits.

[0025] Display panels (PNL) can be implemented as electroluminescent displays based on micro LEDs, but are not limited thereto and may also be implemented with light-emitting elements including mini LEDs.

[0026] Timing control units (TCONs) included in display modules (CBs) can be connected to each other through first and second interface circuits (IF1, IF2). The timing control unit (TCON) of each display module (CB) is mounted on a control printed circuit board (CPCB) and can be connected in parallel to the panel driving circuits of the corresponding display module (CB) through a branch cable (CBL).

[0027] A panel driving circuit may be independently provided for each of a plurality of display panels (PNL) constituting the same display module (CB). The panel driving circuit may include a source printed circuit board (SPCB) connected to a timing control unit (TCON) via a cable (CBL), a memory circuit (MEM) mounted on the source printed circuit board (SPCB), a conductive film (COF) electrically connecting the source printed circuit board (SPCB) and the display panel (PNL), a data driver (SIC) bonded on the conductive film (COF), a gate driver and a power circuit electrically connected to the source printed circuit board (SPCB), etc.

[0028] The memory circuit (MEM) is a non-volatile memory that stores panel characteristics and may be a flash memory and / or EEPROM containing a correction value for gamma setting, a first compensation value for compensating for driving characteristic deviations / color deviations between pixels, a second compensation value for compensating for boundary deviations between adjacent display panels (PNLs), and various image quality and driving control data. In this case, large-capacity data may be stored in the flash memory, and small-capacity data may be stored in the EEPROM.

[0029] The timing control unit (TCON) can operate the panel driving circuit according to a control command signal received from the system chip (SET) through the first interface circuit (IF1) to execute a target operation corresponding to the control command signal and generate a control response signal including the result of the execution of the target operation. The target operation may include reset, mute (blackout), change of APL (Average Picture Level) range, change of gamma, update of image quality compensation value, firmware update, etc. The target operation may further include an operation of writing control command data to a specific memory and storing it, and an operation of reading out control execution data from a specific memory.

[0030] The timing control unit (TCON) can acquire module placement information of the display module (CB) to which it belongs according to a control command signal received from the system chip (SET) through the first interface circuit (IF1) and store it in the memory circuit (MEM). Additionally, the timing control unit (TCON) can read the module placement information from the memory circuit (MEM) according to the control command signal received from the system chip (SET) through the first interface circuit (IF1) and transmit it to the system chip (SET) through the first interface circuit (IF1).

[0031] The timing control unit (TCON) can control the operation of the panel driving circuit so that the segmented image data received through the second interface circuit (IF2) is displayed on the display panels (PNL).

[0032] FIGS. 3 and FIGS. 4 are drawings showing a micro LED-based display panel. FIG. 5 is a schematic equivalent circuit diagram of one pixel provided in the display panel.

[0033] Referring to FIGS. 3 and 4, a pixel array for displaying a segmented image is formed in each of the display panels (PNL). A plurality of pixels are arranged in the pixel array, and signal wiring for driving the pixels may be arranged. These signal wiring may include data lines (DL) for supplying a data voltage (Vdata) to the pixels, gate lines (GL) for supplying a gate signal (GSIG) to the pixels, and power lines for supplying a power voltage to the pixels.

[0034] Each pixel may include a micro LED chip (μLED chip) as a light-emitting element (EL). The micro LED chips (μLED chips) may include red chips (μLED chip_R), green chips (μLED chip_G), and blue chips (μLED chip_B) located on a Thin Film Transistor (TFT) backplane. The R pixel includes a red chip (μLED chip_R) as a light-emitting element (EL), the G pixel includes a green chip (μLED chip_G) as a light-emitting element (EL), and the B pixel includes a blue chip (μLED chip_B) as a light-emitting element (EL).

[0035] Micro LED chips (μLED chips) can be mounted on a TFT backplane by being transferred from R / G / B donors. Red chips (μLED chip_R) can be transferred from an R donor, green chips (μLED chip_G) can be transferred from a G donor, and blue chips (μLED chip_B) can be transferred from a B donor. Transfer technology can utilize electrostatic force, lasers, speed-dependent adhesion, load-dependent adhesion, etc. Transfer technology is not limited to these and may also utilize self-assembly based on electromagnetic force.

[0036] The TFT backplane can be structured as an active matrix for efficient driving. On the TFT backplane, pixels can be defined by the intersection of data lines (DL), gate lines (GL), and power lines.

[0037] Multiple pixels can form a single unit pixel. For example, adjacent R (red), G (green), and B (blue) pixels placed along the extension direction of the gate line (GL) or the extension direction of the data line (DL) can form a single unit pixel.

[0038] As shown in FIG. 5, one pixel (PXL) may include a light-emitting element (EL), a driving TFT (DT), and a node circuit (NCON).

[0039] The node circuit (NCON) can be connected to the gate line (GL) and the data line (DL). The node circuit (NCON) receives a data voltage (Vdata) from the data line (DL) and a gate signal (GSIG) from the gate line (GL). By applying the data voltage (Vdata) to the gate electrode of the driving TFT (DT) in synchronization with the gate signal (GSIG), the node circuit (NCON) can set the gate-source voltage of the driving TFT (DT) to match the conditions for generating the driving current. The node circuit (NCON) may include an internal compensation circuit that compensates the gate voltage of the driving TFT (DT) by sensing the threshold voltage and / or electron mobility of the driving TFT (DT).

[0040] The driving TFT (DT) is a driving element that generates a driving current in response to the voltage between the gate and the source. The gate electrode of the driving TFT (DT) is connected to a node circuit (NCON), the first electrode (drain electrode) is connected to a high-potential pixel power supply (VDD), and the second electrode (source electrode) can be connected to a light-emitting element (EL).

[0041] The light-emitting element (EL) is a light-emitting element that emits light with an intensity corresponding to the driving current input from the driving TFT (DT). The light-emitting element (EL) may be implemented as a micro light-emitting diode including an inorganic light-emitting layer. The first electrode of the light-emitting element (EL) is connected to the driving TFT (DT), and the second electrode may be connected to the low-potential pixel power supply (VSS).

[0042] The connection configuration of such one pixel (PXL) is merely an example, and therefore the technical concept of this specification is not limited thereto. For example, the driving TFT (DT) and the node circuit (NCON) may be implemented based on PMOS or based on NMOS. In addition, there may be multiple gate lines (GL) connected to the node circuit (NCON).

[0043] FIG. 6 schematically shows a procedure for detecting the placement positions of display modules in a tiling display device according to an embodiment of the present specification and automatically adjusting the display positions of a segmented image based on the detection result.

[0044] Referring to FIG. 6, in a tiling display device according to the present embodiment, each display module obtains its module placement information in accordance with a control command from a system chip (SET) and stores it in memory. Each display module can detect connection status information of seam patterns provided in its border areas as module placement information (S10).

[0045] Each display module can read module placement information from memory according to a control command from the system chip (SET) and then transmit the module placement information to the system chip (SET) through the first interface circuit (S20).

[0046] The system chip (SET) can calculate the placement coordinates of the display modules based on the module placement information received from the display modules, and change the display position of the segmented image to correspond to these placement coordinates (S30).

[0047] FIG. 7 is a drawing showing the configuration of the border area of ​​a first display module for detecting the connection status with an adjacent display module. FIG. 8 is a drawing showing the configuration of the border area of ​​a second display module for detecting the connection status with an adjacent display module.

[0048] Although the border areas (BA) are depicted as exaggeratedly large in FIGS. 7 and 8, in reality, the border areas (BA) can be designed to be small so that the dead zone (bezel) is minimized when connecting the display modules.

[0049] Referring to FIGS. 7 and 8, the first display module (CB1) includes four border regions (BA) that can be connected to neighboring display modules. The second display module (CB2) also includes four border regions (BA) that can be connected to neighboring display modules. In each of the first and second display modules (CB1, CB2), the four border regions (BA) may be top, bottom, left, and right border regions (BA).

[0050] For ease of connection with adjacent display modules, some of the four border regions (BA) may have a first seam pattern (PTN1), and the rest may have a second seam pattern (PTN2). The first seam pattern (PTN1) and the second seam pattern (PTN2) may have opposite shapes so that they can interlock with each other. The first seam pattern (PTN1) of the first display module (CB1) and the second seam pattern (PTN2) of the second display module (CB2) can interlock with each other.

[0051] The first seam pattern (PTN1) includes a plurality of protrusions (CP) that are convex toward the outside of each of the first and second display modules (CB1, CB2). The width of one protrusion (CP) becomes the horizontal spacing resolution or the vertical spacing resolution. The number of protrusions (CP) corresponds to the number of bits of connection status information.

[0052] The second seam pattern (PTN2) includes a plurality of grooves (GP) that are concave toward the interior of each of the first and second display modules (CB1, CB2). The width of a groove (GP) becomes the horizontal spacing resolution or the vertical spacing resolution. The number of grooves (GP) corresponds to the number of bits of connection status information.

[0053] In this embodiment, the protrusions (CP) and grooves (GP) are exemplified as hemispherical, but are not limited thereto. The protrusions (CP) and grooves (GP) may be of any shape as long as they are structured to interlock with each other.

[0054] The first seam pattern (PTN1) of each of the first and second display modules (CB1, CB2) may be configured to be identical to the protrusions (CP) shown in FIG. 7. The protrusions (CP) may be provided with first connection terminals (C1) connected to a high-potential logic power supply (VCC) and second connection terminals (C2) connected to a base power supply (GND). The first and second connection terminals (C1, C2) may be made of a conductive material.

[0055] The second seam pattern (PTN2) of each of the first and second display modules (CB1, CB2) may be configured to be identical to the grooves (GP) shown in FIG. 8. The grooves (GP) may be provided with third connection terminals (C3) connected to a high-potential logic power supply (VCC) and fourth connection terminals (C4) connected to a base power supply (GND). The third and fourth connection terminals (C3, C4) may be made of a conductive material.

[0056] In FIG. 7, only the configuration of the lower border area (BA) of the first display module (CB1) is illustrated in detail. In FIG. 8, only the configuration of the upper border area (BA) of the second display module (CB2) is illustrated in detail. However, the configuration of the left border area (BA) of the first display module (CB1) and the configuration of the left and lower border areas (BA) of the second display module (CB2) may be substantially identical to the configuration of the lower border area (BA) of the first display module (CB1). Furthermore, the configuration of the upper and right border areas (BA) of the first display module (CB1) and the configuration of the right border area (BA) of the second display module (CB2) may be substantially identical to the configuration of the upper border area (BA) of the second display module (CB2).

[0057] In the border regions (BA) of the first and second display modules (CB1, CB2), a plurality of interlocking reinforcing parts (MG1, MG2) may be further provided to strengthen the connection between the first seam pattern (PTN1) and the second seam pattern (PTN2) when connected with adjacent display modules. The interlocking reinforcing parts (MG1, MG2) may be implemented by first polarity magnets (MG1) installed in the protrusions (CP) and second polarity magnets (MG2) installed in the grooves (GP). Due to the strong magnetic flux force between the first and second polarity magnets (MG1, MG2), the connection between the first seam pattern (PTN1) and the second seam pattern (PTN2) is solidified, so that the first connection state information of the first seam pattern (PTN1) and the second connection state information of the second seam pattern (PTN2) can be accurately derived.

[0058] In the border areas (BA) of the first and second display modules (CB1, CB2), first and second analog-to-digital converters (ADC1, ADC2) may optionally be further provided. The first analog-to-digital converter (ADC1) converts the first connection state information of the first seam pattern (PTN1) into a digital signal, and the second analog-to-digital converter (ADC2) converts the second connection state information of the second seam pattern (PTN2) into a digital signal. The first and second connection state information converted into digital signals is supplied to a timing control unit (TCON) provided in each of the first and second display modules (CB1, CB2).

[0059] In each of the first and second display modules (CB1, CB2), the four analog-to-digital converters (ADC1, ADC2) provided in the four border regions (BA) may be replaced with a single integrated analog-to-digital converter. In this case, a multiplexer may be further connected to the front of the integrated analog-to-digital converter for sequential processing of the four connection status information.

[0060] The timing control unit (TCON) provided in the first display module (CB1) receives up, down, left, and right connection status information from each of the four border areas (BA) of the first display module (CB1). The up, down, left, and right connection status information detected in the four border areas (BA) of the first display module (CB1) may include two first connection status information and two second connection status information.

[0061] Likewise, the timing control unit (TCON) provided in the second display module (CB2) receives up, down, left, and right connection status information from each of the four border areas (BA) of the second display module (CB2). The up, down, left, and right connection status information detected in the four border areas (BA) of the second display module (CB2) may include two first connection status information and two second connection status information.

[0062] FIG. 9 shows first connection state information and second connection state information generated when the first border area of ​​the first display module (CB1) shown in FIG. 7 and the second border area of ​​the second display module (CB2) shown in FIG. 8 are partially connected.

[0063] Referring to FIGS. 7 to 9, the first border area of ​​the first display module (CB1) may be the lower border area (BA), and the second border area of ​​the second display module (CB2) may be the upper border area (BA).

[0064] The first connection state information of the first seam pattern (PTN1) provided in the first display module (CB1) can be determined according to the number of first connection terminals (C1) that are electrically connected to the fourth connection terminals (C4). For example, in FIG. 9, the first connection state information of the first seam pattern (PTN1) may be "11000". Among the first connection terminals (C1) of the first seam pattern (PTN1), those that are not connected to the fourth connection terminals (C4) of the second seam pattern (PTN2) may be output as a bit value 1, and conversely, those that are connected to the fourth connection terminals (C4) of the second seam pattern (PTN2) may be output as a bit value 0.

[0065] The second connection state information of the second seam pattern (PTN2) provided in the second display module (CB2) can be determined according to the number of third connection terminals (C3) that are electrically connected to the second connection terminals (C2). For example, in FIG. 9, the second connection state information of the second seam pattern (PTN2) may be "00111". Among the third connection terminals (C3) of the second seam pattern (PTN2), those that are not connected to the second connection terminals (C2) of the first seam pattern (PTN1) may be output as a bit value 1, and conversely, those that are connected to the second connection terminals (C2) of the first seam pattern (PTN1) may be output as a bit value 0.

[0066] In this way, the first and second connection status information of the first and second seam patterns (PTN1, PTN2) can indicate the relative placement positions of the first and second display modules (CB1, CB2).

[0067] FIG. 10 is a diagram illustrating an example of calculating the placement coordinates of segmented images in a system chip when the misalignment between adjacent display modules is in the X-axis direction.

[0068] Referring to FIG. 10, the system chip (SET) can calculate the placement coordinates of the first to sixth display modules (#1 to #6) based on multiple connection status information obtained from the first to sixth display modules (#1 to #6) that constitute a heterogeneous tiling screen.

[0069] The system chip (SET) can calculate the placement coordinates of the remaining display modules (#2 to #6) based on the first display module (#1). In this case, the first display module (#1) can serve as the reference display module for calculating coordinate values. The system chip (SET) can calculate the placement coordinates of the remaining display modules (#2 to #6) based on the known placement coordinates (x,y) of the first display module (#1) and connection status information of at least some of the remaining display modules (#2 to #6). The reference display module is not limited to the first display module (#1) and may be selected from among the remaining display modules (#2 to #6).

[0070] The system chip (SET) can calculate the upper left x-coordinate of the second display module (#2) by subtracting (horizontal spacing resolution * number of upper connection status information zeros of the second display module (#2)) from the upper left x-coordinate of the first display module (#1). The horizontal spacing resolution is the value obtained by dividing the horizontal resolution of the second display module (#2) by the number of spacings (i.e., the number of grooves or protrusions). The system chip (SET) can calculate the upper left y-coordinate of the second display module (#2) by adding the vertical resolution of the first display module (#1) to the upper left y-coordinate of the first display module (#1).

[0071] The system chip (SET) can calculate the upper-left x-coordinate of the third display module (#3) by adding the horizontal resolution of the second display module (#2) to the upper-left x-coordinate of the second display module (#2). The system chip (SET) can calculate the upper-left y-coordinate of the third display module (#3) by adding the upper-left y-coordinate of the second display module (#2).

[0072] The system chip (SET) can calculate the upper-left x-coordinate of the fourth display module (#4) by subtracting (horizontal spacing resolution * number of upper connection status information zeros of the fourth display module (#4)) from the upper-left x-coordinate of the second display module (#2). The horizontal spacing resolution is the value obtained by dividing the horizontal resolution of the fourth display module (#4) by the number of spacings (i.e., the number of grooves or protrusions). The system chip (SET) can calculate the upper-left y-coordinate of the fourth display module (#4) by adding the vertical resolution of the second display module (#2) to the upper-left y-coordinate of the second display module (#2).

[0073] The system chip (SET) can calculate the top-left x-coordinate of the fifth display module (#5) by adding the horizontal resolution of the fourth display module (#4) to the top-left x-coordinate of the fourth display module (#4). The system chip (SET) can calculate the top-left y-coordinate of the fifth display module (#5) by adding the top-left y-coordinate of the fourth display module (#4).

[0074] The system chip (SET) can calculate the upper-left x-coordinate of the sixth display module (#6) by adding the horizontal resolution of the fifth display module (#5) to the upper-left x-coordinate of the fifth display module (#5). The system chip (SET) can calculate the upper-left y-coordinate of the sixth display module (#6) by adding the upper-left y-coordinate of the fifth display module (#5).

[0075] In this way, the system chip (SET) can change the display positions of the segmented images to match the placement coordinates of the first to sixth display modules (#1 to #6) after calculating the placement coordinates of the first to sixth display modules (#1 to #6).

[0076] FIG. 11 is a diagram illustrating an example of calculating the placement coordinates of segmented images in a system chip when the misalignment between adjacent display modules is in the Y-axis direction.

[0077] Referring to FIG. 11, the system chip (SET) can calculate the placement coordinates of the first to seventh display modules (#1 to #7) based on multiple connection status information obtained from the first to seventh display modules (#1 to #7) that constitute the heterogeneous tiling screen.

[0078] The system chip (SET) can calculate the placement coordinates of the remaining display modules (#2 to #7) based on the first display module (#1). In this case, the first display module (#1) can serve as the reference display module for calculating coordinate values. The system chip (SET) can calculate the placement coordinates of the remaining display modules (#2 to #7) based on the known placement coordinates (x,y) of the first display module (#1) and connection status information of at least some of the remaining display modules (#2 to #7). The reference display module is not limited to the first display module (#1) and may be selected from among the remaining display modules (#2 to #7).

[0079] The system chip (SET) can calculate the top-left x-coordinate of the first display module (#1) as the top-left x-coordinate of the second display module (#2). The system chip (SET) can calculate the top-left y-coordinate of the second display module (#2) by adding the vertical resolution of the first display module (#1) to the top-left y-coordinate of the first display module (#1).

[0080] The system chip (SET) can calculate the upper-left x-coordinate of the third display module (#3) by adding the horizontal resolution of the first display module (#1) to the upper-left x-coordinate of the first display module (#1). The system chip (SET) can calculate the upper-left y-coordinate of the third display module (#3) by subtracting (vertical spacing resolution * number of left connection status information zeros of the third display module (#3)) from the upper-left y-coordinate of the first display module (#1). The vertical spacing resolution is the value obtained by dividing the vertical resolution of the third display module (#2) by the number of spacings (i.e., the number of grooves or protrusions).

[0081] The system chip (SET) can calculate the top-left x-coordinate of the third display module (#3) as the top-left x-coordinate of the fourth display module (#4). The system chip (SET) can calculate the top-left y-coordinate of the fourth display module (#4) by adding the vertical resolution of the third display module (#3) to the top-left y-coordinate of the third display module (#3).

[0082] The system chip (SET) can calculate the top-left x-coordinate of the fourth display module (#4) as the top-left x-coordinate of the fifth display module (#5). The system chip (SET) can calculate the top-left y-coordinate of the fifth display module (#5) by adding the vertical resolution of the fourth display module (#4) to the top-left y-coordinate of the fourth display module (#4).

[0083] The system chip (SET) can calculate the upper-left x-coordinate of the sixth display module (#6) by adding the horizontal resolution of the third display module (#3) to the upper-left x-coordinate of the third display module (#3). The system chip (SET) can calculate the upper-left y-coordinate of the sixth display module (#6) by adding (vertical spacing resolution * number of left connection status information zeros of the sixth display module (#6)) to the upper-left y-coordinate of the third display module (#3). The vertical spacing resolution is the value obtained by dividing the vertical resolution of the sixth display module (#6) by the number of spacings (i.e., the number of grooves or protrusions).

[0084] The system chip (SET) can calculate the upper-left x-coordinate of the 6th display module (#6) as the upper-left x-coordinate of the 7th display module (#7). The system chip (SET) can calculate the upper-left y-coordinate of the 7th display module (#7) by adding the vertical resolution of the 6th display module (#6) to the upper-left y-coordinate of the 6th display module (#6).

[0085] In this way, the system chip (SET) can change the display positions of the segmented images to match the placement coordinates of the first to seventh display modules (#1 to #7) after calculating the placement coordinates of the first to seventh display modules (#1 to #7).

[0086] FIG. 12 is a comparative example of the present specification showing that, despite the change in the placement positions of the display modules, the display positions of the divided images are not changed, and thus the images are displayed distortedly on the tiling screen.

[0087] Referring to FIG. 12, when a tiling screen based on the first to ninth display modules (#1 to #9) is reconfigured by a user into six display modules (#1, #4, #5, #7, #8, #9), if the display positions of the segmented images are not changed in accordance with the change in the placement positions of the display modules, the images will be displayed distorted in the reconfigured tiling screen. In FIG. 12, image distortion occurs in the three display modules (#1, #4, #5) whose placement positions have been changed.

[0088] FIG. 13 is a diagram showing an embodiment of the present specification in which the display positions of divided images are automatically changed based on module placement information of display modules so that images are displayed normally on a tiling screen.

[0089] Referring to FIG. 13, when a tiling screen based on the first to ninth display modules (#1 to #9) is reconfigured by a user into six display modules (#2, #4, #5, #7, #8, #9), the display positions of the segmented images are automatically changed to match the change in the placement positions of the display modules, so that the output image is displayed normally in the reconfigured tiling screen. The system chip (SET) can prevent distortion of the output image by adjusting the segmented images of the display modules (#4, #5) differently from those immediately before reconfiguration based on the module placement information of the two display modules (#4, #5) whose placement positions have been changed.

[0090] From the above description, those skilled in the art will understand that various changes and modifications are possible within the scope of the technical concept of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0091] CB: Display Module SET: System Chip PTN1,2: Seam pattern BA: Border area CP: Protrusion GP: Groove C1, C2, C3, C4: Connection terminals MG1, MG2: Interlocking reinforcement

Claims

Claim 1 Multiple display modules connected to each other to form a tiling screen and display split images; The system includes a system chip that changes the display position of a segmented image based on module placement information of each display module, wherein the border regions of each display module are provided with seam patterns that can be connected to adjacent display modules, and when the first border region of the first display module and the second border region of the second display module are at least partially connected, the first border region of the first display module is provided with a first seam pattern, and the second border region of the second display module is provided with a second seam pattern that engages with the first seam pattern, wherein the first seam pattern and the second seam pattern have opposite shapes to each other, the first seam pattern includes a plurality of protrusions that are convex toward the outside of the display module, and the second seam pattern includes a plurality of grooves that are concave toward the inside of the display module, wherein the plurality of protrusions are provided with a first connection terminal connected to a high-potential logic power supply and a second connection terminal connected to a base power supply, and the plurality of grooves are provided with a third connection terminal connected to the high-potential logic power supply and the A tiling display device comprising: a fourth connection terminal connected to a base power source, wherein at least a portion of the first connection terminals and at least a portion of the fourth connection terminals are connected to each other, and at least a portion of the second connection terminals and at least a portion of the third connection terminals are connected to each other, wherein the first connection state information of the first seam pattern is determined according to the number of the first connection terminals connected to the fourth connection terminals, and the second connection state information of the second seam pattern is determined according to the number of the third connection terminals connected to the second connection terminals, and wherein each display module derives the first and second connection state information as module placement information. Claim 2 delete Claim 3 delete Claim 4 delete Claim 5 delete Claim 6 A tiling display device according to claim 1, wherein the number of protrusions and the number of grooves correspond to the number of bits of the connection status information. Claim 7 A tiling display device according to claim 1, wherein the first border area of ​​the first display module and the second border area of ​​the second display module further comprise a plurality of interlocking reinforcing parts for reinforcing the connection between the first seam pattern and the second seam pattern. Claim 8 In claim 7, the interlocking reinforcing parts comprise a plurality of first polarity magnets located in the first edge region and a plurality of second polarity magnets located in the second edge region, forming a tiling display device. Claim 9 A tiling display device according to claim 1, wherein a first analog-to-digital converter for converting first connection state information of the first seam pattern into a digital signal is further provided in the first border area of ​​the first display module, and a second analog-to-digital converter for converting second connection state information of the second seam pattern into a digital signal is further provided in the second border area of ​​the second display module.

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