Solid-state device with multiple thermal power states

Abstract

Embodiments of a storage device that apply advanced thermal throttling in response to temperature changes based on multiple thermal power states for various types of cells, such as SLC and MLC, are provided. Initially, a controller determines whether the temperature of the memory satisfies a thermal throttling threshold of a plurality of thermal throttling thresholds. Subsequently, when the temperature satisfies the thermal throttling threshold, the controller transitions to a thermal power state among the plurality of thermal power states. The controller applies a thermal relaxation configuration associated with the thermal power state. Then, based on the thermal relaxation configuration, the controller determines whether the temperature of the memory in the thermal power state has reached thermal equilibrium. Accordingly, the performance of the storage device is improved through advanced thermal throttling without compromising data integrity.

Description

Technology Field

[0001] Cross-reference of related application(s)

[0002] This application claims the benefit of U.S. Regular Application No. 17 / 741,242, filed on May 10, 2022, titled "SOLID-STATE DEVICE WITH MULTIPLE THERMAL POWER STATES," the entire contents of which are incorporated herein by reference for all purposes. Background Technology

[0003] Field

[0004] The present disclosure generally relates to electronic devices, and more specifically, to storage devices.

[0005] introduction

[0006] Storage devices enable users to store and retrieve data. Examples of storage devices include non-volatile memory devices. Non-volatile memory generally retains data after a power cycle. An example of non-volatile memory is flash memory, which may include array(s) of NAND cells on one or more dies. Flash memory can be found in solid-state devices (SSDs), Secure Digital (SD) cards, and the like.

[0007] Flash storage devices can store data in NAND cells of flash memory. NAND cells can include single-level cells (SLC) or multi-level cells (MLC). Examples of MLC include triple-level cell (TLC), quad-level cell (QLC), and penta-level cell (PLC). Generally, flash storage devices can write data directly to pages of SLC blocks. However, data can only be erased from blocks of flash memory. Therefore, when an SLC block becomes full, the flash storage device can relocate data to empty blocks through a garbage collection process to free up space within the flash memory. For example, data can be relocated to blocks of MLC.

[0008] As data is stored and accessed, the temperature of NAND cells can increase beyond their respective reliable operating temperatures. For example, due to the redistribution of data from SLC, the temperature of MLC may exceed a specific thermal throttling threshold (e.g., , If the temperature exceeds 86°C, the integrity or reliability of MLC data may be affected. Therefore, to preserve system data integrity, thermal throttling may be applied to keep the flash storage device below the thermal throttling threshold. For example, if the cell temperature exceeds 86°C, the flash storage device may disable parallel access to one or more dies, or otherwise reduce the rate of data written to the NAND cells to decrease power consumption, and then lower the temperature back below the threshold. However, such reduction in NAND operation can significantly degrade the performance of the flash storage device (e.g., ,It can degrade the user experience by at least 50% and prevent the system from meeting performance benchmarks.

[0009] One embodiment of a storage device is disclosed herein. The storage device includes a memory and a controller. The controller is configured to determine whether the temperature of the memory satisfies a thermal throttling threshold of a plurality of thermal throttling thresholds, and when the temperature satisfies the thermal throttling threshold, to transition to a thermal power state among a plurality of thermal power states, apply a thermal relaxation configuration associated with the thermal power state, and determine whether the temperature of the memory in the thermal power state has reached thermal equilibrium based on the thermal relaxation configuration.

[0010] Other aspects of a storage device are disclosed herein. The storage device includes a memory and a controller. The controller is configured to adjust one or more thermal relaxation parameters associated with a thermal power state based on a transition to a thermal power state among a plurality of thermal power states when the temperature of the memory meets a thermal throttling threshold, and to determine whether the temperature of the memory in the thermal power state has reached thermal equilibrium based on the adjusted one or more thermal relaxation parameters.

[0011] Additional embodiments of a storage device are disclosed herein. The storage device includes a memory and a controller. The memory has a block of cells. The controller is configured to apply a thermal relaxation configuration associated with a thermopower state based on a transition to a thermopower state among a plurality of thermopower states when the temperature of the block of cells satisfies a thermal throttling threshold, and to determine whether the temperature of the block of cells in the thermopower state has reached thermal equilibrium based on the thermal relaxation configuration.

[0012] It is understood that other embodiments of the storage device will be readily apparent to those skilled in the art from the following detailed description, where various embodiments of devices and methods are illustrated and described as examples. As realized, these embodiments may be implemented in different and distinct forms, and various details thereof may be modified in various other embodiments. Accordingly, the drawings and detailed description should be regarded as illustrative in nature and are not limiting. Brief explanation of the drawing

[0013] Now, various embodiments of the present invention will be presented in the detailed description as examples, not as limitations, with reference to the accompanying drawings. FIG. 1 is a block diagram illustrating an exemplary embodiment of a storage device communicating with a host device. FIG. 2 is a conceptual diagram illustrating an example of a logical-physical mapping table within the non-volatile memory of the storage device of FIG. 1. FIG. 3 is a conceptual diagram illustrating an example of an array of memory cells within a storage device of FIG. 1. FIG. 4 is a conceptual diagram illustrating an example of an array of blocks within the storage device of FIG. 1. FIG. 5 is a graphic illustration illustrating an example of a voltage distribution chart for triple-level cells in the storage device of FIG. 1. FIG. 6 is a conceptual diagram illustrating an example of a garbage collection (GC) process that can be implemented within the storage device of FIG. 1. FIG. 7 illustrates an exemplary diagram of thermal throttling in a storage device. FIG. 8 is a conceptual diagram illustrating a controller that writes data to a block at different data rates corresponding to different temperatures of the block using advanced thermal throttling in the storage device of FIG. 1. FIG. 9 is a flowchart illustrating an exemplary process for advanced thermal throttling in the storage device of FIG. 1. FIG. 10 is a conceptual diagram illustrating a controller for advanced thermal throttling using multiple thermal power states in the storage device of FIG. 1. FIG. 11 is a flowchart illustrating an exemplary process for advanced thermal throttling using multiple thermal power states in the storage device of FIG. 1. FIG. 12 is a conceptual diagram illustrating various examples of advanced thermal throttling in the storage device of FIG. 1. FIG. 13 is a conceptual diagram illustrating a state machine of multiple thermoelectric states for advanced thermal throttling in the storage device of FIG. 1. FIG. 14 is a flowchart illustrating an exemplary process for a first thermal power state of advanced thermal throttling in the storage device of FIG. 1. FIG. 15 is a flowchart illustrating an exemplary process for a second thermal power state of advanced thermal throttling in the storage device of FIG. 1. FIG. 16 is a flowchart illustrating an exemplary process for a third thermal power state of advanced thermal throttling in the storage device of FIG. 1. FIG. 17 is a flowchart illustrating an exemplary process for a fourth thermal power state of advanced thermal throttling in the storage device of FIG. 1. FIG. 18a is a graphic illustration illustrating a performance benchmark using legacy thermal throttling in the storage device of FIG. 1. FIG. 18b is a graphic illustration illustrating a performance benchmark using advanced thermal throttling in the storage device of FIG. 1. Specific details for implementing the invention

[0014] The detailed description below, in conjunction with the accompanying drawings, is intended to describe various exemplary embodiments of the invention and is not intended to represent the only embodiments in which the invention may be practiced. The detailed description includes specific details for the purpose of providing a complete understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without such specific details. In some cases, known structures and components are depicted in block diagram form to avoid obscuring the concepts of the invention. Acronyms and other descriptive terms may be used merely for convenience and clarity and are not intended to limit the scope of the invention.

[0015] The words “exemplary” and “example” are used herein to signify an example, case, or illustration. Any exemplary embodiment described as “exemplary” herein is not to be interpreted as being more desirable or advantageous than other exemplary embodiments. Likewise, the term “exemplary embodiment” of an apparatus, method, or manufactured article does not require that all exemplary embodiments of the invention include the described components, structures, features, functionalities, processes, advantages, benefits, or modes of operation.

[0016] As used herein, the term “combined” is used to indicate a direct connection between two components or, where appropriate, an indirect connection to each other through interposed or intermediate components. In contrast, when a component is referred to as “directly combined” to another component, there is no interposed element.

[0017] In the following detailed description, various embodiments of a storage device communicating with a host device will be presented. These embodiments are highly suitable for flash storage devices such as SSDs and SD cards. However, those skilled in the art will recognize that these embodiments can be extended to all types of storage devices capable of storing data. Accordingly, any reference to a specific device or method is intended merely to illustrate such embodiments, with the understanding that various embodiments of the invention may have a wide range of applications without departing from the spirit and scope of the invention.

[0018] When a storage device performs thermal throttling, it typically reduces the rate of data written to the NAND cells as soon as the temperature of the die containing the NAND cells exceeds a threshold. However, when performing thermal throttling, a hard transition occurs at the thermal throttling threshold due to the thermal throttling. For example, the storage device typically performs thermal throttling with relatively large fluctuations in the data rate between transitions. For instance, the storage device may reduce the write data rate to a first set of parameters when the die exceeds a first thermal throttling threshold at 80°C, and further reduce the write data rate from a first set of fixed parameters to a second set of significantly different parameters when the die exceeds a second thermal throttling threshold at 86°C. Due to these large differences between transitions, device performance and power consumption can vary significantly over time between transitions and may affect the user experience.

[0019] Accordingly, to improve storage device performance and user experience, the present disclosure enables a storage device to selectively select a specific thermal configuration and dynamically adjust internal relaxation parameters, thereby progressively adjusting the internal relaxation parameters over time (or preemptively) to align the storage device with a host-specified temperature framework parameter, so as to achieve optimized and deterministic performance within a thermal envelope targeting minimum quality of delayed latency and service interruption. Typically, the controller of the storage device has a first data rate (e.g., , Data is routed to memory in response to a write command from the host by storing data directly in the SLC blocks at the full clock rate. As the number of free SLC blocks decreases, the controller reallocates data within the SLC blocks to MLC blocks. This reallocation can increase the temperature of the MLC blocks. When the temperature of the MLC blocks reaches the first thermal throttling threshold (e.g., , When the TMT1) increases beyond 80°C, the controller disables data relocation from SLC blocks to MLC blocks and restricts host data writing to SLC blocks, thereby changing how data is routed to memory. However, the controller performs thermal throttling by applying a selected thermal relaxation configuration associated with the thermal power state, scaling the power budget according to the temperature gradient to maintain maximum possible performance while maintaining thermal equilibrium within the thermal power state. This is in contrast to the significant performance transitions that occur between thermal power state transitions when the storage device exceeds the corresponding thermal throttling threshold, allowing data to be written at a thermally throttled data rate that translates to desired performance benchmarks for various workloads within the adjusted power budget.

[0020] The controller may initially start writing host data in response to write commands for blocks of cells at a first data rate (e.g., at the full clock rate). Then, the controller continues to write host data in response to write commands for cell blocks, which may increase the temperature of the cell blocks. If the temperature of the blocks of cells increases beyond a first thermal throttling threshold (e.g., TMT1, such as 80°C), the controller may transition to a first thermal power state and enable thermal throttling. For example, the controller may reduce the rate of data written to SLC blocks and MLC blocks to a smaller second data rate (e.g., at 60% of the full clock rate), for example , This is possible by applying a thermal relaxation configuration associated with the first thermal power state. Based on the applied thermal relaxation configuration, the controller can reduce the power budget parameter (reducing the power consumption allocated to the storage device) until thermal equilibrium is reached (e.g., the temperature gradient based on the measured temperature does not indicate a positive or negative rate of change of temperature).

[0021] Consequently, instead of employing thermal throttling that causes hard power state transitions (and consequently reduces performance) when the temperature of the storage device exceeds different thermal throttling thresholds, the storage device of the present disclosure applies advanced thermal throttling that utilizes multiple thermal power states, each progressively reducing power based on a temperature gradient, along with other thermal mitigation parameters such as dynamic voltage and frequency scaling, queue depth adjustment, and bus interconnect scaling. In this way, the storage device of the present disclosure provides an improved user experience, enables the satisfaction of performance benchmarks, and maintains data reliability through efficient NAND block utilization.

[0022] FIG. 1 illustrates an exemplary block diagram (100) of a storage device (102) communicating with a host device (104) (also, "host") according to an exemplary embodiment. The host (104) and the storage device (102) may form a system such as a computer system (e.g., a server, a desktop, a mobile / laptop, a tablet, a smartphone, etc.). The components of FIG. 1 may or may not be physically located together. In this regard, the host (104) may be located remotely from the storage device (102). Although FIG. 1 depicts the host (104) as being separate from the storage device (102), in other embodiments, the host (104) may be integrated within the storage device (102) wholly or partially. Alternatively, the host (104) may be distributed, with the entirety of it spread across multiple remote entities, or alternatively, with some functionality in the storage device (102).

[0023] Those skilled in the art will understand that other exemplary embodiments may include more or fewer elements than those shown in FIG. 1, and that the disclosed processes may be implemented in different environments. For example, other exemplary embodiments may include a different number of hosts communicating with the storage device (102), or a number of storage devices (102) communicating with the host(s).

[0024] The host device (104) can store data in the storage device (102) and / or retrieve data from it. The host device (104) may include any computing device, such as, for example, a computer server, a network attached storage (NAS) unit, a desktop computer, a notebook (e.g., laptop) computer, a tablet computer, a mobile computing device such as a smartphone, a television, a camera, a display device, a digital media player, a video gaming console, a video streaming device, etc. The host device (104) may include at least one processor (101) and a host memory (103). At least one processor (101) may include any type of hardware capable of processing data, and may include a general-purpose processing unit (e.g., a central processing unit (CPU)), dedicated hardware (e.g., an application specific integrated circuit (ASIC)), a digital signal processor (DSP), configurable hardware (e.g., a field programmable gate array (FPGA)), or any other type of processing unit configured by software instructions, firmware, etc. The host memory (103) may be used by the host device (104) to store data or instructions processed by the host or data received from the storage device (102).In some examples, the host memory (103) may include non-volatile memory, such as magnetic memory devices, optical memory devices, holographic memory devices, flash memory devices (e.g., NAND or NOR), phase-change memory (PCM) devices, resistive random-access memory (ReRAM) devices, magnetoresistive random-access memory (MRAM) devices, ferroelectric random-access memory (F-RAM), and any other type of non-volatile memory device. In other examples, the host memory (103) may include volatile memory, such as random-access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM) (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, etc.). The host memory (103) may also include both non-volatile memory and volatile memory, whether integrated together or as separate units.

[0025] The host interface (106) is configured to interface the storage device (102) with the host (104) via a bus / network (108), and can be interfaced using a bus standard such as SATA (Serial Advanced Technology Attachment), PCIe (PCI express), SCSI (Small Computer System Interface), or SAS (Serial Attached SCSI), among other possible candidates, Ethernet or WiFi. Alternatively, the host interface (106) may be wireless and may interface the storage device (102) with the host (104) using, for example, cellular communication (e.g., 5G NR, 4G LTE, 3G, 2G, GSM / UMTS, CDMA One / CDMA2000, etc.), wireless distribution methods through access points (e.g., IEEE 802.11, WiFi, HiperLAN, etc.), infrared (IR), Bluetooth, Zigbee, or other Wireless Wide Area Network (WWAN), Wireless Local Area Network (WLAN), Wireless Personal Area Network (WPAN) technologies, or similar wide area, local area, and personal area technologies.

[0026] The storage device (102) includes memory. For example, in the exemplary embodiment of FIG. 1, the storage device (102) may include non-volatile memory (NVM) (110) for permanent storage of data received from the host (104). The NVM (110) may include, for example, flash integrated circuits, NAND memory (e.g., SLC memory, MLC memory, TLC memory, QLC memory, PLC memory, or any combination thereof), or NOR memory. The NVM (110) may include a plurality of memory locations (112) capable of storing system data for operating the storage device (102) or user data received from the host to be stored in the storage device (102). For example, the NVM n rows and m A crosspoint architecture may have a 2-D NAND array of memory locations (112) having columns, wherein m and nThe size is predefined according to the size of the NVM. In the exemplary embodiment of FIG. 1, each memory location (112) may be a die (114) comprising a plurality of planes each comprising a plurality of blocks of a plurality of cells (116). Alternatively, each memory location (112) may be a plane comprising a plurality of blocks of cells (116). The cells (116) may be, for example, single-level cells, multi-level cells, triple-level cells, quadruple-level cells, and / or quintuple-level cells. Other examples of memory locations (112) are possible; for example, each memory location may be a block or a group of blocks. Each memory location may include one or more blocks within a 3-D NAND array. Each memory location (112) may include one or more logical blocks mapped to one or more physical blocks. Alternatively, the memory and each memory location may be implemented in other ways known to those skilled in the art.

[0027] The storage device (102) also includes a volatile memory (118) which may include, for example, dynamic random access memory (DRAM) or static random access memory (SRAM). Data stored in the volatile memory (118) may include data read from the NVM (110) or data to be written to the NVM (110). In this regard, the volatile memory (118) may include a write buffer or a read buffer for temporarily storing data. Although FIG. 1 depicts the volatile memory (118) as being far from the controller (123) of the storage device (102), the volatile memory (118) may be integrated within the controller (123).

[0028] A memory (e.g., NVM (110)) is configured to store data (119) received from a host device (104). The data (119) may be stored in cells (116) of any of the memory locations (112). As an example, FIG. 1 illustrates that the data (119) is stored in different memory locations (112), but the data may be stored in the same memory location. In another example, the memory locations (112) may be different dies, and the data may be stored in one or more of the different dies.

[0029] Each piece of data (119) may be associated with a logical address. For example, the NVM (110) may store a logical-to-physical (L2P) mapping table (120) for the storage device (102) to associate each piece of data (119) with a logical address. The L2P mapping table (120) stores the mapping of specified logical addresses for data written from the host (104) to physical addresses within the NVM (110) representing the location(s) where each piece of data is stored. This mapping may be performed by the controller (123) of the storage device. The L2P mapping table may be a table or other data structure containing identifiers such as a logical block address (LBA) associated with each memory location (112) within the NVM where the data is stored. Although FIG. 1 illustrates a single L2P mapping table (120) stored in one of the memory locations (112) of the NVM to avoid making the concepts of FIG. 1 overly obscured, the L2P mapping table (120) may actually include multiple tables stored in one or more memory locations of the NVM.

[0030] FIG. 2 is a conceptual diagram (200) of an example of an L2P mapping table (205) illustrating the mapping of data (202) received from a host device to logical addresses and physical addresses within the NVM (110) of FIG. 1. While the data (202) may correspond to the data (119) of FIG. 1, the L2P mapping table (205) may correspond to the L2P mapping table (120) of FIG. 1. In one exemplary embodiment, the data (202) consists of one or more pages (204), e.g., page 1 through page 1 x It can be stored in, and here x is the total number of pages of data being written to the NVM (110). Each page (204) may be associated with a logical block address (LBA) (208), a physical address (210) associated with the data written to the NVM, and one or more entries (206) of an L2P mapping table (205) identifying the length (212) of the data. The LBA (208) may be a logical address specified in a write command for data received from a host device. The physical address (210) may represent the offset and block where the data associated with the LBA (208) is physically written. The length (212) may represent the size of the written data (e.g., 4 KB or some other size).

[0031] Referring again to FIG. 1, the volatile memory (118) also stores a cache (122) for the storage device (102). The cache (122) contains entries showing that the logical addresses specified for data requested by the host (104) are mapped to physical addresses within the NVM (110) representing the location(s) where the data is stored. This mapping can be performed by a controller (123). When the controller (123) receives a read or write command for data (119), the controller checks the cache (122) for the logical-to-physical mapping of each data. If no mapping exists (e.g., when it is the first request for data), the controller accesses the L2P mapping table (120) and stores the mapping in the cache (122). When the controller (123) executes a read command or a write command, the controller accesses a mapping from the cache and reads data from the NVM (110) at a specified physical address or writes data thereto. The cache may be stored in the form of a table or other data structure containing a logical address associated with each memory location (112) within the NVM where data is being read.

[0032] The NVM (110) includes sensing amplifiers (124) and data latches (126) connected to each memory location (112). For example, the memory location (112) may be a block containing cells (116) on a plurality of bit lines, and the NVM (110) may include sensing amplifiers (124) on each bit line. In addition, one or more data latches (126) may be connected to the bit lines and / or sensing amplifiers. The data latches may be, for example, shift registers. When data is read from the cells (116) of the memory location (112), the sensing amplifiers (124) sense the data by amplifying the voltages on the bit lines to a logic level (e.g., readable as '0' or '1'), and the sensed data is stored in the data latches (126). Subsequently, data is transferred from the data latches (126) to the controller (123), and then the data is stored in volatile memory (118) until it is transferred to the host device (104). When data is written to the cells (116) of the memory location (112), the controller (123) stores the programmed data in the data latches (126), and the data is subsequently transferred from the data latches (126) to the cells (116).

[0033] The storage device (102) includes a controller (123) which may include a circuit section such as one or more processors for executing instructions, a microcontroller, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), hard-wired logic, an analog circuit section, and / or a combination thereof.

[0034] The controller (123) is configured to receive data transmitted from one or more of the cells (116) of various memory locations (112) in response to a read command. For example, the controller (123) can read data (119) by activating the sensing amplifiers (124) to detect data from the cells (116) to the data latches (126), and the controller (123) can receive data from the data latches (126). The controller (123) is also configured to program data into one or more of the cells (116) in response to a write command. For example, the controller (123) can write data (119) by transmitting data to the data latches (126) to be programmed into the cells (116). The controller (123) is further configured to access an L2P mapping table (120) within the NVM (110) when reading data or writing to cells (116). For example, the controller (123) may receive logical-physical address mappings from the NVM (110) in response to read or write commands from the host device (104), identify physical addresses mapped to logical addresses identified in the commands (e.g., converting logical addresses to physical addresses), and access data located at the mapped physical addresses or store data in the cells (116) located therein.

[0035] The controller (123) and its components may be implemented as embedded software that performs the various functions of the controller described throughout this disclosure. Alternatively, software for implementing each of the aforementioned functions and components may be stored in the NVM (110), or in memory outside the storage device (102) or the host device (104), and may be accessed by the controller (123) for execution by one or more processors of the controller (123). Alternatively, the functions and components of the controller may be implemented as hardware within the controller (123) or may be implemented using a combination of the aforementioned hardware and software.

[0036] When operating, the host device (104) stores data in the storage device (102) by transmitting a write command to the storage device (102) specifying the length of the data to be written as well as one or more logical addresses (e.g., LBAs). The interface element (106) receives the write command, and the controller allocates a memory location (112) within the NVM (110) of the storage device (102) to store the data. The controller (123) stores an L2P mapping in the NVM (and cache (122)) that maps the logical address associated with the data to the physical address of the memory location (112) allocated for the data. The controller also stores the length of the L2P-mapped data. Subsequently, the controller (123) stores the data in the memory location (112) by transmitting the data to one or more data latches (126) connected to the allocated memory location, from which the data is programmed into the cells (116).

[0037] The host (104) can retrieve data from the storage device (102) by transmitting a read command that specifies the length of the data to be read as well as one or more logical addresses associated with the data to be retrieved from the storage device (102). The interface (106) receives the read command, and the controller (123) accesses the cache (122) or otherwise the L2P mapping within the NVM to convert the logical addresses specified in the read command into physical addresses representing the location of the data. Subsequently, the controller (123) reads the requested data specified by the physical addresses from the memory location (112) by using the sense amplifiers (124) to sense the data and storing them in the data latches (126) until the read data is returned to the host (104) through the host interface (106).

[0038] FIG. 3 illustrates an example of a NAND memory array (300) of cells (302). The cells (302) may correspond to the cells (116) within the NVM (110) of FIG. 1. A plurality of cells (302) are combined into word lines (304) and bit lines (306). For example, the memory array (300) is within a block of the die (114) of the NVM (110). n Word lines and m It may include bit lines, where n and m is predefined according to the size of the block. Each word line and bit line can be associated with row and column addresses, respectively, which the controller (123) can use to select specific word lines and bit lines (e.g., using row and column decoders). For example, word lines 0 to n Each can be associated with its own row address (e.g., word line 0 can correspond to word line address 0, word line 1 can correspond to word line address 1, etc.), and bit lines 0 to mEach can be associated with its own column address (e.g., bit line 0 can correspond to bit line address 0, bit line 1 can correspond to bit line address 1, etc.). Select gate source (SGS) cells (308) and select gate drain (SGD) cells (310) are coupled to memory cells (302) on each bit line (306). The SGS cells (308) and SGD cells (310) connect the memory cells (302) to the source line (312) (e.g., ground) and the bit lines (306), respectively. A string (314) may include a group of cells (302) combined to one bit line within a block (including SGS and SGD cells (308, 310)), while a page (316) may include a group of cells (302) combined to one word line within a block.

[0039] FIG. 4 illustrates an example of a NAND memory array (400) of blocks (402) comprising a plurality of strings (404). The blocks (402) may correspond to blocks of a die (114) within the NVM (110) of FIG. 1, and each string (404) may correspond to a string (314) of FIG. 3. As in the memory array (300) of FIG. 3, each string (404) may include a group of memory cells that are each coupled to a bit line (406) and individually coupled to their respective word lines (408). Similarly, each string may include an SGS cell (410) and an SGD cell (412) that connect the memory cells within each string (404) to a source line (414) and a bit line (406), respectively.

[0040] When the controller (123) reads data from or writes data to the page (316) of the cells (302) (i.e., on the word lines (304, 408)), the controller may transmit a command to apply a read voltage or a programming voltage to the selected word line and a pass-through voltage to the other word lines. Subsequently, the read or programmed state of the cell (e.g., logic '0' or logic '1' for the SLCs) may be determined based on the threshold voltage of the cells (302). For example, during an SLC read operation, if the threshold voltage of the cell (302) is smaller than the read voltage (i.e., current flows through the cell in response to the read voltage), the controller (123) can determine that the cell stores a logic '1', and if the threshold voltage of the cell (302) is larger than the read voltage (i.e., current does not flow through the cell in response to the read voltage), the controller (123) can determine that the cell stores a logic '0'. Similarly, during an SLC programming operation, the controller can store a logic '0' by transmitting a command to apply a programming voltage to a cell (302) on a word line (304, 408) until the cell reaches a threshold voltage, and during an erase operation, the controller can transmit a command to apply an erase voltage to a block (402) containing the cells (302) (e.g., a substrate of cells such as a p-well) until the cells are reduced back below the threshold voltage (back to a logic '1').

[0041] In the case of cells storing multiple bits (e.g., MLC, TLC, etc.), each word line (304, 408) may include multiple pages (316) of cells (302), and a controller may similarly transmit commands to apply a read or programming voltage to the word lines to determine the read or programmed state of the cells based on the threshold voltage of the cells. For example, in the case of TLCs, each word line (304, 408) may include three pages (316) including a lower page (LP), an intermediate page (MP), and an upper page (UP), each corresponding to different bits stored in the TLC. When programming the TLCs, the LP may be programmed first, followed by the MP and then the UP. For example, a programming voltage may be applied to the cell on the word line (304, 408) until the cell reaches a first intermediate threshold voltage corresponding to the least significant bit (LSB) of the cell. Next, LP can be read to determine a first intermediate threshold voltage, and then, a programming voltage can be applied to the cell on the word line until the cell reaches a second intermediate threshold voltage corresponding to the next bit of the cell (between the LSB and the most significant bit (MSB)). Finally, MP can be read to determine a second intermediate threshold voltage, and then, a programming voltage can be applied to the cell on the word line until the cell reaches a final threshold voltage corresponding to the MSB of the cell. Similarly, when reading the TLCs, the controller (123) can read LP to determine whether the LSB stores a logic 0 or 1 according to the threshold voltage of the cell, read MP to determine whether the next bit stores a logic 0 or 1 according to the threshold voltage of the cell, and read UP to determine whether the final bit stores a logic 0 or 1 according to the threshold voltage of the cell.

[0042] FIG. 5 illustrates an example of a voltage distribution chart (500) illustrating different NAND states for TLCs (e.g., 116, 302) storing 3 bits of data (e.g., from logic 000, 001, etc. to logic 111). The TLCs may include an erase state (502) corresponding to logic '111' and a plurality of program states (504) (e.g., A to G) corresponding to other logic values ​​'000 to 110'. The program states (504) may be separated by different threshold voltages (506). Initially, the cells (116, 302) may be in the erase state (502), for example, after the controller (123) erases the block (402) containing the cells. When the controller (123) programs the LPs, MPs, and UPs as described above, the voltages of the cells (116, 302) may be increased until threshold voltages (506) corresponding to the logic values ​​to be stored are satisfied, at which point the cells transition to their respective programmed states (504). FIG. 5 illustrates eight NAND states for TLCs, but the number of states may vary depending on the amount of data stored in each cell (116, 302). For example, SLCs may have two states (e.g., logic 0 and logic 1), MLCs may have four states (e.g., logic 00, 01, 10, 11), and QLCs may have sixteen states (e.g., erase and A through N).

[0043] FIG. 6 is a conceptual diagram (600) of an example of a garbage collection process in which data stored in pages (604) of a block (602) of SLC cells is relocated to pages (608) of a block (606) of MLC cells. The data may correspond to the data (119) of FIG. 1, the blocks (602, 606) may correspond to the blocks (402) of FIG. 4, and the SLC / MLC cells may correspond to the cells (116, 302) of FIG. 1 and FIG. 3. Each page (604, 608) contains data stored in multiple cells along the same row or word line (e.g., word line (304, 408)) of the NVM. Accordingly, each page (604) may contain data stored within a row of cells (116) of one block, while each page (608) may contain data stored within a row of cells (116) of another block. For simplicity of example, the example of FIG. 6 illustrates that each of the blocks (602, 606) contains only four pages (604, 608). However, it should be noted that each block may contain any number of pages.

[0044] In the example of FIG. 6, data represented by identifiers A, B, and C is stored in different pages (604) of block (602). Originally, data A, B, and C are stored in three pages of block (602) in response to write commands from a host device, and in this example, one of the pages is left free. When the storage device receives new or updated data, this data is stored in the free page (610). For example, updated data A' can be received from the host device and written to the free page (610). Since data cannot be overwritten in flash memory, invalid data A remains stored in block (602). As a result of new data and invalid data, block (602) can be quickly filled.

[0045] To free up space within the SLC block, the original and updated data within the block (602) can be transferred to the block (606). The invalid data remains in the old block. For example, in the example of FIG. 6, the original data B and C and the updated data A' are read from pages (604) of the block (602) and written to one or more pages (608) of the block (606). The invalid data A remains in the block (602). When the block (602) is subsequently erased, the invalid data is discarded, and the block (602) can be reused to store new data.

[0046] Referring again to FIG. 1, when there are no empty cells in an SLC block (e.g., block (602)) available for storing data, the controller (123) performs garbage collection (e.g., as described above in relation to FIG. 6) by transferring data from the cells (116) in the SLC block to the available cells in the MLC block (e.g., block (606)). Then, the controller (123) can erase the SLC block containing the cells (116). Once the cells (116) are free, the controller can continue to write data to the empty cells.

[0047] When cells (116) within an MLC block (e.g., block (606)) are read or written, or as the ambient temperature of the storage device (102) increases, the cells may exceed their reliable operating temperatures, thereby compromising data integrity. For example, as the temperature of the cells increases, the threshold voltages (506) of the cells that separate different program states (504) may change. When the temperature reaches a certain temperature, the threshold voltage may no longer sufficiently separate the different program states, potentially causing read errors and affecting data reliability.

[0048] When the storage device performs thermal throttling, the controller (123) generally reduces the rate of data written to the NAND cells (e.g., 606) as soon as the temperature of the die containing the NAND cells exceeds a thermal threshold. However, when performing thermal throttling, a hard transition occurs at the thermal throttling threshold due to the thermal throttling. For example, the controller (123) typically performs thermal throttling in which the variation in the data rate between transitions is relatively large. For example, the controller (123) may reduce the written data rate to a first set of parameters when the MLC block (e.g., 606) exceeds a first thermal throttling threshold at 80°C, and may further reduce the written data rate to a second set of parameters that is significantly different from the first set of fixed parameters when the MLC block exceeds a second thermal throttling threshold at 86°C. Due to these large differences between transitions, device performance and power consumption can vary significantly over time and affect the user experience.

[0049] Accordingly, to improve storage device performance and user experience, the present disclosure enables a controller (123) to selectively select a specific thermal configuration and dynamically adjust internal relaxation parameters, thereby progressively adjusting the internal relaxation parameters over time (or preemptively) to align the storage device with the temperature framework parameters specified by the host, so as to achieve optimized and deterministic performance within a thermal envelope that aims for minimum quality of delayed latency and service interruption. Typically, the controller (123) routes data to memory in response to a write command from the host device (104) by storing data directly in SLC blocks at a first data rate (e.g., full clock rate). As the number of free SLC blocks decreases, the controller (123) redistributes the data within the SLC blocks to MLC blocks. This redistribution may increase the temperature of the MLC blocks. When the temperature of the MLC block increases beyond a first thermal throttling threshold (e.g., TMT1, such as 80°C), the controller disables data relocation from the SLC block to the MLC block and restricts host data writing to the SLC block, thereby changing how data is routed to memory. However, the controller (123) performs thermal throttling this time by applying a selected thermal relaxation configuration associated with the thermal power state by scaling the power budget based on the temperature gradient to maintain thermal equilibrium within the thermal power state and maintain the maximum possible performance. This is in contrast to causing a large performance transition between thermal power state transitions when blocks of cells (e.g., 602, 606) exceed the corresponding thermal throttling threshold, thus allowing data to be written at a thermally throttled data rate that converts to a desired performance benchmark for various workloads within the adjusted power budget.

[0050] The controller (123) may initially start writing host data in response to write commands for blocks of cells (e.g., 606) at a first data rate (e.g., full clock rate). Then, the controller (123) continues to write host data in response to write commands for blocks of cells, which may increase the temperature of the blocks of cells. When the temperature of the blocks of cells increases beyond a first thermal throttling threshold (e.g., TMT1 such as 80°C), the controller (123) may transition to a first thermal power state and enable thermal throttling. For example, the controller (123) may reduce the rate of data written to the SLC blocks and MLC blocks to a smaller second data rate (e.g., 60% of the full clock rate), which is possible, for example, by applying a thermal relaxation configuration associated with the first thermal power state. The controller (123) can reduce the power budget parameter (by reducing the power consumption allocated to the storage device) based on the applied thermal relaxation configuration until thermal equilibrium is reached (e.g., the temperature gradient based on the measured temperature does not indicate a positive or negative rate of change of temperature). The controller (123) can further reduce power consumption through additional thermal power states, which in turn reduces the temperature.

[0051] Consequently, instead of employing thermal throttling that causes hard power state transitions (and consequently reduces performance) when the temperature of a block of cells exceeds different thermal throttling thresholds, the storage device of the present disclosure applies advanced thermal throttling that utilizes multiple thermal power states, each progressively reducing power based on a temperature gradient, along with adjustments to other thermal relaxation parameters such as dynamic voltage and frequency scaling, queue depth adjustment, and bus interconnect scaling. In this way, the storage device of the present disclosure provides an improved user experience, enables the satisfaction of performance benchmarks, and maintains data reliability through efficient NAND block utilization.

[0052] FIG. 7 illustrates an exemplary illustration (700) of thermal throttling in a storage device. In thermal throttling, the controller restricts access to the cells more and more as the temperature rises in order to cool the storage device. For example, cells may be contained in one or more dies, and the controller may disable parallel access for an increasing number of dies as the temperature exceeds various thermal thresholds. In the exemplary illustration (700), multiple thermal thresholds are configured for different levels of throttling, including a low (LO) thermal threshold (702), a medium (MED) thermal threshold (704), a high (HI) thermal threshold (706), and a thermal cutoff (TSD) thermal threshold (708). For example, in the case of QLC temperatures, the LO thermal threshold (702) may be 80° or a different degree, the MED thermal threshold (704) may be 86° or a different degree, the HI thermal threshold (706) may be 94° or a different degree, and the TSD thermal threshold (708) may be the maximum recording temperature, e.g., 95°. These thermal thresholds are merely examples, and any number of temperature thermal thresholds of varying degrees may be used. Furthermore, thermal thresholds may vary depending on the cell type. For example, in the case of TLC temperatures, thermal thresholds can all be higher, whereas in the case of PLC temperatures, thermal thresholds can all be lower.

[0053] The controller may perform different levels of throttling as the temperatures of the cells exceed various thermal thresholds to reduce the temperature more rapidly. For example, when reducing die parallelism, the controller may apply light throttling (712) (e.g., throttling one die) when the temperature exceeds the LO thermal threshold (702), apply heavy throttling (714) (e.g., throttling two dies) when the temperature exceeds the MED thermal threshold (704), apply extreme throttling (716) (e.g., throttling three dies) when the temperature exceeds the HI thermal threshold (706), and apply thermal cutoff (718) (e.g., blocking access to the dies) when the temperature exceeds the TSD thermal threshold (708). Other examples of throttling may be used; For example, instead of disabling parallel access to one, two, or three dies respectively, the storage device may disable parallel access to different numbers of dies, prevent reading or writing to different numbers of dies, regulate or restrict access to different numbers or types of memory locations on the same die, or perform other temperature reduction methods.

[0054] Accordingly, FIG. 7 illustrates various examples (722, 724, 726, 728) of different throttling level operations when the temperatures of the cells (730, 732, 734, 736) rise, for example, due to read or write operations or an increase in ambient temperature. Referring to the first example (722), the storage device initially operates in the full power region (710), for example, without throttling. When the temperature (730) exceeds the LO thermal threshold (702), the controller performs weak throttling (712). In this example, the weak throttling (712) is sufficient to gradually lower the temperature, and throttling continues until the temperature is reduced below the LO thermal threshold (702). Subsequently, the storage device disables throttling and resumes maximum power operation.

[0055] Referring to the second example (724), the storage device initially operates without throttling in the full output region (710). However, unlike the first example, when the temperature (732) exceeds the LO thermal threshold (702), weak throttling (712) is insufficient to reduce the temperature, and the temperature (732) continues to increase. When the temperature exceeds the MED thermal threshold (704), the controller performs strong throttling (714). In this example, strong throttling (714) is sufficient to gradually lower the temperature, and throttling continues until the temperature is reduced below the MED thermal threshold (704). At that point, the controller switches to weak throttling (712), which continues until the temperature is reduced below the LO thermal threshold (702). Subsequently, the storage device disables throttling and resumes maximum power operation.

[0056] Referring to the third example (726), the storage device initially operates without throttling in the full output region (710). However, unlike the first and second examples, when the temperature (734) exceeds the LO thermal threshold (702) and the MED thermal thresholds (704), weak throttling (712) and strong throttling (714) are insufficient to reduce the temperature, so the temperature (734) continues to increase. When the temperature exceeds the HI thermal threshold (706), the controller performs extreme throttling (716). In this example, extreme throttling (716) is sufficient to gradually lower the temperature, and throttling continues until the temperature is reduced below the HI thermal threshold (706). At that point, the controller switches to strong throttling (714), which continues until the temperature is reduced below the MED thermal threshold (704). At that point, the controller switches to weak throttling (712), which continues until the temperature drops below the LO thermal threshold (702). Subsequently, the storage device disables throttling and resumes maximum power operation.

[0057] Referring to the fourth example (728), the storage device initially operates without throttling in the full output region (710). However, unlike the first and second examples, when the temperature (736) exceeds the LO thermal threshold (702) and the MED thermal thresholds (704), weak throttling (712) and strong throttling (714) are insufficient to reduce the temperature, so the temperature (736) continues to increase. When the temperature exceeds the HI thermal threshold (706), the controller performs extreme throttling (716). In this example, extreme throttling (716) is insufficient to gradually reduce the temperature, so the temperature continues to increase until it reaches the TSD thermal threshold (708). At this point, the controller performs a thermal cutoff (718) to block access to the cells and / or storage device, for example, until the temperature is reduced back to a normal level.

[0058] When a storage device performs thermal throttling, the storage device typically reduces the rate of data written to the NAND cells as soon as the temperature of the die containing the NAND cells exceeds a thermal threshold. Thermal throttling, such as that described in relation to Fig. 7, can lower the temperature of the storage device but can also degrade system performance. However, when performing thermal throttling, a hard transition occurs at the thermal throttling threshold due to the thermal throttling. For example, the storage device typically performs thermal throttling with relatively large fluctuations in the data rate between transitions. For instance, the storage device may reduce the written data rate to a first set of parameters when the die exceeds a first thermal throttling threshold at 80°C, and further reduce the written data rate from a first set of fixed parameters to a second set of significantly different parameters when the die exceeds a second thermal throttling threshold at 86°C. Due to such large differences between transitions, device performance and power consumption can vary significantly over time and may affect the user experience. Therefore, device performance and user satisfaction may be degraded.

[0059] To improve device performance, the controller (123) may selectively select a specific thermal configuration and dynamically adjust internal relaxation parameters, as described below with respect to FIGS. 8 through 17, and gradually adjust the internal relaxation parameters over time (or preemptively) to align the storage device with the host-specified temperature framework parameters, thereby achieving optimized and deterministic performance within the thermal envelope that aims for the minimum quality of delayed latency and service interruption. For example, the controller (123) may perform thermal throttling by applying a selected thermal relaxation configuration associated with the thermal power state by scaling the power budget based on the temperature gradient to maintain thermal equilibrium within the thermal power state and maintain the maximum possible performance. This allows data to be written at a thermally throttled data rate that translates to a desired performance benchmark for various workloads within the adjusted power budget, in contrast to when a large performance transition occurs between thermal power state transitions when the storage device exceeds the corresponding thermal throttling threshold.

[0060] The controller (123) may initially start writing host data in response to write commands for blocks of cells at a first data rate (e.g., full clock rate). Then, the controller (123) continues writing host data in response to write commands for blocks of cells, which may increase the temperature of the blocks of cells. When the temperature of the blocks of cells increases beyond a first thermal throttling threshold (e.g., TMT1 such as 80°C), the controller (123) may transition to a first thermal power state and enable thermal throttling. For example, the controller (123) may reduce the rate of data written to the SLC blocks and MLC blocks to a smaller second data rate (e.g., 60% of the full clock rate), which is possible, for example, by applying a thermal relaxation configuration associated with the first thermal power state. The controller (123) can reduce the power budget parameter (by reducing the power consumption allocated to the storage device) based on the applied thermal relaxation configuration until thermal equilibrium is reached (e.g., the temperature gradient based on the measured temperature does not indicate a positive or negative rate of change of temperature).

[0061] Consequently, instead of employing thermal throttling that causes hard power state transitions (and consequently reduces performance) when the temperature of the storage device exceeds different thermal throttling thresholds, the storage device of the present disclosure applies advanced thermal throttling that utilizes multiple thermal power states, each progressively reducing power based on a temperature gradient, along with other thermal mitigation parameters such as dynamic voltage and frequency scaling, queue depth adjustment, and bus interconnect scaling. In this way, the storage device of the present disclosure provides an improved user experience, enables the satisfaction of performance benchmarks, and maintains data reliability through efficient NAND block utilization.

[0062] FIG. 8 illustrates an exemplary illustration (800) of a controller (802) of a storage device that uses advanced thermal throttling having multiple thermal power states within the storage device of FIG. 1 to record data received from a host device (804) in one or more blocks (806, 808, 810) at different data rates corresponding to different temperatures of the blocks. The blocks (808) may include cells that store more bits than the cells of the blocks (806). For example, the blocks (806) may include pages of SLCs, while the blocks (808) may include pages of QMLCs (e.g., 2-bit cells, TLCs, QLCs, PLCs, etc.). Referring to FIG. 1, the controller (802) may correspond to the controller (123), the blocks (806) of SLCs may correspond to the blocks (602) containing cells (116), and the blocks (808) of MLCs may correspond to the blocks (606) containing cells (116). The blocks (806) and blocks (808, 810) may be stored in separate partitions of the die (812) (e.g., the die (114) of FIG. 1). For example, the blocks (806) may be stored in the SLC partition of the die (812), while the blocks (808, 810) may be stored in the MLC partition of the die (812).

[0063] The controller (802) can communicate with a temperature sensor (814) coupled to the die (812). The controller (802) can determine the temperature (816) of the cells within the blocks (806, 808, 810) based on periodically monitored readings from the temperature sensor (814). Once the temperature is determined, the controller (802) can apply advanced thermal throttling to the die (812) based on the different thermal power states of the blocks (806, 808). For example, when the temperature (816) is lower than a first thermal threshold (TMT1 (822)), the controller (802) can initially write first data (840) (e.g., data responding to a single write command) to the blocks (806, 808) at a first data rate (842). Subsequently, when the temperature (816) meets the first thermal threshold (TMT1 (822)), the controller (802) may record second data (844) (e.g., data responding to another record command) to the blocks (806, 808) at a second data rate (846) (a throttled rate below the first data rate (842)). When the temperature (816) meets the second thermal threshold (TMT2 (824)), the controller (802) may record third data (848) (e.g., data responding to another record command) to the blocks (806, 808) at a third data rate (850) (a throttled rate below the second data rate (846)). The controller (802) can write fourth data (852) (e.g., data responding to another write command) to blocks (806, 808) at a third data transfer rate (854) (a throttled rate less than the third data rate (850)) when the temperature (816) meets the third column threshold (TMT3 (826)). The controller (802) can write fifth data (856) (e.g., data responding to another write command) to blocks (806, 808) at a fifth data rate (858) (a throttled rate less than the fourth data rate (854)) when the temperature (816) meets the fourth column threshold (TMT4 (828)).Additionally, the controller may perform a thermal cutoff or disable all data recording when the temperature (816) meets a thermal cutoff temperature (TMTSD 830) higher than TMT4. For example, TMT1 may be 80°C, TMT2 may be 86°C, TMT3 may be 92°C, TMT4 may be 94°C, and TMTSD may be 95°C. Alternatively, TMT1, TMT2, TMT3, TMT4, and TMTSD may differ in other examples. Thermal throttling (e.g., Before a thermal interruption (e.g., in TMT1) or a thermal interruption (e.g., in TMTSD) occurs, the controller may send a message (831) notifying the host device (804) of these events.

[0064] To release block (806) before the temperature (816) reaches TMT1 (822), the controller (802) can transfer data from block (806) to block (808) without thermal throttling dependent on the temperature (816). For example, the controller can perform data redistribution at a first data transfer rate (842) when the temperature is below TMT1 (822) (e.g., below 80°C). When the controller (802) determines that the temperature (816) later meets TMT1 (822) (e.g., 80°C), the controller can perform thermal throttling by applying a thermal relaxation configuration for the first thermal power state, and consequently, write subsequent data (e.g., second data (844)) to blocks (808) at a second data rate (846). For example, the controller may reduce power consumption in the first thermal power state by reducing the power budget parameter value until the temperature gradient indicates that the temperature (816) has reached thermal equilibrium. In another example, the controller may reduce power consumption by scaling down the clock frequency, reducing the voltage of the corresponding voltage domain, reducing the number of bus interconnect lanes for the blocks (808), and / or reducing the host interface queue depth. When the temperature (816) later decreases below TMT1 (822) in response to the throttled rate, the controller may re-enable data relocation from the blocks (806) to the blocks (808), and the controller may rewrite data at the first data rate (842) to the blocks (806, 808) without thermal throttling. Otherwise, if the temperature (816) increases to TMT2 (824) despite the throttled rate, the controller may perform thermal throttling by applying a thermal relaxation configuration for the second thermal power state, and consequently subsequent data at the third data rate (850) (e.g. ,The third data (848)) can be written to the block (808). For example, the controller can reduce power consumption in the second thermal power state by reducing the power budget parameter value until the temperature gradient indicates that the temperature (816) has reached thermal equilibrium. In another example, the controller can reduce power consumption by scaling down the clock frequency, reducing the voltage of the corresponding voltage domain, reducing the number of bus interconnect lanes for the blocks (808), and / or reducing the host interface queue depth.

[0065] If the temperature (816) decreases below TMT2 (822) in response to a later throttled rate, the controller applies a thermal relaxation configuration for the first thermal power state and consequently writes subsequent data at the second data rate (846) to the blocks (808). Otherwise, if the temperature (816) increases to TMT3 (826) despite the throttled rate, the controller may perform thermal throttling by applying a thermal relaxation configuration for the third thermal power state and consequently write subsequent data at the fourth data rate (854) (e.g. , The fourth data (852)) can be written to block (808). For example, the controller can reduce power consumption in the third thermal power state by scaling down the clock frequency, reducing the voltage of the corresponding voltage domain, and / or reducing the host interface queue depth.

[0066] If the temperature (816) decreases below TMT3 (824) in response to a later throttled rate, the controller applies a thermal relaxation configuration for the second thermal power state and consequently writes subsequent data at the third data transfer rate (850) to the blocks (808). Otherwise, if the temperature (816) increases to TMT4 (828) despite the throttled rate, the controller may perform thermal throttling by applying a thermal relaxation configuration for the fourth thermal power state and consequently write subsequent data at the fourth data rate (858) (e.g. , The fifth data (856)) can be written to block (808). For example, the controller can reduce power consumption in the fourth thermal power state by scaling down the clock frequency, reducing the voltage of the corresponding voltage domain, and / or reducing the operation duty cycle.

[0067] If the temperature (816) subsequently decreases below TMT4 (828) in response to the throttled rate, the controller applies a thermal relaxation configuration for the third thermal power state and consequently writes subsequent data at the fourth data transfer rate (854) to the blocks (808). Otherwise, if the temperature (816) increases to TMTSD (830) despite the throttled rate, the controller may initiate a thermal shutdown and disable further data writing to the blocks (808) until the temperature decreases again below TMT4.

[0068] FIG. 9 is a flowchart (900) illustrating an exemplary embodiment of a method for advanced thermal throttling utilizing multiple thermal power states. For example, the method may be performed in a storage device (102) such as that illustrated in FIG. 1. Each step in the flowchart may be controlled using a controller (e.g., controller (123, 802)) as described below, or by some other suitable means.

[0069] As indicated by block (902), the controller can periodically monitor the NAND temperature. For example, referring to FIGS. 1 and FIGS. 8, the controller (123, 802) can obtain the temperature (816) of blocks (402, 806, 808) within the die (114, 812) in the NVM (110) from the temperature sensor (814) at regular intervals, for example, every minute or other amount of time.

[0070] As indicated by block (904), the controller can determine whether the acquired temperature is greater than the first thermal threshold. For example, referring to FIGS. 1 and FIGS. 8, the controller (123, 802) can determine whether the temperature (816) is greater than TMT1 (822).

[0071] If the temperature (816) is greater than TMT1 (822), the controller can reduce power consumption based on the temperature gradient, as indicated by block (906). For example, referring to FIGS. 1 and FIGS. 8, the controller (123, 802) can enable thermal throttling (906) in a first thermal power state (e.g., TPS1). If the temperature (816) is not greater than TMT1, the controller can return to block (902) and continue to periodically monitor the NAND temperature.

[0072] Furthermore, as indicated by block (908), the controller may apply a thermal relaxation configuration for a first thermal power state (e.g., TPS1). For example, referring to FIGS. 1 and FIGS. 8, the controller (123, 802) may reduce power consumption in the first thermal power state with a thermal relaxation configuration by reducing the power budget parameter value until the temperature gradient indicates that the temperature (816) has reached thermal equilibrium. In another example, the controller may also reduce power consumption with a thermal relaxation configuration by scaling down the clock frequency by a predetermined percentage (or scaling factor), by reducing the voltage in the corresponding voltage domain, and / or by reducing a number of bus interconnect lanes for the blocks (808).

[0073] As indicated by block (910), the controller can determine whether the acquired temperature is greater than the second thermal threshold. For example, referring to FIGS. 1 and FIGS. 8, the controller (123, 802) can determine whether the temperature (816) is greater than TMT2 (824).

[0074] If the temperature (816) increases to TMT2 (824) despite the throttled rate, the controller may perform thermal throttling by applying a thermal relaxation configuration for a second thermal power state (e.g., TPS2), as indicated by block (912). For example, referring to FIGS. 1 and FIGS. 8, the controller (123, 802) may reduce power consumption in the second thermal power state by reducing the power budget parameter value until the temperature gradient indicates that the temperature (816) has reached thermal equilibrium. In another example, the controller may also reduce power consumption in the thermal relaxation configuration by scaling down the clock frequency by a predetermined percentage (or scaling factor), by reducing the voltage of the corresponding voltage domain by a predetermined percentage (or scaling factor), and / or by reducing a number of bus interconnect lanes for the blocks (808).

[0075] If the temperature (816) does not increase to TMT2 (822) in response to the throttled rate, the controller can return to block (904) to check whether the temperature meets the first thermal threshold (TMT1). In some embodiments, the controller can also continue to monitor the NAND temperature as described above in block (902). Then, the controller can apply a thermal relaxation configuration for the first thermal power state to also gradually reduce the temperature while maintaining the performance benchmark.

[0076] As indicated by block (914), the controller can determine whether the acquired temperature is greater than the third thermal threshold. For example, referring to FIGS. 1 and FIGS. 8, the controller (123, 802) can determine whether the temperature (816) is greater than TMT3 (826).

[0077] If the temperature (816) increases to TMT3 (826) despite the throttled rate, the controller may perform thermal throttling by applying a thermal relaxation configuration for a third thermal power state (e.g., TPS3), as indicated by block (916). For example, referring to FIGS. 1 and FIGS. 8, the controller (123, 802) may reduce power consumption in the third thermal power state by reducing the power budget parameter value to the minimum allowable power consumption. In another example, the controller may also reduce power consumption in the thermal relaxation configuration by scaling down the clock frequency by a predetermined percentage (or scaling factor), reducing the voltage of the corresponding voltage domain by a predetermined percentage (or scaling factor), reducing a number of bus interconnect lanes for the blocks (808), and / or reducing the host interconnect queue depth.

[0078] If the temperature (816) does not increase to TMT3 (826) in response to the throttled rate, the controller can return to block (910) to check whether the temperature meets the second thermal threshold (TMT2). ​​In some embodiments, the controller can also continue to monitor the NAND temperature as described above in block (902). Then, the controller can apply a thermal relaxation configuration for the second thermal power state to also gradually reduce the temperature while maintaining the performance benchmark.

[0079] As indicated by block (918), the controller can determine whether the acquired temperature is greater than the fourth thermal threshold. For example, referring to FIGS. 1 and FIGS. 8, the controller (123, 802) can determine whether the temperature (816) is greater than TMT4 (828).

[0080] If the temperature (816) increases to TMT4 (828) despite the throttled rate, as indicated by block (920), the controller may perform thermal throttling by applying a thermal relaxation configuration for the fourth thermal power state (e.g., TPS4). For example, referring to FIGS. 1 and FIGS. 8, the controller (123, 802) may reduce power consumption in the fourth thermal power state by reducing the power budget parameter value to the minimum allowable power consumption. In another example, the controller may also reduce power consumption in the thermal relaxation configuration by scaling down the clock frequency by a predetermined percentage (or scaling factor), reducing the voltage of the corresponding voltage domain by a predetermined percentage (or scaling factor), reducing a number of bus interconnect lanes for the blocks (808), and / or reducing the operation duty cycle.

[0081] If the temperature (816) does not increase to TMT4 (828) in response to the throttled rate, the controller can return to block (914) to check whether the temperature meets the third thermal threshold (TMT3). In some embodiments, the controller can also continue to monitor the NAND temperature as described above in block (902). Then, the controller can apply a thermal relaxation configuration for the third thermal power state to also gradually reduce the temperature while maintaining the performance benchmark.

[0082] As indicated by block (918), the controller can determine whether the acquired temperature is greater than the fourth thermal threshold. For example, referring to FIGS. 1 and FIGS. 8, the controller (123, 802) can determine whether the temperature (816) is greater than TMT4 (828).

[0083] If the temperature (816) increases to TMTSD (830) despite the throttled rate, as indicated by block (920), the controller may initiate a thermal cutoff and disable further data writing to the NAND memory until the temperature decreases back below TMT4. If the temperature (816) does not increase to TMTSD (830) in response to the throttled rate, the controller may return to block (918) to check whether the temperature meets the third thermal threshold (TMT4). In some embodiments, the controller may also continue to monitor the NAND temperature as described above in block (902). If so, the controller may apply a thermal relaxation configuration for the fourth thermal power state to also gradually reduce the temperature while maintaining the performance benchmark.

[0084] FIG. 10 is a conceptual diagram illustrating a controller (1010) for advanced thermal throttling using multiple thermal power states in the storage device of FIG. 1. The controller (1010) is communicably coupled to temperature sensors (1002) and a maximum filter module (1004) and to sensors (1006 and 1008). The controller (1010) is also communicably coupled to a host-controlled thermal management (HCTM) module (1050) and a non-volatile memory host controller module (1060). The controller (1010) includes temperature comparators (1011 to 1015) and a thermal power state driver (1020). The controller (1010) is also communicably coupled to a history database (1030) and a prediction model (1040). In some embodiments, the history database (1030) may store historical information related to temperature measurements of a storage device, including performance benchmarks associated with any historical adjustment of temperature and / or power. In some embodiments, the prediction model (1040) may be a neural network trained to infer the temperature of a storage device based on real-time information from the storage device and / or historical information stored in the history database (1030).

[0085] The thermal power state driver (1020) includes a temperature gradient module (1022), a power budget scaling module (1024), a dynamic voltage frequency scaling module (1026), and a host interface management (HIM) queue depth (QD) control module (1028). The HCTM module (1050) can be communicateably coupled with temperature comparators (1013 and 1014). The temperature sensor (1006) can be communicateably coupled with temperature comparators (1015) and temperature comparator (1064). The sensor (1008) can be communicateably connected with the thermal power state driver (1020). The maximum filter module (1004) can be communicateably coupled with temperature comparators (1011 to 1014), the thermal power state driver (1020), and the temperature comparator (1062). Temperature comparators (1062, 1064) can be coupled to communicate with a thermal interruption (TSD) driver (1068). A history database (1030) and a prediction module (1040) can be connected to communicate with a thermal power status driver (1020).

[0086] FIG. 11 is a flowchart illustrating an exemplary process for advanced thermal throttling using multiple thermal power states in the storage device of FIG. 1. For example, the method may be performed in a storage device (102) such as that illustrated in FIG. 1. Each of the steps in the flowchart may be controlled using a controller as described below (e.g., controller (123, 802, 1010)) or by some other suitable means.

[0087] As indicated by block (1102), the controller (1010) can periodically monitor the NAND temperature. For example, referring to FIGS. 1 and FIGS. 10, the controller (123, 1010) can acquire the temperature of blocks (402) within the die (114, 812) within the NVM (110) from temperature sensors (1002) and / or sensors (1006, 1008) at regular intervals, for example, every minute or other amount of time. In some embodiments, the controller (1010) can acquire the NAND temperature of the NVM (110) at a first sampling rate based on the fact that the NAND temperature of the NVM (110) does not exceed a first thermal threshold (e.g., TMT1 set to 80°C). In other embodiments, the controller (1010) may acquire the NAND temperature of the NVM (110) at a second sampling rate greater than the first sampling rate based on the fact that the NAND temperature of the NVM (110) exceeds a first thermal threshold (e.g., TMT1). For example, after the temperature exceeds TMT1, the temperature sampling rate may be increased fourfold.

[0088] In some embodiments, the maximum filter module (1004) may receive an array of temperature measurements from the temperature sensors (1002). In one or more embodiments, the maximum filter module (1004) may filter the temperature measurements so that the sample with the highest measured temperature is filtered and provided to the controller (1010) to be processed by the temperature comparators (1011 to 1014). In one or more other embodiments, the maximum filter module (1004) may filter the samples with the highest temperature measured for each of the temperature sensors (1002) to be processed by the temperature comparators (101 to 1014).

[0089] As indicated by block (1104), the controller may determine that the temperature of the memory satisfies a plurality of thermal thresholds. For example, referring to FIGS. 1 and FIGS. 10, the controller (1010) may compare the NAND temperature of the NVM (110) with the temperature comparator (1014) to determine whether the temperature satisfies or exceeds TMT1. As another example, referring to FIGS. 1 and FIGS. 10, the controller (1010) may compare the NAND temperature of the NVM (110) with the temperature comparator (1013) to determine whether the temperature satisfies or exceeds TMT2. In yet another example, referring to FIGS. 1 and FIGS. 10, the controller (1010) may compare the NAND temperature of the NVM (110) with the temperature comparator (1012) to determine whether the temperature satisfies or exceeds TMT3. In yet another example, referring to FIGS. 1 and FIGS. 10, the controller (1010) The NAND temperature of the NVM (110) can be compared with the temperature comparator (1011) to determine whether the temperature satisfies or exceeds TMT4. In some embodiments, the controller (1010) can compare the temperature obtained by the temperature sensor (1006) with the temperature comparator (1015) to determine whether the temperature satisfies or exceeds a specific thermal threshold for the application-specific integrated circuit (ASIC) in the storage device of FIG. 1. In another example, referring to FIG. 1 and FIG. 10, the controller (1010) can compare the NAND temperature of the NVM (110) with the temperature comparator (1062) to determine whether the temperature satisfies or exceeds TMTSD. In other embodiments, the controller (1010) can compare the temperature obtained by the temperature sensor (1006) with the temperature comparator (1064) to determine whether the temperature satisfies or exceeds a specific thermal threshold for the ASIC in the storage device of FIG. 1.Based on the comparator results of the temperature comparators (1062 and / or 1064), the TSD driver (1068) may be triggered to issue a thermal cutoff of the NVM (110).

[0090] As indicated by block (1106), the controller may transition to a plurality of thermopower states when the temperature satisfies a thermal threshold. For example, referring to FIG. 10, the controller (1010) may follow a state machine algorithm that controls the transition between thermopower states. Results from one or more of the temperature comparators (1011 to 1014) may be supplied as inputs to the state machine. For example, referring to FIG. 10, the controller (1010) may transition to a first thermopower state based on a temperature comparator (1014) indicating that the NAND temperature satisfies or exceeds TMT1. As another example, referring to FIG. 10, the controller (1010) may transition to a second thermopower state based on a temperature comparator (1013) indicating that the NAND temperature satisfies or exceeds TMT2. In yet another example, referring to FIG. 10, the controller (1010) may transition to a second thermopower state when the NAND temperature satisfies or exceeds TMT3 A transition to a third thermoelectric power state can be made based on a temperature comparator (1012) indicating an excess. As another example, referring to FIG. 10, the controller (1010) can transition to a fourth thermoelectric power state based on a temperature comparator (1011), which indicates that the NAND temperature meets or exceeds TMT4.

[0091] As indicated by block (1108), the controller may apply a thermal relaxation configuration associated with the thermal power state. In applying the thermal relaxation configuration, the controller may adjust one or more thermal relaxation parameters associated with the thermal power state. For example, referring to FIGS. 1 and FIGS. 10, the controller (1010) may apply an optional thermal relaxation configuration that gradually reduces power consumption to proportionally reduce the temperature within the NVM (110) while maintaining performance benchmarks for the storage device.

[0092] In some embodiments of adjusting one or more thermal relaxation parameters, the controller may adjust the power budget parameter based on a temperature gradient related to temperature. In some embodiments, the power budget parameter represents a power consumption allocation corresponding to the maximum performance achievable by one or more storage operations of a storage device operating in a thermal power state. For example, referring to FIG. 10, the controller (1010) may adjust the power budget parameter using a power budget scaling module (1024) based on a temperature gradient value provided by a temperature gradient module (1022). In some embodiments, the temperature gradient module (1022) may obtain temperature measurements from temperature sensors (1002) to determine the rate of change of temperature along with the direction of the temperature change (e.g., a positive ratio indicating an increase in rate, a positive value indicating a decrease in rate, or a neutral value indicating no change).

[0093] In some embodiments of adjusting the power budget parameter, the controller may decrease the value of the power budget parameter based on a temperature gradient indicating a positive rate of change in temperature. In some embodiments, the value of the power budget parameter is decreased until the temperature gradient indicates thermal equilibrium (e.g., a neutral value indicating no change in temperature). In other embodiments of adjusting the power budget parameter, the controller may increase the value of the power budget parameter based on a temperature gradient indicating a negative rate of change in temperature. In some embodiments, the value of the power budget parameter is increased until the temperature gradient indicates thermal equilibrium. In this regard, if the temperature gradient indicates no rate of change in either direction, the power budget parameter is not adjusted.

[0094] In other embodiments of adjusting one or more thermal relaxation parameters, the controller may adjust a clock frequency parameter associated with one or more clock domains of the storage device to a value corresponding to a predetermined clock frequency associated with a thermal power state. For example, referring to FIG. 10, the controller (1010) may adjust the clock frequency parameters using a dynamic voltage frequency scaling module (1026). For example, in the case of TPS1, the clock frequency parameter is adjusted from the full clock rate to 60% of the full clock rate. As another example, in the case of TPS2, the clock frequency parameter is adjusted from the full clock rate to 40% of the full clock rate. As yet another example, in the case of TPS3 and / or TPS4, the clock frequency parameter is adjusted from the full clock rate to 10% of the full clock rate.

[0095] In other embodiments of adjusting one or more thermal relaxation parameters, the controller may adjust a voltage parameter associated with one or more voltage domains of the storage device to a value corresponding to a predetermined voltage associated with a thermal power state. For example, referring to FIG. 10, the controller (1010) may adjust the voltage parameter using a dynamic voltage frequency scaling module (1026). For example, for one of the thermal power states (e.g., TPS1 to TPS4), the voltage parameter is adjusted from the total voltage for a specific voltage domain (e.g., core voltage) to 75% of the total voltage.

[0096] In other aspects of adjusting one or more thermal relaxation parameters, the controller may adjust bus interface parameters related to the interconnection between the memory and the controller to a first value corresponding to a predetermined number of interconnection lanes associated with the thermal power state. For example, referring to FIG. 10, the controller (1010) may adjust the bus interface parameters using a non-volatile memory host controller module (1060). For example, for some later thermal power states (e.g., TPS2 to TPS4), the bus interface parameters are proportionally downscaled from the total number of lanes available for bandwidth.

[0097] In other embodiments of adjusting one or more thermal relaxation parameters, the controller may adjust a queue depth parameter associated with the host interface of the storage device to a value corresponding to a predetermined queue depth associated with the thermal power state. For example, referring to FIG. 10, the controller (1010) may adjust the queue depth parameter using the HIM QD control module (1028). For example, for some thermal power states (e.g., TPS3 to TPS4), the queue depth parameter is adjusted from a total queue depth of 256 to a reduced queue depth of 8.

[0098] As indicated by block (1110), the controller can determine whether the temperature of the memory in the thermal power state has reached thermal equilibrium based on the thermal relaxation configuration. For example, referring to FIGS. 1 and FIGS. 10, the controller (1010) can determine that the NAND temperature change rate of the NVM (110) has slowed down to a point where the change rate indicated by the temperature gradient is approximately 0 (or neutral). In this regard, the controller (1010) may refrain from enabling any thermal throttling through the thermal power state driver (1020) and may resume any storage device operation with the NVM (110) until the temperature gradient indicates the temperature change rate.

[0099] FIG. 12 illustrates an exemplary illustration (1200) of advanced thermal throttling in a storage device. In thermal throttling, the controller restricts access to the cells more and more as the temperature rises in order to cool the storage device. For example, cells may be contained in one or more dies, and a controller may disable parallel access for an increasing number of dies as the temperature exceeds various thermal thresholds. In the exemplary illustration (1200), multiple thermal thresholds are configured for different levels of throttling, including a low (LO) thermal threshold (1202), a medium (MED) thermal threshold (1204), a high (HI) thermal threshold (1206), an extra high (XTRA HI) thermal threshold (1208), and a thermal cutoff (TSD) thermal threshold (1210). For example, in the case of QLC temperatures, the LO thermal threshold (1202) may be 80° or a different degree, the MED thermal threshold (1204) may be 86° or a different degree, the HI thermal threshold (1206) may be 92° or a different degree, the XTRA HI thermal threshold (1208) may be 94° or a different degree, and the TSD thermal threshold (1208) may be the maximum recording temperature, e.g., 95° or a different degree. These thermal thresholds are merely examples, and any number of temperature thermal thresholds of varying degrees may be used. Furthermore, the thermal thresholds may vary depending on the cell type. For example, in the case of TLC temperatures, the thermal thresholds may all be higher, whereas in the case of PLC temperatures, the thermal thresholds may all be lower.

[0100] The controller can perform different levels of throttling as the temperature of the cells exceeds various thermal thresholds to reduce the temperature more rapidly. For example, when reducing die parallelism, the controller may apply weak throttling (1214) (e.g., throttling one die) when the temperature exceeds the LO thermal threshold (1202), strong throttling (1216) (e.g., throttling two dies) when the temperature exceeds the MED thermal threshold (1204), apply first-tier extreme throttling (1218), throttle three dies when the temperature exceeds the HI thermal threshold (1206), apply second-tier extreme throttling (1220) when the temperature exceeds the XTRA HI thermal threshold (1208), and apply thermal cutoff (1222) (e.g., blocking access to the dies) when the temperature exceeds the TSD thermal threshold (1210). Other examples of throttling may be used; For example, instead of disabling parallel access to one, two, or three dies respectively, the storage device may disable parallel access to different numbers of dies, prevent reading or writing to different numbers of dies, regulate or restrict access to different numbers or types of memory locations on the same die, or perform other temperature reduction methods.

[0101] Accordingly, FIG. 12 illustrates various examples (1224, 1226, 1228, 1230, 1232) of different throttling level operations when the temperatures of the cells (1234, 1236, 1238, 1240, 1242) rise, for example, due to read or write operations or an increase in ambient temperature. Referring to the first example (1224), the storage device initially operates in the full output region (1212), for example, without throttling. When the temperature (1234) exceeds the LO thermal threshold (1202), the controller performs weak throttling (1214). In this example, the weak throttling (1214) is sufficient to gradually lower the temperature, and throttling continues until the temperature is reduced below the LO thermal threshold (1202). Next, the storage device disables throttling and resumes maximum power operation.

[0102] Referring to the second example (1226), the storage device initially operates without throttling in the full output region (1212). However, unlike the first example, when the temperature (1236) exceeds the LO thermal threshold (1202), weak throttling (1214) is insufficient to reduce the temperature, and the temperature (1236) continues to increase. When the temperature exceeds the MED thermal threshold (1204), the controller performs strong throttling (1216). In this example, strong throttling (1216) is sufficient to gradually lower the temperature, and throttling continues until the temperature is reduced below the MED thermal threshold (1204). At that point, the controller switches to weak throttling (1214), which continues until the temperature is reduced below the LO thermal threshold (1202). Subsequently, the storage device disables throttling and resumes maximum power operation.

[0103] Referring to the third example (1228), the storage device initially operates without throttling in the full output region (1212). However, unlike the first and second examples, when the temperature (1238) exceeds the LO thermal threshold (1202) and the MED thermal thresholds (1204), weak throttling (1214) and strong throttling (1216) are insufficient to reduce the temperature, so the temperature (1238) continues to increase. When the temperature (1238) exceeds the HI thermal threshold (1206), the controller performs extreme throttling (1216). In this example, the first tier extreme throttling (1218) is sufficient to gradually lower the temperature, and throttling continues until the temperature is reduced below the HI thermal threshold (1206). At that point, the controller switches to strong throttling (1216), which continues until the temperature drops below the MED thermal threshold (1204). At that point, the controller switches to weak throttling (1214), which continues until the temperature drops below the LO thermal threshold (1202). Subsequently, the storage device disables throttling to resume maximum power operation.

[0104] Referring to the fourth example (1230), the storage device initially operates without throttling in the full output region (1212). However, unlike the first through third examples, when the temperature (1240) exceeds the LO thermal threshold (1202), MED thermal threshold (1204), and HI thermal thresholds (1206), weak throttling (1214), strong throttling (1216), and first tier extreme throttling (1218) are insufficient to reduce the temperature, so the temperature (1240) continues to increase. When the temperature exceeds the XTRA HI thermal threshold (1208), the controller performs second tier extreme throttling (1220). In this example, the second tier extreme throttling (1220) is sufficient to gradually lower the temperature, and throttling continues until the temperature is reduced below the XTRA-HI thermal threshold (1208). At that point, the controller switches to the first tier extreme throttling (1218), which continues until the temperature is reduced below the HI thermal threshold (1206). At that point, the controller switches to strong throttling (1216), which continues until the temperature is reduced below the MED thermal threshold (1204). At that point, the controller switches to weak throttling (1214), which continues until the temperature is reduced below the LO thermal threshold (1202). Subsequently, the storage device disables throttling to resume maximum power operation.

[0105] Referring to the fifth example (1232), the storage device initially operates without throttling in the full output region (1212). However, unlike the first through fourth examples, when the temperature (1242) exceeds the LO thermal threshold (1202), the MED thermal threshold (1204), HI thermal threshold (1206), record throttling (1214), strong throttling (1216), and first tier refreshing throttling (1218) are insufficient to lower the temperature, and thus the temperature (1242) continues to rise. When the temperature exceeds the XTRA HI thermal threshold (1208), the controller performs second tier extreme throttling (1220). In this example, the second-tier extreme throttling (1220) is insufficient to gradually lower the temperature, so the temperature continues to increase until it reaches the TSD thermal threshold (1210). At this point, the controller performs a thermal cutoff (1222) that blocks access to the cells and / or storage device, for example, until the temperature is reduced back to a normal level.

[0106] FIG. 13 is a conceptual diagram illustrating a state machine (1300) of a plurality of thermal power states for advanced thermal throttling in the storage device of FIG. 1. The state machine (1300) may include a finite number of thermal power states. For example, the state machine (1300) may include a first thermal power state (1302) (TPS0) representing a state of the storage device without thermal throttling, a second thermal power state (1304) (TPS1) associated with a first thermal threshold (TMT1), a third thermal power state (1306) (TPS2) associated with a second thermal threshold (TMT2), a fourth thermal power state (1308) (TPS3) associated with a third thermal threshold (TMT3), and a fifth thermal power state (1310) (TPS4) associated with a fourth thermal threshold (TMT4).

[0107] In some embodiments, referring to FIG. 1 and FIG. 10, when it is determined that the temperature of NVM (110) satisfies (or exceeds) TMT1, the state machine (1300) indicates a transition from TPS0 (1302) to TPS1 (1304). Similarly, when it is determined that the temperature of NVM (110) satisfies (or exceeds) TMT2, the state machine (1300) indicates a transition from TPS1 (1304) to TPS2 (1306). Conversely, when it is determined that the temperature of NVM (110) satisfies (or does not exceed) TMT1b, the state machine (1300) again indicates a transition from TPS1 (1304) to TPS0 (1302). In some embodiments, TMT1b is less than TMT1. For example, TMT1 can be set to 80°C and TMT1b can be set to 77°C.

[0108] When it is determined that the temperature of the NVM (110) satisfies (or exceeds) TMT3, the state machine (1300) indicates a transition from TPS2 (1306) to TPS3 (1308). Conversely, when it is determined that the temperature of the NVM (110) satisfies (or does not exceed) TMT2b, the state machine (1300) again indicates a transition from TPS2 (1306) to TPS1 (1304). In some embodiments, TMT2b is smaller than TMT2. For example, TMT2 can be set to 86°C and TMT2b can be set to 83°C.

[0109] When it is determined that the temperature of the NVM (110) satisfies (or exceeds) TMT4, the state machine (1300) indicates a transition from TPS3 (1308) to TPS4 (1310). Conversely, when it is determined that the temperature of the NVM (110) satisfies (or does not exceed) TMT3b, the state machine (1300) again indicates a transition from TPS3 (1308) to TPS2 (1306). In some embodiments, TMT3b is smaller than TMT3. For example, TMT3 can be set to 92°C and TMT3b can be set to 89°C. Similarly, when it is determined that the temperature of the NVM (110) satisfies (or does not exceed) TMT4b, the state machine (1300) again indicates a transition from TPS4 (1310) to TPS3 (1308). In some embodiments, TMT4b is smaller than TMT4. For example, TMT4 can be set to 94°C and TMT4b can be set to 92°C.

[0110] FIG. 14 is a flowchart illustrating an exemplary process for a first thermal power state of advanced thermal throttling in the storage device of FIG. 1. For example, the method may be performed in a storage device (102) such as that illustrated in FIG. 1. Each of the steps in the flowchart may be controlled using a controller as described below (e.g., controller (123, 802, 1010)) or by some other suitable means.

[0111] In one or more embodiments with reference to FIGS. 10 and FIGS. 13, the controller (1010) may transition to a first thermal power state (e.g., TPS1 (1304)) of a plurality of thermal power states (e.g., TPS1 to TPS4). In some embodiments, the controller (1010) may apply a thermal relaxation configuration by applying one or more thermal relaxation parameters of a first thermal relaxation configuration associated with the first thermal power state.

[0112] As indicated by block (1402), the controller obtains the temperature. For example, referring to FIGS. 1 and FIGS. 10, the controller (1010) can measure the first temperature of the NVM (110) in the first thermal power state based on one or more applied thermal relaxation parameters of the first thermal relaxation configuration.

[0113] As shown by block (1404), the controller (1010) can apply power budget adjustment (e.g., PB=PB(n)a) and can apply clock frequency scaling adjustment with a first predetermined percentage (e.g., x=60% of the full clock rate).

[0114] As indicated by block (1406), the controller (1010) can determine a temperature gradient from the first measured temperature. For example, the controller (1010) can determine whether the rate of change of the measured temperature is positive (increasing), negative (decreasing), or neutral (no change).

[0115] As indicated by block (1408), the controller (1010) can determine that the measured first temperature is greater than the exit heat threshold associated with the first thermopower state and less than the entry heat threshold associated with the second thermopower state of a plurality of thermopower states (e.g., TMT2 > temperature > TMT1b). Otherwise, the process terminates the thermopower state.

[0116] As indicated by block (1410), the controller (1010) can determine whether the temperature gradient indicates that the measured first temperature is in a state of thermal equilibrium. In other words, the controller (1010) can determine whether the temperature gradient is equal to a value of 0. For example, as indicated by block (1410), the controller (1010) determines that the temperature gradient is positive (or greater than 0) and proceeds to block (1412). Alternatively, for example, as indicated by block (1410), the controller (1010) determines that the temperature gradient is not positive (or greater than 0) and proceeds to block (1416).

[0117] As indicated by block (1416), the controller (1010) determines that the temperature gradient is negative (or less than 0) and proceeds to block (1418). Otherwise, the controller (1010) determines that the temperature gradient is not negative and proceeds to block (1422).

[0118] As indicated by blocks (1412 and 1418), the controller (1010) can adjust the first power budget parameter of the first thermal relaxation configuration when the temperature gradient indicates that the measured first temperature is not in a thermal equilibrium state. As indicated by block (1414), the controller (1010) can adjust power consumption by decreasing the power budget value proportional to the degree of change of the temperature gradient when the temperature gradient indicates a positive temperature change rate. As indicated by block (1420), the controller (1010) can adjust power consumption by increasing the power budget value proportional to the degree of change of the temperature gradient when the temperature gradient indicates a negative temperature change rate.

[0119] As indicated by block (1422), the controller (1010) may refrain from adjusting the first power budget parameter when the temperature gradient indicates that the first temperature measured is in a state of thermal equilibrium. In this regard, the controller (1010) determines that there is no rate of temperature change (therefore, temperature equilibrium). Thus, the power budget parameter is not changed.

[0120] FIG. 15 is a flowchart illustrating an exemplary process for a second thermal power state of advanced thermal throttling in the storage device of FIG. 1. For example, the method may be performed in a storage device (102) such as that illustrated in FIG. 1. Each of the steps in the flowchart may be controlled using a controller as described below (e.g., controller (123, 802, 1010)) or by some other suitable means.

[0121] In one or more embodiments with reference to FIGS. 10 and FIGS. 13, the controller (1010) may transition to a second thermal power state (e.g., TPS2 (1306)) of a plurality of thermal power states (e.g., TPS1 to TPS4). In some embodiments, the controller (1010) may apply a thermal relaxation configuration by applying one or more thermal relaxation parameters of a second thermal relaxation configuration associated with the second thermal power state.

[0122] As indicated by block (1502), the controller obtains the temperature. For example, referring to FIGS. 1 and FIGS. 10, the controller (1010) can measure the second temperature of the NVM (110) in the second thermal power state based on one or more applied thermal relaxation parameters of the second thermal relaxation configuration.

[0123] As shown by block (1504), the controller (1010) can apply power budget adjustment (e.g., PB=PB(n)a) and can apply clock frequency scaling adjustment with a second predetermined percentage (e.g., x=40% of the full clock rate).

[0124] As indicated by block (1506), the controller (1010) can determine a temperature gradient from the measured second temperature. For example, the controller (1010) can determine whether the rate of change of the measured temperature is positive (increasing), negative (decreasing), or neutral (no change).

[0125] As indicated by block (1508), the controller (1010) can determine that the measured second temperature is greater than the exit heat threshold associated with the second thermopower state of a plurality of thermopower states (e.g., TMT3 > Temperature > TMT2b) and less than the entry heat threshold associated with the third thermopower state. Otherwise, the process terminates the thermopower state.

[0126] As indicated by block (1510), the controller (1010) can determine whether the temperature gradient indicates that the measured second temperature is in a state of thermal equilibrium. In other words, the controller (1010) can determine whether the temperature gradient is equal to a value of 0. For example, as indicated by block (1510), the controller (1010) determines that the temperature gradient is positive (or greater than 0) and proceeds to block (1512). Alternatively, for example, as indicated by block (1510), the controller (1010) determines that the temperature gradient is not positive (or not greater than 0) and proceeds to block (1516).

[0127] As indicated by block (1516), the controller (1010) determines that the temperature gradient is negative (or less than 0) and proceeds to block (1518). Otherwise, the controller (1010) determines that the temperature gradient is not negative and proceeds to block (1522).

[0128] As indicated by blocks (1512, 1518), the controller (1010) can adjust the second power budget parameter of the second thermal relaxation configuration when the temperature gradient indicates that the measured second temperature is not in a state of thermal equilibrium. As indicated by block (1514), the controller (1010) can adjust power consumption by decreasing the power budget value proportional to the degree of change of the temperature gradient when the temperature gradient indicates a positive temperature change rate. As indicated by block (1520), the controller (1010) can adjust power consumption by increasing the power budget value proportional to the degree of change of the temperature gradient when the temperature gradient indicates a negative temperature change rate.

[0129] As indicated by block (1522), the controller (1010) may avoid adjusting the second power budget parameter when the second temperature measured by the temperature gradient indicates that it is in a state of thermal equilibrium. In this regard, the controller (1010) determines that there is no rate of temperature change (therefore, temperature equilibrium). Thus, the power budget parameter is not changed.

[0130] FIG. 16 is a flowchart illustrating an exemplary process for a third thermal power state of advanced thermal throttling in the storage device of FIG. 1. For example, the method may be performed in a storage device (102) such as that illustrated in FIG. 1. Each step in the flowchart may be controlled using a controller (e.g., controller (123, 802, 1010)) as described below, or by some other suitable means. In one or more implementations, the controller (1010) may transition to a third thermal power state (e.g., TPS3 (1308)) of a plurality of thermal power states (e.g., TPS1 to TPS4).

[0131] As indicated by block (1602), the controller (1010) may apply a third column relaxation configuration associated with a third column power state. In some embodiments, the third column relaxation configuration sets a power budget for the third column power state, which may correspond to an allowable minimum power consumption allocation. In some embodiments, the third column relaxation configuration reduces the host interface queue depth size from the full queue depth (e.g., at 256) to a reduced queue depth (e.g., at 8). In other embodiments, the third column relaxation configuration reduces the clock frequency of the storage device by a predetermined ratio. For example, the third column relaxation configuration may extend the clock frequency from the full clock rate (or previous clock rate) to 10% of the full clock rate.

[0132] As indicated by block (1604), the controller obtains the temperature. For example, referring to FIGS. 1 and FIGS. 10, the controller (1010) can measure the third temperature of the memory in the third thermal power state based on one or more applied thermal relaxation parameters of the third thermal relaxation configuration.

[0133] As indicated by block (1606), the controller can determine whether the measured third temperature is greater than the exit heat threshold associated with the third thermopower state of a plurality of thermopower states (e.g., TMT4 > Temperature > TMT3b) and less than the entry heat threshold associated with the fourth thermopower state. If the measured third temperature satisfies the condition, the process proceeds back to block (1604). Otherwise, the process terminates the thermopower state.

[0134] FIG. 17 is a flowchart illustrating an exemplary process for a fourth thermal power state of advanced thermal throttling in the storage device of FIG. 1. For example, the method may be performed in a storage device (102) such as that illustrated in FIG. 1. Each of the steps in the flowchart may be controlled using a controller (e.g., controller (123, 802, 1010)) as described below, or by some other suitable means. In one or more embodiments, the controller may transition to a fourth thermal power state (e.g., TPS4 (1310)) of a plurality of thermal power states (e.g., TPS1 to TPS4).

[0135] As indicated by block (1702), the controller (1010) may apply a fourth column relaxation configuration associated with a fourth column power state. In some embodiments, the fourth column relaxation configuration sets a power budget for the fourth column power state, which may correspond to an allowable minimum power consumption allocation. In some embodiments, the fourth column relaxation configuration reduces the host interface queue size from a full queue depth (e.g., at 256) to a reduced queue depth (e.g., at 8). In other embodiments, the fourth column relaxation configuration reduces the clock frequency of the storage device by a predetermined ratio. For example, the fourth column relaxation configuration may extend the clock frequency from the full clock rate (or previous clock rate) to 10% of the full clock rate. Additionally, the fourth column relaxation configuration may reduce the operation clock duty cycle (e.g., reduced to 10% of the full clock duty cycle).

[0136] As indicated by block (1704), the controller obtains the temperature. For example, referring to FIGS. 1 and FIGS. 10, the controller (1010) can measure the fourth temperature of the memory in the fourth thermal power state based on one or more applied thermal relaxation parameters of the fourth thermal relaxation configuration.

[0137] As indicated by block (1706), the controller can determine whether the measured fourth temperature is greater than the exit heat threshold associated with the fourth thermopower state and less than the entry heat threshold associated with the heat cutoff state (e.g., TMTSD > temperature > TMT4b). If the measured fourth temperature satisfies the condition, the process proceeds back to block (1704). Otherwise, the process terminates the thermopower state.

[0138] FIG. 18a is a graphic illustration illustrating a performance benchmark using legacy thermal throttling in the storage device of FIG. 1. FIG. 18a illustrates a diagram (1810) showing the temperature change of the memory over time, a diagram (1812) showing the performance of the memory over time according to the temperature change of the memory, and a diagram (1814) showing the power consumption of the memory according to the performance of the memory according to the temperature change of the memory. The diagrams (1812 and 1814) each show significant changes in performance and power consumption due to hard power state transitions according to legacy thermal throttling technology.

[0139] FIG. 18b is a graphic illustration illustrating a performance benchmark using advanced thermal throttling in the storage device of FIG. 1. FIG. 18b shows a illustration (1820) showing a change in memory temperature over time, a illustration (1822) showing memory performance over time according to the change in memory temperature, and a illustration (1824) showing memory power consumption according to memory performance according to the change in memory temperature. In contrast to FIG. 18a, the illustrations (1822 and 1824) each show smaller (and more gradual) changes in performance and power consumption due to a more gradual power state transition under advanced thermal control technology having multiple thermal power states.

[0140] Accordingly, the storage device of the present disclosure improves performance and user experience without compromising data integrity based on multiple thermal power states. Rather, instead of employing thermal throttling that causes hard power state transitions (and consequently reduces performance) when the temperature of the storage device exceeds different thermal throttling thresholds, the storage device of the present disclosure applies advanced thermal throttling that utilizes multiple thermal power states, each progressively reducing power based on a temperature gradient, along with other thermal mitigation parameters such as dynamic voltage and frequency scaling, queue depth adjustment, and bus interconnect scaling. In this way, the storage device of the present disclosure provides an improved user experience, enables the satisfaction of performance benchmarks, and maintains data reliability through efficient NAND block utilization.

[0141] Various aspects of the present disclosure are provided to enable those skilled in the art to practice the invention. Various modifications to the exemplary embodiments presented throughout the present disclosure will be readily apparent to those skilled in the art, and the concepts disclosed herein may be extended to other magnetic storage devices. Accordingly, the claims are not intended to be limited to the various aspects of the present disclosure but should be consistent with the entire scope consistent with the language of the claims. All structural and functional equivalents to the various components of the exemplary embodiments described throughout the present disclosure, which are known to those skilled in the art or will be known later, are expressly incorporated by reference into the present specification and are intended to be encompassed by the claims. Furthermore, nothing disclosed in the present specification is intended to be made available to the public, regardless of whether such disclosure is explicitly cited in the claims. No component of a claim shall be interpreted as being in accordance with the provisions of U.S. 35 USC §112(f) or similar statutes or laws in any other jurisdiction, unless such component is explicitly cited using the phrase “means for doing”, or, in the case of a method claim, unless such component is cited using the phrase “step for doing”.

Claims

Claim 1 A storage device comprising: a memory; and a controller coupled to the memory, wherein the controller is configured to: determine whether the temperature of the memory satisfies a thermal throttling threshold among a plurality of thermal throttling thresholds; transition to a thermal power state among a plurality of thermal power states in response to the temperature satisfying the thermal throttling threshold; apply a thermal relaxation configuration associated with the thermal power state; determine whether the temperature of the memory reaches thermal equilibrium in the thermal power state in response to the thermal relaxation configuration; stop applying the thermal relaxation configuration in response to the temperature of the memory reaching thermal equilibrium; acquire the temperature of the memory at a first sampling rate before the temperature of the memory satisfies the thermal throttling threshold; and acquire the temperature of the memory at a second sampling rate greater than the first sampling rate in response to the temperature of the memory satisfies the thermal throttling threshold. Claim 2 delete Claim 3 A storage device according to claim 1, wherein the controller configured to apply the thermal relaxation configuration is also configured to adjust one or more thermal relaxation parameters associated with the thermal power state. Claim 4 In paragraph 3, the controller configured to adjust the one or more thermal relaxation parameters is also configured to adjust a power budget parameter based on a temperature gradient associated with the temperature, wherein the power budget parameter represents the power consumption allocated to the storage device in the thermal power state. Claim 5 A storage device according to claim 4, wherein the controller configured to adjust the power budget parameter is also configured to reduce the value of the power budget parameter in response to the temperature gradient indicating a positive rate of change of the temperature, wherein the value of the power budget parameter is reduced until the temperature gradient indicates the thermal equilibrium. Claim 6 A storage device according to claim 4, wherein the controller configured to adjust the power budget parameter is also configured to increase the value of the power budget parameter in response to the temperature gradient indicating a negative rate of change of the temperature, wherein the value of the power budget parameter is increased until the temperature gradient indicates the thermal equilibrium. Claim 7 A storage device according to paragraph 3, wherein the controller configured to adjust the one or more thermal relaxation parameters is also configured to adjust a clock frequency parameter associated with one or more clock domains of the storage device to a value corresponding to a predetermined clock frequency associated with the thermal power state. Claim 8 A storage device according to paragraph 3, wherein the controller configured to adjust the one or more thermal relaxation parameters is also configured to adjust a voltage parameter associated with one or more voltage domains of the storage device to a value corresponding to a predetermined voltage associated with the thermal power state. Claim 9 A storage device according to paragraph 3, wherein the controller configured to adjust the one or more thermal relaxation parameters is also configured to adjust a bus interface parameter associated with the interconnection between the memory and the controller to a value corresponding to a predetermined number of interconnection lanes associated with the thermal power state. Claim 10 In claim 1, the controller configured to transition to the thermoelectric state is also configured to transition to a first thermoelectric state among the plurality of thermoelectric states, and the controller configured to apply the thermal relaxation configuration is also configured to apply one or more first thermal relaxation parameters of the first thermal relaxation configuration associated with the first thermoelectric state, and the controller also: measures a first temperature of the memory in the first thermoelectric state based on the one or more first thermal relaxation parameters of the first thermal relaxation configuration, determines a first temperature gradient from the measured first temperature, determines whether the measured first temperature is greater than a first outgoing thermal throttling threshold associated with the first thermoelectric state and less than a first incoming thermal throttling threshold associated with a second thermoelectric state among the plurality of thermoelectric states, and in response to the measured first temperature being greater than the first outgoing thermal throttling threshold and less than the first incoming thermal throttling threshold, determines whether the first temperature gradient indicates that the measured first temperature is in a thermal equilibrium state, and the first A storage device configured to adjust a first power budget parameter of the first thermal relaxation configuration in response to a temperature gradient indicating that the measured first temperature is not in a thermal equilibrium state, and not to adjust the first power budget parameter in response to a first temperature gradient indicating that the measured first temperature is in a thermal equilibrium state. Claim 11 In paragraph 10, the controller configured to transition to the thermopower state is also configured to transition to the second thermopower state, and the controller configured to apply the thermal relaxation configuration is also configured to apply one or more second thermal relaxation parameters of the second thermal relaxation configuration associated with the second thermopower state, and the controller also: measures a second temperature of the memory in the second thermopower state based on the one or more second thermal relaxation parameters of the second thermal relaxation configuration, determines a second temperature gradient from the measured second temperature, determines whether the measured second temperature is greater than a second outgoing thermal throttling threshold associated with the second thermopower state and less than a second incoming thermal throttling threshold associated with a third thermopower state among the plurality of thermopower states, and in response to the measured second temperature being greater than the second outgoing thermal throttling threshold and less than the second incoming thermal throttling threshold, determines whether the second temperature gradient indicates that the measured second temperature is in a thermal equilibrium state, and the second temperature gradient is the A storage device configured to adjust a second power budget parameter of the second thermal relaxation configuration in response to the second temperature being not in a thermal equilibrium state, and not to adjust the second power budget parameter in response to the second temperature gradient being not in a thermal equilibrium state. Claim 12 A storage device according to claim 11, wherein the controller configured to transition to the thermal power state is also configured to transition to the third thermal power state, and the controller configured to apply the thermal relaxation configuration is also configured to apply one or more third thermal relaxation parameters of the third thermal relaxation configuration associated with the third thermal power state, and the controller is configured to reduce the queue depth size and reduce the clock frequency by a predetermined percentage in the third thermal relaxation configuration, and the controller is also configured to: measure a third temperature of the memory in the third thermal power state based on the one or more third thermal relaxation parameters of the third thermal relaxation configuration, and maintain the third thermal power state in response to the measured third temperature being greater than a third outgoing thermal throttling threshold associated with the third thermal power state and less than a third incoming thermal throttling threshold associated with a fourth thermal power state among the plurality of thermal power states. Claim 13 A storage device according to claim 12, wherein the controller configured to transition to the thermal power state is also configured to transition to the fourth thermal power state, and the controller configured to apply the thermal relaxation configuration is also configured to apply one or more fourth thermal relaxation parameters of the fourth thermal relaxation configuration associated with the fourth thermal power state, and the controller is configured to reduce the clock duty cycle in the fourth thermal relaxation configuration, and the controller is also configured to: measure a fourth temperature of the memory in the fourth thermal power state based on the one or more fourth thermal relaxation parameters of the fourth thermal relaxation configuration, and maintain the fourth thermal power state in response to the measured fourth temperature being greater than a fourth outgoing thermal throttling threshold associated with the fourth thermal power state and less than a fourth incoming thermal throttling threshold associated with a thermal cutoff state among the plurality of thermal power states. Claim 14 A storage device comprising: a memory; and a controller coupled to the memory, wherein the controller: adjusts one or more thermal relaxation parameters, including a bus interface parameter associated with the thermal power state, after transitioning to a thermal power state among a plurality of thermal power states in response to the temperature of the memory satisfying a thermal throttling threshold — the bus interface parameter is associated with an interconnection between the memory and the controller and is adjusted to a value corresponding to a predetermined number of interconnection lanes associated with the thermal power state — and is configured not to further adjust the one or more thermal relaxation parameters in response to a determination that the temperature of the memory has reached thermal equilibrium in the thermal power state in response to the adjusted one or more thermal relaxation parameters. Claim 15 A storage device according to claim 14, wherein the controller configured to adjust one or more thermal relaxation parameters is also configured to adjust a power budget parameter based on a temperature gradient associated with the temperature, and the power budget parameter represents a power consumption allocated to the storage device in the thermal power state to maintain the performance of one or more storage operations of the storage device. Claim 16 A storage device according to claim 14, wherein the controller configured to adjust the one or more thermal relaxation parameters is also configured to adjust a clock frequency parameter associated with one or more clock domains of the storage device to correspond to a predetermined clock frequency associated with the thermal power state. Claim 17 A storage device according to claim 14, wherein the controller configured to adjust one or more thermal relaxation parameters is also configured to adjust a voltage parameter associated with one or more voltage domains of the storage device to correspond to a predetermined voltage associated with the thermal power state. Claim 18 A storage device according to claim 14, wherein the controller is also configured to acquire the temperature of the memory at a first sampling rate before the temperature of the memory meets the thermal throttling threshold, and to acquire the temperature of the memory at a second sampling rate greater than the first sampling rate in response to the temperature of the memory meeting the thermal throttling threshold. Claim 19 A storage device comprising: a memory having a block of cells; and a controller coupled to the memory, wherein the controller: applies a thermal relaxation configuration associated with a thermal power state after transitioning to a thermal power state among a plurality of thermal power states in response to the temperature of the block of cells satisfying a thermal throttling threshold — the thermal relaxation configuration constitutes a reduction in the queue depth size —, determines whether the temperature of the block of cells reaches thermal equilibrium in the thermal power state in response to the thermal relaxation configuration, and is configured not to apply the thermal relaxation configuration further in response to the temperature reaching thermal equilibrium. Claim 20 In claim 19, the controller configured to apply the thermal relaxation configuration also: adjusts a power budget parameter based on a temperature gradient associated with the temperature — the power budget parameter represents the power consumption allocated to the storage device in the thermal power state —, adjusts a clock frequency parameter associated with one or more clock domains of the storage device to correspond to a predetermined clock frequency associated with the thermal power state, adjusts a voltage parameter associated with one or more voltage domains of the storage device to correspond to a predetermined voltage associated with the thermal power state, and adjusts a bus interface parameter associated with the interconnection between the memory and the controller to correspond to a predetermined number of interconnection lanes associated with the thermal power state, the storage device.

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