Semiconductor structure and forming method thereof

Abstract

In a semiconductor structure and a method for forming the same, the semiconductor structure comprises a base structure, a first etching stop layer, a second etching stop layer, a first stacked structure, and a slit opening; the base structure comprises a capacitor region and a logic region adjacent thereto; the base structure comprises a first insulating layer and a plurality of conductive portions embedded in the first insulating layer at a distance from each other; the first etching stop layer is located in the capacitor region and covers at least the upper portion of the conductive portions; the second etching stop layer is located in the logic region and covers the upper portion of the first insulating layer; the materials of the first etching stop layer and the second etching stop layer are the same, and the first etching stop layer and the second etching stop layer are separated by a protective layer; or the materials of the first etching stop layer and the second etching stop layer are different, and a contact interface is formed between the first etching stop layer and the second etching stop layer; and the first stacked structure covers a layer on which the first etching stop layer and the second etching stop layer are located. The slit opening penetrates the first stacked structure and exposes the second etching stop layer. The semiconductor structure according to the present invention improves the reliability of the structure.

Description

Technology Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid advancement of mobile consumer electronics, users are placing higher demands on device miniaturization, functional integration, and large-capacity storage. For example, devices such as smartphones and tablet PCs must integrate more functional modules—including processors, memory, and sensors—within limited space, while simultaneously satisfying users' needs for high-capacity storage. To achieve these goals, high-density packaging technology has become key. However, conventional packaging methods are increasingly facing bottlenecks in terms of space utilization and performance improvement, leading to various types of "misaligned" structures during the design process.

[0003] Currently, in the design of capacitor structures, electrode post receiving holes are formed in a structure in which silicon oxide and silicon nitride layers are alternately stacked. The centerline of the electrode post manufactured inside the electrode post receiving hole does not overlap with the centerline of the source and drain electrodes, but rather a structure that is "misaligned" between the two exists. In the etching process of the electrode post receiving hole, an aluminum oxide layer must be formed as an etching stop layer, and the electrode post receiving hole is positioned exactly above the conductive portion by reducing the size of the lower part of the etching stop layer. Next, a slit opening penetrating the stacked structure of silicon oxide and silicon nitride layers is etched, and silicon nitride within the high-stacked structure of silicon oxide and silicon nitride layers is removed through the slit opening using acid washing. Furthermore, during the acid washing process, the acid solution comes into contact with the aluminum oxide etching stop layer and a chemical reaction occurs, which significantly increases the probability of structural collapse in the semiconductor structure.

[0004] Therefore, there is still a need to improve the reliability of semiconductor structures. The problem to be solved

[0005] The problem to be solved in the embodiments of the present invention is to provide a semiconductor structure with improved reliability and a method for forming the same. means of solving the problem

[0006] To solve the above-mentioned problem, an embodiment of the present invention provides a semiconductor structure, wherein the semiconductor structure comprises a base structure, a first etching stop layer, a second etching stop layer, a first stacked structure, a plurality of first electrode posts and slit openings, the base structure comprises a capacitor region and a logic region adjacent thereto, the base structure comprises a first insulating layer and a plurality of conductive portions embedded in the first insulating layer at a distance from each other, the conductive portions are located in the capacitor region, and the first insulating layer exposes the upper surface of the conductive portions; the first etching stop layer is located in the capacitor region and covers at least the upper portion of the conductive portions; the second etching stop layer is located in the logic region and covers the upper portion of the first insulating layer, and the second etching stop layer and the first etching stop layer are located in the same layer, and the upper surfaces of both coincide with each other; the materials of the first etching stop layer and the second etching stop layer are the same, and the first etching stop layer and the second etching stop layer are spaced apart through a protective layer; Alternatively, the materials of the first etching stop layer and the second etching stop layer are different from each other, and a contact interface is formed between the first etching stop layer and the second etching stop layer; the first laminated structure covers the layer where the first etching stop layer and the second etching stop layer are located; each first electrode post is installed through the first laminated structure and the first etching stop layer and is connected in contact with a corresponding conductive part; and a slit opening penetrates the first laminated structure and exposes the second etching stop layer.

[0007] Correspondingly, embodiments of the present invention further provide a method for forming a semiconductor structure. The method comprises the steps of: providing a base structure, wherein the base structure comprises a capacitor region and a logic region adjacent thereto; wherein the base structure comprises a first insulating layer and a plurality of conductive portions embedded in the first insulating layer at a distance from each other, wherein the conductive portions are located in the capacitor region and the first insulating layer exposes the upper surface of the conductive portions; and forming an etching stop structure on the base structure, wherein the etching stop structure comprises a first etching stop layer and a second etching stop layer, wherein the first etching stop layer is located in the capacitor region and covers at least the upper portion of the conductive portions; wherein the second etching stop layer is located in the logic region and covers the upper portion of the first insulating layer, wherein the first etching stop layer and the second etching stop layer are located in the same layer and the upper surfaces of both coincide with each other; wherein the materials of the first etching stop layer and the second etching stop layer are the same, and the first etching stop layer and the second etching stop layer are spaced apart through a protective layer; Alternatively, the materials of the first etching stop layer and the second etching stop layer are different from each other, and a contact interface is formed between the first etching stop layer and the second etching stop layer; a step of forming a first stacked structure on an etching stop structure; a step of forming a plurality of first electrode post receiving holes penetrating the first stacked structure, wherein the first electrode post receiving holes expose a conductive portion; a step of manufacturing a first electrode post within the first electrode post receiving holes, wherein the first electrode post and the conductive portion are contact-connected; a step of forming a slit opening penetrating the first stacked structure, wherein the slit opening exposes the second etching stop layer; is included. Effects of the invention

[0008] Compared to conventional technology, the technical solution according to the embodiment of the present invention has the following advantages.

[0009] The semiconductor structure and the method for forming the same provided in an embodiment of the present invention are configured such that the etching stop layer structure includes a first etching stop layer and a second etching stop layer, and if the materials of the first etching stop layer and the second etching stop layer are the same, the first etching stop layer and the second etching stop layer are separated using a protective layer; or, if the materials of the first etching stop layer and the second etching stop layer are different, a contact interface is formed between the first etching stop layer and the second etching stop layer. Subsequently, during the process of acid cleaning the first laminated structure through the slit opening, the acid cleaning solution may also chemically react with the first etching stop layer. If the materials of the first etching stop layer and the second etching stop layer are the same, a protective layer is installed between the first etching stop layer and the second etching stop layer, and the protective layer acts to protect the sidewall of the first etching stop layer in the capacitor region, thereby reducing the probability of contact between the acid cleaning solution and the first etching stop layer, and consequently lowering the probability of damage to the first etching stop layer in the capacitor region. Alternatively, if the materials of the first etching stop layer and the second etching stop layer are different, a contact interface is formed between the first etching stop layer and the second etching stop layer, and the second etching stop layer acts as a protective agent against the sidewall of the first etching stop layer in the capacitor region, thereby reducing the probability of contact between the acid cleaning solution and the first etching stop layer during the subsequent acid cleaning process, and accordingly, lowering the probability of damage to the first etching stop layer in the capacitor region and further improving the reliability of the semiconductor structure. Brief explanation of the drawing

[0010] FIGS. 1 to 6 show schematic diagrams of structures corresponding to each step of a method for forming a semiconductor structure. FIG. 7 shows a schematic diagram of a structure corresponding to a first embodiment of a semiconductor structure according to the present invention. FIG. 8 shows a schematic diagram of a structure corresponding to a second embodiment of a semiconductor structure according to the present invention. FIG. 9 shows a schematic diagram of a structure corresponding to a third embodiment of a semiconductor structure according to the present invention. FIGS. 10 to 18 show schematic diagrams of structures corresponding to each step of the first embodiment of the method for forming a semiconductor structure according to the present invention. FIGS. 19 to 22 show schematic diagrams of structures corresponding to each step of a second embodiment of the method for forming a semiconductor structure according to the present invention. FIGS. 23 to 27 show schematic diagrams of structures corresponding to each step of a third embodiment of the method for forming a semiconductor structure according to the present invention. Specific details for implementing the invention

[0011] Currently, the reliability of semiconductor structures still needs to be improved. Below, we analyze the reasons why the performance of semiconductor structures must be enhanced by combining semiconductor structure formation methods.

[0012] Referring to FIG. 1, a base structure (12) is provided, wherein the base structure (12) has a capacitor region (10A) and a logic region (10B) adjacent thereto, and the base structure (12) includes a first insulating layer (10) and a plurality of conductive parts (11) embedded in the first insulating layer (10) at intervals from each other, wherein the conductive parts (11) are located in the capacitor region (10A) and the first insulating layer (10) exposes the upper surface of the conductive parts (11).

[0013] Referring to FIG. 2, an etching stop layer (13) covering the first insulating layer (10) and the conductive part (11) is formed on the upper part of the base structure (12) of the capacitor region (10A) and the logic region (10B), and the material of the etching stop layer (13) is aluminum oxide.

[0014] Referring to FIG. 3, a first stacked structure (16) is formed on an etching stop layer (13), and the first stacked structure (16) includes a silicon oxide layer (17) and a silicon nitride layer (18) that are sequentially and alternately deposited, and the top layer of the first stacked structure (16) is a silicon oxide layer (17).

[0015] Referring to FIG. 4, a plurality of first electrode posts (20) are formed in a capacitor region (10A) and embedded through the first laminated structure (16) and the etching stop layer (13), and the first electrode posts (20) are contact-connected to a conductive part (11);

[0016] Referring to FIG. 5, a slit opening (60) penetrating the first laminated structure (16) is formed in the logic region (10B), and the slit opening (60) exposes the etching stop layer (13).

[0017] Referring to FIG. 6, the silicon nitride layer (18) is removed by acid washing through the slit opening (60).

[0018] According to the study, in the process of subsequently removing the silicon nitride layer (18) by acid washing through the slit opening (60), the acid washing solution also reacts chemically with the aluminum oxide etching stop layer (13), so the etching stop layer (13) of the capacitor region (10A) is damaged by internal erosion (e.g., as shown in FIG. 6) by the acid washing solution, and thus the risk of structural collapse of the semiconductor structure increases and the reliability of the semiconductor structure is affected.

[0019] To solve the aforementioned problems, an embodiment of the present invention provides a semiconductor structure. The semiconductor structure comprises a base structure, a first etching stop layer, a second etching stop layer, a first stacked structure, a plurality of first electrode posts and slit openings, wherein the base structure comprises a capacitor region and a logic region adjacent thereto, and the base structure comprises a first insulating layer and a plurality of conductive portions embedded in the first insulating layer at a distance from each other, wherein the conductive portions are located in the capacitor region and the first insulating layer exposes the upper surface of the conductive portions; the first etching stop layer is located in the capacitor region and covers at least the upper portion of the conductive portions; the second etching stop layer is located in the logic region and covers the upper portion of the first insulating layer, wherein the second etching stop layer and the first etching stop layer are located in the same layer and the upper surfaces of both coincide with each other; wherein the material of the first etching stop layer and the second etching stop layer is the same and the first etching stop layer and the second etching stop layer are separated by a protective layer; Alternatively, the materials of the first etching stop layer and the second etching stop layer are different from each other, and a contact interface is formed between the first etching stop layer and the second etching stop layer; the first laminated structure covers the layer where the first etching stop layer and the second etching stop layer are located; each first electrode post is installed through the first laminated structure and the first etching stop layer and is connected in contact with a corresponding conductive part; and a slit opening penetrates the first laminated structure and exposes the second etching stop layer.

[0020] In the semiconductor structure provided in the present invention, the first etching stop layer is located in a capacitor region and covers the upper portion of a conductive portion, the second etching stop layer is located in a logic region and covers the upper portion of a first insulating layer, the second etching stop layer and the first etching stop layer are located in the same layer and their upper surfaces coincide with each other, the materials of the first etching stop layer and the second etching stop layer are the same, and the first etching stop layer and the second etching stop layer are separated by a protective layer; or the materials of the first etching stop layer and the second etching stop layer are different, and a contact interface is formed between the first etching stop layer and the second etching stop layer. Subsequently, during the process of acid cleaning the first stacked structure through a slit opening, the acid cleaning solution may also undergo a chemical reaction with the first etching stop layer. Accordingly, if the materials of the first etching stop layer and the second etching stop layer are the same, a protective layer is installed between the first etching stop layer and the second etching stop layer, and the protective layer acts as a protective layer for the sidewall of the first etching stop layer in the capacitor region, thereby reducing the probability of contact between the acid cleaning solution and the first etching stop layer, and consequently lowering the probability of damage to the first etching stop layer in the capacitor region. Alternatively, if the materials of the first etching stop layer and the second etching stop layer are different, a contact interface is formed between the first etching stop layer and the second etching stop layer, and the second etching stop layer acts as a protective layer for the sidewall of the first etching stop layer in the capacitor region, thereby reducing the probability of contact between the acid cleaning solution and the first etching stop layer during the subsequent acid cleaning process, and consequently lowering the probability of damage to the first etching stop layer in the capacitor region, and further improving the reliability of the semiconductor structure.

[0021] In order to make the above-described objectives, features, and advantages of the embodiments of the present invention clearer and easier to understand, specific embodiments of the present invention will be described in detail below in combination with the drawings. Among these, FIG. 7 shows a schematic diagram of a structure corresponding to a first embodiment of a semiconductor structure according to the present invention.

[0022] The semiconductor structure comprises a base structure (402), a first etching stop layer (404), a second etching stop layer (405), a first stacked structure (410), a plurality of first electrode posts (428) and a slit opening (430); the base structure (402) comprises a capacitor region (400A) and a logic region (400B) adjacent thereto; the base structure (402) comprises a first insulating layer (400) and a plurality of conductive portions (401) embedded in the first insulating layer (400) at intervals from each other, wherein the conductive portions (401) are located in the capacitor region (400A) and the first insulating layer (400) exposes the upper surface of the conductive portions (401); the first etching stop layer (404) is located in the capacitor region (400A) and covers at least the upper portion of the conductive portions (401); The second etching stop layer (405) is located in the logic region (400B) and covers the upper portion of the first insulating layer (400), and the second etching stop layer (405) and the first etching stop layer (404) are located in the same layer and the upper surfaces of both coincide with each other; the materials of the first etching stop layer (404) and the second etching stop layer (405) are the same, and the first etching stop layer (404) and the second etching stop layer (405) are separated by a protective layer (409); the first laminated structure (410) covers the layer where the first etching stop layer (404) and the second etching stop layer (405) are located; each first electrode post (428) is installed through the first laminated structure (410) and the first etching stop layer (404) and is contact-connected to a corresponding conductive portion (401); The slit opening (430) penetrates the first laminated structure (410) and exposes the second etching stop layer (405).

[0023] Specifically, during the process of subsequently performing acid cleaning on the first stacked structure (410) through the slit opening (430), the acid cleaning solution may also chemically react with the first etching stop layer (404) and the second etching stop layer (405). Therefore, a protective layer (409) is installed between the first etching stop layer (404) and the second etching stop layer (405) so that the protective layer (409) acts as a protective layer for the sidewall of the first etching stop layer (404) of the capacitor region (400A), thereby reducing the probability of contact between the acid cleaning solution and the first etching stop layer (404), and accordingly, the probability of damage to the first etching stop layer (404) of the capacitor region (400A) is lowered, thereby reducing the risk of the semiconductor structure collapsing due to damage to the first etching stop layer (404) of the capacitor region (400A) and further improving the reliability of the semiconductor structure.

[0024] Specifically, the base structure (402) provides a process platform for a method of forming a semiconductor structure.

[0025] As an example, a semiconductor structure is a capacitor structure.

[0026] In the capacitor structure, the capacitor area (400A) is used as an area for storing data, and the logic area (400B) is used as an area for controlling data reading and writing operations.

[0027] As to be explained, the first insulating layer (400) acts to electrically block the conductive parts (401) that are adjacent to each other.

[0028] The first insulating layer (400) exposes the upper surface of the conductive portion (401), and in the process of subsequently forming the first electrode post (428), the first electrode post (428) penetrates the first laminated structure (410) and the first etching stop layer (404) that are subsequently formed, so that the first electrode post (428) can be contact-connected with the conductive portion (401).

[0029] As an example, the material of the first insulating layer (400) includes silicon oxide.

[0030] In another embodiment, the material of the first insulating layer (400) may be a different insulating material, but is not limited thereto.

[0031] Specifically, the conductive portion (401) is intended to be electrically connected to the first electrode post (428) that is subsequently formed.

[0032] As an example, in a 1T1C (one transistor and one capacitor) memory, the conductive part (401) can be used as a drain electrode.

[0033] In another embodiment, the conductive portion (401) may be another film layer that performs a conductive function, but is not limited thereto.

[0034] As one example, the material of the conductive part (401) includes tungsten. In other embodiments, the material of the conductive part may be other conductive materials, but is not limited thereto.

[0035] Specifically, the materials of the first etching stop layer (404) and the second etching stop layer (405) are the same, and a protective layer (409) is installed between the first etching stop layer (404) and the second etching stop layer (405), and the protective layer (409) acts as a protective layer for the side wall of the first etching stop layer (404) of the capacitor region (400A), thereby reducing the probability of contact between the acid cleaning solution and the first etching stop layer (404) during the subsequent acid cleaning process, and accordingly, lowering the probability of damage to the first etching stop layer (404) of the capacitor region (400A), thereby reducing the risk of the semiconductor structure collapsing due to damage to the first etching stop layer (404) of the capacitor region (400A), and further improving the reliability of the semiconductor structure.

[0036] As to be explained, in the method for forming a semiconductor structure, the first etching stop layer (404) performs an etching stop function during the process of forming the first electrode post (428), and the second etching stop layer (405) performs an etching stop function during the process of forming the slit opening (430).

[0037] It should also be explained that the first etching stop layer (404) and the second etching stop layer (405) are obtained by patterning the etching stop material layer. Therefore, the materials of the first etching stop layer (404) and the second etching stop layer (405) are the same, and during the subsequent acid washing process, the acid washing solution may also chemically react with the first etching stop layer (404). Accordingly, by installing a protective layer (409) between the first etching stop layer (404) and the second etching stop layer (405), even if the acid cleaning solution removes the second etching stop layer (405), the protective layer (409) can cover the side wall of the first etching stop layer (404) to block contact between the acid cleaning solution and the first etching stop layer (404), thereby significantly reducing the probability of the interior of the first etching stop layer (404) being eroded and further improving the stability of the semiconductor structure of the capacitor region (400A).

[0038] Specifically, the upper surface of the protective layer (409) coincides with the upper surface of the first etching stop layer (404), and accordingly, the protective layer (409) completely covers the side wall of the first etching stop layer (404), thereby reducing the probability of contact between the first etching stop layer (404) and the acid cleaning solution.

[0039] In this embodiment, the first etching stop layer (404) covers the surface of the capacitor region (400A) of the base structure (402), and accordingly, the first etching stop layer (404) performs an etching stop function during the process of forming the first electrode post (428).

[0040] As an example, when the materials of the first etching stop layer (404) and the second etching stop layer (405) are the same, the materials of the first etching stop layer (404) and the second etching stop layer (405) include aluminum oxide.

[0041] Specifically, there is an etching selectivity between the aluminum oxide and the material used in the first laminated structure (410), and the aluminum oxide can stop the etching during the step of forming the first electrode post (428). At the same time, the aluminum oxide has a low dielectric constant, which can reduce signal delay and interference, and since the aluminum oxide has good adhesion to metal materials, the aluminum oxide can form a stable interface with the first electrode post (428).

[0042] In this embodiment, the material of the protective layer (409) is silicon oxide.

[0043] Specifically, silicon oxide can act as a protective agent for the first etching stop layer (404), and since the acid cleaning solution is not easy to remove silicon oxide during the subsequent acid cleaning process, silicon oxide can act to block the acid cleaning solution.

[0044] In other embodiments, the material of the protective layer may be other materials resistant to acid washing, but is not limited thereto.

[0045] As to be explained, the first stacked structure (410) provides a process base for the installation of a subsequent capacitor structure. In this embodiment, the first stacked structure (410) comprises a silicon oxide layer (4101) and a silicon nitride layer (4102) that are sequentially and alternately deposited on a layer where the first etching stop layer (404) and the second etching stop layer (405) are located, and the top layer of the first stacked structure (410) is the silicon oxide layer (4101).

[0046] Specifically, after subsequently performing acid cleaning treatment on the silicon nitride layer (4102), a capacitor dielectric layer and a second electrode layer are formed in the space emitted by the silicon nitride layer (4102), and correspondingly, the silicon oxide layer (4101) acts to electrically block adjacent capacitor unit array layers. In addition, by making the uppermost layer of the first stacked structure (410) the silicon oxide layer (4101), the silicon oxide layer (4101) of the uppermost layer is made to provide protection for the capacitor subsequently formed. At the same time, by making the lowest layer of the first laminated structure (410) also a silicon oxide layer (4101), the silicon oxide layer (4101) of the lowest layer can provide protection to the upper part of the first etching stop layer (404), thereby reducing the probability of the acid cleaning solution and the upper part of the first etching stop layer (404) coming into contact with each other, that is, reducing the probability of the upper part of the first etching stop layer (404) being damaged.

[0047] Specifically, the first electrode post (428) can subsequently form a capacitor dielectric layer and a second electrode layer and a capacitor unit array layer formed in the space where the silicon nitride layer (4102) is emitted.

[0048] As one example, the material of the first electrode post (428) includes tungsten. In other embodiments, the material of the first electrode post may be other electrode materials, but is not limited thereto.

[0049] As to what needs to be explained, the present invention forms a slit opening (430) after forming a first electrode post (428), and the formed first electrode post (428) can provide structural support to remove all silicon nitride layers (4102) by acid washing.

[0050] Specifically, the slit opening (430) provides a process window for acid cleaning removal of the subsequent silicon nitride layer (4102), and the acid cleaning solution can flow into the silicon nitride layer (4102) through the slit opening (430), and the acid cleaning solution can remove the silicon nitride layer (4102).

[0051] As to be explained, if the second etching stop layer (405) is set as the etching stop position during the formation process of the slit opening (430), the probability of the slit opening (430) penetrating the base structure (402) is reduced, thereby reducing the risk of the slit opening (430) causing damage to the lower film layer of the base structure (402).

[0052] FIG. 8 shows a schematic diagram of a structure corresponding to a second embodiment of a semiconductor structure according to the present invention.

[0053] The similarities between the present embodiment and the first embodiment are not described further herein. The differences between the present embodiment and the first embodiment are as follows.

[0054] Referring to FIG. 8, the materials of the first etching stop layer (504) and the second etching stop layer (509) are different from each other, and a contact interface is formed between the first etching stop layer (504) and the second etching stop layer (509).

[0055] Specifically, a contact interface is formed between the first etching stop layer (504) and the second etching stop layer (509). Subsequently, during the process of acid cleaning the first laminated structure (510) through the slit opening (530), the acid cleaning solution may chemically react with the first etching stop layer (504), but since the materials of the first etching stop layer (504) and the second etching stop layer (509) are different, the second etching stop layer (509) of the logic region (500B) acts as a protective agent against the sidewall of the first etching stop layer (504) of the capacitor region (500A), thereby reducing the probability of the acid cleaning solution coming into contact with the first etching stop layer (504) during the subsequent acid cleaning process, and accordingly, lowering the probability of the first etching stop layer (504) of the capacitor region (500A) being damaged.

[0056] In this embodiment, the material of the first etching stop layer (504) is aluminum oxide, and the material of the second etching stop layer (509) is amorphous silicon.

[0057] Specifically, there is an etching selectivity between the aluminum oxide used in the first etching stop layer (504) and the material used in the first laminated structure (510) subsequently formed, and in the step of subsequently installing the first electrode post (528), the aluminum oxide can perform an etching stop action. At the same time, since the aluminum oxide has a low dielectric constant, it can reduce signal delay and interference, and since the aluminum oxide has good adhesion to metal materials, the aluminum oxide can form a stable interface with the first electrode post (528).

[0058] As to be explained, regarding the amorphous silicon used in the second etching stop layer (509), since the amorphous silicon is an acid-resistant material, it is not easily removed by acid washing wet etching, so it can provide protection to the first etching stop layer (504). At the same time, since there is an etching selectivity ratio between the amorphous silicon, the silicon nitride layer, and the silicon oxide layer, the second etching stop layer (509) can provide etching stop action during the process of forming the slit opening (530).

[0059] FIG. 9 shows a schematic diagram of a structure corresponding to a third embodiment of a semiconductor structure according to the present invention.

[0060] The similarities between the present embodiment and the first embodiment are not described further herein. The differences between the present embodiment and the first embodiment are as follows.

[0061] Referring to FIG. 9, the first etching stop layer (640) includes a plurality of first etching stop unit layers (604) installed at intervals from each other, and each first etching stop unit layer (604) covers the upper portion of a corresponding conductive portion (601).

[0062] As to be explained, the fact that each first etching stop unit layer (604) corresponds to covering the upper part of one conductive portion (601) means that in the method of forming a semiconductor structure, in the process of obtaining the first etching stop layer (640) through patterning treatment, the conductive portion (601) and the first etching stop layer (640) can be formed by using a photolithography mask plate that forms the conductive portion (601) through patterning (in other words, using the same photolithography mask plate), and thereby the number of photolithography mask plates used can be reduced, thereby reducing the cost of using photolithography mask plates.

[0063] In this embodiment, the semiconductor structure further includes a second insulating layer (610) covering the upper portion of a base structure (602) in which a plurality of first etching stop unit layers (604) are exposed, and the upper surfaces of the second insulating layer (610) and the first etching stop layer (640) coincide with each other, that is, the plurality of first etching stop unit layers (604) are embedded in the second insulating layer (610) with a gap between them.

[0064] In this embodiment, the second insulating layer (610) and the protective layer (609) are formed integrally.

[0065] Specifically, the fact that the second insulating layer (610) and the protective layer (609) are integrally formed means that the second insulating layer (610) and the protective layer (609) are formed at the same stage during the process of forming the semiconductor structure. In other words, during the process of forming the second etching stop layer, the insulating material between the second etching stop layer and the first etching stop layer (640) is used as the protective layer (609), and the protective layer (609) acts as a protective layer for the sidewall of the first etching stop layer (640), thereby reducing the risk of the first etching stop layer (640) being removed by the acid cleaning solution.

[0066] As an example, the material of the second insulating layer (610) is silicon oxide.

[0067] Accordingly, embodiments of the present invention further provide a method for forming a semiconductor structure. Among these, FIGS. 10 to 18 show schematic diagrams of structures corresponding to each step of a first embodiment of the method for forming a semiconductor structure according to the present invention.

[0068] Referring to FIG. 10, a base structure (102) is provided, wherein the base structure (102) has a capacitor region (100A) and an adjacent logic region (100B), and the base structure (102) includes a first insulating layer (100) and a conductive portion (101) embedded in the first insulating layer (100) at a distance from each other, wherein the conductive portion (101) is located in the capacitor region (100A) and the first insulating layer (100) exposes the upper surface of the conductive portion (101).

[0069] Specifically, the base structure (102) provides a process platform for a subsequent method of forming a semiconductor structure.

[0070] As an example, a semiconductor structure is a capacitor structure.

[0071] In the capacitor structure, the capacitor area (100A) is used as an area for storing data, and the logic area (100B) is used as an area for controlling data reading and writing operations.

[0072] As to be explained, the first insulating layer (100) acts to electrically block adjacent conductive parts (101).

[0073] The first insulating layer (100) exposes the upper surface of the conductive portion (101), and in the process of subsequently forming the first electrode post, the first electrode post penetrates the first laminated structure and the first etching stop layer that are subsequently formed, and accordingly, the first electrode post can be contact-connected with the conductive portion (101).

[0074] As an example, the material of the first insulating layer (100) is silicon oxide.

[0075] In another embodiment, the material of the first insulating layer (100) may be a different insulating material, but is not limited thereto.

[0076] Specifically, the conductive portion (101) is intended to be electrically connected to the first electrode post subsequently formed.

[0077] As an example, in a 1T1C (one transistor and one capacitor) capacitor, the conductive part (101) is used as a drain electrode.

[0078] In another embodiment, the conductive portion (101) may be another film layer that performs a conductive function, but is not limited thereto.

[0079] As an example, the material of the conductive part (101) is tungsten.

[0080] Referring to FIGS. 11 to 13b, an etching stop structure is formed on a base structure (102), wherein the etching stop structure comprises: a first etching stop layer (104) covering the upper surface of the base structure (102) of the capacitor region (100A); a second etching stop layer (105) located in the logic region (100B) and covering the upper surface of the first insulating layer (100), and located in the same layer as the first etching stop layer (104) and having upper surfaces that coincide with each other; wherein the materials of the first etching stop layer (104) and the second etching stop layer (105) are the same, and the first etching stop layer (104) and the second etching stop layer (105) are separated by a protective layer (109).

[0081] Specifically, the materials of the first etching stop layer (104) and the second etching stop layer (105) are the same, and a protective layer (109) is installed between the first etching stop layer (104) and the second etching stop layer (105), and the protective layer (109) acts as a protective layer for the side wall of the first etching stop layer (104) of the capacitor region (100A), thereby reducing the probability of contact between the acid cleaning solution and the first etching stop layer (104) during the subsequent acid cleaning process, and accordingly, the probability of damage to the first etching stop layer (104) of the capacitor region (100A) is lowered, thereby reducing the risk of the semiconductor structure collapsing due to damage to the first etching stop layer (104) of the capacitor region (100A) and further improving the reliability of the semiconductor structure.

[0082] In this embodiment, the step of forming an etching stop structure on a base structure (102) comprises: forming an etching stop material layer (103) that covers the entire surface of the base structure (102) as shown in FIG. 11; and forming a first etching stop layer (104) and a second etching stop layer (105) spaced apart from each other by patterning the etching stop material layer (103) as shown in FIG. 12, wherein the first etching stop layer (104) covers the surface of the capacitor region (100A) of the base structure (102) and the second etching stop layer (105) covers the surface of the logic region (100B) of the base structure (102). As shown in FIG. 13a, a protective layer (109) is formed by filling a protective material into a groove formed by surrounding the first etching stop layer (104) and the second etching stop layer (105) after patterning treatment and flattening the groove, wherein the upper surface of the protective layer (109) coincides with the upper surface of the first etching stop layer (104) and the second etching stop layer (105), and the first etching stop layer (104) and the second etching stop layer (105) are separated by the protective layer (109).

[0083] As an example, the step of patterning the etching stop material layer (103) to form a first etching stop layer (104) and a second etching stop layer (105) spaced apart from each other includes removing the etching stop material layer (103) at the boundary position between the capacitor region (100A) and the logic region (100B), making the remaining etching stop material layer (103) located in the capacitor region (100A) the first etching stop layer (104), and making the remaining etching stop material layer (103) located in the logic region (100B) the second etching stop layer (105).

[0084] In this embodiment, the etching stop material layer (103) at the boundary location of the capacitor region (100A) and the logic region (100B) is removed through an optional etching process.

[0085] The first etching stop layer (104) performs an etching stop function during the process of subsequently forming the first electrode post, and the second etching stop layer (105) performs an etching stop function during the process of subsequently forming the slit opening.

[0086] As to be explained, the first etching stop layer (104) and the second etching stop layer (105) are obtained by patterning the etching stop material layer (103), so the materials of the first etching stop layer (104) and the second etching stop layer (105) are the same, and in the subsequent acid washing process, the acid washing solution can also chemically react with the first etching stop layer (104). Accordingly, by installing a protective layer (109) between the first etching stop layer (104) and the second etching stop layer (105), even if the acid cleaning solution removes the second etching stop layer (105), the protective layer (109) covers the side wall of the first etching stop layer (104), thereby blocking contact between the acid cleaning solution and the first etching stop layer (104), and thus significantly reducing the probability of the interior of the first etching stop layer (104) being eroded, and furthermore, improving the stability of the semiconductor structure of the capacitor region (100A).

[0087] As an example, a planarization process includes a chemical mechanical polishing process.

[0088] In this embodiment, the material of the first etching stop layer (104) and the second etching stop layer (105) is aluminum oxide.

[0089] Specifically, there is an etching selectivity between the aluminum oxide and the material used to form the subsequent first laminated structure, and the aluminum oxide can stop the etching in the step of subsequently forming the first electrode post receiving hole. At the same time, since the aluminum oxide has a low dielectric constant, it can reduce signal delay and interference, and since the aluminum oxide has good adhesion to metal materials, the aluminum oxide can form a stable interface with the first electrode post.

[0090] In this embodiment, the material of the protective layer (109) is silicon oxide.

[0091] Specifically, silicon oxide can act as a protective agent for the first etching stop layer (104), and since the silicon oxide is not easily removed by the acid cleaning solution during the subsequent acid cleaning process, the silicon oxide can act as a blocking agent.

[0092] In this embodiment, as shown in FIG. 13b, the protective layer (109) and the first silicon oxide layer (1101) of the first laminated structure subsequently formed are integrally molded.

[0093] Specifically, by integrally molding the protective layer (109) and the first silicon oxide layer of the first laminated structure subsequently formed, the deposition step for forming the first laminated structure can be reduced, thereby lowering process costs.

[0094] In this embodiment, a protective material layer is formed by filling a groove formed by surrounding the first etching stop layer (104) and the second etching stop layer (105) after patterning treatment and flattening the groove, and the protective material layer includes a protective layer (109) and a first silicon oxide layer (1101).

[0095] Continuing with reference to FIGS. 13a to 14b, a first stacked structure (110) is formed on an etching stop structure.

[0096] As to be explained, the first stacked structure (110) provides a process basis for the formation of a subsequent capacitor structure.

[0097] As one example, the first stacked structure (110) comprises a silicon oxide layer (1101) and a silicon nitride layer (1102) that are sequentially and alternately deposited on the first etching stop structure, and the top layer of the first stacked structure (110) is the silicon oxide layer (1101).

[0098] Specifically, after subsequently performing acid cleaning treatment on the silicon nitride layer (1102), a capacitor dielectric layer and a second electrode layer are formed in the space emitted by the silicon nitride layer (1102), and correspondingly, the silicon oxide layer (1101) acts to electrically block adjacent capacitor unit array layers. In addition, the uppermost layer of the first stacked structure (110) is the silicon oxide layer (1101), and the silicon oxide layer (1101) of the uppermost layer acts as a protective layer for the capacitor structure subsequently formed. At the same time, the lowest layer of the first laminated structure (110) is also a silicon oxide layer (1101), and the silicon oxide layer (1101) of the lowest layer acts as a protective agent for the upper part of the first etching stop layer (104), thereby reducing the probability of the acid cleaning solution and the upper part of the first etching stop layer (104) coming into contact with each other, that is, reducing the probability of the upper part of the first etching stop layer (104) being damaged.

[0099] As an example, the process of forming the first laminated structure (110) includes a thin film deposition process.

[0100] Referring to FIGS. 15 and 16, a first electrode post receiving hole (126) is formed penetrating the first laminated structure (110) and the first etching stop layer (104), and the first electrode post receiving hole (126) exposes the conductive portion (101); a first electrode post (128) is manufactured within the first electrode post receiving hole (126), and the first electrode post (128) is contact-connected to the conductive portion (101).

[0101] Specifically, the first electrode post (128) can subsequently form a capacitor dielectric layer and a second electrode layer and a capacitor structure formed in the space where the silicon nitride layer (1102) is emitted.

[0102] In this embodiment, the process of forming the first electrode post receiving hole (126) includes a dry etching process.

[0103] In this embodiment, after forming the first electrode post (128), a slit opening is formed that penetrates the first laminated structure (110).

[0104] Referring to FIG. 17, a slit opening (130) is formed penetrating the first laminated structure (110), and the slit opening (130) exposes the second etching stop layer (105).

[0105] Specifically, the slit opening (130) provides a process window for acid cleaning removal of the subsequent silicon nitride layer (1102), thereby allowing the acid cleaning solution to flow into the silicon nitride layer (1102) through the slit opening (130) and enabling the acid cleaning solution to remove the silicon nitride layer (1102).

[0106] In this embodiment, the step of forming a slit opening (130) includes the step of performing a patterning process on the first stacked structure (110) with the second etching stop layer (105) as the etching stop position, thereby forming a slit opening (130) that penetrates the first stacked structure (110) on the upper part of the second etching stop layer (105).

[0107] Specifically, if the second etching stop layer (105) is set as the etching stop position, the probability of the slit opening (130) penetrating the base structure (102) is reduced, thereby reducing the risk of the slit opening (130) damaging the lower film layer of the base structure (102).

[0108] As an example, the process of forming the slit opening (130) includes a dry etching process.

[0109] Referring to FIG. 18, after forming a slit opening (130), the above-described forming method further includes the step of performing acid washing removal on all silicon nitride layers (1102) of the first laminated structure (110) through the slit opening (130).

[0110] Specifically, when acid cleaning is performed on the silicon nitride layer (1102), the space occupied by the silicon nitride layer (1102) can be released, which is advantageous for subsequently forming a capacitor dielectric layer and a second electrode layer in the space released by the silicon nitride layer (1102) to form a capacitor structure.

[0111] In this embodiment, the method further includes the step of removing all silicon nitride layers (1102) of the first laminated structure (110) through the slit opening (130), and simultaneously removing part or all of the second etching stop layer (105) by performing acid washing.

[0112] Specifically, the materials of the first etching stop layer and the second etching stop layer are the same, and the materials of the first etching stop layer and the second etching stop layer include aluminum oxide, and a chemical reaction occurs between the acid cleaning solution and the aluminum oxide to remove part or all of the second etching stop layer (105).

[0113] As an example, in the process of removing all silicon nitride layers (1102) of the first laminated structure (110), the acid cleaning solution contains phosphoric acid.

[0114] FIGS. 19 to 22 show schematic diagrams of structures corresponding to each step of a second embodiment of the method for forming a semiconductor structure according to the present invention.

[0115] The similarities between the present embodiment and the first embodiment are not described further herein. The differences between the present embodiment and the first embodiment are as follows.

[0116] Referring to FIGS. 19 to 22, the materials of the first etching stop layer (204) and the second etching stop layer (209) are different from each other, and a contact interface is formed between the first etching stop layer (204) and the second etching stop layer (209).

[0117] Specifically, a contact interface is formed between the first etching stop layer (204) and the second etching stop layer (209). Subsequently, during the process of acid cleaning the first laminated structure (210) through the slit opening, the acid cleaning solution may chemically react with the first etching stop layer (204), but since the materials of the first etching stop layer (204) and the second etching stop layer (209) are different, the second etching stop layer (209) acts as a protective agent for the sidewall of the first etching stop layer (204) of the capacitor region (200A), and reduces the probability of the acid cleaning solution coming into contact with the first etching stop layer (204) during the subsequent acid cleaning process, thereby reducing the probability of the first etching stop layer (204) of the capacitor region (200A) being damaged.

[0118] As an example, the step of forming an etching stop structure on a base structure (202) comprises: forming an etching stop material layer (203) covering the entire surface of the base structure (202) as shown in FIG. 19; and patterning the etching stop material layer (203) to form a first etching stop layer (204) and a second etching stop layer receiving groove (205) spaced apart from each other as shown in FIG. 20. As shown in FIGS. 21 and 22, the method includes the step of filling the second etching stop layer receiving groove (205) with a second etching stop material layer (208) and performing a surface flattening treatment to form a second etching stop layer (209), wherein the materials of the first etching stop layer (204) and the second etching stop layer (209) are different from each other, and a contact interface is formed between the first etching stop layer (204) and the second etching stop layer (209).

[0119] Specifically, the second etching stop layer receiving groove (205) provides a space position to fill the second etching stop layer (209).

[0120] In this embodiment, the step of forming a first etching stop layer (204) and a second etching stop layer receiving groove (205) spaced apart from each other includes: forming a patterned mask layer on top of an etching stop material layer (203), wherein the mask layer exposes the upper surface of the etching stop material layer (203) in the logic region (200B); performing a patterning process on the etching stop material layer (203) using the mask layer as a mask to remove the etching stop material layer (203) in the logic region (200B), thereby forming a second etching stop layer receiving groove (205) in the logic region (200B), and making the remaining etching stop material layer (203) located in the capacitor region (200A) the first etching stop layer (204).

[0121] In this embodiment, the step of performing surface flattening treatment on the second etching stop material layer (208) includes the step of performing flattening treatment on the second etching stop material layer (208) which is higher than the upper surface of the first etching stop layer (204), by setting the upper surface of the first etching stop layer (204) as the stop position.

[0122] In this embodiment, the material of the first etching stop layer (204) includes aluminum oxide, and the material of the second etching stop layer (209) includes amorphous silicon.

[0123] Specifically, there is an etching selectivity between the aluminum oxide used in the first etching stop layer (204) and the material used to form the subsequent first laminated structure (210), and the aluminum oxide can perform an etching stop action in the step of subsequently forming the first electrode post receiving hole. At the same time, since the aluminum oxide has a low dielectric constant, signal delay and interference can be reduced, and since the aluminum oxide has good adhesion to metal materials, a stable interface can be formed between the aluminum oxide and the first electrode post (228).

[0124] As to be explained, the amorphous silicon resistant to acid washing used in the second etching stop layer (209) can provide protection to the first etching stop layer (204) during the subsequent acid washing process. At the same time, since there is an etching selectivity between the amorphous silicon, the silicon nitride layer, and the silicon oxide layer, the second etching stop layer (209) can provide an etching stop function during the process of forming a slit opening.

[0125] FIGS. 23 to 27 show schematic diagrams of structures corresponding to each step of a third embodiment of the method for forming a semiconductor structure according to the present invention.

[0126] The similarities between the present embodiment and the first embodiment are not described further herein. The differences between the present embodiment and the first embodiment are as follows.

[0127] Referring to FIGS. 23 to 27, the step of forming an etching stop structure on a base structure (302) comprises: forming an etching stop material layer (303) that covers the entire surface of the base structure (302) as shown in FIG. 23; and forming a first etching stop layer (360) by patterning the etching stop material layer (303) as shown in FIG. 24, wherein the first etching stop layer (360) comprises a plurality of first etching stop unit layers (304), and each first etching stop unit layer (304) covers the upper portion of a conductive part (301) in a corresponding manner. As shown in FIG. 25, a second insulating material layer is filled into the spacing groove between a plurality of first etching stop unit layers (304) after patterning treatment, and a surface flattening treatment is performed to form a second insulating layer (308), wherein the upper surface of the second insulating layer (308) and the upper surface of the first etching stop layer (360) coincide; as shown in FIG. 26, a second etching stop layer receiving groove (312) penetrating the second insulating layer (308) is formed; As shown in FIG. 27, the second etching stop layer (313) is formed by filling the second etching stop layer receiving groove (312) with a second etching stop material layer (303) and performing a surface flattening treatment, and the second insulating material layer between the second etching stop layer (313) and the first etching stop layer (360) is formed as a protective layer (320), and the materials of the first etching stop layer (360) and the second etching stop layer (313) are the same.

[0128] As to be explained, each first etching stop unit layer (304) corresponds to covering the upper part of one conductive portion (301), which means that in the process of forming the first etching stop layer (360) by patterning the etching stop material layer (303), the conductive portion (301) and the first etching stop layer (360) can be formed by using a photolithography mask plate that forms the conductive portion (301) through patterning (in other words, using the same photolithography mask plate), thereby reducing the number of photolithography mask plates used and reducing the cost of using photolithography mask plates.

[0129] Specifically, the second insulating layer (308) is intended to provide an electrical blocking action with respect to the adjacent first etching stop unit layer (304) to reduce the risk of leakage between the adjacent first etching stop unit layers (304).

[0130] The second insulating layer (308) covers the upper part of the first insulating layer (300) of the capacitor region.

[0131] The second etching stop layer receiving groove (312) provides a spatial position to form the second etching stop layer (313).

[0132] As to be explained, in the process of forming the second etching stop layer (313), the second insulating material layer between the second etching stop layer (313) and the first etching stop layer (360) is made into a protective layer (320), and the protective layer (320) acts as a protective layer for the side wall of the first etching stop layer (360), thereby reducing the risk of the first etching stop layer (360) being removed by the acid cleaning solution.

[0133] As an example, the material of the second insulating layer (308) includes silicon oxide.

[0134] Although the present invention has been disclosed as above, it is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the invention. Accordingly, the scope of protection of the present invention should be based on the scope defined in the claims.

Claims

Claim 1 A semiconductor structure comprises a base structure, a first etching stop layer, a second etching stop layer, a first stacked structure, a plurality of first electrode posts and a slit opening, wherein the base structure comprises a capacitor region and a logic region adjacent thereto, and the capacitor region and the logic region are intended to be used as a capacitor unit array region; the base structure comprises a first insulating layer and a plurality of conductive portions embedded in the first insulating layer at a distance from each other, wherein the conductive portions are located in the capacitor region and the first insulating layer exposes the upper surface of the conductive portions; the first etching stop layer is located in the capacitor region and covers at least the upper portion of the conductive portions; the second etching stop layer is located in the logic region and covers the upper portion of the first insulating layer, wherein the second etching stop layer and the first etching stop layer are located in the same layer and the upper surfaces of both coincide with each other; the first stacked structure covers the layer where the first etching stop layer and the second etching stop layer are located; and each of the first electrode posts is the first stacked structure and the first A semiconductor structure characterized by being installed through an etching stop layer and contact-connected to a corresponding conductive portion; wherein the slit opening penetrates the first stacked structure and exposes the second etching stop layer, the materials of the first etching stop layer and the second etching stop layer are the same, and the first etching stop layer and the second etching stop layer are separated by a protective layer, so that the protective layer protects the sidewall of the first etching stop layer during a process of acid-washing the first stacked structure through the slit opening; or wherein the materials of the first etching stop layer and the second etching stop layer are different, and a contact interface is formed between the first etching stop layer and the second etching stop layer, so that the second etching stop layer protects the sidewall of the first etching stop layer during a process of acid-washing the first stacked structure through the slit opening. Claim 2 A semiconductor structure according to claim 1, wherein the first stacked structure comprises a silicon oxide layer and a silicon nitride layer that are sequentially and alternately cyclically deposited on a layer in which the first etching stop layer and the second etching stop layer are located, and the uppermost layer of the first stacked structure is a silicon oxide layer. Claim 3 A semiconductor structure according to claim 1, wherein the materials of the first etching stop layer and the second etching stop layer are the same, the materials of the first etching stop layer and the second etching stop layer include aluminum oxide, and the material of the protective layer includes silicon oxide. Claim 4 A semiconductor structure according to claim 1, wherein the materials of the first etching stop layer and the second etching stop layer are different from each other, the material of the first etching stop layer comprises aluminum oxide, and the material of the second etching stop layer comprises amorphous silicon. Claim 5 A semiconductor structure according to claim 1, characterized in that the first etching stop layer covers the surface of the capacitor region of the base structure. Claim 6 In claim 1, the first etching stop layer comprises a plurality of first etching stop unit layers installed at intervals from each other, and each of the first etching stop unit layers covers the upper portion of the corresponding conductive portion; the semiconductor structure further comprises a second insulating layer covering the upper portion of a base structure in which the plurality of the first etching stop unit layers are exposed, wherein the upper surface of the second insulating layer and the upper surface of the first etching stop layer coincide with each other, that is, the plurality of the first etching stop unit layers are embedded in the second insulating layer at intervals from each other. Claim 7 A semiconductor structure characterized in that, in claim 6, the second insulating layer and the protective layer are integrally molded; and the material of the second insulating layer comprises silicon oxide. Claim 8 A method for forming a semiconductor structure comprises: providing a base structure, wherein the base structure comprises a capacitor region and a logic region adjacent thereto, and the capacitor region and the logic region are to be used as a capacitor unit array region; wherein the base structure comprises a first insulating layer and a plurality of conductive portions embedded in the first insulating layer at a distance from each other, wherein the conductive portions are located in the capacitor region and the first insulating layer exposes the upper surface of the conductive portions; and forming an etching stop structure on the base structure, wherein the etching stop structure comprises a first etching stop layer and a second etching stop layer, wherein the first etching stop layer is located in the capacitor region and covers at least the upper portion of the conductive portions. The method comprises the steps of: forming the second etching stop layer located in the logic region and covering the upper portion of the first insulating layer, wherein the first etching stop layer and the second etching stop layer are located in the same layer and their upper surfaces coincide with each other; forming a first stacked structure on the etching stop structure; forming a plurality of first electrode post receiving holes penetrating the first stacked structure, wherein the first electrode post receiving holes expose the conductive portion; manufacturing a first electrode post within the first electrode post receiving holes, wherein the first electrode post and the conductive portion are contact-connected; and forming a slit opening penetrating the first stacked structure, wherein the slit opening exposes the second etching stop layer; wherein the materials of the first etching stop layer and the second etching stop layer are the same, and the first etching stop layer and the second etching stop layer are separated by a protective layer, so that in a process of acid-washing the first stacked structure through the slit opening, the protective layer is the first etching stop layer To protect the sidewalls;Alternatively, the materials of the first etching stop layer and the second etching stop layer are different from each other, and a contact interface is formed between the first etching stop layer and the second etching stop layer, so that the second etching stop layer is formed to protect the sidewall of the first etching stop layer during a process of acid cleaning the first stacked structure through the slit opening, characterized in that a method for forming a semiconductor structure.; Claim 9 In claim 8, the step of forming an etching stop structure on the base structure comprises: forming an etching stop material layer covering the entire surface of the base structure; forming a first etching stop layer and a second etching stop layer spaced apart from each other by patterning the etching stop material layer, wherein the first etching stop layer covers the surface of the capacitor region of the base structure and the second etching stop layer covers the surface of the logic region of the base structure; and forming a protective layer by filling a protective material into a groove formed by surrounding the first etching stop layer and the second etching stop layer after patterning and performing a planarization treatment, wherein the upper surface of the protective layer coincides with the upper surface of the first etching stop layer and the second etching stop layer, and the first etching stop layer and the second etching stop layer are spaced apart through the protective layer; characterized in that the method of forming a semiconductor structure comprises Claim 10 In claim 9, the first stacked structure comprises a silicon oxide layer and a silicon nitride layer that are sequentially and alternately deposited on the etching stop structure, the material of the protective layer is silicon oxide, and the protective layer and the first silicon oxide layer of the first stacked structure are integrally formed, and the forming method comprises the step of filling a protective material into a groove formed by surrounding the first etching stop layer and the second etching stop layer after patterning treatment and performing a planarization treatment to form a protective material layer, wherein the protective material layer comprises the protective layer and the first silicon oxide layer. Claim 11 A method for forming a semiconductor structure according to claim 8, wherein the step of forming an etching stop structure on the base structure comprises: a step of forming an etching stop material layer covering the entire surface of the base structure; a step of patterning the etching stop material layer to form a first etching stop layer and a second etching stop layer receiving groove spaced apart from each other; and a step of filling the second etching stop material layer into the second etching stop layer receiving groove and performing a surface planarization treatment to form a second etching stop layer; wherein the materials of the first etching stop layer and the second etching stop layer are different from each other, and a contact interface is formed between the first etching stop layer and the second etching stop layer. Claim 12 In claim 8, the step of forming an etching stop structure on the base structure comprises: forming an etching stop material layer covering the entire surface of the base structure; forming a first etching stop layer by patterning the etching stop material layer, wherein the first etching stop layer includes a plurality of first etching stop unit layers, and each of the etching stop unit layers corresponds to covering the upper portion of one conductive part; forming a second insulating material layer by filling a gap groove between the plurality of first etching stop unit layers after the patterning process and performing a surface flattening treatment, wherein the upper surface of the second insulating layer and the upper surface of the first etching stop layer are formed to coincide; forming a second etching stop layer receiving groove penetrating the second insulating layer; forming a second etching stop layer by filling a second etching stop material layer into the second etching stop layer receiving groove and performing a surface flattening treatment, and the second between the second etching stop layer and the first etching stop layer A method for forming a semiconductor structure comprising the step of making an insulating material layer the protective layer; wherein the materials of the first etching stop layer and the second etching stop layer are the same. Claim 13 A method for forming a semiconductor structure according to claim 8, wherein the first stacked structure comprises a silicon oxide layer and a silicon nitride layer that are sequentially and alternately deposited on the etching stop structure, and the uppermost layer of the first stacked structure is a silicon oxide layer; and after forming the slit opening, the forming method further comprises the step of performing acid washing removal on all silicon nitride layers of the first stacked structure through the slit opening. Claim 14 A method for forming a semiconductor structure according to claim 13, wherein the materials of the first etching stop layer and the second etching stop layer are the same, and the materials of the first etching stop layer and the second etching stop layer include aluminum oxide, and the material of the protective layer includes silicon oxide; and further comprising the step of removing all silicon nitride layers of the first stacked structure through the slit opening, and simultaneously removing part or all of the second etching stop layer by performing acid washing.

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