Communication between integrated circuit (IC) dies within a wafer-level fan-out package

Abstract

The embodiments described herein generally relate to communication between integrated circuit (IC) dies within a wafer-level fan-out package. In one embodiment, an electronic device comprises a wafer-level fan-out package. The wafer-level fan-out package comprises a first integrated circuit (IC) die, a second IC die, and a redistribution structure. The first IC die comprises a transmitter circuit. The second IC die comprises a receiver circuit. The redistribution structure comprises physical channels electrically connected to the transmitter circuit and the receiver circuit and between them. The transmitter circuit is configured to transmit a plurality of single-ended data signals and a differential clock signal to the receiver circuit through the physical channels. The receiver circuit is configured to capture data from the plurality of single-ended data signals using a first single-ended clock signal based on the differential clock signal.

Description

Technology Field

[0001] Government rights

[0002] The present invention was made with the support of the U.S. government under Contract No. HR 0011-19-3-0004 awarded by the Defense Advanced Research Projects Agency. The U.S. government holds specific rights in the present invention.

[0003] Technology field

[0004] Examples of the present disclosure generally relate to communication between integrated circuit (IC) dies within a wafer-level fan-out package. Background Technology

[0005] Recently, it has been observed that Moore's Law is slowing down. Due to this slowdown, the integration of complex systems has been pressured to shift from System-on-Chip (SoC) to Multi-Chip Modules (MCM), where multiple integrated circuit (IC) dies (or chips) are integrated within the same IC package. The advantages of MCM include enabling heterogeneous integration of IC dies from different process nodes and yield improvements through the integration of smaller IC dies with a lower probability of defect.

[0006] Generally, IC dies within an MCM need to communicate with each other. Due to the footprint and thermal constraints of the MCM, high-density, high-bandwidth, and low-power short-reach links are required for die-to-die communication. The ever-increasing data traffic in such die-to-die communication can make it more difficult to achieve short-reach links.

[0007] Signaling techniques such as single-ended and chord signaling have been used in die-to-die transceivers to improve bandwidth density compared to traditional differential signaling. Theoretically, pin-efficiency signaling methods can also be more power-efficient because the amount of capacitive load required for driving is reduced. However, the effectiveness of this signaling method depends heavily on the signal-to-noise ratio (SNR) of the received signal. Therefore, this signaling method can be extremely channel-dependent.

[0008] Another area that may limit bandwidth density and energy efficiency is packaging technology. The organic substrates used by most MCMs as interconnection means generally have relatively large linewidths and spacing, which can limit the achievable bandwidth density and energy efficiency.

[0009] The embodiments described herein generally relate to communication between integrated circuit (IC) dies within a wafer-level fan-out package. Various embodiments can achieve power-efficient and high-bandwidth communication and / or corresponding structures.

[0010] The embodiment described herein is an electronic device comprising a wafer-level fan-out package. The wafer-level fan-out package comprises a first integrated circuit (IC) die, a second IC die, and a redistribution structure. The first IC die comprises a transmitter circuit. The second IC die comprises a receiver circuit. The redistribution structure comprises physical channels electrically connected to the transmitter circuit and the receiver circuit and between them. The transmitter circuit is configured to transmit a plurality of single-ended data signals and a differential clock signal to the receiver circuit through the physical channels. The receiver circuit is configured to capture data from the plurality of single-ended data signals using a first single-ended clock signal based on the differential clock signal.

[0011] Another embodiment described herein is an electronic device. The electronic device includes a first transceiver circuit within a first IC die, a second transceiver circuit within a second IC die, and physical channels. The first IC die is placed within a wafer-level fan-out package. The second IC die is placed within a wafer-level fan-out package. The physical channels are located within a redistribution structure of the wafer-level fan-out package. The first transceiver circuit is configured to transmit a plurality of first single-ended data signals and a first differential clock signal to the second transceiver circuit through a first subset of physical channels. The second transceiver circuit is configured to transmit a plurality of second single-ended data signals and a second differential clock signal to the first transceiver circuit through a second subset of physical channels. The second transceiver circuit is configured to capture data from a plurality of first single-ended data signals using a first single-ended clock signal based on the first differential clock signal. The first transceiver circuit is configured to capture data from a plurality of second single-ended data signals using a second single-ended clock signal based on a second differential clock signal.

[0012] Another embodiment described herein is a method for operating an electronic device. A differential clock signal is generated based on a first single-ended clock signal by a single-ended differential converter circuit of a first transceiver circuit of a first IC die. The first IC die is placed within a wafer-level fan-out package. Parallel data is serialized based on the first single-ended clock signal by a serializer circuit of the first transceiver circuit. The serialized data and the differential clock signal from the serializer circuit are transmitted to a second transceiver circuit of a second IC die through a physical channel of the wafer-level fan-out package. The second IC die is placed within a wafer-level fan-out package. The serialized data is deserialized based on the differential clock signal by a deserializer circuit of the second transceiver circuit.

[0013] These and other aspects can be understood by referring to the following detailed description. Brief explanation of the drawing

[0014] To enable a detailed understanding of the features mentioned above, the description briefly summarized above may be explained in more detail by referring to some of the embodiments illustrated in the attached drawings. However, it should be noted that the attached drawings illustrate only typical exemplary embodiments and should not be construed as limiting the scope of the present invention. FIG. 1 is a cross-sectional view of an exemplary plurality of wafer-level fan-out (WLFO) packages according to some embodiments. FIG. 2 is a layout of an integrated circuit (IC) die and an encapsulant of a WLFO package of FIG. 1 according to some embodiments. FIG. 3 is a cross-sectional view of the WLFO package of FIG. 1 to illustrate an arrangement of metal patterns for physical channels according to some embodiments. FIGS. 4a and FIGS. 4b are circuit schematics of transceiver circuits that are communically coupled together according to some embodiments. FIG. 5 is a schematic diagram of a clock driver circuit according to some embodiments. FIG. 6 is a schematic diagram of a clock driver circuit according to some embodiments. FIG. 7 is a schematic circuit diagram of a programmable inverter according to some embodiments. FIG. 8 is a schematic circuit diagram of a signal driver circuit according to some embodiments. FIG. 9 is a circuit schematic of an impedance array according to some embodiments. FIG. 10 is a circuit schematic of an impedance array according to some embodiments. FIG. 11 is a flowchart of a method for operating an electronic device according to some embodiments. To facilitate understanding, the same reference numerals have been used as much as possible to denote common identical elements in the drawings. It is considered that elements of one example may be advantageously incorporated into other examples. Specific details for implementing the invention

[0015] The embodiments described herein generally relate to communication between integrated circuit (IC) dies within a wafer-level fan-out package. In some examples, an electronic device comprises a wafer-level fan-out package containing at least two IC dies, wherein each of the two IC dies comprises a transceiver circuit. The transmitter circuit of the transceiver circuit comprises a serializer circuit that serializes parallel data based on a single-ended clock signal and outputs the serialized data through one or more signal driver circuits via physical channels of a redistribution structure of the wafer-level fan-out package. The transmitter circuit also comprises a single-ended to differential (S2D) converter circuit that converts the single-ended clock signal into a differential clock signal that the transmitter circuit outputs through one or more signal driver circuits via physical channels of the redistribution structure. The receiver circuit of the transceiver circuit comprises a differential to single-ended (D2S) converter circuit that converts the differential clock signal received from the physical channels of the redistribution structure into a single-ended clock signal. The receiver includes a deserializer circuit that deserializes data captured from the physical channels of the redistribution structure based on a single-ended clock signal from a D2S converter circuit.

[0016] According to some examples, multiple single-ended data signals transmitted from a first IC die (e.g., from the transmitter circuit of the first IC die's transceiver circuit) to a second IC die (e.g., to the receiver circuit of the second IC die's transceiver circuit) share a differential clock signal. Thus, data communication can be source-synchronous. The receiver circuit may omit the clock data recovery (CDR) circuit, which can reduce the power consumption of the receiver circuit. The data signals may be single-ended (furthermore, they may be single-ended NRZ (Non-return to Zero) signals), which can reduce the area consumption for physical channels in the redistribution structure of a wafer-level fan-out package and reduce power consumption because one signal is transmitted per data signal (in contrast to two signals for the differential signal). In addition, when multiple single-ended data signals share a single differential clock signal (in contrast to, for example, each data signal having its own differential clock signal), area consumption in physical channels can be reduced and power consumption can be reduced. Generally, various examples can achieve power-efficient and high-bandwidth communication and / or corresponding structures. Other advantages can be achieved by other examples.

[0017] Various features are described below with reference to the drawings. It should be noted that the drawings may or may not be drawn to scale, and that elements of similar structure or function are represented by similar reference numerals throughout the drawings. It should be noted that these drawings are merely intended to facilitate the description of features. The drawings are not intended to describe the claimed invention in its entirety or to limit the scope of the claimed invention. Furthermore, the illustrated embodiments are not required to have all the aspects or advantages depicted. The aspects or advantages described in conjunction with a particular embodiment are not necessarily limited to that embodiment and may be practiced in any other embodiment even if they are not so illustrated or so explicitly described. Additionally, while the methods described herein may be described in a specific order of operation, other methods according to other embodiments may be implemented in various other orders of operation (e.g., including different serial or parallel performance of various operations) with more or fewer operations.

[0018] In the following description, various signals or data are described in relation to the operation of various circuits. The described signals or data represent corresponding nodes to which the signals or data are applied or propagated, and also represent nodes that are communically coupled and / or electrically connected. For example, the description of a signal or data output from a first circuit and input to a second circuit indicates that the output node of the first circuit (where the signal or data is output from the first circuit) is communically coupled and / or electrically connected to the input node of the second circuit (where the signal or data is input to the second circuit). Explicit descriptions of such nodes may be omitted in the description below, but those skilled in the art will readily understand the existence of the nodes.

[0019] FIG. 1 illustrates a cross-sectional view of an exemplary plurality of die wafer-level fan-out (WLFO) packages (100) according to some embodiments. In some embodiments, the WLFO packages (100) may be plurality of die integrated fan-out (InFO) packages. In other embodiments, other configurations of WLFO packages may be implemented.

[0020] As illustrated, the WLFO package (100) includes integrated circuit (IC) dies (102-1, 102-2) (collectively or individually, IC die(s) (102)). The WLFO package (100) may include two or more IC dies (102). For example, the WLFO package (100) may additionally include IC dies (102-3, 102-4) as described below. Each IC die (102) may be or include a processor, an application-specific integrated circuit (ASIC), a programmable integrated circuit (e.g., a field-programmable gate array (FPGA) or a complex programmable logic device (CPLD)), a memory die, etc.

[0021] Each IC die (102) has conductive pillars (104) (e.g., metal pillars such as copper pillars) disposed on conductive pads (106) (e.g., metal pads such as aluminum pads) disposed on the active side of each IC die (102). The conductive pillars (104) are laterally encapsulated by at least a dielectric material (108). The conductive pillars (104) are on the active side of each IC die (102) and form an electrical connection between the redistribution structure (110) and the circuits of each IC die (102).

[0022] The encapsulating material (112) laterally encapsulates the IC die (102). The encapsulating material (112) may be a molding compound, epoxy, etc. A redistribution structure (110) is on the IC die (102) and the encapsulating material (112). The redistribution structure (110) includes dielectric layers (120, 122, 124, 126) and metal pattern layers (130, 132, 134) disposed therein. Each dielectric layer (120, 122, 124, 126) may be, for example, polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. Each metal pattern of the metal pattern layer (130, 132, 134) may be a metal line and / or via or may include a metal line and / or via, and may be formed on each dielectric layer (120, 122, 124) and / or may be formed on the metal pattern of the lower metal pattern layer (130, 132) or the conductive pillar (104) through each dielectric layer (120, 122, 124). For example, the metal pattern layer (130) is placed on the dielectric layer (120), and at least some of the metal patterns of the metal pattern layer (130) are formed to contact each conductive pillar (104) through the dielectric layer (120). The dielectric layer (122) is placed on the metal pattern layer (130) and the dielectric layer (120). A metal pattern layer (132) is disposed on a dielectric layer (122), and at least some of the metal patterns of the metal pattern layer (132) are formed to contact each metal pattern of the metal pattern layer (130) through the dielectric layer (122). A dielectric layer (124) is disposed on the metal pattern layer (132) and the dielectric layer (122). A metal pattern layer (134) is disposed on the dielectric layer (124), and at least some of the metal patterns of the metal pattern layer (134) are formed to contact each metal pattern of the metal pattern layer (132) through the dielectric layer (124). A dielectric layer (126) is disposed on the metal pattern layer (134) and the dielectric layer (124).The metal patterns of the metal pattern layers (130, 132, 134) may be, for example, copper, titanium, tungsten, aluminum, etc., or may include these. The metal patterns of the metal pattern layers (130, 132, 134) within the redistribution structure (110) may interconnect IC dies (102) and may be used to avoid or route connections from IC dies (102) to under bump metallization (UBM) (140) and bumps (142). The redistribution structure (110) may include any number of dielectric layers and metal pattern layers.

[0023] The UBM (140) is formed on the outer dielectric layer (126) and extends through the outer dielectric layer (126) to the metal patterns of the metal pattern layer (134). In some examples, the UBM (140) may be in the form of a chrome / chrome-copper alloy / copper / gold, a titanium / titanium tungsten / copper, a copper / nickel / gold, or may include various forms of metal layers.

[0024] The bumps (142) are attached to the UBM (140). The bumps (142) may be C4 (controlled collapse chip connection) bumps that may include a conductive material such as, for example, solder (e.g., lead-free solder), copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. The bumps (142) may also be attached to a package substrate to allow the WLFO package (100) to be attached to the package substrate.

[0025] The IC die (102-1) has a lateral sidewall (152-1), and the IC die (102-2) has a lateral sidewall (152-2). The lateral sidewalls (152-1, 152-2) are adjacent to and face each other in the WLFO package (100). The lateral sidewalls (152-1, 152-2) are encapsulated and bonded by a sealing material (112). A cross-section AA is illustrated for orientation of subsequent drawings. The XYZ axes are also illustrated for orientation purposes. The cross-section AA is lateral between the lateral sidewalls (152-1, 152-2) and penetrates the redistribution structure (110).

[0026] FIG. 2 illustrates the layout of an IC die (102) and a sealing material (112) of a WLFO package (100) according to some embodiments. The layout shows IC dies (102-1, 102-2, 102-3, 102-4) laterally encapsulated by the sealing material (112). The layout also schematically illustrates transceiver circuits (202-1, 202-2, 202-3, 202-4) (collectively or individually, transceiver circuit(s) (202)). Each transceiver circuit (202) is placed on each IC die (102). Physical channels (204-12, 204-21, 204-34, 204-43) are schematically illustrated. A physical channel (204-12) is connected from the transmitter circuit of the transceiver circuit (202-1) on the IC die (102-1) to the receiver circuit of the transceiver circuit (202-2) on the IC die (102-2). A physical channel (204-21) is connected from the transmitter circuit of the transceiver circuit (202-2) on the IC die (102-2) to the receiver circuit of the transceiver circuit (202-1) on the IC die (102-1). A physical channel (204-34) is connected from the transmitter circuit of the transceiver circuit (202-3) on the IC die (102-3) to the receiver circuit of the transceiver circuit (202-4) on the IC die (102-4). The physical channel (204-43) is connected from the transmitter circuit of the transceiver circuit (202-4) on the IC die (102-4) to the receiver circuit of the transceiver circuit (202-3) on the IC die (102-3). Different layouts of the IC die and different configurations of the physical channel may be implemented in other embodiments.

[0027] Physical channels (204-12, 204-21) include metal patterns of metal pattern layers (130, 132, 134) within a redistribution structure (110) interconnecting IC die (102-1) and IC die (102-2). Physical channels (204-34, 204-43) include metal patterns of metal pattern layers (130, 132, 134) of a redistribution structure (110) interconnecting IC die (102-3) and IC die (102-4). In some embodiments, physical channels (204-12, 204-21, 204-34, 204-43) do not include metal patterns (e.g., metal lines) within the metal pattern layer (e.g., metal pattern layer (134)) of the redistribution structure (110) furthest from the IC die (102).

[0028] FIG. 3 illustrates a cross-section of a WLFO package (100) to illustrate an arrangement of metal patterns for physical channels according to some embodiments. The cross-section of FIG. 3 is cross-section AA of FIG. 1 and FIG. 2. The cross-section of FIG. 3 shows patterns for channel metal lines and shielding metal lines. The metal patterns in the cross-section are, for example, metal lines extending between the IC dies (102-1, 102-2). A metal pattern layer (130) comprises alternately arranged channel metal lines (130-C) and shielding metal lines (130-S). A metal pattern layer (132) comprises alternately arranged channel metal lines (132-C) and shielding metal lines (132-S). The channel metal lines (130-C, 132-C) form a checkerboard pattern with the shielding metal lines (130-S, 132-S). The metal pattern layer (134) includes shielding metal lines (134-S) or is composed of shielding metal lines (134-S) in the illustrated cross-section.

[0029] Each channel metal line (130-C, 132-C) of the cross-section forms at least a portion of the physical channel (204-12, 204-21) in some embodiments. The shielding metal lines (130-S, 132-S, 134-S) are configured to be electrically connected to the ground potential during operation and / or to form a ground node. In other embodiments, the shielding metal lines (130-S, 132-S, 134-S) are configured to be electrically connected to the power supply voltage VDD during operation and / or to form a power supply node VDD. Due to the checkerboard pattern, there are no channel metal lines (130-C, 132-C) directly adjacent to other channel metal lines (130-C, 132-C) laterally or vertically. For example, the channel metal line (132-C) of FIG. 3 may have a shielding metal line (134-S) immediately above the channel metal line (132-C), a shielding metal line (130-S) immediately below the channel metal line (132-C), and each shielding metal line (132-S) extending laterally from the channel metal line (132-C). This pattern can reduce crosstalk between channel metal lines, which can reduce crosstalk between physical channels (204-12, 204-21). Those skilled in the art will readily understand that this pattern can be extended laterally and / or vertically to accommodate any number of physical channels. Such a pattern can be implemented for metal lines extending between IC dies (102-3, 102-4) for physical channels (204-34, 204-43).

[0030] FIGS. 4a and 4b illustrate schematic diagrams of transceiver circuits (202-1, 202-2) coupled together communicably according to some embodiments. As will be readily understood by those skilled in the art, similar schematic diagrams may be implemented for transceiver circuits (202-3, 202-4). FIGS. 4a and 4b illustrate the transmitter circuit (202-1T) of transceiver circuit (202-1) and the receiver circuit (202-2R) of transceiver circuit (202-2). The receiver circuit (202-1R) of transceiver circuit (202-1) is generally illustrated, and the transmitter circuit (202-2T) of transceiver circuit (202-2) is generally illustrated. The transmitter circuit (202-2T) may implement a schematic circuit as illustrated for the transmitter circuit (202-1T), and the receiver circuit (202-1R) may implement a schematic circuit as illustrated for the receiver circuit (202-2R), and the transmitter circuit (202-2T) and the receiver circuit (202-1R) may be communically coupled as the transmitter circuit (202-1T) and the receiver circuit (202-2R). Those skilled in the art will easily understand such implementations, and thus a detailed description of the transmitter circuit (202-2T) and the receiver circuit (202-1R) is omitted for brevity.

[0031] The circuit schematics illustrated in the following drawings are illustrated and described with details to clearly illustrate and represent various aspects of the embodiments. Other embodiments may implement more general applications of the illustrated embodiments without the illustrated details and / or with other details.

[0032] The transmitter circuit (202-1T) comprises a buffer circuit (402, 404), a clock driver circuit (406), a first bank of serializer circuits (410-1, 410-2, 410-3, 410-4), a first bank of single-ended differential (S2D) converter circuits (412-1, 412-2), a first bank of clock driver circuits (414-1, 414-2, 414-3, 414-4), a retimer circuit (418), a second bank of serializer circuits (420-1, 420-2, 420-3, 420-4), a second bank of S2D converter circuits (422-1, 422-2), and clock driver circuits (424-1, 424-2, 424-3). It includes the second bank of 424-4) and the signal driver circuit (428).

[0033] In the illustrated embodiment, the buffer circuits (402) may include 64 buffer circuits, each buffer circuit having an input node electrically connected to a data lane from an interface circuit (not shown) of the IC die (102-1) and an output node electrically connected to a data lane of the transmitter circuit (202-1T). Thus, 64 data lanes (" / 64") electrically connected to the input nodes of the buffer circuits (402) are illustrated, and a total of 64 data lanes (" / 32", " / 16", and " / 16") electrically connected to the output nodes of the buffer circuits (402) are illustrated. Similarly, in the illustrated embodiment, the buffer circuits (404) may include 64 buffer circuits, each buffer circuit having an input node electrically connected to a data lane from an interface circuit of the IC die (102-1) and an output node electrically connected to a data lane of the transmitter circuit (202-1T). Accordingly, 64 data lanes (" / 64") electrically coupled to the input nodes of the buffer circuits (404) are shown, and a total of 64 data lanes (" / 32", " / 16", and " / 16") electrically coupled to the output nodes of the buffer circuits (402) are shown. The buffer circuits (402, 404) are configured to receive parallel data from each of the 64 data lanes and output parallel data to each of the 64 data lanes of the transmitter circuit (202-1T).

[0034] In the illustrated embodiment, the clock driver circuit (406) includes a capacitor, a resistor, and two buffer circuits. The capacitor has a first terminal electrically connected to a clock node (CLK) from an interface circuit of the IC die (102-1). The second terminal of the capacitor (opposite to the first terminal) is electrically connected to the input node of the first buffer and the first terminal of the resistor. The output node of the first buffer and the second terminal of the resistor (opposite to the first terminal) are electrically connected together and are electrically connected to the input node of the second buffer. The output node of the second buffer is the output node of the clock driver circuit (406). In the illustrated embodiment, the clock driver circuit (406) is configured to receive a single-ended clock signal on the clock node and drive the single-ended clock signal as an output signal on the clock lane (" / 1").

[0035] In the illustrated embodiment, each serializer circuit (410-1, 410-2, 410-3, 410-4, 420-1, 420-2, 420-3, 420-4) includes a pair of 8-to-4 serializers. Each 8-to-4 serializer is configured to receive data from 8 data lanes, serialize the received data, and output the serialized data to 4 data lanes. Each 8-to-4 serializer is configured to serialize data based on a single-ended clock signal. In other embodiments, the serializer circuits may be implemented differently, the serialization ratio may be different, and / or the number of serializers may be different.

[0036] Each serializer circuit (410-1, 410-2) has input nodes electrically connected to each output node of the buffer circuit (402). Accordingly, each serializer circuit (410-1, 410-2) has input nodes electrically connected to data lanes from the buffer circuit (402). In the illustrated embodiment, serializer circuit (410-1) has input nodes electrically connected to 16 data lanes (" / 16") from the buffer circuits (402), and serializer circuit (410-2) has input nodes electrically connected to 16 data lanes (" / 16") from the buffer circuits (402).

[0037] Each serializer circuit (410-3, 410-4) has input nodes electrically connected to each output node of the buffer circuits (404). Accordingly, each serializer circuit (410-3, 410-4) has input nodes electrically connected to data lanes from the buffer circuits (404). In the illustrated embodiment, serializer circuit (410-3) has input nodes electrically connected to 16 data lanes (" / 16") from the buffer circuits (404), and serializer circuit (410-4) has input nodes electrically connected to 16 data lanes (" / 16") from the buffer circuits (404).

[0038] Each serializer circuit (410-1, 410-2, 410-3, 410-4) has output nodes electrically connected to each of the input nodes of the signal driver circuits (428). Accordingly, each serializer circuit (410-1, 410-2, 410-3, 410-4) has output nodes electrically connected to data lanes to the signal driver circuits (428). In the illustrated embodiment, each serializer circuit (410-1, 410-2, 410-3, 410-4) has output nodes electrically connected to eight data lanes (" / 8") to the signal driver circuits (428).

[0039] Each S2D converter circuit (412-1, 412-2, 422-1, 422-2) is configured to receive a single-ended clock signal from a clock lane, generate a differential clock signal from the received single-ended clock signal, and output a differential clock signal. Any single-ended differential converter circuit can be implemented as S2D converter circuits (412-1, 412-2, 422-1, 422-2).

[0040] Each clock driver circuit (414-1, 414-2, 414-3, 414-4, 424-1, 424-2, 424-3, 424-4) is configured to receive a single-ended clock signal, buffer the single-ended clock signal, and output the buffered single-ended clock signal. In some embodiments, each clock driver circuit (414-1, 414-2, 414-3, 414-4, 424-1, 424-2, 424-3, 424-4) can adjust the duty cycle of the single-ended clock signal and can also be programmed to adjust the duty cycle of the single-ended clock signal. Further details regarding this programmability and duty cycle adjustment are described subsequently. Although the clock driver circuits (414-1, 414-2, 414-3, 414-4, 424-1, 424-2, 424-3, 424-4) are illustrated in FIG. 4a independently of the S2D converter circuits and serializer circuits, in practice, the clock driver circuits (414-1, 414-2, 414-3, 414-4, 424-1, 424-2, 424-3, 424-4) may be embedded within the corresponding S2D converter circuit and / or serializer circuit, or may be part of the corresponding S2D converter circuit and / or serializer circuit. Additionally, while a single clock driver circuit is exemplified for the corresponding S2D converter circuit and serializer circuit, multiple clock driver circuits may be implemented for the corresponding S2D converter circuit and serializer circuit.

[0041] Each of the S2D converter circuits (412-1, 412-2) has an input node electrically connected to an output node of the clock driver circuit (406). Each of the S2D converter circuits (412-1, 412-2) has an input node electrically connected to a clock lane driven by the clock driver circuit (406). The S2D converter circuit (412-1) includes one or more single-ended output nodes electrically connected to the input nodes of each of the clock driver circuits (414-1, 414-3). The S2D converter circuit (412-2) includes one or more single-ended output nodes electrically connected to the input nodes of each of the clock driver circuits (414-2, 414-4). The S2D converter circuits (412-1, 412-2) include respective differential output nodes electrically connected to the input nodes of the signal driver circuits (428). Accordingly, each of the S2D converter circuits (412-1, 412-2) has differential output nodes electrically connected to clock lanes to the signal driver circuits (428). In the illustrated embodiment, each S2D converter circuit (412-1, 412-2) has differential output nodes electrically connected to two clock lanes (" / 2") to the signal driver circuits (428).

[0042] The clock driver circuit (414-1) includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the serializer circuit (410-1). The clock driver circuit (414-2) includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the serializer circuit (410-2). The clock driver circuit (414-3) includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the serializer circuit (410-3). The clock driver circuit (414-4) includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the serializer circuit (410-4). Serializer circuits (410-1, 410-2, 410-3, 410-4) are configured to serialize data using single-ended clock signals received on each single-ended clock input node and received from each clock driver circuit (414-1, 414-2, 414-3, 414-4).

[0043] In the illustrated embodiment, as mentioned above, each serializer circuit (410-1, 410-2, 410-3, 410-4) includes a pair of 8:4 serializers. Each 8:4 serializer has a clock driver circuit. Accordingly, each clock driver circuit (414-1, 414-2, 414-3, 414-4) includes two clock driver circuits, although not explicitly illustrated. S2D converter circuits (412-1, 412-2) are configured to provide a single-ended clock signal from the clock lane from the clock driver circuit (406) to each of the two clock driver circuits of each of the clock driver circuits (414-1, 414-2, 414-3, 414-4). Each of the clock driver circuits (414-1, 414-2, 414-3, 414-4) is configured to drive a single-ended clock signal, and in some cases, is configured to adjust the duty cycle of the single-ended clock signal for each 8-to-4 serializer. For example, the S2D converter circuit (412-1) is configured to provide a single-ended clock signal to two clock driver circuits of the clock driver circuit (414-1), and each of these clock driver circuits can drive a single-ended clock signal output to each of the 8-to-4 serializers of the serializer circuit (410-1).

[0044] The retimer circuit (418) has input nodes electrically connected to the output nodes of each of the buffer circuits (402, 404). Thus, the retimer circuit (418) has input nodes electrically connected to the data lanes from the buffer circuits (402, 404). In the illustrated embodiment, the retimer circuit (418) has input nodes electrically connected to 32 data lanes (" / 32") from the buffer circuits (402) and input nodes electrically connected to 32 data lanes (" / 32") from the buffer circuits (404). The retimer circuit (418) further has an input node electrically connected to the output node of the clock driver circuit (406). Thus, the retimer circuit (418) has an input node electrically connected to the clock lane driven by the clock driver circuit (406). The retimer circuit (418) may include, for example, a buffer circuit or a driver circuit for also driving a clock signal received from a clock lane, and may include flip-flops for each data lane connected to an input node of the retimer circuit (418). The clock signal may trigger the flip-flops to reorder data signals received from the data lanes from the buffer circuits (402, 404). The retimer circuit (418) may increase the timing margin when banks of serializer circuits are placed at a relatively long distance from, for example, the buffer circuits (402, 404).

[0045] The retimer circuit (418) has output nodes electrically connected to each data lane. In the illustrated embodiment, a total of 64 data lanes (" / 16", " / 16", " / 16", and " / 16") are illustrated as being electrically connected to the output nodes of the retimer circuit (418). The retimer circuit (418) has output nodes electrically connected to clock lanes. In the illustrated embodiment, the clock lanes are for single-ended clock signals.

[0046] Each serializer circuit (420-1, 420-2, 420-3, 420-4) has input nodes electrically connected to each of the output nodes of the retimer circuit (418). Accordingly, each serializer circuit (420-1, 420-2, 420-3, 420-4) has input nodes electrically connected to the data lanes from the retimer circuit (418). In the illustrated embodiment, each serializer circuit (420-1, 420-2, 420-3, 420-4) has input nodes electrically connected to each of the 16 data lanes (" / 16") from the retimer circuit (418).

[0047] Each serializer circuit (420-1, 420-2, 420-3, 420-4) has output nodes electrically connected to each of the input nodes of the signal driver circuits (428). Accordingly, each serializer circuit (420-1, 420-2, 420-3, 420-4) has output nodes electrically connected to the data lanes to the signal driver circuits (428). In the illustrated embodiment, each serializer circuit (420-1, 420-2, 420-3, 420-4) has output nodes electrically connected to eight data lanes (" / 8") to the signal driver circuits (428).

[0048] Each of the S2D converter circuits (422-1, 422-2) has an input node electrically connected to an output node of the retimer circuit (418). Each of the S2D converter circuits (422-1, 422-2) has an input node electrically connected to a clock lane driven by the retimer circuit (418). The S2D converter circuit (422-1) includes one or more single-ended output nodes electrically connected to one or more single-ended input nodes of the clock driver circuits (424-1, 424-3). The S2D converter circuit (422-2) includes one or more single-ended output nodes electrically connected to one or more single-ended input nodes of the clock driver circuits (424-2, 424-4). The S2D converter circuits (422-1, 422-2) each include differential output nodes electrically connected to each of the input nodes of the signal driver circuits (428). Accordingly, the S2D converter circuits (422-1, 422-2) each have differential output nodes electrically connected to the clock lanes to the signal driver circuits (428). In the illustrated embodiment, each S2D converter circuit (422-1, 422-2) has differential output nodes electrically connected to two clock lanes (" / 2") to the signal driver circuits (428).

[0049] The clock driver circuit (424-1) includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the serializer circuit (420-1). The clock driver circuit (424-2) includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the serializer circuit (420-2). The clock driver circuit (424-3) includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the serializer circuit (420-3). The clock driver circuit (424-4) includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the serializer circuit (420-4). Serializer circuits (420-1, 420-2, 420-3, 420-4) are configured to serialize data using a single-ended clock signal received on each single-ended clock input node and received from each clock driver circuit (424-1, 424-2, 424-3, 424-4). Similar to what was mentioned above for the clock driver circuits (414-1, 414-2, 414-3, 414-4), each clock driver circuit (424-1, 424-2, 424-3, 424-4) includes two clock driver circuits, although not explicitly shown in the illustrated embodiment.

[0050] As described above, the signal driver circuits (428) have input nodes electrically connected to data lanes and clock lanes from various serializer circuits and S2D converter circuits. The signal driver circuits (428) include a signal driver circuit for each input node and corresponding lane and are configured to drive a corresponding signal on a corresponding physical channel of the physical channels (204-12). Each signal driver driving the data signal (e.g., a signal based on serialized data on a data lane from a serializer circuit) may be configured to drive a single-ended data signal, such as a single-ended NRZ data signal, on a corresponding physical channel. Using such single-ended signaling can reduce the number of physical channels (e.g., metal lines) within the WLFO package (100) and reduce power consumption compared to differential signaling. Additionally, each signal driver driving the clock signal may be configured to drive a differential clock signal on a pair of corresponding physical channels. Each signal driver circuit may be configured to provide equalization for the channel response of the corresponding physical channel configured to be driven by the signal driver circuit. Additionally, the signal driver circuit may be programmable to provide equalization. Further details regarding equalization and programmability are described subsequently.

[0051] In the operation of the illustrated embodiment, buffer circuits (402, 404) receive parallel data from each of the 64 data lanes from the interface circuit of the IC die (102-1). Each of the buffer circuits (402, 404) outputs the respective received parallel data to the corresponding 64 data lanes. Of the parallel data on the 64 data lanes from the buffer circuits (402), parallel data on 16 data lanes is input to the serializer circuit (410-1); parallel data on the other 16 data lanes is input to the serializer circuit (410-2); and parallel data on 32 data lanes is input to the retimer circuit (418). Of the parallel data on the 64 data lanes from the buffer circuits (404), parallel data on 16 data lanes is input to the serializer circuit (410-3); Parallel data on the other 16 data lanes is input to the serializer circuit (410-4); parallel data on the 32 data lanes is input to the retimer circuit (418).

[0052] The clock driver circuit (406) receives a single-ended clock signal from the interface circuit of the IC die (102-1) and drives the single-ended clock signal on the clock lane to the S2D converter circuits (412-1, 412-2) and the retimer circuit (418). The S2D converter circuits (412-1, 412-2) each generate a differential clock signal from the single-ended clock signal received from the clock lane. The S2D converter circuit (412-1) provides the differential clock signal to the signal driver circuits (428) through the two clock lanes and provides the single-ended clock signal from the clock lane to the clock driver circuits (414-1, 414-3). The S2D converter circuit (412-2) provides a differential clock signal to the signal driver circuits (428) through two clock lanes and provides a single-ended clock signal from the clock lanes to the clock driver circuits (414-2, 414-4). The clock driver circuits (414-1, 414-2, 414-3, 414-4) buffer the received single-ended clock signal and output the buffered single-ended clock signal to the respective serializer circuits (410-1, 410-2, 410-3, 410-4). In some embodiments, the clock driver circuits (414-1, 414-2, 414-3, 414-4) may generate the buffered single-ended clock signal by adjusting the duty cycle of the received single-ended clock signal.

[0053] The retimer circuit (418) receives parallel data from 32 data lanes from the buffer circuits (402) and from 32 data lanes from the buffer circuits (404). The retimer circuit (418) also receives a signal termination clock signal from a clock lane from the clock driver circuit (406). The retimer circuit (418) can buffer or drive a single termination clock signal and realign or synchronize parallel data with the clock signal. The retimer circuit (418) outputs parallel data on each of the corresponding 64 data lanes. Among these 64 data lanes, the parallel data output for 32 data lanes corresponds to the parallel data received on the 32 data lanes from the buffer circuits (402), and the parallel data output on the 32 data lanes corresponds to the parallel data received on the 32 data lanes from the buffer circuits (404). Among the parallel data outputs on 32 data lanes corresponding to the buffer circuits (402), the parallel data on 16 data lanes is input to the serializer circuit (420-1), and the parallel data on the other 16 data lanes is input to the serializer circuit (420-2). Among the parallel data outputs on 32 data lanes corresponding to the buffer circuits (404), the parallel data on 16 data lanes is input to the serializer circuit (420-3), and the parallel data on the other 16 data lanes is input to the serializer circuit (420-4). The retimer circuit (418) drives the single-ended clock signal on the clock lane to the S2D converter circuits (422-1, 422-2).

[0054] S2D converter circuits (422-1, 422-2) each generate a differential clock signal from a single-ended clock signal received from a clock lane from a retimer circuit (418). S2D converter circuit (422-1) provides the differential clock signal to signal driver circuits (428) through two clock lanes and provides the single-ended clock signal from the clock lane to clock driver circuits (424-1, 424-3). S2D converter circuit (422-2) provides the differential clock signal to signal driver circuits (428) through two clock lanes and provides the single-ended clock signal from the clock lane to clock driver circuits (424-2, 424-4). Clock driver circuits (424-1, 424-2, 424-3, 424-4) buffer a received single-ended clock signal and output the buffered single-ended clock signal to each serializer circuit (420-1, 420-2, 420-3, 420-4). In some embodiments, the clock driver circuits (424-1, 424-2, 424-3, 424-4) can generate a buffered single-ended clock signal by adjusting the duty cycle of the received single-ended clock signal.

[0055] Each serializer circuit (410-1, 410-2, 410-3, 410-4, 420-1, 420-2, 420-3, 420-4) serializes the parallel data received on each of the 16 data lanes based on the received single-ended clock signal and outputs the serialized data on the 8 data lanes to the signal driver circuits (428). The signal driver circuits (428) drive the respective data or clock signal received from each data or clock lane onto the corresponding physical channel of the physical channels (204-12). The signal driver circuits (428) drive the serialized data on each data lane as each single-ended data signal (e.g., single-ended NRZ data signal) onto the corresponding physical channel (204-12) and drive the differential clock signal on each pair of clock lanes onto the corresponding pair of physical channels. The signal driver circuits (428) can also equalize signals on the physical channels (204-12).

[0056] The receiver circuit (202-2R) comprises a first bank of deserializer circuits (450-1, 450-2, 450-3, 450-4), a first bank of differential-single-ended (D2S) converter circuits (452-1, 452-2), a first bank of clock driver circuits (454-1, 454-2, 454-3, 454-4), a buffer circuit (458), a second bank of deserializer circuits (460-1, 460-2, 460-3, 460-4), a second bank of D2S converter circuits (462-1, 462-2), a second bank of clock driver circuits (464-1, 464-2, 464-3, 464-4), and a buffer It includes circuits (470, 472).

[0057] In the illustrated embodiment, each deserializer circuit (450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, 460-4) includes a pair of 4-to-8 deserializers. Each 4-to-8 deserializer is configured to receive data from four data lanes, deserialize the received data, and output the deserialized parallel data onto eight data lanes. Each 4-to-8 deserializer is configured to deserialize data based on a single-ended clock signal. Each 4-to-8 deserializer is further configured to output a single-ended clock signal used to deserialize data. In other embodiments, the deserializer circuits may be implemented differently, the serialization ratio may be different, and / or the number of deserializers may be different.

[0058] Each deserializer circuit (450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, 460-4) has input nodes electrically connected to each physical channel of the physical channels (204-12). In the illustrated embodiment, each deserializer circuit (450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, 460-4) has input nodes electrically connected to eight physical channels (" / 8") of the physical channels (204-12). The physical channels to which the input nodes of the deserializer circuit (450-1) are electrically connected carry data signals coming from the serializer circuit (410-1). Accordingly, the deserializer circuit (450-1) is communically coupled to the serializer circuit (410-1). Similarly, the deserializer circuit (450-2) is communically coupled to the serializer circuit (410-2); the deserializer circuit (450-3) is communically coupled to the serializer circuit (410-3); the deserializer circuit (450-4) is communically coupled to the serializer circuit (410-4); the deserializer circuit (460-1) is communically coupled to the serializer circuit (420-1); the deserializer circuit (460-2) is communically coupled to the serializer circuit (420-2); the deserializer circuit (460-3) is communically coupled to the serializer circuit (420-3); The deserializer circuit (460-4) is coupled to the serializer circuit (420-4) so ​​as to be communicable.

[0059] In some embodiments, the first bank of serializer circuits (410-1, 410-2, 410-3, 410-4) is physically positioned furthest from the lateral sidewall (152-1) of the IC die (102-1) in the transmitter circuit (202-1T), and the second bank of serializer circuits (420-1, 420-2, 420-3, 420-4) is physically positioned closest to the lateral sidewall (152-1) of the IC die (102-1) in the transmitter circuit (202-1T). The first bank of deserialization circuits (450-1, 450-2, 450-3, 450-4) is physically positioned closest to the lateral sidewall (152-2) of the IC die (102-2) in the receiver circuit (202-2R), and the second bank of deserialization circuits (460-1, 460-2, 460-3, 460-4) is physically positioned furthest from the lateral sidewall (152-2) of the IC die (102-2) in the receiver circuit (202-2R). Thus, the banks of serialization circuits are communicably coupled to the banks of deserialization circuits through physical channels (204-12) that can generally be matched and balanced due to the same or similar lengths of the physical channels (204-12). Since such matching and balancing can reduce the load on the physical channels overall, it can reduce the overall power consumption for driving signals through the physical channels.

[0060] Each deserializer circuit (450-1, 450-2, 450-3, 450-4) has an output node electrically connected to each input node of the buffer circuit (458). Accordingly, each deserializer circuit (450-1, 450-2, 450-3, 450-4) has an output node electrically connected to a data lane to the buffer circuit (458). In the illustrated embodiment, each deserializer circuit (450-1, 450-2, 450-3, 450-4) has an output node electrically connected to 16 data lanes (" / 16") to the buffer circuit (458). Each deserializer circuit (460-1, 460-2) has an output node electrically connected to each input node of the buffer circuit (470). Accordingly, each of the deserializer circuits (460-1, 460-2) has an output node electrically connected to a data lane to the buffer circuit (470). In the illustrated embodiment, each of the deserializer circuits (460-1, 460-2) has an output node electrically connected to 16 data lanes (" / 16") to the buffer circuit (470). Each of the deserializer circuits (460-3, 460-4) has output nodes electrically connected to the respective input nodes of the buffer circuits (472). Accordingly, the deserializer circuits (460-3, 460-4) each have output nodes electrically connected to the data lanes to the buffer circuits (472). In the illustrated embodiment, each deserializer circuit (460-3, 460-4) has output nodes electrically connected to 16 data lanes (" / 16") to buffer circuits (472).

[0061] Each D2S converter circuit (452-1, 452-2, 462-1, 462-2) receives a differential clock signal from each of the physical channels (204-12), generates a single-ended clock signal from the received differential clock signal, and outputs a single-ended clock signal. Any differential-single-ended converter circuit can be implemented as D2S converter circuits (452-1, 452-2, 462-1, 462-2).

[0062] Each clock driver circuit (454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4) is configured to receive a single-ended clock signal, buffer the single-ended clock signal, and output the buffered single-ended clock signal. In some embodiments, each clock driver circuit (454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4) can adjust the duty cycle of the single-ended clock signal and can also be programmed to adjust the duty cycle of the single-ended clock signal. In some embodiments, each clock driver circuit (454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4) can deskew a single-ended clock signal and can also be programmed to deskew a single-ended clock signal. Further details regarding this programmability, duty cycle adjustment, and deskew correction are described subsequently. In FIG. 4b, clock driver circuits (454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4) are shown independently of D2S converter circuits and serializer circuits, but in reality, clock driver circuits (454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4) may be embedded within the corresponding D2S converter circuit and / or deserializer circuit, or may be part of the corresponding D2S converter circuit and / or deserializer circuit. Additionally, a single clock driver circuit is exemplified for the corresponding D2S converter circuit and deserializer circuit, but multiple clock driver circuits may be implemented for the corresponding D2S converter circuit and deserializer circuit.

[0063] Each of the D2S converter circuits (452-1, 452-2, 462-1, 462-2) has differential input nodes electrically connected to the physical channels of the physical channels (204-12). In the illustrated embodiment, each D2S converter circuit (452-1, 452-2, 462-1, 462-2) has differential input nodes electrically connected to two physical channels (" / 2") of the physical channels (204-12). The D2S converter circuit (452-1) includes one or more single-ended output nodes electrically connected to the input nodes of each of the clock driver circuits (454-1, 454-3). The D2S converter circuit (452-2) includes one or more single-ended output nodes electrically connected to the input nodes of each of the clock driver circuits (454-2, 454-4). The D2S converter circuit (462-1) includes one or more single-ended output nodes electrically connected to each input node of the clock driver circuits (464-1, 464-3). The D2S converter circuit (462-2) includes one or more single-ended output nodes electrically connected to each input node of the clock driver circuits (464-2, 464-4).

[0064] A clock driver circuit (454-1) includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of a deserializer circuit (450-1). A clock driver circuit (454-2) includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of a deserializer circuit (450-2). A clock driver circuit (454-3) includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of a deserializer circuit (450-3). A clock driver circuit (454-4) includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of a deserializer circuit (450-4). A clock driver circuit (464-1) includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of a deserializer circuit (460-1). A clock driver circuit (464-2) includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of a deserializer circuit (460-2). A clock driver circuit (464-3) includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of a deserializer circuit (460-3). A clock driver circuit (464-4) includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of a deserializer circuit (460-4).

[0065] In the illustrated embodiment, as mentioned above, each deserializer circuit (450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, 460-4) includes a pair of 4:8 deserializers. Each 4:8 deserializer has a clock driver circuit. Thus, each clock driver circuit (454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4) includes two clock driver circuits, although not explicitly illustrated. The D2S converter circuits (452-1, 452-2, 462-1, 462-2) are configured to generate and provide a single-ended clock signal to each of the two clock driver circuits of the clock driver circuits (454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4). Each of the clock driver circuits of the clock driver circuits (454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4) is configured to drive the single-ended clock signal to the 4-to-8 deserializer, and in some cases, to skew the single-ended clock signal and / or adjust the duty cycle of the single-ended clock signal. For example, the D2S converter circuit (452-1) is configured to provide a single-ended clock signal to two clock driver circuits of the clock driver circuit (454-1), and each of these clock driver circuits can drive a single-ended clock signal output to each of the 4-to-8 deserializers of the deserializer circuit (450-1).

[0066] The deserializer circuits (450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, 460-4) are configured to deserialize data using a single-ended clock signal received on each single-ended clock input node and received from each clock driver circuit (454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4). Each deserializer circuit (450-1, 450-2, 450-3, 450-4) has a clock output node electrically connected to each input node of the buffer circuit (458). Accordingly, each deserializer circuit (450-1, 450-2, 450-3, 450-4) has a clock output node electrically connected to a clock lane to a buffer circuit (458). In the illustrated embodiment, each deserializer circuit (450-1, 450-2, 450-3, 450-4) has a clock output node electrically connected to two data lanes (" / 2") to a buffer circuit (458). Each deserializer circuit (460-1, 460-2) has clock output nodes electrically connected to the respective input nodes of the buffer circuits (470). Accordingly, each deserializer circuit (460-1, 460-2) has clock output nodes electrically connected to the clock lanes to the buffer circuits (470). In the illustrated embodiment, each deserializer circuit (460-1, 460-2) has clock output nodes electrically connected to two data lanes (" / 2") to buffer circuits (470). Each deserializer circuit (460-3, 460-4) has clock output nodes electrically connected to each input node of buffer circuits (472). Thus, each deserializer circuit (460-3, 460-4) has clock output nodes electrically connected to clock lanes to buffer circuits (472).In the illustrated embodiment, each deserializer circuit (460-3, 460-4) has clock output nodes electrically connected to two data lanes (" / 2") to buffer circuits (472). As previously mentioned, each deserializer circuit includes a pair of 4-to-8 deserializers, and each 4-to-8 deserializer is configured to output a clock signal that each 4-to-8 deserializer uses to deserialize data. Accordingly, in the illustrated embodiment, each deserializer circuit is illustrated as outputting two clock signals to each of the two clock lanes.

[0067] The buffer circuit (458) has an input node electrically connected to the output node of each of the deserializer circuits (450-1, 450-2, 450-3, 450-4). Accordingly, the buffer circuit (458) has input nodes electrically connected to the data lanes and the clock lanes from the deserializer circuits (450-1, 450-2, 450-3, 450-4). In the illustrated embodiment, the buffer circuit (458) has an input node electrically connected to 16 data lanes (" / 16") and 2 clock lanes (" / 2") from each of the deserializer circuits (450-1, 450-2, 450-3, 450-4). The buffer circuit (458) may include, for example, a buffer circuit or a driver circuit for also driving data signals and clock signals received from each of the data lanes and clock lanes.

[0068] The buffer circuit (458) has output nodes electrically connected to each of the data lanes and clock lanes. In the illustrated embodiment, a total of 64 data lanes (" / 32" and " / 32") electrically coupled to the output nodes of the buffer circuit (458) are illustrated, and a total of 8 clock lanes (" / 4" and " / 4") electrically coupled to the output nodes of the buffer circuit (458) are illustrated.

[0069] The buffer circuits (470) may include 72 buffer circuits in the illustrated embodiment, each buffer circuit having an input node electrically connected to a data lane or clock lane from the deserializer circuits (460-1, 460-2) or buffer circuit (458) and an output node electrically connected to an interface circuit (not shown) of the IC die (102-2). Thus, a total of 64 data lanes (" / 32", " / 16", and " / 16") electrically coupled to the input nodes of the buffer circuits (470) are illustrated, and a total of 64 data lanes (" / 64") electrically coupled to the output nodes of the buffer circuits (470) are illustrated. Additionally, a total of eight clock lanes (" / 4", " / 2", and " / 2") electrically coupled to the input nodes of the buffer circuits (470) are shown, and eight clock lanes (" / 8") electrically coupled to the output nodes of the buffer circuits (470) are shown. Similarly, the buffer circuits (472) may include 72 buffer circuits in the illustrated embodiment, where each buffer circuit has an input node electrically connected to a data lane or clock lane from the deserializer circuits (460-3, 460-4) or buffer circuit (458) and an output node electrically connected to an interface circuit of the IC die (102-2). Accordingly, a total of 64 data lanes (" / 32", " / 16", and " / 16") electrically coupled to the input nodes of the buffer circuits (472) are shown, and a total of 64 data lanes (" / 64") electrically coupled to the output nodes of the buffer circuits (472) are shown. Additionally, a total of 8 clock lanes (" / 4", " / 2", and " / 2") electrically coupled to the input nodes of the buffer circuits (472) are shown, and 8 clock lanes (" / 8") electrically coupled to the output nodes of the buffer circuits (472) are shown.The buffer circuits (470, 472) are configured to receive parallel data and single-ended clock signals from each of the 64 data lanes and 8 clock lanes, and to output the parallel data and single-ended clock signals to each of the 64 data lanes and 8 clock lanes to the interface circuit of the IC die (102-2).

[0070] In the operation of the illustrated embodiment, each deserializer circuit (450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, 460-4) receives single-ended data signals from each of the eight physical channels of the physical channels (204-12), and each D2S converter circuit (452-1, 452-2, 462-1, 462-2) receives differential clock signals from each of the two physical channels of the physical channels (204-12). Each D2S converter circuit (452-1, 452-2, 462-1, 462-2) converts the received differential clock signal into a single-ended clock signal and provides the single-ended clock signal to each clock driver circuit (454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4). The D2S converter circuit (452-1) provides the single-ended clock signal to the clock driver circuits (454-1, 454-3). The D2S converter circuit (452-2) provides the single-ended clock signal to the clock driver circuits (454-2, 454-4). The D2S converter circuit (462-1) provides a single-ended clock signal to the clock driver circuits (464-1, 464-3). The D2S converter circuit (462-2) provides a single-ended clock signal to the clock driver circuits (464-2, 464-4). The clock driver circuits (454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4) buffer the received single-ended clock signal and output the buffered single-ended clock signal to their respective deserializer circuits (450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, 460-4).In some embodiments, each clock driver circuit (454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4) skews and / or adjusts the duty cycle of a received single-ended clock signal, and the output single-ended clock signal may have a skewed and / or adjusted duty cycle.

[0071] Each deserializer circuit (450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, 460-4) captures and deserializes data received from each of the eight physical channels of each of the physical channels (204-12) based on the received single-ended clock signal, outputs parallel data onto 16 data lanes to buffer circuits (458, 470, or 472), and outputs the single-ended clock signal used to deserialize the data onto each clock lane to the buffer circuits (458, 470, or 472). As mentioned, in the illustrated embodiment, each deserializer circuit (450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, 460-4) includes two 4-to-8 deserializers, and each of the 4-to-8 deserializers outputs a single-ended clock signal. Accordingly, in the illustrated embodiment, each deserializer circuit (450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, 460-4) outputs two single-ended clock signals on each clock lane. Each deserializer circuit (450-1, 450-2, 450-3, 450-4) outputs parallel data and single-ended clock signals to a buffer circuit (458). Each deserializer circuit (460-1, 460-2) outputs parallel data and single-ended clock signals to a buffer circuit (470). Each deserializer circuit (460-3, 460-4) outputs parallel data and single-ended clock signals to buffer circuits (472).

[0072] The buffer circuit (458) receives parallel data from 16 data lanes and two single-ended clock signals from two clock lanes from each of the deserializer circuits (450-1, 450-2, 450-3, 450-4). The buffer circuit (458) buffers or drives the data and single-ended clock signals and outputs each parallel data and single-ended clock signal onto the corresponding 64 data lanes and 8 clock lanes to the buffer circuits (470, 472). Among these 64 data lanes and 8 clock lanes, the parallel data output on 32 data lanes to the buffer circuits (470) and the single-ended clock signals on 4 clock lanes correspond to the parallel data received on 16 data lanes from the deserializer circuit (450-1) and the single-ended clock signals on 2 clock lanes, and the single-ended clock signals on 16 data lanes and 2 clock lanes from the deserializer circuit (450-2). Additionally, among these 64 data lanes and 8 clock lanes, the parallel data output on 32 data lanes and single-ended clock signals on 4 clock lanes to the buffer circuits (472) correspond to the parallel data received on 16 data lanes from the deserializer circuit (450-3) and single-ended clock signals on 2 clock lanes, and the single-ended clock signals on 16 data lanes and 2 clock lanes from the deserializer circuit (450-4).

[0073] Buffer circuits (470, 472) receive parallel data from each of the 64 data lanes and single-ended clock signals from the 8 clock lanes, and output parallel data and clock signals on the corresponding 64 data lanes and 8 clock lanes to the interface circuit of the IC die (102-2). Among the parallel data on the 64 data lanes and single-ended clocks on the 8 clock lanes input to the buffer circuits (470), the parallel data on the 16 data lanes and single-ended clock signals on the 2 clock lanes are inputs from the deserializer circuit (460-1); the parallel data on the 16 data lanes and single-ended clock signals on the 2 clock lanes are inputs from the deserializer circuit (460-2); Parallel data on 32 data lanes and single-ended clock signals on 4 clock lanes are inputs from the deserializer circuit (458). Among the parallel data on 64 data lanes and single-ended clocks on 8 clock lanes input to the buffer circuits (472), parallel data on 16 data lanes and single-ended clock signals on 2 clock lanes are inputs from the deserializer circuit (460-3); parallel data on 16 data lanes and single-ended clock signals on 2 clock lanes are inputs from the deserializer circuit (460-4); and parallel data on 32 data lanes and single-ended clock signals on 4 clock lanes are inputs from the deserializer circuit (458).

[0074] In the above-described embodiment, the receiver circuit (202-2R) receives differential clock signals from the transmitter circuit (202-1T) and uses the received differential clock signals to capture data transmitted to the transmitter circuit (202-1T) through physical channels (204-12) (by converting them into single-ended clock signals). Thus, the above-described communication is source synchronous communication. Implementing source synchronous communication eliminates the need to implement a clock data recovery (CDR) circuit in the receiver circuit, which can increase power efficiency.

[0075] Additionally, in the above-described embodiment, a plurality of single-ended data signals are generated, and then data is captured from the plurality of single-ended data signals with respect to a single clock signal. In the illustrated embodiment, the 16 single-ended data signals (transmitted through 16 physical channels) share a single clock signal. For example, parallel data is serialized by serializer circuits (410-1, 410-3) based on single-ended clock signals from the S2D converter circuit (412-1), and the 16 single-ended data signals are transmitted over 16 physical channels from signal driver circuits (428) based on the serialized data on each of the 8 data lanes from the serializer circuits (410-1, 410-3). A single differential clock signal from the S2D converter circuit (412-1) is transmitted over 2 physical channels through the signal driver circuits (428). The D2S converter circuit (452-1) receives a differential clock signal and generates a single-ended clock signal used to capture data from 16 single-ended data signals on 16 physical channels by deserializer circuits (450-1, 450-3). Different data signal to clock signal ratios can be implemented. Using a high data signal to clock signal ratio can be efficient in terms of area for the physical channels within the WLFO package (100) and efficient in terms of power because the number of clock signals per data signal is reduced.

[0076] The transmitter circuit may contain more or fewer banks of serializer circuits, corresponding S2D converter circuits, and clock driver circuits. Retimer circuits may be appropriately included or omitted for the timing of signals propagated through the transmitter circuit. For example, one or more retimer circuits may be implemented for additional banks included in the transmitter circuit. Similarly, the receiver circuit may contain more or fewer banks of deserializer circuits, corresponding D2S converter circuits, and clock driver circuits. A buffer circuit (same as buffer circuit (458)) may be appropriately included or omitted for signals propagated through the receiver circuit having more or fewer banks of deserializer circuits.

[0077] FIG. 5 is a circuit schematic of a clock driver circuit (500) according to some examples. The clock driver circuit (500) may be implemented as any clock driver circuit within the transmitter circuit of FIG. 4a and FIG. 4b. As previously mentioned, the clock driver circuit (500) may be a circuit spaced apart from and interposed between the corresponding S2D converter circuit and the serializer circuit, or it may be embedded or implemented within the corresponding S2D converter circuit and / or the corresponding serializer circuit. The clock driver circuit (500) is programmable to adjust the duty cycle of a single-ended clock signal.

[0078] The clock driver circuit (500) includes p-type transistors (502, 504) (e.g., p-type field-effect transistors (FETs)) and n-type transistors (506, 508) (e.g., n-type FETs). The source node of the p-type transistor (502) is electrically connected to a first power supply node (e.g., VDD power supply node), and the drain node of the p-type transistor (502) is electrically connected to the source node of the p-type transistor (504). The drain node of the p-type transistor (504) is electrically connected to the drain node of the n-type transistor (506), and the source node of the n-type transistor (506) is electrically connected to the drain node of the n-type transistor (508). The source node of the n-type transistor (508) is electrically connected to a second power supply node (e.g., ground node). The gate nodes of the p-type transistor (504) and the n-type transistor (506) are electrically connected to at least a portion of the input node (510) and / or form at least a portion of the input node. The drain nodes of the p-type transistor (504) and the n-type transistor (506) are electrically connected to at least a portion of the output node (512) and / or form at least a portion of the output node. The gate node of the p-type transistor (502) is electrically connected to the first control node (514), and the gate node of the n-type transistor (508) is electrically connected to the second control node (516).

[0079] When in operation, a single-ended input clock signal (Clkin) is input to the clock driver circuit (500) on the input node (510), and a complementary single-ended output clock signal (Clkout_b) is output from the clock driver circuit (500) on the output node (512). Generally, the complementary single-ended output clock signal (Clkout_b) is logically complementary to the single-ended input clock signal (Clkin). When in operation, respective control signals (Ctl_1 and Ctl_2) are applied to the first control node (514) and the second control node (516). The control signals bias the clock driver circuit (500) to adjust the switching threshold of an inverter (e.g., a p-type transistor (504) and an n-type transistor (506)) electrically connected between a p-type transistor (502) and an n-type transistor (508). By adjusting the switching threshold, the transition point of the voltage on the output node (512) (e.g., the complementary single-ended output clock signal (Clkout_b)) from a logically low state to a logically high state or from a logically high state to a logically low state with respect to the voltage on the input node (510) (e.g., the single-ended input clock signal (Clkin)) is changed. Accordingly, by biasing the clock driver circuit (500) using control signals, the complementary single-ended output clock signal (Clkout_b) can be made to have a duty cycle adjusted with respect to the single-ended input clock signal (Clkin).

[0080] In some embodiments, the first control node (514) and the second control node (516) are electrically connected to the output node of each digital-to-analog converter (DAC). The DAC may be electrically connected to a programmable memory element (e.g., a register, an electronic fuse (eFuse), or other memory). The memory element may be programmed or written to a digital value corresponding to the voltage of each control signal (Ctl_1, Ctl_2) applied to the first control node (514) or the second control node (516). The memory element is configured to provide the digital value to each DAC, and the DAC converts the digital value into an analog voltage that the DAC applies to each first control node (514) and the second control node (516). Different values ​​programmed or written to the memory element cause different analog voltages to be applied to each first control node (514) and the second control node (516), which can ultimately cause the duty cycle of the single-ended clock to be adjusted differently. Accordingly, in these examples, the clock driver circuit (500) may be programmable to adjust the duty cycle of a single-ended clock signal.

[0081] The clock driver circuit (500) may include additional components in other examples. For example, the clock driver circuit (500) may include an inverter having an input node electrically connected to the drains of a p-type transistor (504) and an n-type transistor (506), and an output node electrically connected to an output node (512) (for example, the inverter may be electrically connected between the drains and the output node (512)). In this embodiment, the single-ended output clock signal may logically correspond to the single-ended input clock signal (Clkin), possibly by an adjusted duty cycle (for example, not logically complementary to the single-ended input clock signal (Clkin)).

[0082] FIG. 6 is a schematic circuit diagram of a clock driver circuit (600) according to some embodiments. The clock driver circuit (600) may be implemented as any clock driver circuit within the receiver circuit of FIG. 4a and FIG. 4b. As previously described, the clock driver circuit (600) may be a circuit spaced apart from and interposed between the corresponding D2S converter circuit and the deserializer circuit, or it may be embedded or implemented within the corresponding D2S converter circuit and / or the corresponding deserializer circuit. The clock driver circuit (600) is programmable to correct and adjust the duty cycle of a single-ended clock signal.

[0083] The clock driver circuit (600) includes a skew correction stage and a duty cycle adjustment stage. The skew correction stage includes buffers (602-1, 602-2, 602-3, 602-4, 602-5, 602-6, 602-7), inverters (610-0, 610-2, 610-4, 610-6, 620-1, 620-3, 620-5, 620-7, 630, 632), multiplexers (612, 622), and programmable inverters (614, 624). The buffers (602-1, 602-2, 602-3, 602-4, 602-5, 602-6, 602-7) are connected in series. The input node of buffer (602-1) is the input node of the clock driver circuit (600) and is the tap-0 node (604-0). The output node of buffer (602-1) is the tap-1 node (604-1) and is electrically connected to the input node of buffer (602-2). The output node of buffer (602-2) is the tap-2 node (604-2) and is electrically connected to the input node of buffer (602-3). The output node of buffer (602-3) is the tap-3 node (604-3) and is electrically connected to the input node of buffer (602-4). The output node of buffer (602-4) is the tap-4 node (604-4) and is electrically connected to the input node of buffer (602-5). The output node of buffer (602-5) is tap-5 node (604-5) and is electrically connected to the input node of buffer (602-6). The output node of buffer (602-6) is tap-6 node (604-6) and is electrically connected to the input node of buffer (602-7). The output node of buffer (602-7) is tap-7 node (604-7).

[0084] Even tap nodes (e.g., tap-0 node (604-0), tap-2 node (604-2), etc.) are electrically connected to the respective input nodes of the inverters (610-0, 610-2, 610-4, 610-6), and odd tap nodes (e.g., tap-1 node (604-1), tap-3 node (604-3), etc.) are electrically connected to the respective input nodes of the inverters (620-1, 620-3, 620-5, 620-7). The output nodes of the inverters (610-0, 610-2, 610-4, 610-6) are electrically connected to the respective input nodes of the multiplexer (612), and the output nodes of the inverters (620-1, 620-3, 620-5, 620-7) are electrically connected to the respective input nodes of the multiplexer (622).

[0085] More specifically, the tap-0 node (604-0) is electrically connected to the input node of the inverter (610-0), and the output node of the inverter (610-0) is electrically connected to the input node of the multiplexer (612). The tap-2 node (604-2) is electrically connected to the input node of the inverter (610-2), and the output node of the inverter (610-2) is electrically connected to the input node of the multiplexer (612). The tap-4 node (604-4) is electrically connected to the input node of the inverter (610-4), and the output node of the inverter (610-4) is electrically connected to the input node of the multiplexer (612). The tap-6 node (604-6) is electrically connected to the input node of the inverter (610-6), and the output node of the inverter (610-6) is electrically connected to the input node of the multiplexer (612).

[0086] The tap-1 node (604-1) is electrically connected to the input node of the inverter (620-1), and the output node of the inverter (620-1) is electrically connected to the input node of the multiplexer (622). The tap-3 node (604-3) is electrically connected to the input node of the inverter (620-3), and the output node of the inverter (620-3) is electrically connected to the input node of the multiplexer (622). The tap-5 node (604-5) is electrically connected to the input node of the inverter (620-5), and the output node of the inverter (620-5) is electrically connected to the input node of the multiplexer (622). The tap-7 node (604-7) is electrically connected to the input node of the inverter (620-7), and the output node of the inverter (620-7) is electrically connected to the input node of the multiplexer (622).

[0087] The output node of the multiplexer (612) is electrically connected to the input node of the programmable inverter (614), and the output node of the multiplexer (622) is electrically connected to the input node of the programmable inverter (624). The output node of the programmable inverter (614) and the output node of the programmable inverter (624) are electrically connected together and connected to the input node of the inverter (630). The output node of the inverter (630) is electrically connected to the input node of the inverter (632), and the output node of the inverter (632) is the output node of the skew correction stage and is electrically connected to the input node (510) of the duty cycle adjustment stage.

[0088] The multiplexers (612, 622) may have respective selection control nodes electrically coupled to each memory element. The memory elements may be programmed or written with digital values ​​provided to the selection control nodes of the multiplexers (612, 622). Thus, the multiplexers (612, 622) may be configured to selectively output a signal input on a given input node of each multiplexer (612, 622) based on the digital values ​​programmed or written to the memory elements.

[0089] Before describing the operation of the exemplary embodiment of FIG. 6, FIG. 7 is a circuit schematic of a programmable inverter (700) according to some embodiments. Each of the programmable inverters (614, 624) of FIG. 6 can be implemented as the programmable inverter (700) of FIG. 7. The programmable inverter (700) includes n inverter stages (702-1, 702-2, ... 702-n) (individually or collectively, inverter stage(s) (702)).

[0090] Each inverter stage (702) includes a p-type transistor (704, 706) and an n-type transistor (708, 710). The source node of the p-type transistor (704) is electrically connected to a first power supply node (e.g., VDD power supply node), and the drain node of the p-type transistor (704) is electrically connected to the source node of the p-type transistor (706). The drain node of the p-type transistor (706) is electrically connected to the drain node of the n-type transistor (708), and the source node of the n-type transistor (708) is electrically connected to the drain node of the n-type transistor (710). The source node of the n-type transistor (710) is electrically connected to a second power supply node (e.g., ground node). The gate nodes of the p-type transistor (706) and the n-type transistor (708) are electrically connected to and / or form at least a portion of the input node (712). The drain nodes of the p-type transistor (706) and the n-type transistor (708) are electrically connected to and / or form at least a portion of the output node (714). The gate node of the p-type transistor (704) is electrically connected to the respective complementary enable node (ENBx) (716), and the gate node of the n-type transistor (710) is electrically connected to the enable node (ENx) (718), where x represents the corresponding inverter stage (702) (e.g., x is 1 in the case of the inverter stage (702-1)).

[0091] In some embodiments, each enable node (ENx) (718) is electrically coupled to a programmable memory element (e.g., a register, eFuse, or other memory). The memory element may be programmed or written to a logically high or logically low digital value, and the logically high or logically low value is applied to each enable node (ENx) (718) of a given inverter stage (702). An inverter may be electrically coupled between the memory element and each complementary enable node (ENBx) (716) of a given inverter stage (702) to logically complement the value programmed or written to the memory element, and the logically complemented value is applied to each complementary enable node (ENBx) (716).

[0092] The inverter stage (702) includes an inverter that can be optionally operably coupled within a programmable inverter (700) based on values ​​recorded in memory elements of the inverter stage (702). For a given inverter stage (702-x), when the signal on the enable node (ENx) (718) is logically high (e.g., power supply voltage VDD) and the signal on the complementary enable node (ENBx) (716) is correspondingly logically low (e.g., ground potential), the p-type transistor (704) and the n-type transistor (710) are in a conductive state, which allows the inverter formed by the p-type transistor (706) and the n-type transistor (708) to be operably coupled within the programmable inverter (700). Conversely, when the signal on the enable node (ENx) (718) is logically low and the signal on the complementary enable node (ENBx) (716) is correspondingly logically high, the p-type transistor (704) and the n-type transistor (710) are in a non-conductive or open state, which causes the inverter formed by the p-type transistor (706) and the n-type transistor (708) to be operablely separated within the programmable inverter (700).

[0093] By programming a desired number of inverters of inverter stages (702) to be operablely coupled within the programmable inverter (700), the driving properties of the signal output by the programmable inverter (700) can be programmed. Assuming that the inverters of each inverter stage (702) have the same driving properties (e.g., the corresponding transistors (706, 708) have the same width and length of their respective channels), increasing the number of inverters of inverter stages (702) operablely coupled within the programmable inverter (700) increases the driving properties of the programmable inverter (700), and conversely, decreasing the number of inverters of inverter stages (702) operablely coupled within the programmable inverter (700) decreases the driving properties of the programmable inverter (700).

[0094] Referring again to FIG. 6, during operation, a clock signal (Clk0) is input to the tap-0 node (604-0) of the clock driver circuit (600). This clock signal is propagated through serially connected buffers (602-1 to 602-7). The latency of the clock signal propagating through the buffers causes the clock signal output by the buffers to be delayed. Accordingly, the clock signal (Clk1) output by the buffer (602-1) on the tap-1 node (604-1) is delayed once. The clock signal (Clk2) output by the buffer (602-2) on the tap-2 node (604-2) is delayed twice. The clock signal (Clk3) output by the buffer (602-3) on the tap-3 node (604-3) is delayed three times. The clock signal (Clk4) output by the buffer (602-4) on the tap-4 node (604-4) is delayed 4 times. The clock signal (Clk5) output by the buffer (602-5) on the tap-5 node (604-5) is delayed 5 times. The clock signal (Clk6) output by the buffer (602-6) on the tap-6 node (604-6) is delayed 6 times. The clock signal (Clk7) output by the buffer (602-7) on the tap-7 node (604-7) is delayed 7 times.

[0095] Various clock signals are input to each inverter (610-0 to 610-6, 620-1 to 620-7), which invert the clock signals and output the inverted clock signals to each multiplexer (612, 622). The multiplexer (612) selectively outputs clock signals with an even number of delays (e.g., clock signals (Clk0, Clk2, Clk4, Clk6)) based on digital values ​​programmed or written to memory elements provided to the selection control nodes of the multiplexer (612). The multiplexer (622) selectively outputs clock signals with an odd number of delays (e.g., clock signals (Clk1, Clk3, Clk5, Clk7)) based on digital values ​​programmed or written to memory elements provided to the selection control nodes of the multiplexer (622). Generally, although it varies in some cases, the clock signals output by the multiplexers (612, 622) have a delay difference of one delay (e.g., a delay resulting from propagation through one buffer). For example, if a 4-times delayed inverted clock signal (Clk4) is selectively output from the multiplexer (612), a 3-times delayed inverted clock signal (Clk3) or a 5-times delayed inverted clock signal (Clk5) will generally be output from the multiplexer (622).

[0096] Inverted clock signals output from multiplexers (612, 622) are input to each programmable inverter (614, 624). The clock signal output from the programmable inverters (614, 624) to the input node of the inverter (630) is based on the respective driveability of the programmable inverters (614, 624). To clarify the description herein, the clock signal output by the multiplexer (612) has a phase difference ( The clock signal output by the multiplexer (622) has a phase difference (with respect to the phase of the clock signal (Clk0) ) has. Also, the programmable inverter (612) has a driving strength ( ) having, the programmable inverter (622) has a driving strength ( The resulting clock signal input to the inverter (630) has a phase difference ( It has ). Phase difference ( ) is generally (i) (a) driving strength( ) vs. driving strength( ) and driving strength( The ratio of agreement with ) and (b) phase difference ( The product of ) and (ii) (a) driving strength ( ) vs. driving strength( ) and driving strength ( The ratio of agreement with ) and (b) phase difference ( It is the sum of the products of ). This is mathematically reiterated below:

[0097]

[0098] The resulting clock signal passes through an inverter (630, 632) acting as a buffer circuit and is input to a duty cycle adjustment stage. As can be seen from the description above, by programmatically selecting which clock signals to output from the multiplexer (612, 622), the phase differences ( , ) can be programmatically selected, and by programmatically connecting the inverter stages in the programmable inverters (614, 624), the drivability and drive strengths ( , ) can be programmatically selected. Accordingly, the resulting phase difference of the clock signal output from the skew correction stage of the clock driver circuit (600) ( ) can be selected programmatically.

[0099] In the illustrated embodiment, multiplexers (612, 622), programmable inverters (614, 624), and inverters (630, 632) form a complementary metal-oxide-semiconductor-based (CMOS-based) phase interpolator and / or are contained within the phase interpolator. Being CMOS-based makes the phase interpolator efficient in terms of power and consumes low power.

[0100] The duty cycle adjustment stage of the clock driver circuit (600) includes p-type transistors (502, 504) and n-type transistors (506, 508) as described above in relation to FIG. 5. Since the duty cycle adjustment stage (e.g., the p-type transistors (502, 504) and n-type transistors (506, 508)) is configured to adjust the duty cycle of the clock signal as described above in relation to FIG. 5, a detailed description of the duty cycle adjustment stage in FIG. 6 is therefore omitted for brevity.

[0101] The clock driver circuit (600) may include additional components in other embodiments. For example, the clock driver circuit (600) may include an additional inverter having an input node electrically connected to the drains of a p-type transistor (504) and an n-type transistor (506), and an output node electrically connected to an output node (512) (for example, the inverter may be electrically connected between the drains and the output node (512)). In this embodiment, the single-ended output clock signal may logically correspond to the single-ended input clock signal (Clkin), possibly by an adjusted duty cycle (for example, not logically complementary to the single-ended input clock signal (Clkin)).

[0102] FIG. 8 is a schematic diagram of a signal driver circuit (800) according to some embodiments. The signal driver circuits (428) of FIG. 4a may include an example of a signal driver circuit (800) for each physical channel of the physical channels (204-12) driven by the signal driver circuits (428). The signal driver circuit (800) may be configured to equalize the signal to, for example, to offset variable signal attenuation at various different frequencies through the corresponding physical channel.

[0103] The signal driver circuit (800) includes inverters (802, 804, 806, 810, 814, 818), programmable impedance circuits (808, 812, 816), a p-type transistor (820), an n-type transistor (822), and an electrostatic discharge (ESD) protection circuit (824). The input node of the inverter (802), which is the input node (840) of the signal driver circuit (800), is electrically connected to a lane (842) (e.g., a data lane). The signal driver circuit (800) includes a primary path and a feedforward path from the output node of the inverter (802) to the output node (844) of the signal driver circuit (800), which is electrically connected to a physical channel (846) (e.g., a physical channel of the physical channels (204-12)). The main path includes an inverter (804). The input node of the inverter (804) is electrically connected to the output node of the inverter (802), and the output node of the inverter (804) is electrically connected to the output node (844) of the signal driver circuit (800).

[0104] The feedforward path includes inverters (806, 810, 814, 818) and programmable impedance circuits (808, 812, 816). The input node of inverter (806) is electrically connected to the output node of inverter (802). The output node of inverter (806) is electrically connected to the first terminal of programmable impedance circuit (808) and the input node of inverter (810). The output node of inverter (810) is electrically connected to the first terminal of programmable impedance circuit (812) and the input node of inverter (814). The output node of inverter (814) is electrically connected to the first terminal of programmable impedance circuit (816) and the input node of inverter (818). The output node of inverter (818) is electrically connected to the output node (844) of signal driver circuit (800). Each of the second terminals (the terminal opposite to the first terminal) of the programmable impedance circuits (808, 812, 816) is electrically connected to a second power supply node (e.g., a ground node).

[0105] A p-type transistor (820) is electrically connected between a first power supply (e.g., VDD power supply node) and a power input node of an inverter (818), and an n-type transistor (822) is electrically connected between another power input node of the inverter (818) and a second power supply node (e.g., a ground node). The source node of the p-type transistor (820) is electrically connected to the first power supply node (e.g., VDD power supply node), and the drain node of the p-type transistor (820) is electrically connected to a power input node of the inverter (818). The other power input node of the inverter (818) is electrically connected to the drain node of the n-type transistor (822). The source node of the n-type transistor (822) is electrically connected to a second power supply node (e.g., a ground node). The gate node of the p-type transistor (820) is electrically connected to the complementary enable node (ENB) (848), and the gate node of the n-type transistor (822) is electrically connected to the enable node (EN) (850).

[0106] In some embodiments, an enable node (EN) (850) is electrically coupled to a programmable memory element (e.g., a register, eFuse, or other memory). The memory element may be programmed or written to a logically high or logically low digital value, and the logically high or logically low value is applied to the enable node (EN) (850). An inverter may be electrically coupled between the memory element and a complementary enable node (ENB) (848) to logically complement the value programmed or written to the memory element, and the logically complemented value is applied to the complementary enable node (ENB) (848).

[0107] The inverter (818) can be selectively operably coupled between power supply nodes based on values ​​recorded in memory elements. When the signal on the enable node (EN) (850) is logically high (e.g., power supply voltage VDD) and the signal on the complementary enable node (ENB) (848) is correspondingly logically low (e.g., ground potential), the p-type transistor (820) and the n-type transistor (822) are in a conductive state, which causes the inverter (818) to be operably coupled between the power supply nodes. Conversely, when the signal on the enable node (EN) (850) is logically low and the signal on the complementary enable node (ENB) (848) is correspondingly logically high, the p-type transistor (820) and the n-type transistor (822) are in a non-conductive or open state, which causes the inverter (818) to be operably disconnected from the power supply nodes.

[0108] When the inverter (818) is operably disconnected from the feedforward path, the equalization in the signal driver circuit (800) is turned off. When operably coupled, the inverter (818) provides a current to the output node (844) that is added to the current output by the inverter (804). In the illustrated embodiment, the feedforward path is configured subtractively so that the current output from the inverter (818) is inverted and effectively subtracted from the current output output by the inverter (804). In the illustrated embodiment, the inverters (806, 810, 814, 818) in the feedforward path are configured to generate a signal of opposite polarity to the main path. In some embodiments, the feedforward path is configured additively so that the current output from the inverter (818) is not logically inverted and is added to the current output output by the inverter (804). If the inverter (818) is isolated to be operable between power supply nodes, generally no current is output from the inverter (818), so generally no equalization is provided by the feedforward path.

[0109] When the inverter (818) is operably coupled, the signal driver circuit (800) can provide sub-UI type equalization. In the illustrated embodiment, the feedforward path can create an inversion for the main path. The feedforward path creates a delay difference for the main path that may be equal to 1 UI, where 1 UI is the inverse of the data rate of the data through the signal driver circuit (800). In this way, the low-frequency components of the signal at the output node (844) can be attenuated, while the high-frequency components of the signal at the output node (844) can be amplified. Programmable impedance circuits (808, 812, 816) allow the delay introduced by the feedforward path to be tuned to be close to 1 UI, where equalization may be more effective. When the inverter (818) is operably coupled between the power supply nodes, the signal driver circuit (800) can implement a finite impulse response (FIR) filter.

[0110] Additionally, the ESD protection circuit (824) is electrically connected to the output node (844). The ESD protection circuit (824) includes diodes (826, 828). Diode (826) has a cathode electrically connected to a first power supply node (e.g., VDD power supply node) and an anode electrically connected to the output node (844). Diode (828) has a cathode electrically connected to the output node (844) and an anode electrically connected to a second power supply node (e.g., ground node).

[0111] FIG. 9 is a schematic circuit diagram of an impedance array (900) according to some embodiments. The impedance array (900) comprises q impedance elements (902-1, 902-2 to 902-q) (individually or collectively, impedance element(s) (902)) and q switches (904-1, 904-2 to 904-q) (individually or collectively, switch(s) (904)). An impedance element (902) is electrically connected in series with a corresponding switch (904). The series-connected pairs of impedance elements (902) and switches (904) are electrically connected in parallel between a first terminal (906) of the impedance array (900) and a second terminal (908) of the impedance array (900).

[0112] Each switch (904) is controlled (C x It also has a ) node, where x is the indicator of the corresponding switch (904) (e.g., x is 1 in the case of switch (904-1)). Each switch (904) is a control (C x It is configured to be selectively opened or closed based on a signal received at the node. Each switch (904) may be a transistor (e.g., a p-type or n-type transistor), a transmission gate, or another switch. Each impedance element (902) may be a resistor, a capacitor, an inductor, or any combination or permutation thereof, or may include such.

[0113] The impedance array (900) is configured to selectively electrically connect or disconnect impedance elements in parallel based on the state (e.g., open or closed) of the switches (904). The impedance array (900) is programmable. In some embodiments, a control signal (C x ) can be stored in a memory element (e.g., a register, eFuse, or other memory). The output node of the memory element is each control (C x Electrically coupled to the ) node, the control signal (C xControl ) (C x Provided to the node so that the state of the corresponding switch (904) is controlled.

[0114] FIG. 10 is a schematic circuit diagram of an impedance array (1000) according to some embodiments. The impedance array (1000) comprises r impedance elements (1002-1, 1002-2 to 1002-r) (individually or collectively, impedance element(s) (1002)) and r switches (1004-1, 1004-2 to 1004-r) (individually or collectively, switch(s) (1004)). The impedance elements (1002) are electrically connected in parallel with the corresponding switches (1004). Pairs of impedance elements (1002) and switches (1004) connected in parallel are electrically connected in series between the first terminal (1006) of the impedance array (1000) and the second terminal (1008) of the impedance array (1000).

[0115] Each switch (1004) is controlled (C x ) additionally, where x is an indication of the corresponding switch (1004) (e.g., x is 1 in the case of switch (1004-1)). Each switch (1004) is a control (C x It is configured to be selectively opened or closed based on a signal received at the node. Each switch (1004) may be a transistor (e.g., a p-type or n-type transistor), a transmission gate, or another switch. Each impedance element (1002) may be a resistor, a capacitor, an inductor, or any combination or permutation thereof, or may include such.

[0116] The impedance array (1000) is configured to selectively electrically connect or disconnect impedance elements in series based on the state (e.g., open or closed) of the switches (1004). When the switch (1004) is open, the corresponding impedance element (1002) of the parallel-connected pair is electrically connected in series with any other impedance element of the impedance array (1000). When the switch (1004) is closed, the corresponding impedance element (1002) of the parallel-connected pair is electrically short-circuited and bypassed by the closed switch (1004), so the impedance element (1002) is not connected in series with any other impedance element of the impedance array (1000). The impedance array (1000) is programmable. In some embodiments, a control signal (C x ) can be stored in storage elements such as memory, registers, etc. The output node of the storage element is each control (C x Electrically coupled to the ) node, the control signal (C x Control ) (C x Provided to the node so that the state of the corresponding switch (1004) is controlled.

[0117] The impedance arrays (900, 1000) of FIGS. 9 and 10 may be implemented as any or each of the programmable impedance circuits (808, 812, 816) of FIG. 8, together or individually, in any configuration, arrangement, or permutation. Thus, the programmable impedance circuits (808, 812, 816) may be programmable to provide multiple impedances, which allows the signal driver circuit (800) to be programmable to provide multiple different delays for equalization.

[0118] According to some examples, the structure of the WLFO package (100) and IC dies (102) (and the circuits within them) is co-designed, which enables high bandwidth density and high power efficiency to be achieved. In a specific embodiment, the WLFO package (100) is an InFO package. Single-ended source synchronous data links (e.g., physical channels) operating at 13.25 Gbps are connected through a redistribution structure (110) of the innFO package. By utilizing the fine dimensions of lnFO packaging technology (e.g., 2 μm metal line width of adjacent metal lines, 2 μm spacing between adjacent metal lines, and 4 μm pitch of adjacent metal lines), the integrated throughput can be 2.53 Tbps over 2.5 mm along the lateral sidewalls (152-1, 152-2) of the IC dies (102-1, 102-2), and thus a high bandwidth density of more than 1 Tbps / mm can be achieved. In some embodiments, a high bandwidth density of more than 2 Tbps / mm can be achieved. The joint design of the IC dies and the WLFO package (100) can provide additional degrees of freedom. For example, metal line spacing and shielding (as shown, for example, in FIG. 3) can be implemented to reduce crosstalk noise and improve the received signal-to-noise ratio (SNR) while achieving 0.13 pJ / bit or better power efficiency.

[0119] In some embodiments, a single-ended signaling scheme (e.g., a single-ended NRZ signaling scheme) is implemented to transmit data signals between transceiver circuits (202) of different IC dies (102). The single-ended NRZ signaling scheme may have high pin efficiency and low power requirements. The single-ended NRZ signaling scheme may be at least partially enabled by co-designing the IC dies (102) and the WLFO package (100), which allows channel characteristics (e.g., crosstalk) and electrical performance to be considered and processed together. In some embodiments, the supply voltage (e.g., supply voltage VDD) is selected to be 0.65 V, which is 1x10 -12 Power consumption can be reduced while achieving a bit error rate (BER).

[0120] Various embodiments implement source-synchronous transceivers. Transmitter circuits (e.g., transmitter circuit (202-1T)) transmit a clock signal that corresponding receiver circuits (e.g., receiver circuit (202-1R)) use to capture data transmitted from each transmitter circuit and received by the receiver circuit. Data can be transmitted as individual single-ended signals as mentioned above, and clock signals can be transmitted as differential signals. The received clock signal can be used to capture data, optionally after skew correction. The receiver circuit can capture data from data signals on multiple physical channels using a single clock signal. In the illustrated embodiment of FIGS. 4a and 4b, one clock signal is used to capture data from 16 physical channels as previously described. Thus, in the illustrated embodiment, the data lane to clock signal ratio is 16:1. Transmitting clock signals in this manner can simplify the design of clock generation in receiver circuits and improve power efficiency. A high data lane-to-clock ratio can minimize the number of clock signals transmitted from the transmitter circuit to the receiver circuit, which can improve bandwidth density and power efficiency.

[0121] In some cases, a high clock sharing ratio can degrade the horizontal eye margin. Therefore, in such cases, low clock and data skew may be desirable. To reduce this skew, the characteristics of the physical channels can be well matched through the redistribution structure of the WLFO package. For example, the metal line lengths of the physical channels transmitting data signals that share the clock signal can be substantially the same as the metal line lengths of the physical channels transmitting the clock signal. For instance, if the metal line lengths are not well matched, the clock signal or data signal may experience more latency during transmission due to the larger resistance-capacitance (RC) time constant of the metal lines, which can, for instance, generate greater skew. This matching may explain other reasons for the joint design of the IC die and the WLFO package.

[0122] In some embodiments, clock signals used in the receiver circuit to capture data may need to be tuned to capture data at a relatively large eye opening. To tune the clock signals, a clock driver circuit (600) may be implemented. In some embodiments, the clock driver circuit (600) implements a CMOS-based phase interpolator, which may be power-efficient, such as 0.018 pJ / bit, and easy to scale with frequency. The CMOS-based phase interpolator may have a step size of approximately 3 ps. Additionally, duty cycle distortion of the clock signal may be corrected or adjusted for a better eye margin. In some embodiments, the clock driver circuit (600) may have a correction range of approximately 3 ps for both the rising edge and the falling edge.

[0123] In some cases, however, under given power constraints, it may be desirable to operate each physical channel so that data is transmitted at the highest possible data rate to maximize bandwidth density. Accordingly, in some embodiments, the transmitter circuit implements the signal driver circuit (800) of FIG. 8, which selectively enables equalization. When equalization is performed, channel loss can be equalized, and in some cases, a data rate of 13.25 Gbps can be achieved at a cost of 0.01 pJ / bit. It has been found that performing equalization increases the eye-opening margin in the receiver circuit.

[0124] Various components of the embodiments described above have been described as programmable. In some embodiments, the transceiver circuits implemented in the WLFO package are not programmable. In other embodiments implementing various programmable components, these components may be programmed once or multiple times. For example, once the WLFO package is manufactured, the channel characteristics of the WLFO package become largely static. After manufacturing, tests may be performed, and appropriate memory elements may be programmed based on the test results to achieve, for example, a clock signal with an appropriate duty cycle and / or skew, and / or to implement appropriate equalization. The memory elements may be, for example, eFuses that can be disconnected for programming the memory elements. Because the channel characteristics are largely static, the appropriate functionality of the WLFO package may be achieved by disconnecting the eFuse once. In other embodiments, the channel characteristics may change over the lifetime of the WLFO package, for example, due to process voltage-temperature (PVT) fluctuations. In such cases, the IC die may implement a processor or controller capable of implementing an adaptive algorithm that can dynamically program memory elements, for example, based on a PVT monitor, BER, or any other criterion. In these embodiments, the memory elements may be, for example, static random access memory (SRAM) or other latch circuits.

[0125] FIG. 11 is a flowchart of a method (1100) for operating an electronic device according to some embodiments. This method (1100) is described in the context of the aforementioned embodiments and drawings, particularly FIG. 4a and FIG. 4b. A subset of the functionality of the aforementioned embodiments and drawings is described in relation to the method (1100), and those skilled in the art will readily understand that the method (1100) can be applied to each of the entire embodiments. The following description relating to FIGS. 4a and 4b is provided in the sense that the transmitter circuit (202-1T) of the transceiver circuit (202-1) transmits a data signal to the receiver circuit (202-2R) of the transceiver circuit (202-2), but it will be understood that the transceiver circuit (202-1) may include the receiver circuit (202-1R), the transceiver circuit (202-2) may include the transmitter circuit (202-2T), and the transmitter circuit (202-2T) may transmit a data signal to the receiver circuit (202-1R).

[0126] In block 1102, a first single-ended clock signal and parallel data are received in the transmitter circuit of the transceiver circuit of the first IC die. For example, the parallel data is received in the buffer circuit (402) of the transmitter circuit (202-1T), and the single-ended clock signal is received in the clock driver circuit (406) of the transmitter circuit (202-1T).

[0127] In block 1104, a differential clock signal is generated based on a first single-ended clock signal by a single-ended differential converter circuit of the transmitter circuit. For example, the S2D converter circuit (412-1) generates a differential clock signal based on a single-ended clock signal received from the clock driver circuit (406).

[0128] In block 1106, optionally, a second single-ended clock signal is generated by adjusting the duty cycle of the first single-ended clock signal by the clock driver circuit of the transmitter circuit. For example, the clock driver circuit (414-1) can adjust the duty cycle of the single-ended clock signal from the clock driver circuit (406). In other embodiments, the clock driver circuit (414-1) buffers the single-ended clock signal received from the clock driver circuit (406) without adjusting the duty cycle.

[0129] In block 1108, parallel data is serialized based on a second single-ended clock signal by the serializer circuit of the transmitter circuit. For example, the serializer circuit (410-1) serializes parallel data received from the buffer circuit (402) based on a single-ended clock signal generated by the clock driver circuit (414-1).

[0130] In block 1110, serialized data and differential clock signals from the serializer circuit are transmitted to the transceiver circuit of the second IC die through physical channels. For example, serialized data output by the serializer circuit (410-1) and differential clock signals output by the S2D converter circuit (412-1) are transmitted to the transceiver circuit (202-2) through physical channels (204-12) by signal driver circuits (428). The signal driver circuits (428) can drive serialized data (e.g., single-ended data signals) and differential clock signals on the physical channels. The signal driver circuits (428) can also equalize the single-ended data signals and differential clock signals.

[0131] In block 1112, a third single-ended clock signal is generated based on the differential clock signal by the differential-single-ended converter circuit of the receiver circuit. For example, the D2S converter circuit (452-1) receives the differential clock signal generated by the S2D converter circuit (412-1) and generates a single-ended clock signal based on the differential clock signal.

[0132] In block 1114, optionally, a fourth single-ended clock signal is generated by skew correction and adjustment of the duty cycle of the third single-ended clock signal by the clock driver circuit of the receiver circuit. For example, the clock driver circuit (454-1) can generate a single-ended clock signal by skew correction and adjustment of the duty cycle of the single-ended clock signal generated by the D2S converter circuit (452-1). In other embodiments, the clock driver circuit (454-1) buffers the single-ended clock signal generated by the D2S converter circuit (452-1) without skew correction and / or adjustment of the duty cycle.

[0133] In block 1116, serialized data is captured and deserialized by the deserializer circuit of the receiver circuit based on a fourth single-ended clock signal. For example, the deserializer circuit (450-1) captures serialized data from data signals on physical channels (204-12) that is serialized by the serializer circuit (410-1), and deserializes the data based on a single-ended clock signal generated by the clock driver circuit (454-1).

[0134] In block 1118, deserialized parallel data is output from the receiver circuit. For example, deserialized parallel data from the deserializer circuit (450-1) is output from the receiver circuit (202-2R) through buffer circuits (458, 470).

[0135] Other functions of the embodiments and the structures of the embodiments have been described above, and those skilled in the art will easily understand these functions and structures from the foregoing description.

[0136] Although the foregoing describes specific embodiments, other embodiments and additional embodiments may be devised without departing from the basic scope of the present invention, and the scope of the present invention is determined by the following claims.

Claims

Claim 1 An electronic device comprising a wafer-level fan-out package, wherein the wafer-level fan-out package comprises: a first integrated circuit (IC) die comprising a transmitter circuit; a second IC die comprising a receiver circuit; and a redistribution structure comprising physical channels electrically connected to the transmitter circuit and the receiver circuit and between the transmitter circuit and the receiver circuit, wherein the transmitter circuit is configured to transmit a plurality of single-ended data signals and a differential clock signal to the receiver circuit through the physical channels, and the receiver circuit is configured to capture data from the plurality of single-ended data signals using a first single-ended clock signal based on the differential clock signal, wherein the physical channels comprise channel metal lines within the redistribution structure, and the channel metal lines are alternately arranged with shielding metal lines within the redistribution structure. Claim 2 delete Claim 3 An electronic device according to claim 1, wherein the transmitter circuit comprises: a single-ended differential converter circuit configured to generate the differential clock signal based on a second single-ended clock signal; and a serializer circuit configured to receive parallel data, serialize the parallel data based on the second single-ended clock signal or a third single-ended clock signal based on the second single-ended clock signal, and output the serialized data - the transmitter circuit is configured to transmit the serialized data as the plurality of single-ended data signals. Claim 4 An electronic device according to paragraph 3, wherein the transmitter circuit comprises a clock driver circuit configured to generate the third single-ended clock signal by adjusting the duty cycle of the second single-ended clock signal. Claim 5 An electronic device according to claim 1, wherein the transmitter circuit comprises signal driver circuits configured to drive the plurality of single-ended data signals and the differential clock signal on the physical channels. Claim 6 An electronic device according to claim 5, wherein each of the signal driver circuits is configured to equalize the plurality of single-ended data signals. Claim 7 An electronic device according to claim 5, wherein each of the signal driver circuits comprises: a main path electrically connected between a first node and a driver output node and comprising a first inverter; and a secondary path electrically connected between the first node and the driver output node and comprising second inverters and an impedance circuit, wherein the second inverters are configured to generate a signal of opposite polarity to the main path. Claim 8 An electronic device according to claim 7, wherein the impedance circuit is programmable; and at least one of the second inverters is configured to be programmably and selectively coupled to the secondary path. Claim 9 An electronic device according to claim 1, wherein the receiver circuit comprises: a differential-single-ended converter circuit configured to generate a second single-ended clock signal based on the differential clock signal; and a deserializer circuit configured to receive at least some of the plurality of single-ended data signals and deserialize data from at least some of the plurality of single-ended data signals based on the second single-ended clock signal or the first single-ended clock signal based on the second single-ended clock signal. Claim 10 An electronic device according to claim 9, wherein the receiver circuit comprises a clock driver circuit configured to generate the first single-ended clock signal by deskewing the second single-ended clock signal and adjusting the duty cycle of the second single-ended clock signal. Claim 11 As an electronic device, a first transceiver circuit in a first integrated circuit (IC) die disposed within a wafer-level fan-out package; a second transceiver circuit in a second IC die disposed within the wafer-level fan-out package; and includes physical channels within a redistribution structure of the wafer-level fan-out package; the first transceiver circuit is configured to transmit a plurality of first single-ended data signals and a first differential clock signal to the second transceiver circuit through a first subset of the physical channels; the second transceiver circuit is configured to transmit a plurality of second single-ended data signals and a second differential clock signal to the first transceiver circuit through a second subset of the physical channels; the second transceiver circuit is configured to capture data from the plurality of first single-ended data signals using a first single-ended clock signal based on the first differential clock signal; and the first transceiver circuit is configured to capture data from the plurality of second single-ended data signals using a second single-ended clock signal based on the second differential clock signal, and the physical channels are channel metal lines laterally arranged between the first IC die and the second IC die within the redistribution structure - the channel An electronic device comprising metal lines that are alternately arranged with shielding metal lines within the redistribution structure. Claim 12 delete Claim 13 In claim 11, the first transceiver circuit comprises: a first single-ended differential converter circuit configured to generate the first differential clock signal based on the third single-ended clock signal; and a first serializer circuit configured to receive first parallel data, serialize the first parallel data based on the third single-ended clock signal or a fourth single-ended clock signal based on the third single-ended clock signal, and output the first serialized data - the first transceiver circuit is configured to transmit the first serialized data as the plurality of first single-ended data signals -; and a first differential single-ended converter circuit configured to generate the fifth single-ended clock signal based on the second differential clock signal; and includes a first deserializer circuit configured to deserialize data from the plurality of second single-ended data signals based on the fifth single-ended clock signal or the second single-ended clock signal based on the fifth single-ended clock signal; the second transceiver circuit comprises: a second single-ended-differential converter circuit configured to generate the second differential clock signal based on the sixth single-ended clock signal; and a second serializer circuit configured to receive second parallel data, serialize the second parallel data based on the sixth single-ended clock signal or the seventh single-ended clock signal based on the sixth single-ended clock signal, and output the second serialized data - the second transceiver circuit is configured to transmit the second serialized data as the plurality of second single-ended data signals -; and a second differential-single-ended converter circuit configured to generate an eighth single-ended clock signal based on the first differential clock signal;An electronic device comprising a second deserializer circuit configured to deserialize data from a plurality of first single-ended data signals based on the eighth single-ended clock signal or the first single-ended clock signal based on the eighth single-ended clock signal. Claim 14 An electronic device according to claim 11, wherein the first transceiver circuit comprises first signal driver circuits configured to drive the plurality of first single-ended data signals and the first differential clock signal in a first subset of the physical channels—the first signal driver circuits are configured to equalize the plurality of first single-ended data signals; and the second transceiver circuit comprises second signal driver circuits configured to drive the plurality of second single-ended data signals and the second differential clock signal in a second subset of the physical channels—the second signal driver circuits are configured to equalize the plurality of second single-ended data signals. Claim 15 A method for operating an electronic device, comprising: generating a differential clock signal based on a first single-ended clock signal by a single-ended differential converter circuit of a first transceiver circuit of a first integrated circuit (IC) die, wherein the first IC die is disposed within a wafer-level fan-out package; serializing parallel data based on the first single-ended clock signal by a serializer circuit of the first transceiver circuit; transmitting the serialized data and the differential clock signal from the serializer circuit to a second transceiver circuit of a second IC die through physical channels of the wafer-level fan-out package, wherein the second IC die is disposed within the wafer-level fan-out package; and deserializing the serialized data based on the differential clock signal by a deserializer circuit of the second transceiver circuit.

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