Memory device performing target refresh operation and operating method thereof

Abstract

A memory device according to an embodiment of the present invention comprises: a memory cell region including normal cells connected to a plurality of normal column selection lines, redundancy cells and raw-hammer cells respectively connected to a plurality of redundancy column selection lines; a repair control circuit providing repair addresses and raw-hammer flag signals corresponding to repair information according to a raw address; and a column control circuit that activates one of the redundancy column selection lines in response to a comparison result between a column address and the repair addresses, or in response to the raw-hammer flag signals, according to a tracking signal.

Description

Technology Field

[0001] The present invention relates to semiconductor design technology, and specifically, the present invention relates to a memory system including a memory device that performs a target refresh operation. Background Technology

[0003] Recently, in addition to the normal refresh operation that sequentially refreshes multiple rows, an additional refresh operation (hereinafter referred to as the “target refresh operation”) is performed on memory cells of a specific row (hereinafter referred to as the “target row”) that is highly likely to lose data due to the row hammering phenomenon. The row hammering phenomenon refers to a phenomenon in which data in memory cells connected to the target row or adjacent rows is damaged due to a high number of activations of a specific row. To prevent such row hammering phenomena, a target refresh operation is performed on the target row or adjacent rows of the target row that are activated more than a predetermined number of times. The problem to be solved

[0005] Embodiments of the present invention provide a memory device capable of allocating memory cells connected to unused columns of a redundancy cell region, which are arranged to repair a normal cell region, into raw-hammer cells, and selecting a target address according to the access counting value of each row stored in the allocated raw-hammer cells. means of solving the problem

[0007] According to one embodiment of the present invention, the memory device may include: a memory cell region comprising normal cells connected to a plurality of normal column selection lines, redundancy cells and raw-hammer cells each connected to a plurality of redundancy column selection lines; a repair control circuit providing repair addresses and raw-hammer flag signals corresponding to repair information according to a raw address; and a column control circuit that activates one of the redundancy column selection lines in response to a comparison result between a column address and the repair addresses, or in response to the raw-hammer flag signals, according to a tracking signal.

[0008] According to one embodiment of the present invention, the memory device may include: a memory cell region comprising a plurality of normal column selection lines and a plurality of redundancy column selection lines, wherein memory cells connected to a redundancy column selection line not used for repair among the redundancy column selection lines are allocated as raw-hammer memory cells; a refresh control circuit that, in a raw-hammer tracking mode, selects a target address based on access counting data output from the raw-hammer cells, updates the access counting data, and controls it to write back to the raw-hammer cells; and a row control circuit that refreshes one or more adjacent rows corresponding to the target address according to a target refresh command.

[0009] According to one embodiment of the present invention, a method of operating a memory device may include: a step of outputting repair information stored in a non-volatile storage device as fuse array data according to a fuse address during boot-up; a step of providing the fuse array data as a plurality of fuse data and a plurality of flag data according to the fuse address, wherein if the fuse array data is detected to be unused data, the corresponding fuse data is masked and the corresponding flag data is activated; and a step of storing the plurality of fuse data and the plurality of flag data in a plurality of latch circuits, respectively.

[0010] According to one embodiment of the present invention, a method of operating a memory device may include: storing a plurality of repair addresses and a plurality of low-hammer flag signals corresponding to a plurality of redundancy column selection lines based on repair information stored during boot-up, wherein the repair address corresponding to an unused redundancy column selection line among the redundancy column selection lines is not stored and the corresponding low-hammer flag signal is set to a high bit; during a low-hammer tracking mode, selecting one of the redundancy column selection lines according to the low-hammer flag signals and reading access counting data from low-hammer cells connected to the selected redundancy column selection line; and selecting a target address using the access counting data and updating the access counting data to write back to the low-hammer cells. Effects of the invention

[0012] According to embodiments of the present invention, by utilizing memory cells connected to unused columns of the redundancy cell area as raw-hammer cells, the utilization of the redundancy cell area can be increased without adding a separate raw-hammer area.

[0013] In addition, by selecting a target address based on the access counting value stored in the low-hammer cells, the low-hammer defense capability can be optimized and power consumption minimized. Furthermore, by performing a target refresh operation based on the target address, the accuracy and efficiency of the refresh operation can be improved. Brief explanation of the drawing

[0015] FIG. 1 is a block diagram of a memory device according to an embodiment of the present invention. FIG. 2a and FIG. 2b are drawings for explaining the memory cell region of FIG. 1 in more detail. FIG. 3 is a detailed configuration diagram of the refresh control circuit of FIG. 1. FIG. 4 is a detailed configuration diagram of the repair control circuit of FIG. 1. FIG. 5 is a detailed circuit diagram of the latch control circuit of FIG. 4. FIG. 6 is a detailed configuration diagram of the first latch circuit of FIG. 4. FIG. 7 and FIG. 8 are a flowchart and a timing diagram for explaining the boot-up operation according to an embodiment of the present invention. FIG. 9 is a detailed configuration diagram of the column control circuit of FIG. 1. FIG. 10 is a detailed circuit diagram of the address comparison circuit of FIG. 9. FIG. 11 is an operation flowchart for explaining the operation of a memory device according to an embodiment of the present invention. FIG. 12 is a drawing to aid in understanding the operation of FIG. 11. FIG. 13 is a detailed configuration diagram of the repair control circuit of FIG. 1 according to another embodiment of the present invention. FIG. 14 is a detailed configuration diagram of the latch control circuit of FIG. 13. FIG. 15 is a detailed configuration diagram of the first latch circuit of FIG. 13. FIG. 16 is a detailed circuit diagram of the flag setting circuit of FIG. 15. Specific details for implementing the invention

[0016] Hereinafter, in order to explain in detail enough for a person skilled in the art to easily implement the technical concept of the present invention, embodiments of the present invention will be described with reference to the accompanying drawings.

[0017] Furthermore, throughout the specification, when a part is described as being "connected" to another part, this includes not only cases where they are "directly connected" but also cases where they are "electrically connected" with an intermediate circuit in between. Additionally, when a part is described as "including" or "equipped" with a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include or be equipped with additional components. Moreover, it will be understood that even if some components are described in the singular form throughout the specification, the present invention is not limited thereto, and such components may be composed of multiple units.

[0019] FIG. 1 is a block diagram of a memory device (100) according to an embodiment of the present invention. FIG. 2a and FIG. 2b are drawings for explaining the memory cell region of FIG. 1 in more detail.

[0020] Referring to FIG. 1, the memory device (100) may include a memory cell area (110), a refresh control circuit (120), a row control circuit (130), a repair control circuit (140), a column control circuit (150), an error correction circuit (160), a data input / output circuit (170), a command decoder (182), and an address buffer (184).

[0021] The command decoder (182) can receive a command (CMD) from an external device (e.g., a memory controller), decode it, and generate an active command (ACT), a precharge command (PCG), a target refresh command (TREF), a read command (RD), a write command (WT), etc. In addition, the command decoder (182) can decode the input command (CMD) to generate a mode register command, a normal refresh command, etc., but since these are not directly related to the memory device according to one embodiment of the present invention, they are omitted from illustration and description here. The address buffer (184) can receive an address (ADD) from an external device and generate a row address (RA) and a column address (CA). Each of the command (CMD) and the address (ADD) may include multi-bit signals.

[0022] In the memory cell region (110), a plurality of memory cells (MC, RC, RHC) connected to a plurality of word lines (WL) (hereinafter, rows) and a plurality of bit lines (BL, RBL) (hereinafter, columns) may be arranged in an array form. A plurality of rows (WL) may be extended in a first direction (e.g., row direction) and arranged sequentially in a second direction (e.g., column direction). A plurality of columns (BL, RBL) may be extended in a column direction and arranged sequentially in a row direction. According to an embodiment, the memory cell region (110) may include a plurality of cell blocks. In an embodiment of the present invention, a “cell block” may be defined as a set of memory cells that share rows (WL) and columns (BL, RBL) and are arranged in the same form. The number of cell blocks or the number of memory cells may be determined according to the capacity of the memory device (100).

[0023] In an embodiment of the present invention, the memory cell region (110) may be divided into a normal cell region (112) and a redundancy cell region (114). In the normal cell region (112), a plurality of normal cells (MC) connected to a plurality of rows (WL) and a plurality of columns (BL) may be arranged in an array form. In the redundancy cell region (114), a plurality of redundancy cells (RC) and a plurality of raw-hammer cells (RHC) connected to a plurality of rows (WL) and a plurality of columns (RBL) may be arranged in an array form. That is, a plurality of normal cells (MC), a plurality of redundancy cells (RC), and a plurality of raw-hammer cells (RHC) may be arranged in each of the plurality of rows (WL). The plurality of normal cells (MC) may store normal data including user data. Multiple redundancy cells (RC) may be placed to repair defective cells among multiple normal cells (MC). Multiple row-hammer cells (RHC) may store access counting data (A_CNT) that stores the number of accesses for each row. Hereinafter, multiple columns (BL) connected to the normal cell area (112) are referred to as “normal columns,” and multiple columns (RBL) connected to the redundancy cell area (114) are referred to as “redundancy columns.”

[0024] Referring to FIG. 2a, the memory cell region (110) may include a plurality of cell blocks (MB00~MB07, MB10~MB17, …, MB70~MB77, MB0ECC, MB1ECC, …, MB7ECC) arranged in an array form in the row direction and column direction. For example, FIG. 2a illustrates a case in which nine cell blocks (MB00~MB07, MB7ECC) arranged in the row direction form a first group (G0), nine cell blocks (MB10~MB17, MB1ECC) arranged in the next row direction form a second group (G1), and in this way, nine cell blocks (MB70~MB77) arranged in the row direction form an eighth group (G7). That is, the first to eighth groups (G0 to G7) are arranged sequentially in the column direction, and the cell blocks within each group may be arranged sequentially in the row direction. Cell blocks of the same group may share rows (WL), and cell blocks placed in the same column of each group may share columns (BL, RBL). The column control circuit (150) may include a plurality of column control circuits (150_0 to 150_ECC). The plurality of column control circuits (150_0 to 150_ECC) may be connected to corresponding cell blocks through the shared columns (BL, RBL), each corresponding to the cell blocks placed in the same column.

[0025] Since the cell blocks of each group have the same configuration, the first group (G0) is used as an example for explanation. The cell blocks (MB00~MB07, MB0ECC) within the first group (G0) may include a plurality of normal cell blocks (MB00~MB07) and an ECC cell block (MB0ECC). The normal cell blocks (MB00~MB07) can store data (D1) received from an external device or output stored data through a column control circuit (150_0~150_7) and a data input / output circuit (170). The normal cell blocks (MB00~MB07) are memory blocks that determine the memory capacity of the memory device (100) and are areas for storing user data. The ECC cell block (MB0ECC) can store or output an error correction code (PTY) generated from an error correction circuit (160) through the column control circuit (150_ECC). The error correction code (PTY) may include known parity bits. Cell blocks (MB00~MB07, MB0ECC) may each include a normal cell region (112) and a redundancy cell region (114) of FIG. 1. That is, cell blocks (MB00~MB07, MB0ECC) may each include a plurality of memory cells (MC, RC, RHC) arranged in an array form between a plurality of rows (WL) and a plurality of columns (BL, RBL).

[0026] Referring to FIG. 2b, the configuration of a cell block (e.g., cell block (MB00)) is illustrated. In the normal cell area (112), a plurality of normal cells (MC) connected to a plurality of rows (WL) and a plurality of normal columns (BL) may be arranged in an array form. In the redundancy cell area (114), a plurality of redundancy cells (RC) and a plurality of row-hammer cells (RHC) connected to a plurality of rows (WL) and a plurality of redundancy columns (RBL) may be arranged in an array form. Meanwhile, a predetermined number (e.g., 8) of columns (BL, RBL) may be connected to a single column selection line (CSL, RCSL), and the column control circuit (150_0) may simultaneously select a predetermined number (e.g., 8) of columns by selecting at least one column selection line among the plurality of column selection lines (CSL, RCSL) according to the column address (CA). Accordingly, 64-bit data (D1) and 8-bit error correction code (PTY) can be read or written simultaneously from the cell blocks (MB00~MB07, MB0ECC) of the first group (G0).

[0027] Hereinafter, column selection lines (CSL) connected to normal columns (BL) are referred to as “normal column selection lines,” and multiple column selection lines (RCSL) connected to redundancy columns (RBL) are referred to as “redundancy column selection lines.” In an embodiment of the present invention, each cell block of the memory cell region (110) may include normal cells (MC) connected to a plurality of normal column selection lines (CSL), redundancy cells (RC) and raw-hammer cells (RHC) each connected to a plurality of redundancy column selection lines (RCSL), and memory cells connected to a redundancy column selection line (hereinafter referred to as 'raw-hammer column selection line') among the redundancy column selection lines (RCSL) of the redundancy cell region (114) that is not used for repair may be allocated as raw-hammer cells (RHC), and access counting data (A_CNT) that stores the number of accesses of each row may be stored in the allocated raw-hammer cells (RHC).

[0028] Referring again to FIG. 1, the refresh control circuit (120) can select a row address (RA) as a target address (TADD in FIG. 3) based on access counting data (A_CNT) provided from the row hammer cells (RHC) during the row hammer tracking mode. The refresh control circuit (120) can operate according to a tracking signal (RHT_EN) that is activated during the row hammer tracking mode and deactivated during the normal mode. For reference, the tracking signal (RHT_EN) may be a signal that is activated after a predetermined time from the input of an active command (ACT) and deactivated before a read command (RD) or write command (WT) is input. That is, the refresh control circuit (120) can receive access counting data (A_CNT) read from the low-hammer cells (RHC) connected to the low activated by the active command (ACT) during the low-hammer tracking mode. According to an embodiment, the tracking signal (RHT_EN) may be generated internally according to the active command (ACT) or provided from an external device after a predetermined time from the input of the active command (ACT).

[0029] The refresh control circuit (120) can output a target address (TADD) or a row address (RA) as a final row address (XADD) according to a target refresh command (TREF). Additionally, the refresh control circuit (120) can update access counting data (A_CNT) in the row hammer tracking mode and write back to multiple row hammer cells (RHC). The refresh control circuit (120) can sequentially issue an internal read signal (IRD) and an internal write signal (IWT) to read and write back access counting data (A_CNT) from multiple row hammer cells (RHC). The detailed configuration of the refresh control circuit (120) will be described in detail in FIG. 3.

[0030] The row control circuit (130) can be connected to the normal cells (MC) of the normal cell area (112), the redundancy cells (RC) of the redundancy cell area (114), and the row-hammer cells (RHC) through a plurality of rows (WL). The row control circuit (130) can activate a row corresponding to the final row address (XADD) when the active command (ACT) is activated, and can precharge the activated row when the precharge command (PCG) is activated. The row control circuit (130) can perform a target refresh operation to refresh one or more adjacent rows corresponding to the final row address (XADD) according to the target refresh command (TREF).

[0031] The repair control circuit (140) may include a non-volatile storage circuit (142) that stores repair information (INF_R) at the fault addresses of the cell blocks. The non-volatile storage circuit (142) can store the internal repair information (INF_R) without losing it even when the power is turned off. The repair control circuit (140) can store the repair information (INF_R) stored in the non-volatile storage circuit (142) in internal latch circuits (145_1 to 145_3 of FIG. 4) according to the boot-up signal (BOOT_UP) and clock signal (CLK) during boot-up. The repair control circuit (140) can provide repair addresses (REP_ADD#) and low-hammer flag signals (CRHT#) corresponding to repair information (INF_R) stored in latch circuits (145_1 to 145_3) according to the low address (RA).

[0032] For reference, the repair addresses (REP_ADD#) may correspond to column addresses for specifying column selection lines to which the defective cells are connected among the normal column selection lines. The repair addresses (REP_ADD#) and the low-hammer flag signals (CRHT#) may be provided in a number corresponding to the number of redundancy column selection lines (RCSL) of the redundancy cell area (114). Hereinafter, the case where three redundancy column selection lines (RCSL) are provided for each cell block will be described as an example. In this case, the reference numeral “#” may be defined as a natural number from 1 to 3.

[0033] Since the cell blocks of each group share the same rows (WL) and read the stored data simultaneously, the same fault address can be stored as repair information (INF_R) for each group. Accordingly, the repair control circuit (140) can provide repair addresses (REP_ADD#) and low-hammer flag signals (CRHT#) corresponding to the repair information (INF_R) stored in the latch circuits (145_1 to 145_3) according to the bits of the row address (RA) for specifying each group. In particular, in an embodiment of the present invention, the repair control circuit (140) stores repair addresses (REP_ADD#) corresponding to each of the redundancy column selection lines (RCSL) based on the repair information (INF_R) upon boot-up, but does not store the repair address corresponding to the unused redundancy column selection line among the redundancy column selection lines (RCSL) and can set the corresponding low-hammer flag signal to a high bit. The detailed configuration and operation of the repair control circuit (140) will be described in detail in FIGS. 4 to 8.

[0034] The column control circuit (150) can be connected to the normal cells (MC) of the normal cell region (112) through a plurality of normal columns (BL) and connected to the redundancy cells (RC) and low-hammer cells (RHC) of the redundancy cell region (114) through a plurality of redundancy columns (RBL). The column control circuit (150) can select at least one of the redundancy column selection lines (RCSL) according to the result of comparing the column address (CA) and the repair addresses (REP_ADD#) or according to the low-hammer flag signals (CRHT#) according to the tracking signal (RHT_EN). The column control circuit (150) can control the column address (CA) to be decoded in normal mode to select at least one normal column selection line among the normal column selection lines (CSL), and if the comparison result between the column address (CA) and the repair address (REP_ADD#) matches, to perform a repair operation to select the corresponding redundancy column selection line (RCSL) instead of the normal column selection line. Additionally, the column control circuit (150) can control the column to select a low-hammer column selection line among the redundancy column selection lines (RCSL) according to the activated low-hammer flag signal (CRHT#) in low-hammer tracking mode, so that access counting data (A_CNT) is read out and written back from the low-hammer cells (RHC) connected to the selected low-hammer column selection line. The detailed configuration of the column control circuit (150) will be described in detail in FIGS. 9 and FIGS. 10.

[0035] The error correction circuit (160) can transmit and receive data (D1) and an error correction code (PTY) to and from the memory cell area (110) through the column control circuit (150). The error correction circuit (160) can generate an error correction code (PTY) using data (D2) provided from the data input / output circuit (170) through data pads (DQ) according to a write command (WT) during a write operation. Additionally, the error correction circuit (160) can correct errors in the data (D1) provided from the memory cell area (110) using the error correction code (PTY) provided from the memory cell area (110) according to a read command (RD) during a read operation. The data (D2) with errors corrected by the error correction circuit (160) can be provided to the data input / output circuit (170).

[0036] Additionally, in an embodiment of the present invention, the error correction circuit (160) can generate an error correction code (PTY) using updated access counting data (A_CNT) provided from the refresh control circuit (120) according to an internal write signal (IWT), and correct an error in the data (D1) provided from the memory cell area (110) using the error correction code (PTY) read from the memory cell area (110) according to an internal read signal (IRD), and provide the data to the refresh control circuit (120) as access counting data (A_CNT). Accordingly, the error correction circuit (160) can correct an error in the access counting data (A_CNT) during the low-hammer tracking mode.

[0037] The data input / output circuit (170) can transmit and receive data (D2) to and from an external device through data pads (DQ). The data input / output circuit (170) can receive data (D2) from an external device according to a write command (WT) during a write operation, and output error-corrected data (D2) to the outside through data pads (DQ) according to a read command (RD) during a read operation.

[0039] Hereinafter, the specific configuration of a memory device (100) according to an embodiment of the present invention will be described with reference to FIGS. 3 to 10.

[0040] FIG. 3 is a detailed configuration diagram of the refresh control circuit (120) of FIG. 1.

[0041] Referring to FIG. 3, the refresh control circuit (120) may include a counting control circuit (121), a target address storage circuit (123), and a selection circuit (125).

[0042] The counting control circuit (121) can issue an internal read signal (IRD) according to the tracking signal (RHT_EN). The counting control circuit (121) can receive access counting data (A_CNT) from the error correction circuit (160) after a predetermined delay time from the issuance of the internal read signal (IRD). The counting control circuit (121) can provide the access counting data (A_CNT) to the target address storage circuit (123) as reference counting data (LA_CNT) and update the value of the access counting data (A_CNT). For example, the access counting data (A_CNT) is 64-bit data and can have the same counting value in 8-bit increments. The counting control circuit (121) can update the access counting data (A_CNT) by increasing it by “+1” in 8-bit increments. The counting control circuit (121) can issue an internal light signal (IWT) and provide updated access counting data (A_CNT) to the error correction circuit (160).

[0043] The target address storage circuit (123) can store the row address (RA) as the target address (TADD) when the reference counting data (LA_CNT) exceeds a preset threshold.

[0044] The selection circuit (125) can output the stored target address (TADD) or row address (RA) as the final row address (XADD) according to the target refresh command (TREF). The selection circuit (125) can output the target address (TADD) as the final row address (XADD) when the target refresh command (TREF) is input.

[0045] With the above configuration, the refresh control circuit (120) can select a target address (TADD) based on access counting data (A_CNT) provided from the low-hammer cells (RHC) during the low-hammer tracking mode, and update the access counting data (A_CNT) to write back to the multiple low-hammer cells (RHC). Additionally, the refresh control circuit (120) can output a low address (RA) as a final low address (XADD), but output the target address (TADD) as the final low address (XADD) only when a target refresh command (TREF) is input.

[0047] FIG. 4 is a detailed configuration diagram of the repair control circuit (140) of FIG. 1.

[0048] Referring to FIG. 4, the repair control circuit (140) may include a non-volatile storage circuit (142), a latch control circuit (144), and first to third latch circuits (145_1 to 145_3).

[0049] The non-volatile storage circuit (142) can store the fault addresses of cell blocks for each group as repair information (INF_R). According to an embodiment, the non-volatile storage circuit (142) may be composed of one of non-volatile memories such as an array e-fuse (ARE) circuit, a laser fuse (LASER FUSE) circuit, NAND flash memory, NOR flash memory, MRAM (Magnetic Random Access Memory), STT-MRAM (Spin Transfer Magnetic Random Access Memory), ReRAM (Resistive Random Access Memory), and PC RAM (Phase Change Random Access Memory). Below, the case where the non-volatile storage circuit (142) is an array e-fuse (ARE) circuit will be described as an example.

[0050] The non-volatile storage circuit (142) can generate a fuse address (FADD) for specifying the first to eighth groups (G0 to G7) according to the clock signal (CLK) when the boot-up signal (BOOT_UP) is activated, and sequentially output the previously stored repair information (INF_R) as fuse array data (FD) according to the fuse address (FADD). For example, when a fuse address (FADD) specifying the first group (G0) is generated, fuse array data (FD) for the fault addresses of the cell blocks placed in the first group (G0) can be sequentially output.

[0051] The non-volatile storage circuit (142) may include a plurality of memory sets (i.e., fuse sets). Each fuse set may include an enable fuse and a plurality of address fuses. The enable fuse programs information regarding whether the corresponding fuse set is programming a valid address. The plurality of address fuses may program a fault address by having a number of fuse cells for programming bits of a fault address. For reference, the fuse array data (FD) may be output in units of bits corresponding to the enable fuse and the plurality of address fuses, synchronized with the clock signal (CLK). Hereinafter, an example is described in which the fuse array data (FD) is output in units of 1 bit of enable bit and (k+1) bits of address bits (i.e., (k+2) bits) at every rising edge of the clock signal (CLK).

[0052] The latch control circuit (144) can receive fuse array data (FD) according to the fuse address (FADD) and clock signal (CLK) and provide first to third fuse data (FD1_G~FD3_G) and first to third flag data (FD1_GF~FD3_GF) to the first to third latch circuits (145_1~145_3), respectively. If the latch control circuit (144) detects that the fuse array data (FD) is data of an unused fuse set, it can mask the fuse array data (FD) so that it is not output as the corresponding fuse data, and activate the corresponding flag data to provide it to the corresponding latch circuit.

[0053] The first to third latch circuits (145_1 to 145_3) correspond to the redundancy column select lines (RCSL) respectively and can receive the first to third fuse data (FD1_G to FD3_G) and the first to third flag data (FD1_GF to FD3_GF) respectively and store them as group latch data for the corresponding redundancy column select lines. The first to third latch circuits (145_1 to 145_3) can select one of the stored group latch data according to the predetermined bits of the row address (RA) and provide it as the first to third repair addresses (REP_ADD1 to REP_ADD3) and the first to third row-hammer flag signals (CRHT1 to CRHT3).

[0055] FIG. 5 is a detailed circuit diagram of the latch control circuit (144) of FIG. 4.

[0056] Referring to FIG. 5, the latch control circuit (144) may include a fuse decoder (210), a tracking circuit (220), and a select output circuit (230).

[0057] The fuse decoder (210) can generate a first selection signal (SEL1) by decoding the fuse address (FADD). The first selection signal (SEL1) may be a signal composed of multiple bits (e.g., 3 bits) to designate groups.

[0058] The tracking circuit (220) can detect when a fuse set is unused while a low-hammer column selection line within the same group is not assigned, activate a detection signal (DET), and synchronize the detection signal (DET) with a clock signal (CLK) to output a reserve flag signal (FD_FL). That is, the tracking circuit (220) can output a reserve flag signal (FD_FL) when a case where a fuse set within the same group is unused is detected for the first time. The tracking circuit (220) can determine that a low-hammer column selection line within the same group is not assigned by checking the logic levels of the first flag data (FD1_GF0~FD1_GF7), the second flag data (FD2_GF0~FD2_GF7), and the third flag data (FD3_GF0~FD3_GF7) according to the first selection signal (SEL1) and the clock signal (CLK). The tracking circuit (220) is all bits (FD) of the fuse array data (FD).<k+1:0> When this is a low bit, the corresponding fuse set can be determined to be unused after initialization.

[0059] More specifically, the tracking circuit (220) may include a first detection circuit (221), a second detection circuit (223), and a synchronization circuit (225).

[0060] The first detection circuit (221) can generate a flag detection signal (DET_FL) by checking the logic levels of the first flag data (FD1_GF0~FD1_GF7), the second flag data (FD2_GF0~FD2_GF7), and the third flag data (FD3_GF0~FD3_GF7) according to the first selection signal (SEL1) and the clock signal (CLK). For example, when the first selection signal (SEL1) specifying the first group (G0) is input to the first detection circuit (221), it receives the first flag data (FD1_GF0), the second flag data (FD2_GF0), and the third flag data (FD3_GF0) for the first group according to the clock signal (CLK), and outputs the flag detection signal (DET_FL) at a logic low level when all the received data are at a logic low level. On the other hand, the first detection circuit (221) can output a flag detection signal (DET_FL) at a logic high level if any one of the first flag data (FD1_GF0), the second flag data (FD2_GF0), and the third flag data (FD3_GF0) is at a logic high level. If the flag detection signal (DET_FL) is at a logic low level, it can be determined that the low-hammer column selection line within the same group is not assigned.

[0061] The second detection circuit (223) is a flag detection signal (DET_FL) and bits (FD) of fuse array data (FD).<k+1:0> A detection signal (DET) can be generated based on ). The second detection circuit (223) includes the flag detection signal (DET_FL) and the bits (FD) of the fuse array data (FD).<k+1:0> When all of ) are low bits, the detection signal (DET) can be output at a logic high level. On the other hand, the second detection circuit (223) can output the bits (FD) of the flag detection signal (DET_FL) and the fuse array data (FD).<k+1:0> When any of the above is a high bit, the detection signal (DET) can be output at a logic low level. When the detection signal (DET) is at a logic high level, and the low-hammer column selection line within the same group is not assigned, it can be determined that the corresponding fuse set is unused after initialization. The second detection circuit (223) may be composed of a plurality of OR gates (OR1~OR3) and an inverter (INV1).

[0062] The synchronization circuit (225) can synchronize the detection signal (DET) with the clock signal (CLK) and output it as a reserve flag signal (FD_FL). The synchronization circuit (225) may include a delay circuit (D) and an AND gate (AD1). The delay circuit (D) can delay the clock signal (CLK) for a predetermined delay time. The AND gate (AD1) can perform a logic AND operation on the detection signal (DET) and the output of the delay circuit (D). Accordingly, the synchronization circuit (225) can synchronize the detection signal (DET) with the predetermined time delay of the clock signal (CLK) and output it as a reserve flag signal (FD_FL).

[0063] The selection output circuit (230) may include a first selection circuit (231) and a second selection circuit (233).

[0064] The first selection circuit (231) fuse array data (FD) according to the first selection signal (SEL1) and the clock signal (CLK).<k+1:0> ) is the first fuse data (FD1_G0<k+1:0> ~FD1_G7<k+1:0> ), 2nd fuse data(FD2_G0<k+1:0> ~FD2_G7<k+1:0> ), 3rd fuse data(FD3_G0<k+1:0> ~FD3_G7<k+1:0> Output as ), but depending on the reserve flag signal (FD_FL), output fuse array data (FD<k+1:0> ) can be masked. For example, when a first selection signal (SEL1) specifying a first group (G0) is input to the first selection circuit (231), fuse array data (FD) according to the clock signal (CLK).<k+1:0> ) is the first fuse data for the first group (FD1_G0<k+1:0> ), 2nd fuse data(FD2_G0<k+1:0> ), 3rd fuse data(FD3_G0<k+1:0> It can be output sequentially as ).

[0065] The second selection circuit (233) can output a reserve flag signal (FD_FL) as first flag data (FD1_GF0~FD1_GF7), second flag data (FD2_GF0~FD2_GF7), and third flag data (FD3_GF0~FD3_GF7) according to the first selection signal (SEL1) and the clock signal (CLK). For example, when the first selection signal (SEL1) specifying the first group (G0) is input to the second selection circuit (233), the reserve flag signal (FD_FL) can sequentially output the first flag data (FD1_GF0), second flag data (FD2_GF0), and third flag data (FD3_GF0) for the first group according to the clock signal (CLK). The second selection circuit (233) can set the first flag data (FD1_GF0), the second flag data (FD2_GF0), and the third flag data (FD3_GF0) according to the activation of the reserve flag signal (FD_FL), and reset and output them according to the first selection signal (SEL1).

[0066] According to an embodiment, the tracking circuit (220) comprises bits (FD) of fuse array data (FD).<k+1:0> A detection circuit may be additionally provided to detect whether the corresponding fuse set is defective based on ). For example, the detection circuit may include an enable bit (FD) corresponding to the enable fuse.<k+1> Although ) is a low bit, if two or more of the address fuses are set to a high bit, the case can be detected to detect that the corresponding fuse set is defective and output a defective detection signal. The first selection circuit (231) can mask the fuse array data (FD) so that it is not output as the first to third fuse data (FD1_G~FD3_G) according to the defective detection signal.

[0068] FIG. 6 is a detailed configuration diagram of the first latch circuit (145_1) among the latch circuits (145_1 to 145_3) of FIG. 4.

[0069] Referring to FIG. 6, the first latch circuit (145_1) may include a row decoder (310), a plurality of latch sets (320_0 to 320_k+2) and a latch selection circuit (330).

[0070] The row decoder (310) can generate a second select signal (SEL2) by decoding some bits of the row address (RA). The second select signal (SEL2) may be a signal composed of multiple bits (e.g., 3 bits) to specify groups.

[0071] A plurality of latch sets (320_0~320_k+2) each include a plurality of unit latches (L_G0~L_G7), and the first fuse data (FD1_G0<k+1:0> ~FD1_G7<k+1:0> ) and each bit of the first flag data (FD1_GF0~FD1_GF7) can be stored. For example, the first unit latches (L_G0) of the latch sets (320_0~320_k+2) can store the first fuse data (FD1_G0) for the first group.<k+1:0> ) and each bit of the first flag data (FD1_GF0) are stored, and the second unit latches (L_G1) store the first fuse data (FD1_G1 for the second group<k+1:0> ) and each bit of the first flag data (FD1_GF1) are stored, and in this way, the eighth unit latches (L_G7) store the first fuse data (FD1_G7 for the eighth group<k+1:0> Each bit of ) and the first flag data (FD1_GF7) can be stored.

[0072] The latch selection circuit (330) may include a plurality of selection circuits (330_0 to 330_k+2) corresponding to a plurality of latch sets (320_0 to 320_k+2). Each of the plurality of selection circuits (330_0 to 330_k+2) may select one of the unit latches (L_G0 to L_G7) of the corresponding latch set according to a second selection signal (SEL2) and output a bit stored in the selected unit latch. The bits stored in the selected unit latches may be output as a first repair address (REP_ADD1) and a first low-hammer flag signal (CRHT1). The first repair address (REP_ADD1) includes an enable bit (CREN1) and address bits (CRA1 <k:0>It can be composed of ).

[0074] FIGS. 7 and FIGS. 8 are a flowchart and a timing diagram for explaining the boot-up operation of a repair control circuit (140) according to an embodiment of the present invention.

[0075] Referring to FIG. 7, when the boot-up signal (BOOT_UP) is activated during boot-up (S110), the non-volatile storage circuit (142) can generate a fuse address (FADD) for sequentially assigning the first to eighth groups (G0~G7) according to the clock signal (CLK).

[0076] First, the non-volatile storage circuit (142) can provide fuse array data (FD1) for the first group from a fuse set specified by a fuse address (FADD) for specifying the first group (G0) at the first rising edge of the clock signal (CLK) (S120) (① of FIG. 8).

[0077] The tracking circuit (220) can detect whether the corresponding fuse set is unused by checking the fuse array data (FD1) for the first group (S130) (S140). For example, the tracking circuit (220) can detect the bits (FD) of the fuse array data (FD1) for the first group.<k+1:0> When any of the above is a high bit, it is determined that the corresponding fuse set is used (NO of S140), and a detection signal (DET) is output at a logic low level, and accordingly, a reserve flag signal (FD_FL) can be output at a logic low level.

[0078] Since the corresponding fuse set is not used (YES of S140), the tracking circuit (220) can check whether a low-hammer column selection line within the same group is not assigned (S150). Since a low-hammer column selection line within the same group is not assigned (NO of S150), the tracking circuit (220) can output a detection signal (DET) at a logic high level and output a reserve flag signal (FD_FL) synchronized with a predetermined time delay of a clock signal (CLK) (② of FIG. 8). The first selection circuit (231) can mask the fuse array data (FD1), and the second selection circuit (233) can output a first flag data (FD1_GF0) that is set to a logic high level according to the reserve flag signal (FD_FL). Accordingly, the first flag data (FD1_GF0) can be stored in the first unit latch (L_G0) of the latch set (320_k+2) of the first latch circuit (145_1) (S160).

[0079] Next (NO in S170), the non-volatile storage circuit (142) can provide fuse array data (FD2) for the first group at the next rising edge of the clock signal (CLK) (S120) (③ in FIG. 8). The tracking circuit (220) can check the fuse array data (FD2) for the first group (S130) to detect whether the corresponding fuse set is unused (S140). If the corresponding fuse set is unused (YES in S140) but a low-hammer column selection line within the same group has already been assigned (YES in S150), the tracking circuit (220) can output a detection signal (DET) at a logic low level according to the first flag data (FD1_GF0) and maintain a reserve flag signal (FD_FL) at a logic low level. Accordingly, valid latch data is not stored in the second latch circuit (145_2).

[0080] Next (NO of S170), the non-volatile storage circuit (142) can provide fuse array data (FD3) for the first group at the next rising edge of the clock signal (CLK) (S120) (④ of FIG. 8). If the corresponding fuse set is used (NO of S140), the tracking circuit (220) can detect whether the corresponding fuse set is defective (S180). For example, the tracking circuit (220) can detect an enable bit (FD) corresponding to the enable fuse.<k+1> Although ) is a low bit, it is possible to detect that the corresponding fuse set is faulty by detecting the case where two or more address fuses among the address fuses are set to a high bit. If the corresponding fuse set is faulty (YES of S180), the first selection circuit (231) can mask the fuse array data (FD3). Accordingly, valid latch data is not stored in the third latch circuit (145_3). On the other hand, if the corresponding fuse set is not faulty (NO of S180), the first selection circuit (231) masks the fuse array data (FD3) to the third fuse data (FD3_G0<k+1:0> It can be output as ). Accordingly, the first unit latches (L_G0) of the latch sets (320_0~320_k+1) of the third latch circuit (145_3) have the third fuse data (FD3_G0<k+1:0> ) can be stored (S190).

[0081] Next (NO of S170), the non-volatile storage circuit (142) can provide fuse array data (FD1) for the second group from a fuse set specified by a fuse address (FADD) for specifying the second group (G1) at the next rising edge of the clock signal (CLK) (S120) (⑤ of FIG. 8). Since the corresponding fuse set is used (NO of S140), the first fuse data (FD1_G1) is provided in the second unit latches (L_G1) of the latch sets (320_0 to 320_k+1) of the first latch circuit (145_1).<k+1:0> ) can be stored (S190).

[0082] Next (NO in S170), the non-volatile storage circuit (142) can provide fuse array data (FD2) for the second group at the next rising edge of the clock signal (CLK) (S120) (⑥ in FIG. 8). Since the corresponding fuse set is not used (YES in S140), the tracking circuit (220) can check whether a low-hammer column selection line within the same group has not been assigned (S150). Since a low-hammer column selection line within the same group has not been assigned (NO in S150), the tracking circuit (220) can output a detection signal (DET) at a logic high level and output a reserve flag signal (FD_FL) synchronized with a predetermined time delay of the clock signal (CLK) (⑦ in FIG. 8). The first selection circuit (231) masks the fuse array data (FD2), and the second selection circuit (233) can output second flag data (FD2_GF1) which is set to a logic high level according to the reserve flag signal (FD_FL). Accordingly, the second flag data (FD2_GF1) can be stored in the second unit latch (L_G1) of the latch set (320_k+2) of the second latch circuit (145_2) (S160).

[0083] The repair control circuit (140) can repeat the above processes until the fuse array data of all fuse sets is stored in the latch circuits (YES of S170). Accordingly, the boot-up operation of the repair control circuit (140) can be terminated.

[0084] As described above, during a boot-up operation, the repair control circuit (140) can store the fuse array data (FD) as fuse data (FD1_G~FD3_G) in the latch circuits (145_1~145_3) when fuse data of the used fuse set is detected. On the other hand, the repair control circuit (140) can activate one of the flag data (FD1_GF~FD3_GF) and store it in the latch circuits (145_1~145_3) when fuse data of the unused fuse set is detected. Afterward, the repair control circuit (140) can provide the repair addresses (REP_ADD#) and low-hammer flag signals (CRHT#) stored in the group of latch circuits designated according to some bits of the low address (RA) to the column control circuit (150).

[0086] FIG. 9 is a detailed configuration diagram of the column control circuit (150_x) of FIG. 1. The column control circuit (150_x) shown in FIG. 9 may correspond to any one of a plurality of column control circuits (150_0 to 150_ECC).

[0087] Referring to FIG. 9, the column control circuit (150_x) may include an address comparison circuit (410), a column decoder (420), a normal column driver (430), and a redundancy column driver (440).

[0088] The address comparison circuit (410) can enable the normal column disable signal (YI_DIS) and enable one of the redundancy column selection signals (RYI#) when the result of the comparison between the column address (CA) and the repair addresses (REP_ADD#) matches in normal mode when the tracking signal (RHT_EN) is disabled. On the other hand, the address comparison circuit (410) can enable the normal column disable signal (YI_DIS) and enable one of the redundancy column selection signals (RYI#) according to the low-hammer flag signals (CRHT#) when the tracking signal (RHT_EN) is enabled in low-hammer tracking mode.

[0089] The column decoder (420) can decode the column address (CA) to enable one of the multiple normal column selection signals (YI). The column decoder (420) can disable all normal column selection signals (YI) when the normal column disable signal (YI_DIS) is enabled.

[0090] For reference, normal column selection signals (YI) may correspond to normal column selection lines (CSL) respectively, and redundancy column selection signals (RYI#) may correspond to redundancy column selection lines (RCSL) respectively. For example, if three redundancy column selection lines (RCSL) are provided, first to third redundancy column selection signals (RYI1~RYI3) may be provided.

[0091] The normal column driver (430) can drive normal column selection lines (CSL) according to normal column selection signals (YI). The normal column driver (430) can select one normal column selection line (CSL) according to the activated normal column selection signal. According to the selected normal column selection line (CSL), the normal column driver (430) can be connected to normal cells (MC) of the normal cell area (112) through a plurality of normal columns (BL).

[0092] The redundancy column driver (440) can drive redundancy column selection lines (RCSL) according to redundancy column selection signals (RYI#). The redundancy column driver (440) can select one redundancy column selection line (RCSL) according to the activated redundancy column selection signal (RYI#). According to the selected redundancy column selection line (RCSL), the redundancy column driver (440) can be connected to the redundancy cells (RC) and low-hammer cells (RHC) of the redundancy cell area (114) through a plurality of redundancy columns (RBL).

[0093] Accordingly, the error correction circuit (160) can transmit and receive data (D1) and an error correction code (PTY) to and from the memory cell area (110) through the normal column driver (430) and the redundancy column driver (440).

[0095] FIG. 10 is a detailed circuit diagram of the address comparison circuit (410) of FIG. 9.

[0096] Referring to FIG. 10, the address comparison circuit (410) may include first to third redundancy control circuits (412 to 416) and a disable control circuit (418). Since the first to third redundancy control circuits (412 to 416) have substantially the same configuration, the first redundancy control circuit (412) will be described as an example.

[0097] The first redundancy control circuit (412) may include a first mode circuit (412A), a second mode circuit (412B), and an output control circuit (412C).

[0098] The first mode circuit (412A) may include a plurality of XOR gates (XR1~XR4), an inverter (INV2), a plurality of NOR gates (NR1, NR2), and a first NAND gate (ND1). The XOR gates (XR1~XR4) include bits of the column address (CA) and address bits (CRA1) of the first repair address (REP_ADD1). <k:0>Each of the following can be compared. The inverter (INV2) can invert the enable bit (CREN1). The NOR gates (NR1, NR2) can perform a logic XOR operation on the tracking signal (RHT_EN), the outputs of the XOR gates (XR1~XR4), and the output of the inverter (INV2). The first NAND gate (ND1) can perform a logic NAND operation on the outputs of the NOR gates (NR1, NR2) to output a first pre-signal (PRE_B1). That is, the first mode circuit (412A) can output the first reserve signal (PRE_B1) by enabling it to a logic low level when the tracking signal (RHT_EN) is disabled, the enable bit (CREN1) is a high bit, and the comparison result between the column address (CA) and the first repair address (REP_ADD1) matches.

[0099] The second mode circuit (412B) may include a second NAND gate (ND2). The second NAND gate (ND2) may output a second pre-signal (PRE_B2) by performing a logic NAND operation on the first low-hammer flag signal (CRHT1) and the tracking signal (RHT_EN). With the above configuration, when the tracking signal (RHT_EN) is activated to a logic high level, the second mode circuit (412B) may invert the first low-hammer flag signal (CRHT1) and output it as the second pre-signal (PRE_B2). That is, the second mode circuit (412B) can output the second reserve signal (PRE_B2) by activating it to a logic low level when the tracking signal (RHT_EN) is activated to a logic high level, as the first low-hammer flag signal (CRHT1) is set to a high bit.

[0100] The output control circuit (412C) may include a third NAND gate (ND3). The third NAND gate (ND3) can perform a logic NAND operation on the first pre-signal (PRE_B1) and the second pre-signal (PRE_B2). That is, the output control circuit (412C) can activate the first redundancy column selection signal (RYI1) to a logic high level and output it when either the first pre-signal (PRE_B1) or the second pre-signal (PRE_B2) is activated to a logic low level.

[0101] With the above configuration, the first redundancy control circuit (412) has the enable bit (CREN1) activated in normal mode and the bits of the column address (CA) and the address bits (CRA1) of the first repair address (REP_ADD1). <k:0>If the comparison result of ) matches, the first redundancy column selection signal (RYI1) can be activated. Additionally, the first redundancy control circuit (412) can activate the first redundancy column selection signal (RYI1) when the first low-hammer flag signal (CRHT1) is set to a high bit during low-hammer tracking mode.

[0102] The disable control circuit (418) may include a plurality of NOR gates (NR3, NR4) and a fourth NAND gate (ND4). The NOR gates (NR3, NR4) can perform a logic XOR operation on the first to third redundancy column selection signals (RYI1~RYI3) and the tracking signal (RHT_EN). The fourth NAND gate (ND4) can perform a logic NAND operation on the outputs of the NOR gates (NR3, NR4). With the above configuration, the disable control circuit (418) can activate and output a normal column disable signal (YI_DIS) to a logic high level regardless of the logic level of the first to third redundancy column selection signals (RYI1~RYI3) when the tracking signal (RHT_EN) is activated to a logic high level. On the other hand, the disable control circuit (418) can enable and output the normal column disable signal (YI_DIS) to a logic high level when the tracking signal (RHT_EN) is disabled to a logic low level and any one of the first to third redundancy column selection signals (RYI1~RYI3) is enabled.

[0104] Hereinafter, with reference to FIGS. 1 to 12, the operation of the memory device (100) in normal mode and low-hammer tracking mode will be described. For convenience of explanation, only the cell blocks (MB00~MB07, MB0ECC) of the first group (G0) will be described.

[0105] FIG. 11 is a flowchart illustrating the operation of a memory device (100) according to an embodiment of the present invention. FIG. 12 is a diagram to aid in understanding the operation of FIG. 11.

[0106] Referring to FIG. 11, first, the repair control circuit (140) can perform a boot-up operation in which repair information (INF_R) stored in the non-volatile storage circuit (142) is stored in internal latch circuits (145_1 to 145_3) according to the boot-up signal (BOOT_UP) and the clock signal (CLK) (S210). As described in FIG. 7 and FIG. 8, the flag data (FD1_GF0) of the first latch circuit (145_1) can be set to a high bit for the cell blocks (MB00 to MB07, MB0ECC) of the first group (G0). Accordingly, as illustrated in FIG. 12, among the redundancy column selection lines (RCSL) of the first group (G0), the first redundancy column selection line driven by the first redundancy column selection signal (RYI1) can be set as the low-hammer column selection line (RH_CSL).

[0107] Afterwards, when an active command (ACT) is input (S220), the refresh control circuit (120) outputs the row address (RA) as the final row address (XADD), and the row control circuit (130) can activate the row (SEL_WL) corresponding to the final row address (XADD). The repair control circuit (140) can provide first to third repair addresses (REP_ADD1~REP_ADD3) for the first group and first to third row-hammer flag signals (CRHT1~CRHT3) according to the predetermined bits of the row address (RA) (S230). At this time, the first row-hammer flag signal (CRHT1) provided from the first latch circuit (145_1) is a valid signal, but the first repair address (REP_ADD1) is an invalid address.

[0108] If a tracking signal (RHT_EN) indicating entry into low-hammer tracking mode is not generated (NO of S240), and a read command (RD) or write command (WT) is input after a time of tRCD (RAS to CAS Delay time), the memory device (100) can perform a read / write operation in normal mode (S250).

[0109] For example, when a write command (WT) is input, the data input / output circuit (170) receives data (D2) from an external device through data pads (DQ), and the error correction circuit (160) can generate an error correction code (PTY) using the data (D2). The column control circuit (150) can decode the column address (CA) to activate at least one normal column selection signal among the normal column selection signals (YI), but if the column address (CA) matches the second or third repair address (REP_ADD2, REP_ADD3), the normal column selection signal can be deactivated and the second or third redundancy column selection signals (RYI2, RYI3) can be activated. Accordingly, data (D1) and error correction code (PTY) provided from the error correction circuit (160) can be written to the cell blocks (MB00~MB07, MB0ECC) of the first group (G0) through the selected column selection line.

[0110] When a read command (RD) is input, data (D1) and an error correction code (PTY) can be read from the cell blocks (MB00~MB07, MB0ECC) of the first group (G0) connected to the selected column selection line. The error correction circuit (160) can correct errors in the data (D1) provided from the memory cell area (110) using the error correction code (PTY). The data input / output circuit (170) can output the error-corrected data (D2) to the outside through the data pads (DQ).

[0111] When a tracking signal (RHT_EN) is generated internally or provided externally according to an active command (ACT), the memory device (100) can enter a low-hammer tracking mode (YES of S240). The column control circuit (150) can activate a first redundancy column selection signal (RYI1) as the first low-hammer flag signal (CRHT1) is activated, and drive a low-hammer column selection line (RH_CSL) according to the first redundancy column selection signal (RYI1) (S260). Accordingly, data (D1) and an error correction code (PTY) can be read from cell blocks (MB00~MB07, MB0ECC) of the first group (G0) connected to the selected low-hammer column selection line (RH_CSL) (S270). At this time, the data (D1) may include access counting data (A_CNT).

[0112] At this time, the refresh control circuit (120) can sequentially issue an internal lead signal (IRD) and an internal light signal (IWT) according to the tracking signal (RHT_EN).

[0113] In response to an internal lead signal (IRD), the error correction circuit (160) can correct an error in the access counting data (A_CNT) using an error correction code (PTY) (S280). The refresh control circuit (120) can receive the access counting data (A_CNT) from the error correction circuit (160). The refresh control circuit (120) can store the row address (RA) as the target address (TADD) if the access counting data (A_CNT) exceeds a preset threshold. The refresh control circuit (120) can update the value of the access counting data (A_CNT) (S290).

[0114] In response to an internal write signal (IWT), the error correction circuit (160) generates an error correction code (PTY) using updated access counting data (A_CNT) provided by the refresh control circuit (120), and accordingly, the access counting data (A_CNT) and the error correction code (PTY) provided by the error correction circuit (160) can be written back to the cell blocks (MB00~MB07, MB0ECC) of the first group (G0) through the selected low-hammer column selection line (RH_CSL) (S292). Accordingly, the memory device (100) can terminate the low-hammer tracking mode (S294).

[0115] After that, when a target refresh command (TREF) is input, the stored target address (TADD) is provided as the final row address (XADD), and the row control circuit (130) can perform a target refresh operation to refresh one or more adjacent rows corresponding to the final row address (XADD) according to the target refresh command (TREF).

[0116] As described above, in an embodiment of the proposed invention, the memory device (100) may designate a redundancy column selection line (RCSL) that is not used for repair as a raw-hammer column selection line, and store access counting data (A_CNT) that stores the number of accesses of each row in the raw-hammer cells (RHC) connected to the designated raw-hammer column selection line. Accordingly, access counting data for each row can be managed without increasing the additional area. In addition, by selecting a target address (TADD) according to the access counting data (A_CNT) stored in the raw-hammer cells (RHC), the raw-hammer defense capability can be optimized and power consumption minimized. Furthermore, by selectively performing a target refresh operation according to the target address (TADD), the accuracy of the refresh operation and the refresh efficiency can be improved.

[0118] Meanwhile, in the above embodiment, in order to store the low-hammer flag signal (CRHT#), the latch circuits (145_1 to 145_3) each had to be equipped with a separate latch set (320_k+2). Below, we will discuss a method of setting the low-hammer flag signal (CRHT#) using a repair address (REP_ADD#) without storing the low-hammer flag signal (CRHT#) in each latch circuit.

[0119] FIG. 13 is a detailed configuration diagram of the repair control circuit (140) of FIG. 1 according to another embodiment of the present invention.

[0120] Referring to FIG. 13, the repair control circuit (140) may include a non-volatile storage circuit (146), a latch control circuit (147), and first to third latch circuits (148_1 to 148_3).

[0121] The non-volatile storage circuit (146) may have substantially the same configuration as the non-volatile storage circuit (142) of FIG. 4. That is, when the boot-up signal (BOOT_UP) is activated, the non-volatile storage circuit (146) may generate a fuse address (FADD) for designating the first to eighth groups according to the clock signal (CLK), and sequentially output the previously stored repair information (INF_R) as fuse array data (FD) according to the fuse address (FADD).

[0122] The latch control circuit (147) can provide fuse array data (FD) to the first to third latch circuits (148_1 to 148_3) respectively as first to third fuse data (FD1_G to FD3_G) according to the fuse address (FADD) and clock signal (CLK). In particular, in the proposed embodiment, the latch control circuit (147) can check the first to third fuse data (FD1_G to FD3_G) and, if it detects that the fuse array data (FD) is data of an unused fuse set, it can set the corresponding fuse data to a specific pattern and provide it to the corresponding latch circuit. For example, the latch control circuit (147) can set the enable bit to a low bit and set the remaining bits among the address bits, excluding a specific bit, to have a high bit. Below, the case where the address bits are set to "11…1011" will be explained as an example.

[0123] The first to third latch circuits (148_1 to 148_3) correspond to the redundancy column selection lines (RCSL) respectively, and each receive the first to third fuse data (FD1_G to FD3_G) and store it as group latch data for the corresponding redundancy column selection line. The first to third latch circuits (148_1 to 148_3) can select one of the stored group latch data according to the predetermined bits of the row address (RA) and provide it as the first to third repair address (REP_ADD1 to REP_ADD3). In particular, in the proposed embodiment, the first to third latch circuits (148_1 to 148_3) can set the first to third low-hammer flag signals (CRHT1 to CRHT3) using the first to third repair addresses (REP_ADD1 to REP_ADD3).

[0125] FIG. 14 is a detailed configuration diagram of the latch control circuit (147) of FIG. 13.

[0126] Referring to FIG. 14, the latch control circuit (147) may include a fuse decoder (510), a tracking circuit (520), and a select output circuit (530).

[0127] The fuse decoder (510) and the tracking circuit (520) may each have substantially the same configuration as the fuse decoder (210) and the tracking circuit (220) of FIG. 5. That is, the fuse decoder (510) may generate a first selection signal (SEL1) by decoding a fuse address (FADD). The tracking circuit (520) may detect when a fuse set is unused while a low-hammer column selection line within the same group is not assigned, activate a detection signal (DET), and synchronize the detection signal (DET) with a clock signal (CLK) to output a reserve flag signal (FD_FL).

[0128] The selection output circuit (530) may include a first selection circuit (531) and a second selection circuit (533).

[0129] The first selection circuit (531) fuse array data (FD) according to the first selection signal (SEL1) and the clock signal (CLK).<k+1:0> ) is the first fuse data (FD1_G0<k+1:0> ~FD1_G7<k+1:0> ), 2nd fuse data(FD2_G0<k+1:0> ~FD2_G7<k+1:0> ), 3rd fuse data(FD3_G0<k+1:0> ~FD3_G7<k+1:0> It outputs as ), but the address bits of the corresponding fuse data can be set to a specific pattern (i.e., "11…1011") according to the reserve flag signal (FD_FL). For example, when the first selection circuit (531) receives a first selection signal (SEL1) specifying the first group (G0), the fuse array data (FD) according to the clock signal (CLK).<k+1:0> ) is the first fuse data for the first group (FD1_G0<k+1:0> ), 2nd fuse data(FD2_G0<k+1:0> ), 3rd fuse data(FD3_G0<k+1:0> Output sequentially as ), but depending on the reserve flag signal (FD_FL), the first fuse data (FD1_G0<k+1:0> ) address bits (FD1_G0 <k:0>) can be set to a specific pattern ("11…1011").

[0130] The second selection circuit (533) may have substantially the same configuration as the second selection circuit (233) of FIG. 5. That is, the second selection circuit (533) may generate a preliminary flag signal (FD_FL) into first flag data (FD1_GF0~FD1_GF7), second flag data (FD2_GF0~FD2_GF7), and third flag data (FD3_GF0~FD3_GF7) according to the first selection signal (SEL1) and the clock signal (CLK). However, the generated flag data may not be output to the latch circuits (148_1~148_3) but may be provided to the tracking circuit (520).

[0132] FIG. 15 is a detailed configuration diagram of the first latch circuit (148_1) among the latch circuits (148_1 to 148_3) of FIG. 13.

[0133] Referring to FIG. 15, the first latch circuit (148_1) may include a row decoder (610), a plurality of latch sets (620_0 to 620_k+1), a latch selection circuit (630), and a flag setting circuit (640).

[0134] The row decoder (610) may have substantially the same configuration as the row decoder (310) of FIG. 6. The row decoder (610) may generate a second select signal (SEL2) by decoding some bits of the row address (RA).

[0135] A plurality of latch sets (620_0 to 620_k+1) may have substantially the same configuration as the plurality of latch sets (320_0 to 320_k+1) of FIG. 6. That is, the number of latch sets (620_0 to 620_k+1) may be reduced compared to the plurality of latch sets (320_0 to 320_k+2) of FIG. 6.

[0136] The latch selection circuit (630) may include a plurality of selection circuits (630_0 to 630_k+1) corresponding to a plurality of latch sets (620_0 to 620_k+1), respectively. That is, the number of selection circuits in the latch selection circuit (630) may be reduced compared to the latch selection circuit (330) of FIG. 6. Each of the selection circuits (630_0 to 630_k+1) may select one of the unit latches (L_G0 to L_G7) of the corresponding latch set according to the second selection signal (SEL2) and output a bit stored in the selected unit latch. The bits stored in the selected unit latches may be output as a first repair address (REP_ADD1). The first repair address (REP_ADD1) includes an enable bit (CREN1) and address bits (CRA1 <k:0>It can be composed of ).

[0137] The flag setting circuit (640) includes an enable bit (CREN1) and address bits (CRA1 <k:0>The first low-hammer flag signal (CRHT1) can be set based on ). For example, the flag setting circuit (640) has the enable bit (CREN1) as a low bit and the address bits (CRA1 <k:0>If ) matches a specific pattern ("11…1011"), the first low-hammer flag signal (CRHT1) can be set to a high bit.

[0139] FIG. 16 is a detailed circuit diagram of the flag setting circuit (640) of FIG. 14.

[0140] Referring to FIG. 16, the flag setting circuit (640) may include a plurality of XOR gates (XR11 to XR14), a plurality of NOR gates (NR11, NR12), a NAND gate (ND11) and an inverter (INV11).

[0141] The XOR gates (XR11~XR14) are the address bits (CRA1) of the first repair address (REP_ADD1). <k:0>) and bits of a specific pattern ("11…1011") can be compared respectively. NOR gates (NR11, NR12) can perform a logic XOR operation with the outputs of XOR gates (XR11~XR14) and the enable bit (CREN1). NAND gate (ND11) and inverter (INV11) can output a first low-hammer flag signal (CRHT1) by performing a logic AND operation on the outputs of NOR gates (NR11, NR12). With the above configuration, the flag setting circuit (640) has the enable bit (CREN1) as a low bit and the address bits (CRA1 <k:0>If ) matches a specific pattern ("11…1011"), the first low-hammer flag signal (CRHT1) can be set to a high bit.

[0142] According to an embodiment, the flag setting circuit (640) may be included in the address comparison circuit (410) of the column control circuit (150).

[0143] Meanwhile, in the above embodiment, when data of an unused fuse set is detected, the latch control circuit (147) sets the corresponding fuse data to a specific pattern, as an example, but the proposed invention is not limited thereto. According to the embodiment, the non-volatile storage circuit (146) stores repair information (INF_R) for the fault addresses of cell blocks for each group during a rupture operation, and may pre-program a specific pattern in the unused fuse set for each group. For example, the non-volatile storage circuit (146) may program the enable fuse of the unused fuse set to a low bit and program only a specific fuse cell among the address fuses to have a high bit.

[0144] As described above, in the proposed embodiment, the memory device (100) can designate a redundancy column selection line among the redundancy column selection lines (RCSL) that is not used for repair as a low-hammer column selection line without having separate latch sets for storing the low-hammer flag signal (CRHT#). Thus, area utilization can be maximized in managing access counting data for each row.

[0146] Although the technical concept of the present invention has been specifically described according to the preferred embodiments above, it should be noted that the above-described embodiments are for illustrative purposes only and are not intended to be limiting. Furthermore, a person skilled in the art will understand that various embodiments are possible within the scope of the technical concept of the present invention.

[0147] For example, the logic gates and transistors exemplified in the above-described embodiment must be implemented with different positions and types depending on the polarity of the input signal.

Claims

Claim 1 A memory cell region comprising normal cells connected to a plurality of normal column selection lines, redundancy cells and low-hammer cells respectively connected to a plurality of redundancy column selection lines; a repair control circuit providing repair addresses and low-hammer flag signals corresponding to repair information according to a low address; and a column control circuit selecting one of the redundancy column selection lines according to a tracking signal, based on the result of comparing a column address with the repair addresses or in response to the low-hammer flag signals. Claim 2 In claim 1, the column control circuit selects a redundancy column selection line connected to the low-hammer cells according to the activated signal among the low-hammer flag signals when the tracking signal is activated, and selects one of the normal column selection lines or one of the redundancy column selection lines connected to the redundancy cells according to the comparison result when the tracking signal is deactivated. Claim 3 A memory device according to claim 1, wherein the memory cell region comprises a plurality of groups arranged in a column direction, each including a plurality of cell blocks that are arranged in a row direction and share rows, and the repair control circuit stores the repair information for each group and provides the repair addresses and the row-hammer flag signals corresponding to the repair information of the group designated according to some bits of the row address. Claim 4 A memory device according to claim 1, wherein the repair control circuit stores the repair addresses corresponding to the redundancy column selection lines based on the repair information upon boot-up, but does not store the repair address corresponding to the unused redundancy column selection line among the redundancy column selection lines and sets the corresponding low-hammer flag signal to a high bit. Claim 5 In claim 1, the repair control circuit comprises: a non-volatile storage device that outputs repair information as fuse array data according to a fuse address when a boot-up signal is activated; a latch control circuit that provides the fuse array data as a plurality of fuse data and a plurality of flag data according to the fuse address, wherein if it is detected that the fuse array data is unused data, the corresponding fuse data is masked and the corresponding flag data is activated; and a memory device comprising a plurality of latch circuits that each receive and store the plurality of fuse data and the plurality of flag data, and provide the data stored according to the row address as the repair addresses and the row-hammer flag signals. Claim 6 In claim 5, the latch control circuit comprises: a tracking circuit that generates a detection signal when the case where the fuse array data is unused data is detected for the first time and outputs it as a reserve flag signal synchronized with a clock signal; a first selection circuit that outputs the fuse array data as the plurality of fuse data according to the fuse address and the clock signal, and masks the corresponding fuse array data according to the reserve flag signal; and a second selection circuit that outputs the reserve flag signal as the plurality of flag data according to the fuse address and the clock signal. Claim 7 A memory device according to claim 5, wherein each latch circuit comprises: a plurality of latch sets each storing corresponding fuse data and corresponding flag data; and a latch selection circuit providing the data stored in the latch sets according to the row address to the repair addresses and the row-hammer flag signals. Claim 8 In claim 1, the repair control circuit comprises: a non-volatile storage device that outputs repair information as fuse array data according to a fuse address when a boot-up signal is activated; a latch control circuit that provides the fuse array data as a plurality of fuse data according to the fuse address, and sets the fuse data to a specific pattern when it is detected that the fuse array data is unused data; and a memory device comprising a plurality of latch circuits that each receive and store the plurality of fuse data, provide the data stored according to the row address to the repair addresses, and set and provide the row-hammer flag signals based on the repair addresses. Claim 9 In claim 8, the latch control circuit comprises: a tracking circuit that generates a detection signal when the case where the fuse array data is unused data is detected for the first time and outputs a reserve flag signal synchronized with a clock signal; and a selection output circuit that outputs the fuse array data as the plurality of fuse data according to the fuse address and the clock signal, and sets the corresponding fuse data to the specific pattern according to the reserve flag signal. Claim 10 In claim 8, the memory device comprises: a plurality of latch sets each storing corresponding fuse data; a latch selection circuit providing data stored in the latch sets to the repair addresses according to the row address; and a flag setting circuit providing the row-hammer flag signals based on the repair addresses. Claim 11 In claim 1, the column control circuit comprises: an address comparison circuit that generates a normal column disable signal in response to the comparison result or the low-hammer flag signals according to the tracking signal and activates one of a plurality of redundancy column select signals; a column decoder that decodes the column address to activate one of a plurality of normal column select signals and disables all normal column select signals according to the normal column disable signal; a normal driver that drives the normal column select lines according to the normal column select signals; and a redundancy driver that drives the redundancy column select lines according to the redundancy column select signals. Claim 12 A memory device according to claim 11, wherein the address comparison circuit comprises: a redundancy control circuit that activates one of the redundancy column selection signals when the tracking signal is deactivated and the comparison result matches, and activates one of the redundancy column selection signals according to the low-hammer flag signals when the tracking signal is activated; and a disable control circuit that activates the normal column disable signal when the tracking signal is deactivated and at least one of the redundancy column selection signals is activated, and activates the normal column disable signal when the tracking signal is activated. Claim 13 A memory device comprising: a plurality of normal column selection lines and a plurality of redundancy column selection lines, wherein memory cells connected to a redundancy column selection line not used for repair among the redundancy column selection lines are allocated as raw-hammer cells; and a refresh control circuit that, in a raw-hammer tracking mode, selects a target address based on access counting data output from the raw-hammer cells, updates the access counting data, and controls write-back to the raw-hammer cells. Claim 14 In claim 13, the refresh control circuit is a memory device that operates in the low-hammer tracking mode according to a tracking signal that is activated after a predetermined time from the input of an active command and deactivated before a read command or write command is input. Claim 15 In claim 13, the refresh control circuit comprises: a counting control circuit that updates the access counting data according to a tracking signal; and a target address storage circuit that stores a row address as the target address when the access counting data exceeds a preset threshold. Claim 16 A memory device according to claim 13, further comprising: a row control circuit that refreshes one or more adjacent rows corresponding to the target address according to a target refresh command; and an error correction circuit that corrects an error in the access counting data output from the row-hammer cells and provides it to the refresh control circuit, and generates an error correction code using the updated data provided from the refresh control circuit and provides it to the row-hammer cells. Claim 17 A method of operating a memory device comprising: a step of outputting repair information stored in a non-volatile storage device as fuse array data according to a fuse address during boot-up; a step of providing the fuse array data as a plurality of fuse data and a plurality of flag data according to the fuse address, wherein if it is detected that the fuse array data is unused data, the corresponding fuse data is masked and the corresponding flag data is activated; and a step of storing the plurality of fuse data and the plurality of flag data in a plurality of latch circuits, respectively. Claim 18 A method of operation of a memory device according to claim 17, further comprising the step of storing repair information for each of a plurality of groups arranged in a column direction, each including a plurality of cell blocks arranged in a row direction and sharing rows, in the non-volatile storage device. Claim 19 A method of operation of a memory device according to claim 17, further comprising the step of providing data stored in the latch circuits according to a row address as repair addresses and low-hammer flag signals; and, according to a tracking signal, selecting one of the redundancy column selection lines in a memory region in which normal column selection lines and redundancy column selection lines are arranged, based on the result of comparing a column address with the repair addresses or in response to the low-hammer flag signals. Claim 20 A method of operation of a memory device according to claim 19, wherein when the tracking signal is activated, the redundancy column selection line is selected according to the activated signal among the low-hammer flag signals, and when the tracking signal is deactivated, one of the normal column selection lines or one of the redundancy column selection lines is selected according to the comparison result. Claim 21 A method of operating a memory device comprising: a step of storing multiple repair addresses and multiple low-hammer flag signals corresponding to multiple redundancy column selection lines based on repair information stored during boot-up, wherein the repair address corresponding to an unused redundancy column selection line among the redundancy column selection lines is not stored and the corresponding low-hammer flag signal is set to a high bit; a step of selecting one of the redundancy column selection lines according to the low-hammer flag signals during a low-hammer tracking mode and reading access counting data from low-hammer cells connected to the selected redundancy column selection line; and a step of selecting a target address using the access counting data, updating the access counting data, and writing back to the low-hammer cells. Claim 22 A method of operation of a memory device according to claim 21, wherein the low-hammer tracking mode is activated after a predetermined time from the input of an active command and deactivated before a read command or a write command is input. Claim 23 A method of operation of a memory device according to claim 21, wherein the step of selecting the target address includes the step of storing a row address as the target address when the access counting data exceeds a preset threshold. Claim 24 A method of operation of a memory device according to claim 21, further comprising: a step of correcting an error in the access counting data output from the raw-hammer cells; and a step of generating an error correction code using the updated data and providing it to the raw-hammer cells.

Images