Imaging element and imaging device

Abstract

An imaging element composed of multiple stacked semiconductor substrates is miniaturized. The imaging element has a pixel, a pixel circuit, a separation unit, an embedded electrode, and a connection unit. The pixel comprises a photoelectric conversion unit disposed on a first semiconductor substrate that performs photoelectric conversion of incident light, a charge holding unit that holds a charge generated by photoelectric conversion, and a charge transfer unit that transfers the charge from the photoelectric conversion unit to the charge holding unit. The pixel circuit is disposed on a second semiconductor substrate stacked on the surface side of the first semiconductor substrate and generates an image signal based on the retained charge. The separation unit is disposed at the boundary of the pixel. The embedded electrode is disposed by being embedded on the surface side of the first semiconductor substrate at the boundary of the pixel that overlaps with the separation unit and is connected to the first semiconductor substrate. The connection unit is connected to the embedded electrode.

Description

Technology Field

[0001] The present disclosure relates to an imaging element and an imaging device. Background Technology

[0002] In an imaging element that captures an image of a subject, an imaging element composed of multiple stacked substrates is used. These multiple substrates include, for example, a substrate on which pixels are formed to convert incident light from the subject into an image signal using photoelectric conversion, and a substrate on which circuits for generating control signals for the pixels or processing image signals are formed. Circuits for handling analog image signals are placed in the pixels. On the other hand, high-speed digital circuits are mainly used for the circuits that process image signals. By placing circuits of different characteristics on different substrates in this way, it is possible to manufacture the substrates by applying optimal processes to these circuits. Furthermore, by stacking these substrates, it becomes possible to reduce the area of ​​the imaging element.

[0003] For example, an imaging device is proposed in which a first substrate on which a photoelectric conversion element that performs photoelectric conversion of incident light is mainly disposed, and a second substrate on which a reading circuit that outputs an image signal based on the charge generated by the photoelectric conversion element is disposed, are stacked (see, for example, Patent Document 1). In this imaging device, a third substrate on which a logic circuit that processes the image signal is disposed is also stacked to form the imaging device. Prior art literature

[0004] International Publication No. 2019 / 131965 The problem to be solved

[0005] However, the above-described conventional technology has a problem in that the pixel cannot be miniaturized. Since the circuit constituting the pixel is divided into two substrates and stacked, a connection part (contact) for making the reference potential of these substrates common is placed between the substrates. Here, the reference potential is a potential that serves as a reference for the pixel circuit signal or power supply voltage, and, for example, corresponds to the ground potential. It is necessary to provide an area for connecting this contact on the first substrate, which increases the pixel area.

[0006] Therefore, the present disclosure proposes an imaging element and an imaging device capable of miniaturization, wherein a plurality of semiconductor substrates are stacked to form an imaging element and an imaging device. means of solving the problem

[0007] The present disclosure is made to resolve the above-described problems, and an embodiment thereof is an imaging element having a pixel comprising a photoelectric conversion unit disposed on a first semiconductor substrate and performing photoelectric conversion of incident light, a charge holding unit that holds a charge generated by the photoelectric conversion, and a charge transfer unit that transmits the charge from the photoelectric conversion unit to the charge holding unit; a pixel circuit disposed on a second semiconductor substrate stacked on the surface side of the first semiconductor substrate and generating an image signal based on the held charge; a separation unit disposed at the boundary of the pixel; an embedded electrode disposed on the surface side of the first semiconductor substrate at the boundary of the pixel that overlaps with the separation unit and connected to the first semiconductor substrate; and a connection unit connected to the embedded electrode. Brief explanation of the drawing

[0008] FIG. 1 is a block diagram showing an example of the functional configuration of an imaging device according to one embodiment of the present disclosure. FIG. 2 is a planar schematic diagram illustrating the schematic configuration of the imaging device shown in FIG. 1. FIG. 3 is a schematic diagram illustrating a cross-sectional configuration along the line III-III' shown in FIG. 2. FIG. 4 is an equivalent circuit diagram illustrating an example of the configuration of a pixel sharing unit according to an embodiment of the present disclosure. FIG. 5 is a cross-sectional view illustrating an example of the configuration of an imaging device according to an embodiment of the present disclosure. FIG. 6 is a cross-sectional view illustrating another configuration example of an imaging device according to an embodiment of the present disclosure. FIG. 7 is a cross-sectional view illustrating another configuration example of an imaging device according to an embodiment of the present disclosure. FIG. 8 is a drawing illustrating an example of the configuration of a pixel sharing unit according to a first embodiment of the present disclosure. FIG. 9 is a drawing illustrating an example of a pixel configuration according to a first embodiment of the present disclosure. FIG. 10a is a drawing illustrating an example of a method for manufacturing an imaging element according to a first embodiment of the present disclosure. FIG. 10b is a drawing illustrating an example of a method for manufacturing an imaging element according to a first embodiment of the present disclosure. FIG. 10c is a drawing illustrating an example of a method for manufacturing an imaging element according to a first embodiment of the present disclosure. FIG. 10d is a drawing illustrating an example of a method for manufacturing an imaging element according to a first embodiment of the present disclosure. FIG. 10e is a drawing illustrating an example of a method for manufacturing an imaging element according to a first embodiment of the present disclosure. FIG. 10f is a drawing illustrating an example of a method for manufacturing an imaging element according to a first embodiment of the present disclosure. FIG. 10g is a drawing illustrating an example of a method for manufacturing an imaging element according to a first embodiment of the present disclosure. FIG. 10h is a drawing illustrating an example of a method for manufacturing an imaging element according to a first embodiment of the present disclosure. FIG. 10i is a drawing illustrating an example of a method for manufacturing an imaging element according to a first embodiment of the present disclosure. FIG. 11 is a drawing illustrating another configuration example of a pixel sharing unit according to a first embodiment of the present disclosure. FIG. 12a is a drawing illustrating another configuration example of a buried electrode according to the first embodiment of the present disclosure. FIG. 12b is a drawing illustrating another configuration example of a buried electrode according to the first embodiment of the present disclosure. FIG. 13 is a drawing illustrating another configuration example of a pixel sharing unit according to a first embodiment of the present disclosure. FIG. 14 is a drawing illustrating an example of the configuration of a pixel sharing unit according to a second embodiment of the present disclosure. FIG. 15a is a drawing illustrating an example of the configuration of boundary wiring according to a second embodiment of the present disclosure. FIG. 15b is a drawing illustrating an example of the configuration of boundary wiring according to a second embodiment of the present disclosure. FIG. 16a is a drawing illustrating an example of a method for manufacturing boundary wiring according to a second embodiment of the present disclosure. FIG. 16b is a drawing illustrating an example of a method for manufacturing boundary wiring according to a second embodiment of the present disclosure. FIG. 16c is a drawing illustrating an example of a method for manufacturing boundary wiring according to a second embodiment of the present disclosure. FIG. 16d is a drawing illustrating an example of a method for manufacturing boundary wiring according to a second embodiment of the present disclosure. FIG. 16e is a drawing illustrating an example of a method for manufacturing boundary wiring according to a second embodiment of the present disclosure. FIG. 17a is a drawing illustrating another configuration example of boundary wiring according to a second embodiment of the present disclosure. FIG. 17b is a drawing illustrating another configuration example of boundary wiring according to a second embodiment of the present disclosure. FIG. 18a is a drawing illustrating an example of another method of manufacturing boundary wiring according to a second embodiment of the present disclosure. FIG. 18b is a drawing illustrating an example of another method of manufacturing boundary wiring according to a second embodiment of the present disclosure. FIG. 18c is a drawing illustrating an example of another method of manufacturing boundary wiring according to a second embodiment of the present disclosure. FIG. 18d is a drawing illustrating an example of another method of manufacturing boundary wiring according to a second embodiment of the present disclosure. FIG. 18e is a drawing illustrating an example of another method of manufacturing boundary wiring according to a second embodiment of the present disclosure. FIG. 18f is a drawing illustrating an example of another method of manufacturing boundary wiring according to a second embodiment of the present disclosure. FIG. 18g is a drawing illustrating an example of another method of manufacturing boundary wiring according to a second embodiment of the present disclosure. FIG. 19 is a drawing illustrating another configuration example of a pixel sharing unit according to a second embodiment of the present disclosure. FIG. 20a is a drawing illustrating an example of the configuration of a pixel array section according to a third embodiment of the present disclosure. FIG. 20b is a drawing illustrating an example of the configuration of a pixel array section according to a third embodiment of the present disclosure. FIG. 20c is a drawing illustrating an example of the configuration of a pixel array section according to a third embodiment of the present disclosure. FIG. 21 is a drawing illustrating an example of the configuration of a pixel array section according to a third embodiment of the present disclosure. FIG. 22 is a drawing illustrating the comparison results of a pixel array section according to a third embodiment of the present disclosure. FIG. 23a is a drawing illustrating an example of the configuration of a pixel array section according to a fourth embodiment of the present disclosure. FIG. 23b is a drawing illustrating an example of the configuration of a pixel array section according to a fourth embodiment of the present disclosure. FIG. 23c is a drawing illustrating an example of the configuration of a pixel array section according to a fourth embodiment of the present disclosure. FIG. 24 is a drawing illustrating the comparison results of a pixel array section according to a fourth embodiment of the present disclosure. FIG. 25a is a drawing illustrating an example of the configuration of a pixel array section according to the fifth embodiment of the present disclosure. FIG. 25b is a drawing illustrating an example of the configuration of a pixel array section according to a fifth embodiment of the present disclosure. FIG. 25c is a drawing illustrating an example of the configuration of a pixel array section according to the fifth embodiment of the present disclosure. FIG. 25d is a drawing illustrating an example of the configuration of a pixel array section according to a fifth embodiment of the present disclosure. FIG. 25e is a drawing illustrating an example of the configuration of a pixel array section according to a fifth embodiment of the present disclosure. FIG. 26 is a drawing illustrating the comparison results of a pixel array section according to the fifth embodiment of the present disclosure. FIG. 27a is a drawing illustrating an example of the configuration of a pixel array section according to the sixth embodiment of the present disclosure. FIG. 27b is a drawing illustrating an example of the configuration of a pixel array section according to the sixth embodiment of the present disclosure. FIG. 27c is a drawing illustrating an example of the configuration of a pixel array section according to the sixth embodiment of the present disclosure. FIG. 27d is a drawing illustrating an example of the configuration of a pixel array section according to the sixth embodiment of the present disclosure. FIG. 27e is a drawing illustrating an example of the configuration of a pixel array section according to the sixth embodiment of the present disclosure. FIG. 27f is a drawing illustrating an example of the configuration of a pixel array section according to the sixth embodiment of the present disclosure. FIG. 28 is a drawing illustrating the comparison results of a pixel array section according to the sixth embodiment of the present disclosure. FIG. 29a is a drawing illustrating an example of the configuration of a separation part according to the seventh embodiment of the present disclosure. FIG. 29b is a drawing illustrating an example of the configuration of a separation part according to the seventh embodiment of the present disclosure. FIG. 30 is a drawing illustrating an example of the configuration of a pixel sharing unit according to the eighth embodiment of the present disclosure. FIG. 31 is a drawing illustrating an example of a pixel configuration according to the eighth embodiment of the present disclosure. FIG. 32 is a drawing illustrating an example of the configuration of a pixel sharing unit according to the ninth embodiment of the present disclosure. FIG. 33 is a drawing illustrating an example of a pixel configuration according to the ninth embodiment of the present disclosure. FIG. 34a is a drawing illustrating an example of a method for manufacturing an imaging element according to the ninth embodiment of the present disclosure. FIG. 34b is a drawing illustrating an example of a method for manufacturing an imaging element according to the ninth embodiment of the present disclosure. FIG. 34c is a drawing illustrating an example of a method for manufacturing an imaging element according to the ninth embodiment of the present disclosure. FIG. 34d is a drawing illustrating an example of a method for manufacturing an imaging element according to the ninth embodiment of the present disclosure. FIG. 34e is a drawing illustrating an example of a method for manufacturing an imaging element according to the ninth embodiment of the present disclosure. FIG. 34f is a drawing illustrating an example of a method for manufacturing an imaging element according to the ninth embodiment of the present disclosure. FIG. 34g is a drawing illustrating an example of a method for manufacturing an imaging element according to the ninth embodiment of the present disclosure. FIG. 34h is a drawing illustrating an example of a method for manufacturing an imaging element according to the ninth embodiment of the present disclosure. FIG. 34i is a drawing illustrating an example of a method for manufacturing an imaging element according to the ninth embodiment of the present disclosure. FIG. 34j is a drawing illustrating an example of a method for manufacturing an imaging element according to the ninth embodiment of the present disclosure. FIG. 34k is a drawing illustrating an example of a method for manufacturing an imaging element according to the ninth embodiment of the present disclosure. FIG. 341 is a drawing illustrating an example of a method for manufacturing an imaging element according to the ninth embodiment of the present disclosure. FIG. 34m is a drawing illustrating an example of a method for manufacturing an imaging element according to the ninth embodiment of the present disclosure. FIG. 35 is a drawing illustrating a first variation of the configuration of a charge transfer unit according to the ninth embodiment of the present disclosure. FIG. 36a is a drawing illustrating a second variation of the configuration of a charge transfer unit according to the ninth embodiment of the present disclosure. FIG. 36b is a drawing illustrating a second variation of the configuration of a charge transfer unit according to the ninth embodiment of the present disclosure. FIG. 36c is a drawing illustrating a second variation of the configuration of a charge transfer unit according to the ninth embodiment of the present disclosure. FIG. 36d is a drawing illustrating a second variation of the configuration of a charge transfer unit according to the ninth embodiment of the present disclosure. FIG. 36e is a drawing illustrating a second variation of the configuration of a charge transfer unit according to the ninth embodiment of the present disclosure. FIG. 37 is a drawing illustrating an example of the configuration of a pixel sharing unit according to the 10th embodiment of the present disclosure. FIG. 38 is a drawing illustrating an example of a schematic configuration of an imaging system equipped with an imaging device according to the above embodiment and a variation thereof. FIG. 39 is a diagram illustrating an example of a flowchart of an imaging operation in an imaging system. FIG. 40 is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology of the present disclosure may be applied. FIG. 41 is a drawing illustrating an example of the installation location of the imaging unit (12031). FIG. 42 is a drawing illustrating an example of a schematic configuration of an endoscopic surgical system to which the technology of the present disclosure (the technology) can be applied. FIG. 43 is a block diagram illustrating an example of the functional configuration of the camera head (11102) and CCU (11201) shown in FIG. 42. Specific details for implementing the invention

[0009] Hereinafter, embodiments of the present disclosure will be described in detail based on the drawings. The description will be given in the following order. In addition, in each of the following embodiments, the same parts are assigned the same number to omit redundant descriptions.

[0010] 1. First embodiment

[0011] 2. Second embodiment

[0012] 3. Third embodiment

[0013] 4. Fourth embodiment

[0014] 5. Fifth embodiment

[0015] 6. Sixth embodiment

[0016] 7. Seventh embodiment

[0017] 8. Eighth Embodiment

[0018] 9. Ninth embodiment

[0019] 10. 10th Embodiment

[0020] 11. Application Examples

[0021] 12. Examples of Application to Moving Objects

[0022] 13. Examples of Applications to Endoscopic Surgical Systems

[0023] (1. First embodiment)

[0024] [Functional configuration of the imaging device (1)]

[0025] FIG. 1 is a block diagram illustrating an example of the functional configuration of an imaging device (imaging device (1)) according to one embodiment of the present disclosure.

[0026] The imaging device (1) of FIG. 1 includes, for example, an input unit (510A), a row driving unit (520), a timing control unit (530), a pixel array unit (540), a column signal processing unit (550), an image signal processing unit (560), and an output unit (510B).

[0027] In the pixel array section (540), pixels (541) are repeatedly arranged in an array. More specifically, a pixel sharing unit (539) containing multiple pixels serves as a repeating unit, and this is repeatedly arranged in an array formed in a row direction and a column direction. Additionally, for convenience in this specification, the row direction may be referred to as the H direction, and the column direction orthogonal to the row direction as the V direction. In the example of FIG. 1, one pixel sharing unit (539) includes four pixels (pixels (541A, 541B, 541C, and 541D)). Each of the pixels (541A, 541B, 541C, and 541D) has a photoelectric conversion unit (101) (shown in FIG. 8, etc., described later). The pixel sharing unit (539) is a unit that shares one pixel circuit (pixel circuit (210) of FIG. 3, described later). In other words, for every four pixels (pixels (541A, 541B, 541C, and 541D)), there is one pixel circuit (pixel circuit (210) described later). By operating this pixel circuit in time division, the pixel signals of each pixel (541A, 541B, 541C, and 541D) are sequentially read. The pixels (541A, 541B, 541C, and 541D) are arranged, for example, in a 2x2 row arrangement. In the pixel array section (540), along with the pixels (541A, 541B, 541C, and 541D), a plurality of row driving signal lines (542) and a plurality of vertical signal lines (column reading lines) (543) are provided. The row driving signal line (542) drives a pixel (541) included in each of the plurality of pixel sharing units (539) arranged in a row direction in the pixel array section (540). It drives each pixel arranged in a row direction among the pixel sharing units (539). Although it will be explained in detail later with reference to FIG. 4, the pixel sharing unit (539) is provided with a plurality of transistors. In order to drive each of these plurality of transistors, a plurality of row driving signal lines (542) are connected to one pixel sharing unit (539).A pixel sharing unit (539) is connected to a vertical signal line (column reading line) (543). A pixel signal is read through the vertical signal line (column reading line) (543) from each of the pixels (541A, 541B, 541C and 541D) included in the pixel sharing unit (539).

[0028] The row driving unit (520) includes, for example, a row address control unit that determines a row position for driving a pixel, in other words, a row decoder unit, and a row driving circuit unit that generates a signal for driving pixels (541A, 541B, 541C and 541D).

[0029] The thermal signal processing unit (550) is, for example, connected to a vertical signal line (543) and has a load circuit that forms a source follower circuit with pixels (541A, 541B, 541C and 541D) (pixel sharing unit (539)). The thermal signal processing unit (550) may have an amplification circuit that amplifies a signal read from the pixel sharing unit (539) through the vertical signal line (543). The thermal signal processing unit (550) may have a noise processing unit. In the noise processing unit, for example, a noise level of the system is removed from a signal read from the pixel sharing unit (539) as a result of photoelectric conversion.

[0030] The column signal processing unit (550) has, for example, an analog-to-digital converter (ADC). In the analog-to-digital converter, the signal read from the pixel sharing unit (539) or the noise-processed analog signal is converted into a digital signal. The ADC includes, for example, a comparator and a counter. In the comparator, the analog signal to be converted is compared with a reference signal to be compared with it. In the counter, the time until the comparison result in the comparator is inverted is measured. The column signal processing unit (550) may also include a horizontal scanning circuit that performs control for scanning the read column.

[0031] The timing control unit (530) supplies a timing control signal to the row driving unit (520) and the column signal processing unit (550) based on a reference clock signal or a timing control signal input to the device.

[0032] The image signal processing unit (560) is a circuit that performs various signal processing on data obtained as a result of photoelectric conversion, in other words, data obtained as a result of the imaging operation in the imaging device (1). The image signal processing unit (560) includes, for example, an image signal processing circuit unit and a data holding unit. The image signal processing unit (560) may include a processor unit.

[0033] An example of signal processing performed in the image signal processing unit (560) is a tone curve correction process that increases the gradation when the AD-converted image data is data that captures a dark subject, and decreases the gradation when the data captures a bright subject. In this case, it is desirable to store in advance the characteristic data of the tone curve in the data holding unit of the image signal processing unit (560) which tone curve will be used to correct the gradation of the image data.

[0034] The input unit (510A) is intended to input, for example, the reference clock signal, timing control signal, and characteristic data, etc., from outside the device to the imaging device (1). The timing control signal is, for example, a vertical synchronization signal and a horizontal synchronization signal. The characteristic data is intended to be stored, for example, in the data holding unit of the image signal processing unit (560). The input unit (510A) includes, for example, an input terminal (511), an input circuit unit (512), an input amplitude change unit (513), an input data conversion circuit unit (514), and a power supply unit (not shown).

[0035] The input terminal (511) is an external terminal for inputting data. The input circuit section (512) is intended to introduce the signal input to the input terminal (511) into the interior of the imaging device (1). In the input amplitude changing section (513), the amplitude of the signal introduced from the input circuit section (512) is changed to an amplitude that is easy to use inside the imaging device (1). In the input data conversion circuit section (514), the arrangement of the data column of the input data is changed. The input data conversion circuit section (514) is configured, for example, by a serial-parallel conversion circuit. In this serial-parallel conversion circuit, the serial signal received as input data is converted into a parallel signal. Additionally, in the input section (510A), the input amplitude changing section (513) and the input data conversion circuit section (514) may be omitted. The power supply unit supplies power set to various voltages required inside the imaging device (1) based on power supplied to the imaging device (1) from the outside.

[0036] When the imaging device (1) is connected to an external memory device, the input section (510A) may be provided with a memory interface circuit for receiving data from the external memory device. The external memory device is, for example, a flash memory, SRAM, and DRAM.

[0037] The output unit (510B) outputs image data to the outside of the device. This image data is, for example, image data captured by the imaging device (1) and image data processed by the image signal processing unit (560). The output unit (510B) includes, for example, an output data conversion circuit unit (515), an output amplitude changing unit (516), an output circuit unit (517), and an output terminal (518).

[0038] The output data conversion circuit (515) is configured, for example, by a parallel serial conversion circuit, and in the output data conversion circuit (515), a parallel signal used inside the imaging device (1) is converted into a serial signal. The output amplitude changing unit (516) changes the amplitude of the signal used inside the imaging device (1). The signal with the changed amplitude becomes easy to use by an external device connected to the outside of the imaging device (1). The output circuit (517) is a circuit that outputs data from inside the imaging device (1) to the outside of the device, and the wiring outside the imaging device (1) connected to the output terminal (518) is driven by the output circuit (517). At the output terminal (518), data is output from the imaging device (1) to the outside of the device. In the output unit (510B), the output data conversion circuit (515) and the output amplitude changing unit (516) may be omitted.

[0039] When the imaging device (1) is connected to an external memory device, the output section (510B) may be provided with a memory interface circuit that outputs data to the external memory device. The external memory device is, for example, a flash memory, SRAM, and DRAM.

[0040] [Synthetic configuration of the imaging device (1)]

[0041] FIGS. 2 and FIGS. 3 illustrate an example of a schematic configuration of an imaging device (1). The imaging device (1) is equipped with three substrates (a first substrate (100), a second substrate (200), and a third substrate (300)). FIG. 2 schematically illustrates the planar configuration of each of the first substrate (100), the second substrate (200), and the third substrate (300), and FIG. 3 schematically illustrates the cross-sectional configuration of the first substrate (100), the second substrate (200), and the third substrate (300) stacked together. FIG. 3 corresponds to the cross-sectional configuration along the line III-III' shown in FIG. 2. The imaging device (1) is an imaging device with a three-dimensional structure formed by joining three substrates (a first substrate (100), a second substrate (200), and a third substrate (300)). The first substrate (100) includes a semiconductor layer (100S) and a wiring layer (100T). The second substrate (200) includes a semiconductor layer (200S) and a wiring layer (200T). The third substrate (300) includes a semiconductor layer (300S) and a wiring layer (300T). Here, the wiring included in each of the first substrate (100), the second substrate (200), and the third substrate (300), and the interlayer insulating film surrounding it are combined, for convenience, referred to as the wiring layer (100T, 200T, 300T) provided in each substrate (first substrate (100), second substrate (200), and third substrate (300)). The first substrate (100), the second substrate (200), and the third substrate (300) are stacked in this order, and along the stacking direction, they are arranged in the order of a semiconductor layer (100S), a wiring layer (100T), a semiconductor layer (200S), a wiring layer (200T), a wiring layer (300T), and a semiconductor layer (300S). The specific configuration of the first substrate (100), the second substrate (200), and the third substrate (300) will be described later. The arrow shown in FIG. 3 indicates the direction of incidence of light (L) to the imaging device (1).For convenience in this specification, in the cross-sectional views thereafter, the light incident side of the imaging device (1) may be referred to as “low,” “lower side,” “downward,” and the side opposite to the light incident side may be referred to as “up,” “upper side,” or “upward.” Additionally, for convenience in this specification, regarding a substrate having a semiconductor layer and a wiring layer, the side of the wiring layer may be referred to as the surface, and the side of the semiconductor layer may be referred to as the back side. Furthermore, the description in this specification is not limited to the above designations. The imaging device (1) is, for example, a back-illumination type imaging device in which light is incident from the back side of a first substrate (100) having a photodiode.

[0042] The pixel array section (540) and the pixel sharing unit (539) included in the pixel array section (540) are both configured using both the first substrate (100) and the second substrate (200). The first substrate (100) is provided with a plurality of pixels (541A, 541B, 541C, and 541D) that the pixel sharing unit (539) has. Each of these pixels (541) has a photodiode (photoelectric conversion unit (101) described later) and a transfer transistor (charge transfer unit (102) described later). The second substrate (200) is provided with a pixel circuit (pixel circuit (210) described later) that the pixel sharing unit (539) has. The pixel circuit reads a pixel signal transmitted through a transmission transistor from each photodiode of the pixels (541A, 541B, 541C, and 541D), or resets the photodiode. In addition to this pixel circuit, the second substrate (200) has a plurality of row driving signal lines (542) extending in the row direction and a plurality of vertical signal lines (543) extending in the column direction. The second substrate (200) also has a power line (544) extending in the row direction. The third substrate (300) has, for example, an input unit (510A), a row driving unit (520), a timing control unit (530), a column signal processing unit (550), an image signal processing unit (560), and an output unit (510B). A row driving unit (520) is provided in an area that partially overlaps with a pixel array unit (540) in the stacking direction (hereinafter simply referred to as the stacking direction) of, for example, the first substrate (100), the second substrate (200), and the third substrate (300). More specifically, the row driving unit (520) is provided in an area that partially overlaps with the pixel array unit (540) near the end of the H direction in the stacking direction (Fig. 2). A thermal signal processing unit (550) is provided in an area that partially overlaps with the pixel array unit (540) in the stacking direction, for example.More specifically, the thermal signal processing unit (550) is provided in an area that overlaps near the end of the V direction of the pixel array unit (540) in the stacking direction (Fig. 2). Although not illustrated, the input unit (510A) and the output unit (510B) may be placed in a part other than the third substrate (300), for example, on the second substrate (200). Alternatively, the input unit (510A) and the output unit (510B) may be provided on the back side (light incident surface) of the first substrate (100). Furthermore, the pixel circuit provided on the second substrate (200) may be referred to by other names such as pixel transistor circuit, pixel transistor group, pixel transistor, pixel read circuit, or read circuit. In this specification, the term "pixel circuit" is used.

[0043] The first substrate (100) and the second substrate (200) are electrically connected, for example, by a through electrode (the through electrode (252, 253A and 253B) of FIG. 8 described later). The second substrate (200) and the third substrate (300) are electrically connected, for example, through contact portions (201, 202, 301 and 302). Contact portions (201, 202) are provided on the second substrate (200), and contact portions (301, 302) are provided on the third substrate (300). The contact portion (201) of the second substrate (200) is in contact with the contact portion (301) of the third substrate (300), and the contact portion (202) of the second substrate (200) is in contact with the contact portion (302) of the third substrate (300). The second substrate (200) has a contact area (201R) provided with a plurality of contact portions (201) and a contact area (202R) provided with a plurality of contact portions (202). The third substrate (300) has a contact area (301R) provided with a plurality of contact portions (301) and a contact area (302R) provided with a plurality of contact portions (302). Contact regions (201R and 301R) are provided between the pixel array section (540) and the row driving section (520) in the stacking direction (Fig. 3). In other words, contact regions (201R and 301R) are provided, for example, in the area where the row driving section (520) (third substrate (300)) and the pixel array section (540) (second substrate (200)) overlap in the stacking direction, or in the vicinity thereof. Contact regions (201R and 301R) are, for example, placed at the end of the H direction in such an area (Fig. 2). In the third substrate (300), contact regions (301R) are provided at a position that overlaps, for example, a part of the row driving section (520), specifically at the end of the row driving section (520) in the H direction (Figs. 2 and 3). The contact portion (201 and 301) connects, for example, a row driving portion (520) provided on a third substrate (300) and a row driving signal line (542) provided on a second substrate (200).The contact portions (201 and 301) may, for example, be connected to the input portion (510A) provided on the third substrate (300), the power line (544), and the reference potential line (ground line described later). The contact areas (202R and 302R) are provided between the pixel array portion (540) and the thermal signal processing portion (550) in the stacking direction (Fig. 3). In other words, the contact areas (202R and 302R) are provided, for example, in the area where the thermal signal processing portion (550) (third substrate (300)) and the pixel array portion (540) (second substrate (200)) overlap in the stacking direction, or in the area near therefrom. The contact areas (202R and 302R) are, for example, placed at the end of the V direction among these areas (Fig. 2). In the third substrate (300), a contact area (301R) is provided at a position that overlaps, for example, a part of the thermal signal processing unit (550), specifically the end of the thermal signal processing unit (550) in the V direction (Figs. 2 and 3). The contact portions (202 and 302) are intended to connect a pixel signal (a signal corresponding to the amount of charge generated as a result of photoelectric conversion in a photodiode) output from each of the plurality of pixel sharing units (539) of the pixel array unit (540), for example, to the thermal signal processing unit (550) provided in the third substrate (300). The pixel signal is configured to be sent from the second substrate (200) to the third substrate (300).

[0044] FIG. 3 is an example of a cross-sectional view of an imaging device (1) as described above. A first substrate (100), a second substrate (200), and a third substrate (300) are electrically connected through wiring layers (100T, 200T, and 300T). For example, the imaging device (1) has an electrical connection portion that electrically connects the second substrate (200) and the third substrate (300). Specifically, contact portions (201, 202, 301, and 302) are formed with electrodes formed of a conductive material. The conductive material is formed of a metal material such as copper (Cu), aluminum (Al), and gold (Au), for example. The contact regions (201R, 202R, 301R and 302R) electrically connect the second substrate and the third substrate by directly joining the wiring formed as electrodes, for example, thereby enabling the input and / or output of signals from the second substrate (200) and the third substrate (300).

[0045] An electrical connection portion that electrically connects the second substrate (200) and the third substrate (300) can be provided at a desired location. For example, as described in FIG. 3 as contact areas (201R, 202R, 301R and 302R), it may be provided in an area that overlaps with the pixel array portion (540) in the stacking direction. Additionally, the electrical connection portion may be provided in an area that does not overlap with the pixel array portion (540) in the stacking direction. Specifically, it may be provided in an area that overlaps with a peripheral portion placed on the outside of the pixel array portion (540) in the stacking direction.

[0046] For example, the first substrate (100) and the second substrate (200) are provided with connection holes (H1 and H2). The connection holes (H1 and H2) penetrate the first substrate (100) and the second substrate (200) (Fig. 3). The connection holes (H1 and H2) are provided on the outside of the pixel array portion (540) (or the portion overlapping the pixel array portion (540)) (Fig. 2). For example, the connection hole portion (H1) is positioned further outward than the pixel array portion (540) in the H direction, and the connection hole portion (H2) is positioned further outward than the pixel array portion (540) in the V direction. For example, the connection hole portion (H1) extends to an input portion (510A) provided on the third substrate (300), and the connection hole portion (H2) extends to an output portion (510B) provided on the third substrate (300). The connection hole portions (H1 and H2) may be hollow, or may contain a conductive material in at least a part thereof. For example, there is a configuration in which a bonding wire is connected to an electrode formed as the input portion (510A) and / or the output portion (510B). Alternatively, there is a configuration in which an electrode formed as the input portion (510A) and / or the output portion (510B) is connected to a conductive material provided in the connection hole portions (H1 and H2). The conductive material provided in the connection hole portions (H1 and H2) may be embedded in part or all of the connection hole portions (H1 and H2), or the conductive material may be formed on the side wall of the connection hole portions (H1 and H2).

[0047] Additionally, in FIG. 3, the structure is configured such that an input section (510A) and an output section (510B) are provided on the third substrate (300), but this is not limited thereto. For example, the input section (510A) and / or the output section (510B) may be provided on the second substrate (200) by sending a signal from the third substrate (300) to the second substrate (200) through wiring layers (200T and 300T). Likewise, the input section (510A) and / or the output section (510B) may be provided on the first substrate (100) by sending a signal from the second substrate (200) to the first substrate (1000) through wiring layers (100T and 200T).

[0048] In addition, the imaging device (1) and the pixel array unit (540) are examples of imaging elements described in the claims.

[0049] FIG. 4 is an equivalent circuit diagram illustrating an example of the configuration of a pixel sharing unit. The pixel sharing unit (539) includes a plurality of pixels (541) (in FIG. 4, four pixels (541) of pixels (541A, 541B, 541C and 541D) are shown), one pixel circuit (210) connected to the plurality of pixels (541), and a vertical signal line (543) connected to the pixel circuit (210). The pixel circuit (210) includes, for example, four transistors, specifically, an amplifier transistor (213), a select transistor (214), a reset transistor (211), and a capacitance switching transistor (212). As described above, the pixel sharing unit (539) is configured to output the pixel signals of each of the four pixels (541) (pixels (541A, 541B, 541C, and 541D)) included in the pixel sharing unit (539) to sequential vertical signal lines (543) by operating one pixel circuit (210) in a time-division manner. A manner in which one pixel circuit (210) is connected to a plurality of pixels (541) and the pixel signals of these plurality of pixels (541) are output in a time-division manner by one pixel circuit (210) is referred to as "a plurality of pixels (541) share one pixel circuit (210)."

[0050] Pixels (541A, 541B, 541C, and 541D) have common components.

[0051] Pixels (541A, 541B, 541C, and 541D) have, for example, a photoelectric conversion unit (101), a charge transfer unit (102) electrically connected to the photoelectric conversion unit (101), and a charge holding unit (103) electrically connected to the charge transfer unit (102). In the photoelectric conversion unit (101) (photoelectric conversion units (101A, 101B, 101C, and 101D)), the cathode is electrically connected to the source of the charge transfer unit (102), and the anode is electrically connected to a reference potential line (for example, a ground line). The photoelectric conversion unit (101) converts incident light into an electric charge according to the amount of light received. The charge transfer unit (102) (charge transfer units (102A, 102B, 102C, and 102D)) is, for example, an n-channel MOS transistor. In the charge transfer unit (102), the drain is electrically connected to the charge holding unit (103), and the gate is electrically connected to the driving signal line (signal line (TG1, TG2, TG3, and TG4)). This driving signal line is part of a plurality of row driving signal lines (542) (see FIG. 1) connected to one pixel sharing unit (539). The charge transfer unit (102) transmits the charge generated in the photoelectric conversion unit (101) to the charge holding unit (103). The charge holding unit (103) (charge holding units (103A, 103B, 103C, and 103D)) is an n-type diffusion layer region formed in the p-type semiconductor layer. This charge holding unit (103) is referred to as Floating Diffusion (FD). The charge holding unit (103) is a charge holding means that temporarily holds a charge transmitted from the photoelectric conversion unit (101), and is also a charge-voltage conversion means that generates a voltage according to the amount of charge.

[0052] Four charge holding portions (103) (charge holding portions (103A, 103B, 103C, and 103D)) included in one pixel sharing unit (539) are electrically connected to each other and are also electrically connected to the gate of an amplification transistor (213) and the source of a capacitance switching transistor (212). The drain of the capacitance switching transistor (212) is connected to the source of a reset transistor (211), and the gate of the capacitance switching transistor (212) is connected to a driving signal line (FDG). This driving signal line (FDG) is part of a plurality of row driving signal lines (542) connected to one pixel sharing unit (539). The drain of the reset transistor (211) is connected to a power line (Vdd), and the gate of the reset transistor (211) is connected to a driving signal line (RST). This driving signal line (RST) is part of a plurality of row driving signal lines (542) connected to one pixel sharing unit (539). The gate of the amplification transistor (213) is connected to the charge holding unit (103), the drain of the amplification transistor (213) is connected to the power line (Vdd), and the source of the amplification transistor (213) is connected to the drain of the selection transistor (214). The source of the selection transistor (214) is connected to the vertical signal line (543), and the gate of the selection transistor (214) is connected to the driving signal line (SEL). This driving signal line (SEL) is part of a plurality of row driving signal lines (542) connected to one pixel sharing unit (539).

[0053] When the charge transfer unit (102) is turned on, it transfers the charge of the photoelectric conversion unit (101) to the charge holding unit (103). The gate (transmission gate) of the charge transfer unit (102) includes, for example, a so-called vertical electrode and is provided to extend from the surface of the semiconductor layer (the semiconductor layer (100S) of Fig. 8 described later) to a depth reaching the photoelectric conversion unit (101), as shown in Fig. 8 described later. The reset transistor (211) resets the potential of the charge holding unit (103) to a predetermined potential. When the reset transistor (211) is turned on, it resets the potential of the charge holding unit (103) to the potential of the power line (Vdd). The select transistor (214) controls the output timing of the pixel signal from the pixel circuit (210). The amplification transistor (213) generates a voltage signal according to the level of charge held in the charge holding portion (103) as a pixel signal. The amplification transistor (213) is connected to the vertical signal line (543) through the selection transistor (214). This amplification transistor (213) forms a source follower together with the load circuit portion (see FIG. 1) connected to the vertical signal line (543) in the column signal processing portion (550). When the selection transistor (214) is turned on, the amplification transistor (213) outputs the voltage of the charge holding portion (103) to the column signal processing portion (550) through the vertical signal line (543). The reset transistor (211), the amplification transistor (213), and the selection transistor (214) are, for example, n-channel MOS transistors.

[0054] The capacitance switching transistor (212) is used to change the gain of charge-voltage conversion in the charge holding unit (103). Generally, the pixel signal is small when shooting in a dark place. When performing charge-voltage conversion based on Q=CV, if the capacitance of the charge holding unit (103) (capacitance of FD (C)) is large, V becomes small when converted into voltage by the amplification transistor (213). On the other hand, since the pixel signal is large in a bright place, if the capacitance of FD (C) is not large, the charge holding unit (103) cannot receive all the charge from the photoelectric conversion unit (101). In addition, the capacitance of FD (C) needs to be large so that V when converted into voltage by the amplification transistor (213) does not become excessively large (in other words, becomes small). Based on these, when the capacitance switching transistor (212) is turned on, the gate capacitance of the capacitance switching transistor (212) increases, so the total capacitance (C) of the FD increases. On the other hand, when the capacitance switching transistor (212) is turned off, the total capacitance (C) of the FD decreases. In this way, by switching the capacitance switching transistor (212) on / off, the capacitance (C) of the FD can be varied, thereby allowing the conversion efficiency to be switched. The capacitance switching transistor (212) is, for example, an n-channel MOS transistor.

[0055] Additionally, a configuration without a capacitance switching transistor (212) is also possible. In this case, for example, the pixel circuit (210) is composed of three transistors, for example, an amplification transistor (213), a selection transistor (214), and a reset transistor (211). The pixel circuit (210) has at least one pixel transistor, such as an amplification transistor (213), a selection transistor (214), a reset transistor (211), and a capacitance switching transistor (212).

[0056] The selection transistor (214) may be provided between the power line (Vdd) and the amplification transistor (213). In this case, the drain of the reset transistor (211) is electrically connected to the power line (Vdd) and the drain of the selection transistor (214). The source of the selection transistor (214) is electrically connected to the drain of the amplification transistor (213), and the gate of the selection transistor (214) is electrically connected to the row driving signal line (542) (see FIG. 1). The source of the amplification transistor (213) (output terminal of the pixel circuit (210)) is electrically connected to the vertical signal line (543), and the gate of the amplification transistor (213) is electrically connected to the source of the reset transistor (211). Additionally, although not shown, the number of pixels (541) sharing one pixel circuit (210) may be other than 4. For example, two or eight pixels (541) may share one pixel circuit (210).

[0057] [Cross-sectional configuration of the imaging device]

[0058] FIG. 5 is a cross-sectional view illustrating an example configuration of an imaging device according to an embodiment of the present disclosure. FIG. 5 is a cross-sectional view illustrating a schematic of an imaging device (1). The imaging device (1) of FIG. 5 comprises a first substrate (100), a second substrate (200), and a third substrate (300). As described above, the first substrate (100) comprises a semiconductor layer (100S) and a wiring layer (100T), the second substrate (200) comprises a semiconductor layer (200S) and a wiring layer (200T), and the third substrate (300) comprises a semiconductor layer (300S) and a wiring layer (300T). In addition, the imaging device (1) further comprises a protective film (181), a color filter (182), and an on-chip lens (401). In addition, pixels (541A and 541B) are indicated in the drawing.

[0059] The semiconductor layer (100S) comprises a first semiconductor substrate (120), an insulating film (129), and a separation portion (171).

[0060] The first semiconductor substrate (120) is a semiconductor substrate on which a photoelectric conversion unit (101) is disposed. A charge transfer unit (102) and a charge retention unit (103) are also disposed on the first semiconductor substrate (120) of the drawing. The photoelectric conversion unit (101A and 101B), the charge transfer unit (102A and 102B), and the charge retention unit (103A and 103B) are described in the drawing. The first semiconductor substrate (120) can be composed of, for example, silicon (Si). Additionally, a wiring layer (100T) is disposed on the surface side of the first semiconductor substrate (120).

[0061] The insulating film (129) is a film that insulates the surface side of the first semiconductor substrate (120). This insulating film (129) can be composed of silicon oxide (SiO2) or silicon nitride (SiN).

[0062] The separating part (171) is positioned at the boundary of the pixel (541) to separate the pixel (541). In this drawing, an example is described in which pixels (541A and 541B) are separated by the separating part (171). Additionally, embedded electrodes (161 and 162) are also positioned at the boundary of the pixel (541) in this drawing.

[0063] The wiring layer (100T) is provided with an insulating layer (141). The insulating layer (141) insulates a gate electrode or a through electrode (251), etc., disposed on the surface side of the first semiconductor substrate (120). This insulating layer (141) can be composed of, for example, SiO2. In addition, through electrodes (251 and 252), which will be described later, are disposed in the wiring layer (100T).

[0064] The semiconductor layer (200S) comprises a second semiconductor substrate (220) and an insulating film (229). Additionally, a through hole (262) is disposed in the semiconductor layer (200S).

[0065] The second semiconductor substrate (220) is a semiconductor substrate on which a pixel circuit (210) is placed. In the second semiconductor substrate (220) of the drawing, a reset transistor (211) and an amplification transistor (213) of the pixel circuit (210) are described. The second semiconductor substrate (220) can be composed of Si, just like the first semiconductor substrate (120). The through hole (262) is a through hole formed in the second semiconductor substrate (220) to allow the through electrode (251), etc., described later to pass through. An insulating layer (241) is placed in this through hole (262).

[0066] The wiring layer (200T) comprises an insulating layer (241), wiring (242), via plugs (243), through electrodes (251 to 253), and contact portions (201 and 202). The wiring (242) is a conductor that transmits electrical signals, etc. to an element disposed on the second semiconductor substrate (220). This wiring (242) can be composed of a metal such as copper (Cu). The insulating layer (241) insulates the wiring (242), etc. This insulating layer (241) can be composed of SiO2, etc., similar to the insulating layer (141). The wiring (242) and the insulating layer (241) can be composed of multiple layers. The drawing describes, as an example, wiring (242) and insulating layer (241) composed of two layers. Wiring (242) placed on different layers can be connected to each other by via plugs (243). These via plugs (243) can be made of a columnar metal, for example, columnar Cu.

[0067] The through electrodes (251 and 252) are main electrodes that connect the wiring (242) and a member disposed on the surface side of the first semiconductor substrate (120). The through electrodes (251 and 252) are each connected to the embedded electrodes (161 and 162). These through electrodes (252), etc., can be made of a metal such as tungsten and can be disposed in the through hole (262).

[0068] The through electrode (251) connects the first semiconductor substrate (120) and another semiconductor substrate in order to have a common reference potential. The through electrode (252) transfers the charge of the charge holding portion (103) of the first semiconductor substrate (120) to the second semiconductor substrate (220). These through electrodes (251 and 252) can be constructed, for example, of columnar tungsten. Additionally, the through electrode (251) of the same drawing is connected to the third substrate (300) through wiring (242), via plugs (243), and contact portions (201).

[0069] As described above, the contact portions (201 and 202) are respectively connected to the contact portions (301 and 303) of the third substrate (300). The contact portion (201) is connected to the through electrode (251) and transmits a reference potential. The contact portion (202) is used for transmitting signals, etc.

[0070] The semiconductor layer (300S) comprises a third semiconductor substrate (320). The image signal processing unit (560) (not shown) described above is disposed on this third semiconductor substrate (320). Additionally, a well region is formed on the third semiconductor substrate (320). A semiconductor region (321) is disposed in this well region. The semiconductor region (321) is composed of a relatively high impurity concentration, and a contact plug (344) is connected thereto.

[0071] The wiring layer (300T) comprises an insulating layer (341), wiring (342), via plug (343), contact plug (344), and contact portions (301 and 302). Since these configurations are similar to the insulating layer (241), wiring (242), via plug (243), contact plug (244), and contact portions (301 and 302), the description is omitted.

[0072] The protective film (181) protects the back side of the first semiconductor substrate (120). This protective film (181) can be composed of, for example, SiO2. The color filter (182) is an optical filter that is placed at each pixel (541) and transmits light of a predetermined wavelength among the incident light. The on-chip lens (401) is a lens that is placed at each pixel (541) and collects the incident light to the photoelectric conversion unit (101).

[0073] Additionally, in this embodiment, the first substrate (100) and the second substrate (200) are connected through a through electrode, and the second substrate (200) and the third substrate (300) are connected through a contact portion, but this example is not limited thereto. For example, the first substrate (100) and the second substrate (200) may also be connected through a contact portion.

[0074] FIG. 6 is a cross-sectional view illustrating another configuration example of an imaging device according to an embodiment of the present disclosure. In the second substrate (200) of the same figure, an insulating layer (241) is formed on the back side of the semiconductor layer (200S), and a contact portion (249) is disposed therein. This contact portion (249) is connected to a contact portion (149) disposed on the first substrate (100) of the same figure.

[0075] FIG. 7 is a cross-sectional view illustrating another configuration example of an imaging device according to an embodiment of the present disclosure. The second substrate (200) of the same figure corresponds to the second substrate (200) of FIG. 6 with the top and bottom reversed.

[0076] Additionally, FIGS. 3, 5 to 7 illustrate an example in which an electrical connection portion between the first substrate (100) and the second substrate (200), or an electrical connection portion between the second substrate (200) and the third substrate (300), is positioned in a location that overlaps with the pixel array portion (540). A configuration may also be adopted in which the electrical connection portion between the first substrate (100) and the second substrate (200), or an electrical connection portion between the second substrate (200) and the third substrate (300), is positioned in an outer region of the pixel array portion (540). Specifically, in FIGS. 3, 5 to 7, the contact portion (201, 202, 301 and 302), which is the electrical connection portion between the second substrate (200) and the third substrate (300), may be positioned in an outer region of the pixel array portion (540). Likewise, in FIGS. 6 and 7, the contact portion (149 and 249), which is an electrical connection portion between the first substrate (100) and the second substrate (200), may be placed in an outer region of the pixel array portion (540).

[0077] [Composition of Pixel Sharing Unit]

[0078] FIG. 8 is a drawing illustrating an example of the configuration of a pixel sharing unit according to a first embodiment of the present disclosure. FIG. 8 is a plan view illustrating an example of the configuration of a pixel sharing unit (539) in a pixel array section (540). FIG. 8 is also a drawing illustrating the configuration of a first substrate (100) and a second substrate (200) viewed from the side of the second substrate (200).

[0079] In the drawing, the rectangular area on the white background represents an area of ​​the first semiconductor substrate (120) corresponding to the area of ​​the pixel (541). Additionally, the area with dot hatching represents a semiconductor area formed on the first semiconductor substrate (120). Additionally, the slanted rectangular area represents the gate electrode of the charge transfer unit (102). The circle on the white background represents the through electrodes (251 to 253). The dotted rectangle represents the elements of the pixel circuit (210) (reset transistor (211), capacitance switching transistor (212), amplification transistor (213), and selection transistor (214)). Additionally, the dotted rectangle written on the boundary of the pixel (541) represents the area of ​​the pixel sharing unit (539). The two-dot dashed rectangle represents the area of ​​the pixel group (538) described later.

[0080] A separation portion (171) is disposed at the boundary of the pixel (541). The separation portion (171) is configured to surround the pixel (541). Additionally, a buried electrode (161 and 162) is also disposed on the first semiconductor substrate (120) at the boundary of the pixel (541). The buried electrode (161) is connected to the well region of the first semiconductor substrate (120). Additionally, a semiconductor region (123) is disposed on the first semiconductor substrate (120) of the pixel (541) adjacent to the buried electrode (161) of the same drawing. The buried electrode (161) is connected to the well region through the semiconductor region (123). The buried electrode (162) is connected to the semiconductor region (122) constituting the charge holding portion (103). The embedded electrodes (161 and 162) of the same drawing are embedded and disposed in the first semiconductor substrate (120) adjacent to the corner portions of the four pixels (541).

[0081] As described above, pixels (541A, 541B, 541C, and 541D) are arranged on the first substrate (100). As shown in the drawing, pixels (541A, 541B, 541C, and 541D) are arranged in 2 rows and 2 columns, and charge holding units (103A, 103B, 103C, and 103D) are arranged near the center of them. Adjacent to these charge holding units (103A, 103B, 103C, and 103D), charge transfer units (102A, 102B, 102C, and 102D) and photoelectric conversion units (101A, 101B, 101C, and 101D) are respectively arranged. Additionally, the configuration of the pixel sharing unit (539) is not limited to this example. For example, the pixel sharing unit (539) may be configured to have a number of pixels (541) other than 4.

[0082] The embedded electrode (162) is placed in the center of the 2 rows and 2 columns of pixels (541A, 541B, 541C, and 541D). The pixels (541A, 541B, 541C, and 541D) and the pixel circuit (210) of the second semiconductor substrate (220) constitute a pixel sharing unit (539). In other words, in the pixel sharing unit (539) of the same drawing, the pixels (541A, 541B, 541C, and 541D) are commonly connected to the embedded electrode (162) and the pixel circuit (210). Such pixel sharing units (539) are arranged in a two-dimensional matrix shape.

[0083] Meanwhile, the pixel group (538) also has four pixels (541) arranged in two rows and two columns. The pixels (541) constituting the pixel group (538) correspond to pixels located at positions offset by one pixel in the up, down, left, and right directions of the drawing relative to the pixel sharing unit (539). The embedded electrode (161) is placed in the center of the four pixels (541) arranged in two rows and two columns constituting the pixel group (538). These four pixels (541) are connected in common to the embedded electrode (161). Furthermore, the configuration of the pixel group (538) is not limited to this example. For example, the pixel group (538) may be configured to have a number of pixels (541) other than four.

[0084] [Composition of pixels]

[0085] FIG. 9 is a drawing illustrating an example of a pixel configuration according to a first embodiment of the present disclosure. FIG. 9 is a schematic cross-sectional view illustrating an example of a pixel configuration (541). FIG. 8 corresponds to a cross-sectional view along line a-a'. FIG. 9 illustrates pixels (541A and 541B). FIG. 9 also omits the description of a third semiconductor substrate (320). FIG. 9

[0086] As described above, a photoelectric conversion unit (101), a charge transfer unit (102), and a charge retention unit (103) are disposed on the first semiconductor substrate (120). In this drawing, photoelectric conversion units (101A and 101B), charge transfer units (102A and 102B), and charge retention units (103A and 103B) are described. These devices are disposed in a well region formed on the first semiconductor substrate (120). For convenience, the first semiconductor substrate (120) in this drawing is assumed to constitute a p-type well region. By disposing of an n-type semiconductor region in this p-type well region, a device (a diffusion layer) can be formed.

[0087] The area of ​​dot hatching described on the first semiconductor substrate (120) of the same drawing represents an n-type semiconductor region. The photoelectric conversion unit (101A) is composed of the n-type semiconductor region (121A). Specifically, the photodiode composed of a pn junction formed at the interface between the n-type semiconductor region (121A) and the surrounding p-type well region corresponds to the photoelectric conversion unit (101A). As shown in the same drawing, the photoelectric conversion unit (101A) is formed on the back side of the first semiconductor substrate (120). Additionally, a part of the photoelectric conversion unit (101A) extends near the surface side of the first semiconductor substrate (120). Furthermore, the photoelectric conversion unit (101B) is also configured in the same way as the photoelectric conversion unit (101A).

[0088] The charge holding portions (103A and 103B) are each composed of n-type semiconductor regions (122A and 122B). These n-type semiconductor regions (122A and 122B) constitute the FD described above. Additionally, the semiconductor regions (122A and 122B) are arranged adjacent to the buried electrode (162).

[0089] The charge transfer unit (102A) is composed of semiconductor regions (121A and 122A) and a gate electrode (131A). The n-type semiconductor regions (121A and 122A) correspond to the source region and drain region of the charge transfer unit (102A). The charge transfer unit (102A) of the same figure is composed of a planar or horizontal MOS transistor in which a channel is formed along the surface of a semiconductor substrate. The gate electrode (131A) is disposed on the surface side of the first semiconductor substrate (120). In addition, the gate electrode (131A) of the same figure has a side wall. When a driving voltage is applied to this gate electrode (131A), a channel is formed in the well region adjacent to the gate electrode (131A), and the n-type semiconductor regions (121A and 122A) become conductive. That is, the photoelectric conversion unit (101A) and the charge holding unit (103A) are electrically connected, so that the charge of the photoelectric conversion unit (101A) is transferred to the charge holding unit (103A).

[0090] Similar to the charge transfer section (102A), the charge transfer section (102B) is composed of semiconductor regions (121B and 122B) and a gate electrode (131B). Additionally, the gate electrodes (131A and 131B) may be composed of polycrystalline silicon with impurities implanted. Furthermore, the insulating film (129) between the gate electrodes (131A and 131B) and the first semiconductor substrate (120) constitutes a gate insulating film.

[0091] A through electrode (253) is connected to the gate electrode (131A) of the charge transfer unit (102A). The gate electrode (131A) of the charge transfer unit (102A) is connected to a signal line (TG1) through the through electrode (253). Likewise, the gate electrode (131B) of the charge transfer unit (102B) is also connected to a signal line (TG2) through the through electrode (253).

[0092] Additionally, semiconductor regions (123A and 123B) are disposed on the first semiconductor substrate (120). These semiconductor regions (123A and 123B) are semiconductor regions disposed in the well region of the first semiconductor substrate (120) and are semiconductor regions composed of a relatively high impurity concentration of the same conductivity type as the well region. Additionally, the semiconductor regions (123A and 123B) are disposed adjacent to the buried electrode (161). Additionally, the semiconductor region (123) is an example of a high-concentration impurity region as described in the claims.

[0093] The separation portion (171) is positioned at the boundary of the pixel (541) to separate the pixel (541). This separation portion (171) separates adjacent pixels (541) on the first semiconductor substrate (120). The separation portion (171) can be configured, for example, by embedding an insulating material such as SiO2 in a groove portion (179) that penetrates from the surface side to the back side of the first semiconductor substrate (120). Additionally, a light-blocking member that blocks incident light may be placed in the separation portion (171).

[0094] The buried electrodes (161 and 162) are electrodes placed at the boundary of the pixel (541). Additionally, the buried electrodes (161 and 162) are placed on the surface side of the first semiconductor substrate (120) at a position overlapping with the separation portion (171). The buried electrodes (161 and 162) can be composed, for example, of polycrystalline silicon with impurities implanted.

[0095] As described above, the buried electrode (161) is positioned adjacent to the semiconductor region (123) (semiconductor regions (123A and 123B)) and connected to the well region of the first semiconductor substrate (120). A through electrode (251) is connected to the buried electrode (161) to supply a reference potential (well potential). Additionally, the semiconductor region (123) is a semiconductor region positioned to make the connection between the buried electrode (161) and the first semiconductor substrate (120), etc., an ohmic connection, and is a semiconductor region composed of a relatively high impurity concentration of the same conductivity type as the well region.

[0096] The embedded electrode (162) is positioned adjacent to the semiconductor region (122) (semiconductor regions (122A and 122B)) and connected to the charge holding portion (103) (charge holding portions (103A and 103B)). A through electrode (252) is connected to the embedded electrode (162). Through this through electrode (252), the charge holding portion (103) and the pixel circuit (210) are connected. Additionally, the through electrodes (251 and 252) are examples of the connection portions described in the claims.

[0097] A pixel circuit (210) is disposed on the second semiconductor substrate (220). A reset transistor (211) and an amplifier transistor (213) are described in the drawing. These reset transistors (211) and amplifier transistors (213) are disposed in the well region of the second semiconductor substrate (220). Similar to the first semiconductor substrate (120), a p-type well region is formed in the second semiconductor substrate (220). For convenience, the second semiconductor substrate (220) in the drawing is assumed to constitute a p-type well region. The reset transistor (211) is composed of an n-type semiconductor region (221 and 222) and a gate electrode (231). The gate electrode (231) of the reset transistor (211) is connected to a signal line (RST) through a contact plug (244). Additionally, the amplifying transistor (213) is composed of n-type semiconductor regions (223 and 224) and a gate electrode (232). The gate electrode (232) of the amplifying transistor (213) is connected to a through electrode (252) through a contact plug (244) and wiring (242). That is, the gate electrode (232) of the amplifying transistor (213) is connected to charge holding portions (103A and 103B) through a contact plug (244), wiring (242), through electrode (252), and buried electrode (162).

[0098] A second semiconductor substrate (220) has semiconductor regions (225A and 225B) composed of a relatively high concentration of p-type impurities. These p-type semiconductor regions (225A and 225B) are connected to a through electrode (251) through a contact plug (244) and wiring (242). By doing so, the well region of the second semiconductor substrate (220) is connected to the well region of the first semiconductor substrate (120). A common well potential is supplied to the first semiconductor substrate (120) and the second semiconductor substrate (220). Additionally, the through electrode (251) is also connected to a ground wire (Vss) of a third semiconductor substrate (320) (not shown) through wiring (242) and a contact plug (244). The ground potential of the third semiconductor substrate (320) is supplied to the through electrode (251) as a reference potential (well potential). In addition, a fixed potential other than the ground potential can be applied to the reference potential.

[0099] A buried electrode (161) is placed at the boundary of a pixel (541) and connected to a well region of the first semiconductor substrate (120) of the pixel (541). By supplying a reference potential (well potential) to this buried electrode (161), a well potential can be supplied to the first semiconductor substrate (120) of the pixel (541). The semiconductor region (123) for obtaining an ohmic connection can be configured as a narrow exclusive area adjacent to the buried electrode (161). Additionally, by connecting the buried electrode (161) to a plurality of pixels (541) in common, the through electrode (251) can be shared among a plurality of pixels (541). By doing so, the number of through electrodes (251) can be reduced. Additionally, the opening area of ​​the through hole (262) of the second semiconductor substrate (220) where the through electrode (251) is placed may be reduced, and the arrangement of the pixel circuit (210) in the second semiconductor substrate (220) may be facilitated.

[0100] Meanwhile, if the embedded electrode (161) is not used, it is necessary to supply a well potential by connecting a through electrode (251) to the first semiconductor substrate (120) of the pixel (541). Specifically, the through electrode (251) is connected to the semiconductor region (123). In this case, it is necessary to place a relatively large semiconductor region (123). This is to reduce the occurrence of problems caused by misalignment of the through electrode (251) during the manufacturing process. Because of this, the area allocated to the photoelectric conversion unit (101), etc., in the pixel (541) is reduced.

[0101] Additionally, by placing the embedded electrode (162) at the boundary of the pixel (541) and connecting it to the charge holding portion (103) of the first semiconductor substrate (120) of the pixel (541), the area of ​​the semiconductor region (122) constituting the charge holding portion (103) can be reduced, similar to the semiconductor region (123) described above. Furthermore, by connecting the embedded electrode (162) to a plurality of pixels (541) in common, the through electrode (252) can be shared among a plurality of pixels (541). By doing so, the number of through electrodes (252) can be reduced, and the opening area of ​​the through hole (262) can be reduced.

[0102] In this way, the embedded electrode (162) is placed at a position overlapping the separation portion (171) of the boundary of the pixel (541) and connected to the first semiconductor substrate (120) of the pixel (541). The through electrode (251), etc., which was connected to the first semiconductor substrate (120) inside the pixel (541), can be moved to the outside of the pixel (541), thereby reducing the exclusive area of ​​the pixel (541).

[0103] Additionally, the embedded electrodes (161 and 162) are configured to be embedded in a groove (179) formed in the first semiconductor substrate (120) at the boundary of the pixel (541). By doing so, the embedded electrodes (161 and 162) are configured to be connected to the side of the first semiconductor substrate (120) adjacent to the groove (179). By arranging the connection surface between the embedded electrodes (161 and 162) and the first semiconductor substrate (120) in a direction perpendicular to the surface of the first semiconductor substrate (120), the exclusive area of ​​the embedded electrodes (161 and 162) can be reduced. This makes it possible to reduce the exclusive area of ​​the pixel (541). The depth of embedding ("D" in the drawing) of the embedded electrodes (161), etc., into the first semiconductor substrate (120) is suitable to be 50 nm or more. This is because the connection surface between the buried electrodes (161 and 162) and the first semiconductor substrate (120) can be widened, thereby reducing the connection resistance.

[0104] In contrast, when electrically connecting to the first semiconductor substrate (120) through an electrode placed on the surface of the first semiconductor substrate (120), it is necessary to place an electrode with a relatively large area as shown in FIG. 21, which will be described later. This is to reduce the connection resistance between the electrode and the semiconductor region. Because of this, the area of ​​the pixel (541) increases.

[0105] In addition, by configuring the buried electrode (162) in a narrow size while placing it at the boundary of the pixel (541), the distance between it and the gate electrode (131) ("W" in the drawing) can be increased. By doing so, the parasitic capacitance between the gate electrode (131) of the charge transfer unit (102) and the charge holding unit (103) can be reduced. The charge transfer efficiency of the charge transfer unit (102) can be improved. Furthermore, the height of the gate electrode (131) ("H2" in the drawing) is suitable to be less than or equal to the height of the buried electrodes (161 and 162) ("H1" in the drawing). This is because the parasitic capacitance between the gate electrode (131) and the buried electrodes (161 and 162) can be reduced.

[0106] [Method for manufacturing an image sensor]

[0107] FIGS. 10a to 10i are drawings illustrating an example of a method for manufacturing an imaging element according to a first embodiment of the present disclosure. FIGS. 10a-10i are drawings illustrating an example of a manufacturing process of an imaging device (1), and an example of a manufacturing process regarding a region of a first semiconductor substrate (120).

[0108] First, a well region and a semiconductor region (121) (not shown) are formed on the first semiconductor substrate (120). Next, a resist (601) is placed on the surface side of the first semiconductor substrate (120). An opening (602) is placed in the resist (601) at the boundary portion of the pixel (541) (Fig. 10a).

[0109] Next, the surface side of the first semiconductor substrate (120) is etched using a resist (601) as a mask to form a groove (179) (Fig. 10b). This can be done, for example, by dry etching.

[0110] Next, a separation portion (171) is placed in the groove portion (179) (Fig. 10c). This can be done, for example, by forming a film of SiO2, which is the material of the separation portion (171), on the surface side of the first semiconductor substrate (120) including the groove portion (179) using CVD (Chemical Vapor Deposition) and grinding it to a desired thickness. Chemical Mechanical Polishing (CMP) can be used for grinding the SiO2 film.

[0111] Next, the separation portion (171) is ground to expose the side near the surface of the first semiconductor substrate (120) in the groove portion (179) (Fig. 10d). This can be done by etching the separation portion (171) using a resist (601) as a mask. For this etching, for example, anisotropic dry etching can be applied.

[0112] Next, embedded electrodes (161 and 162) are placed in the groove (179) (Fig. 10e). This can be done, for example, by placing polycrystalline silicon, which is the material of the embedded electrodes (161 and 162), into the groove (179) by CVD or the like. Next, the resist (601) is removed (Fig. 10f).

[0113] Next, a gate insulating film, a gate electrode (131), and a side wall are formed (Fig. 10g). Next, a semiconductor region (123), etc., are formed (Fig. 10h). This can be done by ion implantation. Next, an insulating film (129) is formed on the surface side of the first semiconductor substrate (120). Next, an insulating layer (141) is placed (Fig. 10i). This can be done, for example, by forming a film of SiO2, which is the material of the insulating layer (141), by CVD. By the above process, the first semiconductor substrate (120) portion of the imaging device (1) can be manufactured.

[0114] Additionally, the configuration of the separation portion (171) is not limited to this example. For example, the separation portion (171) may be configured to be placed in a groove portion (179) formed on the back side of the first semiconductor substrate (120). Additionally, the separation portion (171) may be configured to a depth reaching from the surface side of the first semiconductor substrate (120) to the vicinity of the back side without penetrating the first semiconductor substrate (120).

[0115] [Other configurations of the pixel sharing unit]

[0116] FIG. 11 is a drawing illustrating another configuration example of a pixel sharing unit according to a first embodiment of the present disclosure. Like FIG. 8, FIG. 8 is a plan view showing a configuration example of a pixel sharing unit (539). The pixel sharing unit (539) of FIG. 8 differs from the pixel sharing unit (539) of FIG. 8 in that a strip-shaped embedded electrode is disposed instead of an embedded electrode (161).

[0117] The embedded electrode (166) of the same drawing is an embedded electrode connected to the well region of the first semiconductor substrate (120). This embedded electrode (166) is configured in a strip shape and is an embedded electrode arranged along the side of a rectangular pixel (541) when viewed from a planar view. Additionally, the embedded electrode (166) of the same drawing is an example configured in a shape that extends in the horizontal direction of the same drawing. Furthermore, the embedded electrode (166) is connected to the well region through the semiconductor region (123). The semiconductor region (123) of the same drawing is configured in a strip shape along the embedded electrode (166). By arranging such a strip-shaped embedded electrode (166), the contact area between the embedded electrode (166) and the well region of the semiconductor substrate (110) can be widened, thereby reducing the contact resistance.

[0118] [Other configurations of buried electrodes]

[0119] FIGS. 12a and 12b are drawings illustrating other configuration examples of a buried electrode according to the first embodiment of the present disclosure. FIG. 12a is a cross-sectional view showing an configuration example of a buried electrode (166), and is a cross-sectional view along the line d-d' of FIG. 11. The buried electrode (166) in the said drawing is an example configured to have a width approximately equal to that of the separating part (171).

[0120] FIG. 12b is a drawing showing an example of a buried electrode (166) configured with a width wider than that of the separation portion (171). The buried electrode (166) of the drawing is configured with a cross-section that is wider than that of the separation portion (171) on the surface of the semiconductor substrate (110). Additionally, the buried electrode (166) of the drawing is shown as an example configured with a width wider than that of the opening of the insulating film (129).

[0121] In addition, the method of manufacturing the imaging element is not limited to the method described in FIGS. 10a-10i. For example, after forming the insulating film (129) of FIG. 10i, a groove-shaped opening may be formed in the insulating film (129) adjacent to the separation part (171), and a polycrystalline silicon film may also be placed adjacent to the embedded electrode (161) of FIG. 10i. In addition, after FIG. 10d, the resist (601) may be peeled off to form the insulating film (129), and after removing the insulating film (129) inside the groove part (179) and the upper shoulder surface part by pattern etching, a polycrystalline silicon film may be formed, and the embedded electrode (166) may be formed by performing pattern etching. By applying such a manufacturing method, an embedded electrode such as the embedded electrode (166) described in FIG. 12b, in which the upper width is wider than the width of the separation part (171), can be formed.

[0122] FIG. 13 is a drawing illustrating another configuration example of a pixel sharing unit according to a first embodiment of the present disclosure. FIG. 13 is a plan view showing a configuration example of a pixel sharing unit (539) in which a strip-shaped embedded electrode (166) is arranged, similar to FIG. 11. The pixel sharing unit (539) of FIG. 13 differs from the pixel sharing unit (539) of FIG. 11 in that a pixel (541), configured in a rectangular shape, is arranged therein.

[0123] In addition, in the pixel array section (540) of the same drawing, pixels (541A and 541C) constitute phase difference pixels. These phase difference pixels can generate a phase difference signal for detecting an image plane phase difference by dividing the incident light from the subject and an image signal based on the incident light from the subject. When generating the phase difference signal, two image signals based on charges generated by the photoelectric conversion of the photoelectric conversion section of the pixels (541A and 541C) are output as phase difference signals. Meanwhile, when generating the image signal, the charges generated by the photoelectric conversion of the two photoelectric conversion sections are summed in the pixels, and an image signal generated based on the summed charges is output. Pixels (541B and 541D) also constitute phase difference pixels in the same way as pixels (541A and 541C).

[0124] Additionally, a gap is formed in the separation portion (171) between pixels (541A and 541C) and pixels (541B and 541D). An overflow path is formed in the portion of this gap.

[0125] Additionally, a common on-chip lens (401) for pupil splitting is placed in the pixels (541A and 541C) constituting the phase difference pixels. Likewise, a common on-chip lens (401) is also placed in the pixels (541B and 541D).

[0126] Additionally, the aforementioned pixels (541A and 541C) and pixels (541B and 541D) may be used as normal pixels that do not generate a phase difference signal. Furthermore, phase difference pixel and normal pixel functions may be assigned to each area of ​​the pixel array section (540). Specifically, some of the pixels (541A), etc. in the pixel array section (540) may be made to function as phase difference pixels, and other pixels (541A), etc. may be made to function as normal pixels. Additionally, in the imaging device (1), some or all of the pixels (541A), etc. may be made to function as phase difference pixels when detecting an upper surface phase difference, etc., and in other cases, the pixels (541A), etc. may be made to function as normal pixels.

[0127] In the drawing, the semiconductor region (122A to 122D) constituting the FD of the pixel (541A to 541D) is shown as an example in which it is configured in a shape that is elongated in the horizontal direction of the drawing compared to the semiconductor region (122A to 122D) of FIG. 8. Furthermore, the shape of the semiconductor region (122A to 122D) is not limited to this example. For example, it may be configured in a shape that is elongated in the vertical direction of the drawing or in a symmetrical shape similar to FIG. 8.

[0128] In this way, the imaging device (1) of the first embodiment of the present disclosure places an embedded electrode (161) at the boundary of the pixel (541). A reference potential is supplied to the first semiconductor substrate (120) through this embedded electrode (161). By doing so, the region related to the supply of the reference potential can be placed outside the pixel (541), thereby allowing the pixel (541) to be miniaturized.

[0129] (2. Second embodiment)

[0130] In the imaging device (1) of the first embodiment described above, an embedded electrode (161) was disposed in the separation portion (171) of the first semiconductor substrate (120). In contrast, the imaging device (1) of the second embodiment of the present disclosure differs from the first embodiment described above in that the embedded electrodes (161) are connected to each other.

[0131] [Composition of Pixel Sharing Unit]

[0132] FIG. 14 is a drawing illustrating an example of the configuration of a pixel sharing unit according to a second embodiment of the present disclosure. Like FIG. 8, FIG. 8 is a plan view showing an example of the configuration of a pixel sharing unit (539). The pixel sharing unit (539) of FIG. 8 differs from the pixel sharing unit (539) of FIG. 8 in that it is equipped with boundary wiring (163) that connects embedded electrodes (161) to each other.

[0133] The boundary wiring (163) is wiring connected to the embedded electrode (161) placed at the boundary of the pixel (541). The boundary wiring (163) in the drawing illustrates an example configured to be embedded in the first semiconductor substrate (120). Specifically, the boundary wiring (163) in the drawing is configured to be embedded in the separation portion (171). This boundary wiring (163) can be configured, for example, by polycrystalline silicon with impurities injected. By arranging the boundary wiring (163) to connect the embedded electrodes (161) to each other, the reference potential (well potential) of adjacent embedded electrodes (161) can be made common. The potential difference of the well potential between different pixels (541) can be reduced. In addition, by arranging the boundary wiring (163) to make the well potential of the pixel (541) common, the through electrode (251) can be reduced. Additionally, the drawing illustrates an example in which boundary wiring (163) is arranged between adjacent buried electrodes (161) in one direction (horizontal direction in the drawing).

[0134] Additionally, the boundary wiring (163) may be placed between the buried electrodes (162) to connect the buried electrodes (161). In this case, adjacent charge holding parts (103) are connected by the boundary wiring (163).

[0135] [Configuration of Boundary Wiring]

[0136] FIGS. 15a and 15b are drawings illustrating examples of the configuration of boundary wiring according to a second embodiment of the present disclosure. FIGS. 15a and 15b respectively show examples of the configuration of cross-sections of boundary wiring (163) along the b-b' and c-c' lines of FIG. 14. The boundary wiring (163) of FIG. 15a is connected to the side of the embedded electrode (161). FIG. 15b. In addition, the boundary wiring (163) of FIG. 15b is configured such that its upper surface is exposed to the surface side of the first semiconductor substrate (120). As shown in FIG. 15b, the boundary wiring (163) of FIG. 15b can be configured such that it is spaced apart from the area of ​​the first semiconductor substrate (120). The width of the separation portion (171) between the boundary wiring (163) and the first semiconductor substrate (120) ("W2" in FIG. 15b) can be 20 nm or more. Additionally, the penetrating electrode (251) may be placed on the boundary wiring (163). This is because the boundary wiring (163) is electrically connected to the embedded electrode (161).

[0137] [Method for manufacturing boundary wiring]

[0138] FIGS. 16a to 16e are drawings illustrating an example of a method for manufacturing a boundary wiring according to a second embodiment of the present disclosure. FIGS. 16a to 16e are drawings illustrating an example of a manufacturing process for a boundary wiring (163).

[0139] First, a separation portion (171) is formed on the first semiconductor substrate (120) (Fig. 16a). Next, a resist (603) is placed on the surface side of the first semiconductor substrate (120). An opening (604) is placed in the portion of the resist (603) where the boundary wiring (163) is placed (Fig. 16b). Next, the resist (603) is used as a mask to etch the separation portion (171) to form an opening (178) (Fig. 16c). This can be done, for example, by anisotropic dry etching. Next, a material film (605) of the boundary wiring (163) is placed on the surface side of the first semiconductor substrate (120) including the opening (178) (Fig. 16d). This can be done, for example, by forming a polycrystalline silicon film by CVD. Next, the material film (605) is etched to remove the material film (605) in the portion other than the opening (178) (Fig. 16e). By doing so, the boundary wiring (163) can be formed. After that, the resist (603) is removed.

[0140] [Other configurations of boundary wiring]

[0141] FIGS. 17a and 17b are drawings illustrating other configuration examples of boundary wiring according to a second embodiment of the present disclosure. FIGS. 17a and 17b are drawings illustrating configuration examples of boundary wiring (164). This boundary wiring (164) is wiring disposed adjacent to the surface of the first semiconductor substrate (120). FIG. 17a shows a configuration example of a cross-section of the boundary wiring (164) in a direction along the boundary of the pixel (541), and FIG. 17b shows a configuration example of a cross-section of the boundary wiring (164) in a direction perpendicular to the boundary of the pixel (541). The boundary wiring (164) of the same figure is connected to the upper surface of the embedded electrode (161) ( FIG. 17a). Additionally, the boundary wiring (163) of the same figure is configured in a shape such that its upper surface and side surface are exposed to the surface side of the first semiconductor substrate (120) ( FIG. 17b). Similar to the boundary wiring (163), the boundary wiring (164) of FIG. 17b can also be configured to be spaced apart from the area of ​​the first semiconductor substrate (120). The distance between the boundary wiring (164) and the first semiconductor substrate (120) can be 20 nm or more. Additionally, the through electrode (251) can be placed on the boundary wiring (163) instead of the embedded electrode (161).

[0142] [Other manufacturing methods for boundary wiring]

[0143] FIGS. 18a to 18g are drawings illustrating an example of another manufacturing method of boundary wiring according to a second embodiment of the present disclosure. FIGS. 18a to 18g are drawings illustrating an example of a manufacturing process of boundary wiring (164). Additionally, in each of FIGS. 18a to 18g, the left drawing shows a portion where the buried electrode (161) is not placed, and the right drawing shows a portion where the buried electrode (161) is placed.

[0144] First, a separation portion (171) is formed on the first semiconductor substrate (120) and a buried electrode (161) is placed (Fig. 18a). Next, an insulating film (129) is placed on the surface side of the first semiconductor substrate (120) (Fig. 18b). This can be done, for example, by thermal oxidation. Next, a resist (606) is placed on the surface side of the first semiconductor substrate (120). An opening (607) is placed in the portion of the resist (606) where the boundary wiring (164) is placed (Fig. 18c). Next, the resist (606) is used as a mask to etch the insulating film (129) and form an opening (608) in the area adjacent to the buried electrode (161) (Fig. 18d). This can be done, for example, by dry etching.

[0145] Next, the resist (606) is removed (Fig. 18e). Next, a material film (620) of the boundary wiring (164) is placed on the surface side of the first semiconductor substrate (120) including the opening (608) (Fig. 18f). This can be done, for example, by forming a polycrystalline silicon film by CVD. Next, the material film (620) is etched to remove the material film (620) other than the boundary of the pixel (541) (Fig. 18g). By doing so, the boundary wiring (164) can be formed.

[0146] [Other configurations of the pixel sharing unit]

[0147] FIG. 19 is a drawing illustrating another configuration example of a pixel sharing unit according to a second embodiment of the present disclosure. Like FIG. 14, FIG. 19 is a plan view showing a configuration example of a pixel sharing unit (539). FIG. 19 is different from FIG. 14's pixel sharing unit (539) in that the boundary wiring (163) is arranged in a mesh shape.

[0148] The boundary wiring (163) of the same drawing connects the embedded electrodes (161) to each other in the vertical and horizontal directions of the same drawing. By doing so, the wiring supplying the well potential in the first semiconductor substrate (120) can be made even lower resistance, thereby reducing the potential difference of the well potential between different pixels (541).

[0149] The configuration of the imaging device (1) other than that is the same as the configuration of the imaging device (1) in the first embodiment of the present disclosure, so the description is omitted.

[0150] In this way, the imaging device (1) of the second embodiment of the present disclosure connects adjacent embedded electrodes (161) to each other by boundary wiring (163), etc. By doing so, the potential difference of the well potential between other pixels (541) can be reduced.

[0151] (3. Third Embodiment)

[0152] In the imaging device (1) of the first embodiment described above, a through electrode (251) was arranged for each pixel group (538). In contrast, in the third embodiment of the present disclosure, an example is described in which the through electrode (251) is reduced by arranging boundary wiring (163), etc.

[0153] [Composition of the pixel array section]

[0154] FIGS. 20a to 20c are drawings illustrating an example of the configuration of a pixel array section according to a third embodiment of the present disclosure. FIGS. 20a to 20c are drawings showing an example of the configuration of a pixel array section (540). In addition, in FIGS. 20a to 20c, reference numerals are omitted.

[0155] FIG. 20a is a drawing showing an example in which through electrodes (251 and 252) are placed on all buried electrodes (161 and 162), similar to FIG. 8. FIG. 20b is a drawing showing an example in which boundary wiring (163) is placed between adjacent buried electrodes (161) in the horizontal direction of the drawing, and through electrodes (251) are placed alternately on adjacent buried electrodes (161). FIG. 20c is a drawing showing an example in which through electrodes (251) are omitted along with the placement of boundary wiring (163).

[0156] In addition, in the pixel array section (540) of FIG. 20c, a through electrode (251) that supplies a reference potential is placed outside the pixel array section (540), as described later in FIG. 30. The through electrode (251) placed outside the pixel array section (540) can, for example, be connected to a well region that extends to an area outside the pixel array section (540). In addition, the through electrode (251) can be connected to a buried electrode (161) of the pixel array section (540) and also connected to a boundary wiring (163) that extends to an area outside the pixel array section (540). In this way, a reference potential (well potential) can be supplied to the pixel (541) even when the through electrode (251) is not placed in the pixel array section (540).

[0157] FIG. 21 is a drawing illustrating an example of the configuration of a pixel array portion according to a third embodiment of the present disclosure. This drawing illustrates an example in which electrodes (661 and 662) adjacent to the surface of the first semiconductor substrate (120) are used instead of embedded electrodes (161 and 162). This drawing illustrates a comparative example of an embodiment of the present disclosure. The electrodes (661 and 662) are configured in a shape that is not embedded in the first semiconductor substrate (120) and are bonded to a semiconductor region on the surface of the first semiconductor substrate (120). In order to reduce the connection resistance between the electrodes and the semiconductor region, the electrodes (661 and 662) need to be configured with a larger area than the embedded electrodes (161 and 162).

[0158] In each of the cases of FIGS. 20a to 20c and FIGS. 21, the number of connecting parts, such as through electrodes (251), is compared.

[0159] [Comparison Results]

[0160] FIG. 22 is a drawing illustrating the comparison results of a pixel array section according to a third embodiment of the present disclosure. In the same figure, Comparative Example 1, Application Example 1, Application Example 2, and Application Example 3 represent examples of the pixel array section (540) of FIG. 21, FIG. 20a, FIG. 20b, and FIG. 20c, respectively. Additionally, the “charge holding section shared pixel” in the same figure represents the number of pixels of a charge holding section (103) that are commonly connected by an embedded electrode (162). The “pixel circuit shared unit” represents the number of pixels per pixel circuit (210). The “connection section” in the same figure represents the number of connection sections connecting the first semiconductor substrate (120) and the second semiconductor substrate (220) in the pixel array section (540). Specifically, it represents the number of through electrodes (251 to 253). The “charge transfer section,” “charge holding section,” and “well region” of the drawing represent the number of connection sections of the charge transfer section (102) (gate electrode (131) of the charge transfer section), the charge holding section (103), and the well region (semiconductor region (123)), respectively. The “total” of the drawing represents the total number of connection sections of the charge transfer section (102), the charge holding section (103), and the well region.

[0161] The “boundary wiring” in the drawing indicates the presence or absence of the boundary wiring (163), etc. The “well contact” in the drawing indicates the location where the well contact is placed. The FD capacitance in the drawing indicates the capacitance (parasitic capacitance) between the gate electrode (131) and the charge holding portion (103).

[0162] In the four examples of the same drawing, the "charge holding part shared pixel" and the "pixel circuit shared unit" are 4 pixels, and the "charge transmission part" and the "charge holding part" of the "connection part" are 4 and 1, respectively. In any example, the pixel sharing unit (539) is composed of 4 pixels (541) and 1 pixel circuit (210).

[0163] In Comparative Example 1 and Application Example 1, the "well area" of the "connection part" becomes 1. This is because a through electrode (251) is placed for each buried electrode (161). In contrast, in Application Example 2, the "well area" of the "connection part" becomes 0.5. This is because the through electrode (251) is shared among two pixel groups (538). Also, in Application Example 3, the "well area" of the "connection part" becomes 0. The "total" of the "connection part" in Comparative Example 1, Application Example 1, Application Example 2, and Application Example 3 becomes 6, 6, 5.5, and 5, respectively. Regarding the "well contact," Application Example 3 is outside the pixel, and the others are inside the pixel. As described above, in Application Example 3, where the well contact (through electrode (251)) is omitted, the well contact is placed outside the pixel array portion (540). In the item of "FD capacity," Comparative Example 1 has a higher value than Application Examples 1 to 3. This is because the distance between the gate electrode (131) and the electrodes (661 and 662) is short.

[0164] In this way, the number of connection parts can be reduced in the application example where boundary wiring (163 and 164) is arranged.

[0165] (4. Fourth embodiment)

[0166] In the third embodiment described above, a comparison was made for an example having a pixel sharing unit (539) having four pixels (541). In contrast, in the fourth embodiment of the present disclosure, an example having a pixel sharing unit (539) having eight pixels (541) is described.

[0167] The pixel sharing unit (539) of the same drawing has two sets of four pixels (541) that share the embedded electrode (162). The pixel sharing unit (539) has a total of eight pixels (541).

[0168] [Composition of the pixel array section]

[0169] FIGS. 23a to 23c are drawings illustrating an example of the configuration of a pixel array section according to a fourth embodiment of the present disclosure. FIGS. 23a to 23c are drawings illustrating an example of the configuration of a pixel array section (540), similar to FIGS. 20a to 20c. The pixel sharing unit (539) of FIGS. 23a to 23c differs from the pixel sharing unit (539) of FIGS. 20a to 20c in that it has eight pixels (541).

[0170] FIG. 23a is a drawing showing an example in which through electrodes (251), etc. are disposed on all buried electrodes (161 and 162), similar to FIG. 20a. Through electrodes (252) are disposed on each of the two buried electrodes (162) of the pixel sharing unit (539). These through electrodes (252) are connected in common to the wiring (242) of the second semiconductor substrate (220) and connected to the pixel circuit (210). FIG. 23b is a drawing showing an example in which boundary wiring (163) is disposed between adjacent buried electrodes (161) in the horizontal direction of the same figure, and the two buried electrodes (162) of the pixel sharing unit (539) are connected by boundary wiring (163), etc. Additionally, FIG. 23b describes an example in which through electrodes (251) are connected to boundary wiring (163), etc. FIG. 23c is a drawing showing an example in which the penetrating electrode (251) is also omitted for the example of FIG. 23b.

[0171] [Comparison Results]

[0172] FIG. 24 is a drawing illustrating the comparison results of a pixel array section according to a fourth embodiment of the present disclosure. In the drawing, Comparative Example 2 assumes an example in which a pixel sharing unit (539) has eight pixels (541) in a pixel array section (540) having a pixel (541) of FIG. 21. Application Example 4 represents an example in the case of a pixel array section (540) of FIG. 23a. Application Examples 5 and 6 assume examples in which a pixel sharing unit (539) has eight pixels (541) in a pixel array section (540) of FIG. 20b and FIG. 15c, respectively. Application Examples 7 and 8 represent examples in the case of a pixel array section (540) of FIG. 23b and FIG. 23c, respectively.

[0173] In the six examples of the same drawing, the "charge holding part shared pixel" and the "pixel circuit sharing unit" each have 4 pixels and 2×4 pixels, and the "charge transmission part" of the "connection part" has 8. In any example, the pixel sharing unit (539) is composed of 8 pixels (541) and 1 pixel circuit (210).

[0174] In Comparative Example 2 and Application Example 4, the "charge holding portion" and "well region" of the "connection portion" become 2. This is because a penetrating electrode (251) is disposed for each buried electrode (161), and a penetrating electrode (252) is disposed for each buried electrode (162). In Comparative Example 2 and Application Example 4, the "total" of the "connection portion" becomes 12.

[0175] In Application Examples 5 and 6, just like in Application Example 4, the "charge holding portion" of the "connection portion" becomes 2. Meanwhile, in Application Example 5, the "well area" of the "connection portion" becomes 1. This is because the through electrode (251) is shared between two pixel groups (538). Also, in Application Example 6, the "well area" of the "connection portion" becomes 0. The "total" of the "connection portion" in Application Examples 5 and 6 becomes 11 and 10, respectively.

[0176] In Application Examples 7 and 8, the "charge holding portion" of the "connection portion" becomes 1. This is because the penetrating electrode (252) is shared between the two embedded electrodes (162). Also, in Application Examples 7 and 8, just like in Application Examples 5 and 6, the "well region" of the "connection portion" becomes 1 and 0, respectively. The "total" of the "connection portion" in Application Examples 7 and 8 becomes 10 and 9, respectively.

[0177] In Comparative Example 2 and Application Example 4, the "boundary wiring" is "none," while in other cases, the "boundary wiring" is "present." Additionally, in Application Example 6 and Application Example 8, where the through electrode (251) is omitted, the "well contact" is "outside the pixel," while in other cases, the "well contact" is "inside the pixel." In the item for "FD capacitance," Comparative Example 1 has a higher value than Application Examples 4 to 8. This is because, as in Comparative Example 1, the distance between the gate electrode (131) and the electrodes (661 and 662) is short.

[0178] In this way, the number of connection parts can be further reduced in an application example in which the boundary wiring (163 and 164) is connected to the buried electrodes (161 and 162).

[0179] (5. Fifth Embodiment)

[0180] In the above-described fourth embodiment, the embedded electrode (162) connected to the charge holding portion (103) was shared among four pixels (541). In contrast, in the fifth embodiment of the present disclosure, an example is described in which the embedded electrode (162) connected to the charge holding portion (103) is shared among two pixels (541).

[0181] [Composition of the pixel array section]

[0182] FIGS. 25a to 25e are drawings illustrating an example of the configuration of a pixel array section according to a fifth embodiment of the present disclosure. FIGS. 25a to 25e are drawings illustrating an example of the configuration of a pixel array section (540), similar to FIGS. 23a to 23c. The pixel array section (540) of FIGS. 25a to 25e differs from the pixel array section (540) of FIGS. 23a to 23c in that the embedded electrodes (161 and 162) are shared among two pixels (541), and the pixel sharing unit (539) has six pixels (541).

[0183] The pixel sharing unit (539) of the same drawing has three sets of two pixels (541) that share the embedded electrode (162). The pixel sharing unit (539) has a total of six pixels (541).

[0184] FIG. 25a is a drawing showing an example in which through electrodes (251), etc. are disposed on all buried electrodes (161 and 162), similar to FIG. 23a. The through electrodes (252) disposed on the three buried electrodes (162) of the pixel sharing unit (539) are connected in common to the wiring (242) of the second semiconductor substrate (220) and connected to the pixel circuit (210). FIG. 25b is a drawing showing an example in which three buried electrodes (161) are connected to each other by boundary wiring (163), etc. Also, FIG. 23b describes an example in which the through electrodes (251) are connected to boundary wiring (163), etc. FIG. 25c is a drawing showing an example in which, for the example of FIG. 25b, boundary wiring (163), etc. connecting three buried electrodes (162) to each other is further provided. FIG. 25d is a drawing showing an example in which, with respect to the example of FIG. 25a, a boundary wiring (163) connecting the embedded electrodes (161) of two rows of pixels (541) in the horizontal direction of the drawing is further provided. FIG. 25e is a drawing showing an example in which, with respect to the example of FIG. 25b, a boundary wiring (163) connecting the embedded electrodes (161) of two rows of pixels (541) in the horizontal direction of the drawing is further provided.

[0185] [Comparison Results]

[0186] FIG. 26 is a drawing illustrating the comparison results of a pixel array section according to the fifth embodiment of the present disclosure. In the same figure, Comparative Example 3 assumes an example in which, in a pixel array section (540) having a pixel (541) of FIG. 21, the embedded electrodes (161 and 162) are shared among two pixels (541), and the pixel sharing unit (539) has six pixels (541). Application Examples 9 to 13 each represent examples of the case of the pixel array section (540) of FIG. 25a to 20e.

[0187] In the six examples of the same drawing, the "charge holding part shared pixel" and the "pixel circuit sharing unit" each have 2 pixels and 3×2 pixels, and the "charge transmission part" of the "connection part" has 6. In any example, the pixel sharing unit (539) is composed of 6 pixels (541) and 1 pixel circuit (210).

[0188] In Comparative Example 3 and Application Example 9, the "charge holding portion" and "well region" of the "connection portion" become 3. This is because a through electrode (251) is placed for every 3 buried electrodes (161), and a through electrode (252) is placed for every 3 buried electrodes (162). In Comparative Example 2 and Application Example 4, the "total" of the "connection portion" becomes 12.

[0189] In Application Example 10, just like in Application Example 9, the "charge holding portion" of the "connection portion" becomes 2. Meanwhile, in Application Example 10, the "well area" of the "connection portion" becomes 1. This is because the penetrating electrode (251) is shared among three buried electrodes (161) that are connected to each other by boundary wiring (163), etc. The "total" of the "connection portion" in Application Example 10 becomes 10.

[0190] In Application Example 11, the "charge holding portion" of the "connection portion" becomes 1. This is because the penetrating electrode (252) is shared among three buried electrodes (162) that are connected to each other by boundary wiring (163), etc. Also, as in Application Example 10, the "well area" of the "connection portion" becomes 1. The "total" of the "connection portion" in Application Example 11 becomes 8.

[0191] In Application Example 12, just like in Application Example 10, the “charge holding portion” of the “connection portion” becomes 3. Also, just like in Application Example 5 of FIG. 24, the “well region” of the “connection portion” becomes 0. The “total” of the “connection portion” in Application Example 12 becomes 9.

[0192] In Application Example 13, just like in Application Example 11, the “charge holding portion” of the “connection portion” becomes 1. Also, just like in Application Example 5 in FIG. 24, the “well region” of the “connection portion” becomes 0. The “total” of the “connection portion” in Application Example 13 becomes 7.

[0193] In Comparative Example 3 and Application Example 9, "boundary wiring" is "none," and in other cases, "boundary wiring" is "present." Also, in Application Example 12 and Application Example 13, where the through electrode (251) is omitted, "well contact" is "outside the pixel," and in other cases, "well contact" is "inside the pixel." Additionally, the item for "FD capacitance" is omitted.

[0194] In this way, in an application example where the embedded electrode (162) connected to the charge holding portion (103) is shared in two pixels (541) and the boundary wiring (163 and 164) is connected to the embedded electrode (161 and 162), the number of connection portions can be further reduced.

[0195] (6. Sixth Embodiment)

[0196] In the above-described fifth embodiment, a comparison was made regarding an example having a pixel sharing unit (539) having six pixels (541), in which two pixels (541) share a buried electrode (162) connected to a charge holding portion (103). In contrast, in the sixth embodiment of the present disclosure, an example in which the number of pixels (541) of the pixel sharing unit (539) is further increased is described.

[0197] [Composition of the pixel array section]

[0198] FIGS. 27a to 27f are drawings illustrating an example configuration of a pixel array section according to a sixth embodiment of the present disclosure. FIGS. 27a to 27f are drawings illustrating an example configuration of a pixel array section (540), similar to FIGS. 25a to 25e. The pixel array section (540) of FIGS. 27a to 25f differs from the pixel array section (540) of FIGS. 25a to 25e in that it is equipped with pixel sharing units (539A and 539B).

[0199] The pixel sharing unit (539A) has 4 sets of 2 pixels (541) that share the embedded electrode (162), thereby having 8 pixels (541). Additionally, the pixel sharing unit (539B) has 5 sets of 2 pixels (541) that share the embedded electrode (162), thereby having 10 pixels (541).

[0200] FIG. 27a is a drawing showing an example in which through electrodes (251), etc. are disposed on all embedded electrodes (161 and 162), similar to FIG. 23a. The through electrodes (252) disposed on multiple embedded electrodes (162) of the pixel sharing unit (539A and 539B) are commonly connected to the wiring (242) of the second semiconductor substrate (220) and connected to the pixel circuit (210). FIG. 27b is a drawing showing an example in which boundary wiring (163), etc., is provided to connect the embedded electrodes (161) of two rows of pixels (541) in the horizontal direction of the same figure. In this example, the through electrodes (251) are omitted. FIG. 27c is a drawing showing an example in which boundary wiring (163), etc., is further provided to connect three embedded electrodes (162) to each other, with respect to the example of FIG. 27b. FIG. 27d is a drawing showing an example in which a pixel sharing unit (539A) is provided with boundary wiring (163) connecting four embedded electrodes (162), and a pixel sharing unit (539B) is provided with boundary wiring (163) connecting five embedded electrodes (162).

[0201] FIG. 27e is a diagram illustrating an example in which, with respect to the example of FIG. 27c, boundary wiring (163), etc., is further provided to connect the embedded electrodes (161) of the two horizontal rows of pixels (541) in FIG. 27b. Additionally, the boundary wiring (163), etc., connecting the embedded electrodes (161) to each other is positioned at the top and bottom of the pixel sharing units (539A and 539B) in the same diagram and is connected to adjacent embedded electrodes (161). It is necessary to connect a through electrode (251) to the embedded electrode (161) in the central part of the pixel sharing units (539A and 539B). Also, unlike FIG. 27b, in FIG. 27e, the through electrode (251) is positioned in the boundary wiring (163), etc. FIG. 27f is a drawing showing an example in which a penetrating electrode (251), such as a boundary wiring (163), is omitted with respect to the example of FIG. 27e.

[0202] [Comparison Results]

[0203] FIG. 28 is a drawing illustrating the comparison results of a pixel array section according to the sixth embodiment of the present disclosure. In the same figure, Comparative Example 4 assumes a pixel array section (540) having pixel sharing units (539A and 539B) having the pixel (541) of FIG. 21. Application Examples 14 to 19 each represent examples of the case of the pixel array section (540) of FIG. 27a to 27f. In addition, the "4×2 portion" and "5×2 portion" of the "connection section" in the same figure correspond to the portions of the pixel sharing units (539A and 539B), respectively. In addition, the "total" of the "connection section" is the sum of the number of through electrodes (251), etc., of each of the "4×2 portion" and the "5×2 portion."

[0204] In the six examples of the same drawing, the "charge holding part shared pixel" is 2 pixels, and the "pixel circuit shared unit" is 4×2 pixels (pixel sharing unit (539A)) and 5×2 pixels (pixel sharing unit (539B)). Also, in the seven examples of the same drawing, the "charge transfer part" of the "4×2 part" and "5×2 part" in the "connection part" is 8 and 10, respectively.

[0205] In Comparative Example 4 and Application Example 14, the "charge holding portions" of the "4×2 portion" and "5×2 portion" in the "connection portion" are 8 and 10, respectively, and the "well regions" of the "4×2 portion" and "5×2 portion" in the "connection portion" are 4 and 5, respectively. The sums of the "4×2 portion" and "5×2 portion" are 16 and 20, respectively. Therefore, the "total" in the "connection portion" is 36.

[0206] In Application Example 15, just as in Application Example 14, the "charge holding portions" of the "4×2 portion" and "5×2 portion" of the "connection portion" become 4 and 5, respectively. Meanwhile, in Application Example 15, just as in Application Example 5 of FIG. 24, the "well regions" of the "4×2 portion" and "5×2 portion" of the "connection portion" become 0. The "total" of the "connection portion" in Application Example 5 becomes 27.

[0207] In Application Example 16, the “charge holding portion” of the “4×2 portion” and “5×2 portion” of the “connection portion” becomes 2. Also, as in Application Example 15, the “well area” of the “connection portion” becomes 0. The “total” of the “connection portion” in Application Example 11 becomes 22.

[0208] In Application Example 17, the "charge holding portion" of the "connection portion" becomes 1. This is because a plurality of through electrodes (252) of each pixel sharing unit (539A and 539B) are connected in common by boundary wiring (163), etc. Also, similar to Application Example 14, the "well area" of the "4×2 portion" and "5×2 portion" of the "connection portion" becomes 4 and 5, respectively. The "total" of the "connection portion" in Application Example 12 becomes 29.

[0209] In Application Example 18, just like in Application Example 17, the "charge holding portion" of the "connection portion" becomes 1. Also, the "well regions" of the "4×2 portion" and "5×2 portion" of the "connection portion" become 2 and 3, respectively. This is because, unlike Application Examples 15 and 16, a through electrode (251) is placed in the buried electrode (161). The "total" of the "connection portion" in Application Example 18 becomes 25.

[0210] In Application Example 19, just like in Application Example 17, the "charge holding portion" of the "connection portion" becomes 1. Also, the "well area" of the "4×2 portion" and "5×2 portion" of the "connection portion" becomes 1 and 2, respectively. This is because, unlike Application Examples 15 and 16, a through electrode (251) is placed on the embedded electrode (161) in the central portion of the pixel sharing unit (539A and 539B). The "total" of the "connection portion" in Application Example 19 becomes 23.

[0211] In Comparative Example 4 and Application Example 14, the "boundary wiring" is "none," while in all other cases, the "boundary wiring" is "present." Additionally, in Application Example 15 and Application Example 16, where the through electrode (251) is omitted, the "well contact" is "outside the pixel." Also, in Application Example 19, the "well contact" is a combination of "inside the pixel" and "outside the pixel." In all other cases, the "well contact" is "inside the pixel."

[0212] In this way, the number of connection parts can be further reduced in an application example where the embedded electrodes (162) of the pixel sharing units (539A and 539B) are connected to each other by boundary wiring (163), etc., to share the penetrating electrode (251).

[0213] (7. Seventh Embodiment)

[0214] The imaging device (1) of the first embodiment described above used a separation part (171) composed of an insulating material. In contrast, the imaging device (1) of the seventh embodiment of the present disclosure differs from the first embodiment described above in that it uses a separation part (171) composed of a different material.

[0215] [Composition of the Separator]

[0216] FIGS. 29a and 29b are drawings illustrating an example of the configuration of a separating part according to the seventh embodiment of the present disclosure. FIGS. 29a and 29b are cross-sectional views showing an example of the configuration of a separating part.

[0217] The separation portion (171) of FIG. 29a is configured at a relatively shallow depth from the surface side of the first semiconductor substrate (120). A polycrystalline silicon layer (172) is disposed below this separation portion (171). A separation portion (173) is disposed adjacent to this polycrystalline silicon layer (172). This separation portion (173) is a semiconductor region composed of a relatively high impurity concentration of the same conductivity type as the well region.

[0218] The polycrystalline silicon layer (172) is composed of polycrystalline silicon with impurities injected. By placing this polycrystalline silicon layer (172) in the groove (179) of the first semiconductor substrate (120) and performing heat treatment, the impurities of the polycrystalline silicon layer (172) diffuse into the surrounding first semiconductor substrate (120). By doing so, a separation portion (173) including a semiconductor region with a relatively high impurity concentration adjacent to the polycrystalline silicon layer (172) can be formed. This method of impurity diffusion is called a solid-state diffusion method. The first semiconductor substrate (120) in the pixel (541) can be separated by this separation portion (173).

[0219] The separation portion (174) of FIG. 29b is a semiconductor region composed of a relatively high impurity concentration of the same conductivity type as the well region, similar to the separation portion (173). This separation portion (174) can be formed by performing ion implantation on the first semiconductor substrate (120).

[0220] The configuration of the imaging device (1) other than that is the same as the configuration of the imaging device (1) in the first embodiment of the present disclosure, so the description is omitted.

[0221] In this way, the imaging device (1) of the seventh embodiment of the present disclosure separates the boundaries of the pixels (541) by means of a separation part (173 and 174) formed by a semiconductor region.

[0222] (8. Eighth Embodiment)

[0223] The imaging device (1) of the first embodiment described above had embedded electrodes (161 and 162) placed at the boundary of the pixel (541) and each transmitted a reference potential and a potential of the charge holding part. In contrast, the imaging device (1) of the eighth embodiment of the present disclosure differs from the first embodiment described above in that it has embedded electrodes arranged in a shape surrounding the pixel (541) and transmits only the reference potential.

[0224] [Composition of Pixel Sharing Unit]

[0225] FIG. 30 is a drawing illustrating an example of the configuration of a pixel sharing unit according to the eighth embodiment of the present disclosure. Like FIG. 8, FIG. 30 is a plan view showing an example of the configuration of a pixel sharing unit (539). FIG. 8 is different from FIG. 8's pixel sharing unit (539) in that FIG. 8's pixel sharing unit (539) is provided with a buried electrode (165) instead of buried electrodes (161 and 162), and the charge holding portion (103) is spaced apart from the boundary of the pixel (541).

[0226] The embedded electrode (165) is an embedded electrode configured to surround the pixel (541) by being placed at the boundary of the pixel (541). This embedded electrode (165), like the embedded electrode (161), transmits a reference potential (well potential). A semiconductor region (123) is placed on a first semiconductor substrate (120) adjacent to the embedded electrode (165). As described above, the semiconductor region (123) is a semiconductor region with a relatively high impurity concentration placed in the well region of the first semiconductor substrate (120). By interposing this semiconductor region (123), the connection between the embedded electrode (165) and the well region can be made low-resistance. As shown in the drawing, the semiconductor region (123) can be configured to be adjacent to a part of the embedded electrode (165). Additionally, the semiconductor region (123) may be configured as an annular shape along the inner side of the embedded electrode (165) when viewed from a planar perspective.

[0227] As shown in the drawing, the through electrode (251) supplying the reference potential (well potential) is connected to the portion of the embedded electrode (165) extending to the outside of the pixel array portion (540). By doing so, a common well potential is supplied to the well area of ​​each pixel (541), and the through electrode (251) for each pixel (541) can be omitted.

[0228] In addition, as shown in the drawing, by configuring the buried electrode (165) in a mesh shape, the region of the buried electrode (165) that serves as the transmission path for the reference potential can be made low-resistance. The potential difference of the well potential between other pixels (541) can be reduced.

[0229] As shown in the drawing, the semiconductor region (122) constituting the charge holding portion (103) is positioned at a location spaced apart from the boundary of the pixel (541). This is to space it apart from the embedded electrode (165) at the boundary of the pixel (541). In the pixel (541) of the drawing, an electrode (143) is connected to the semiconductor region (122) constituting the charge holding portion (103). This electrode (143) is placed in the charge holding portion (103) of all pixels (541) of the pixel sharing unit (539). A plurality of electrodes (143) of this pixel sharing unit (539) are connected to the charge holding portion wiring (142) of the drawing. This charge holding portion wiring (142) is wiring placed between the first semiconductor substrate (120) and the second semiconductor substrate (220). A through electrode (254) is also connected to the charge holding portion wiring (142). The through electrode (254) is an electrode shaped to penetrate the second semiconductor substrate (220). This through electrode (254) is connected to the pixel circuit (210).

[0230] [Composition of pixels]

[0231] FIG. 31 is a drawing illustrating an example of a pixel configuration according to the eighth embodiment of the present disclosure. Like FIG. 9, FIG. 31 is a schematic cross-sectional view showing an example of a pixel configuration (541). FIG. 9 is different from FIG. 9's pixel (541) in that FIG. 9's pixel (541) is provided with a buried electrode (165) instead of buried electrodes (161 and 162), and the charge holding portion (103) is spaced apart from the boundary of FIG. 9's pixel (541).

[0232] The embedded electrode (165) is embedded and disposed on the surface side of the first semiconductor substrate (120) at the boundary of the pixel (541) that overlaps the separation portion (171). A semiconductor region (123) is disposed adjacent to this embedded electrode (165). The semiconductor region (122) constituting the charge holding portion (103) is disposed spaced apart from the boundary of the pixel (541) and an electrode (143) is connected thereto. This electrode (143) is an electrode composed of a main metal or the like, similar to the through electrode (251). Additionally, the electrode (143) is connected to the charge holding portion wiring (142). Furthermore, the through electrode (254), wiring (242), and via plug (243) are connected in sequence to the charge holding portion wiring (142) and connected to the element (amplifier transistor (213) of the second semiconductor substrate (220). Additionally, the electrode (143) is an example of the second connection part described in the claim.

[0233] A portion of the embedded electrode (165) extends to an area outside the pixel array portion (540) and is connected to a through electrode (251). This through electrode (251) is connected to the ground line (Vss) of the third semiconductor substrate (320) via wiring (242) and a contact plug (244), as in FIG. 9, so that the ground potential is supplied as a reference potential (well potential). Additionally, the through electrode (251) is also connected to the semiconductor area (225) of the second semiconductor substrate (220).

[0234] The configuration of the imaging device (1) other than that is the same as the configuration of the imaging device (1) in the first embodiment of the present disclosure, so the description is omitted.

[0235] In this way, the imaging device (1) of the eighth embodiment of the present disclosure supplies a reference potential by arranging an embedded electrode (165) that surrounds the pixel (541). The area related to the supply of the reference potential can be arranged outside the pixel (541), so that the pixel (541) can be miniaturized.

[0236] (9. Ninth Embodiment)

[0237] The imaging device (1) of the eighth embodiment described above had a charge transfer unit (102) composed of a planar (horizontal) MOS transistor. In contrast, the imaging device (1) of the ninth embodiment of the present disclosure differs from the eighth embodiment described above in that it has a charge transfer unit (102) composed of a vertical MOS transistor in which a carrier moves in the vertical direction.

[0238] [Composition of Pixel Sharing Unit]

[0239] FIG. 32 is a drawing illustrating an example of the configuration of a pixel sharing unit according to a ninth embodiment of the present disclosure. Like FIG. 30, FIG. 32 is a plan view showing an example of the configuration of a pixel sharing unit (539). The pixel sharing unit (539) of FIG. 30 differs from the pixel sharing unit (539) of FIG. 30 in that it is equipped with a charge transfer unit (102) composed of a vertical MOS transistor.

[0240] In the pixel (541) of the same drawing, a charge holding portion (103) and a charge transfer portion (102) are arranged in the central portion. The charge transfer portion (102) is arranged on the lower layer of the semiconductor region (125) constituting the charge holding portion (103). This charge transfer portion (102) is composed of a vertical MOS transistor as described above. The channel region of the charge transfer portion (102) is arranged on a protrusion formed on the surface side of the first semiconductor substrate (120) and is equipped with a gate electrode (132). This gate electrode (132) is configured in a shape that surrounds the channel region. The charge transfer portion (102) of the same drawing is an example configured in a rectangular shape similar to that of the pixel (541) when viewed from a planar perspective. A through electrode (253) is connected to the gate electrode (132). Additionally, an electrode (143) is connected to the charge holding portion (103).

[0241] [Composition of pixels]

[0242] FIG. 33 is a drawing illustrating an example of a pixel configuration according to the ninth embodiment of the present disclosure. FIG. 33 is a schematic cross-sectional view showing an example of a pixel configuration (541). The pixel (541) of FIG. 31 differs from the pixel (541) of FIG. 31 in that the charge holding portion (103) is configured by a vertical MOS transistor.

[0243] A protrusion (126) is formed on the surface side of the first semiconductor substrate (120). A channel region (124) of the charge holding portion (103) is disposed on this protrusion (126). An annular groove (127) is disposed on the surface side of the first semiconductor substrate (120). The protrusion (126) in the drawing is formed by grinding the surface side of the first semiconductor substrate (120) into the shape of an annular groove (127). A photoelectric conversion portion (101) is disposed on the lower part of the charge transfer portion (102), and a charge holding portion (103) is disposed on the upper part of the charge transfer portion (102). The channel region (124) of the charge transfer portion (102) is composed of an n-type semiconductor. The n-type semiconductor region (121) of the photoelectric conversion unit (101) and the n-type semiconductor region (125) of the charge holding unit (103) correspond to the source region and drain region of the charge transfer unit (102), respectively. In the channel region (124), carriers (electrons in the same figure) move in the thickness direction (vertical direction) of the first semiconductor substrate (120) from the source region toward the drain region.

[0244] By applying such a vertical MOS transistor to the charge transfer unit (102), the area of ​​the charge transfer unit (102) on the surface side of the first semiconductor substrate (120) can be reduced. In addition, the transfer of charge from the photoelectric conversion unit (101), which is configured as a back-illuminated type and disposed in the core of the first semiconductor substrate (120), can be easily performed.

[0245] An insulating film (129) corresponding to a gate insulating film is disposed on the surface of the channel region (124). A gate electrode (132) having a shape adjacent to the channel region (124) is disposed through this insulating film (129). In this way, the charge transfer unit (102) is configured in a depletion-type MOS transistor. The charge transfer unit (102) is a so-called normalion-type MOS transistor. When the charge transfer unit (102) is in a non-conducting state, a negative polarity control signal is applied to the gate electrode (132).

[0246] The gate electrode (132) of the same drawing is configured in a shape that surrounds the channel region (124), as shown in the example. By placing the gate electrode (132) around the channel region (124) in this way, the effective channel width can be widened, and the channel resistance can be reduced. In addition, a depletion layer can be formed by applying a gate voltage to all sides of the channel region, making complete depletion of the channel region possible. The leakage current during off can be reduced.

[0247] Additionally, the gate electrode (132) of the same drawing is spaced apart from the charge holding portion (103) in the thickness direction of the first semiconductor substrate (120). A spacing portion (134) is disposed between the gate electrode (132) of the same drawing and the semiconductor region (125) of the charge holding portion (103). An insulating material similar to the insulating layer (141) is disposed in this spacing portion (134). Additionally, the spacing portion (134) can be formed by placing an annular groove (128) between the gate electrode (132) and the protrusion (126). In this way, by spacing the gate electrode (132) and the charge holding portion (103), the electric field between the gate electrode (132) and the semiconductor region (125) constituting the charge holding portion (103) can be reduced. When a high electric field is applied between the gate electrode (132) and the semiconductor region (125), charges from the valence band are ejected, and the ejected charges remain at the interface between the insulating film (129) near the gate electrode (132) and the first semiconductor substrate (120). Because of this, the performance of the charge transfer unit (102) is degraded. By making the distance between the gate electrode (132) and the charge holding unit (103) 100 nm or more, the electric field between the gate electrode (132) and the semiconductor region (125) constituting the charge holding unit (103) can be reduced.

[0248] Meanwhile, if the distance between the gate electrode (132) and the charge holding portion (103) is excessively large, the diffusion region of the drain of the charge transfer portion (102) becomes longer. As the equivalent region of the charge holding portion (103) increases, the capacity (FD capacity) of the charge holding portion (103) increases.

[0249] In addition, as described above, the charge transfer unit (102) of the same drawing is configured in a rectangular shape similar to the pixel (541) when viewed from a planar perspective. By configuring the charge transfer unit (102) in a planar shape similar to the pixel (541), the area of ​​the charge transfer unit (102) relative to the pixel (541) can be expanded.

[0250] Additionally, the configuration of the pixel (541) is not limited to this example. For example, the embedded electrode (165) may be omitted. In this case, a through electrode (251) is placed in each pixel (541) and connected to the semiconductor region (123) to supply a reference potential.

[0251] [Method for manufacturing an image sensor]

[0252] FIGS. 34a to 34m are drawings illustrating an example of a method for manufacturing an imaging element according to the ninth embodiment of the present disclosure. FIGS. 34a to 34m are drawings illustrating an example of a manufacturing process of an imaging device (1), and an example of a manufacturing process mainly related to the area of ​​the charge transfer unit (102).

[0253] First, a separation part (171) and an embedded electrode (165) are placed on the first semiconductor substrate (120) (Fig. 34a).

[0254] Next, a resist (609) is placed on the surface side of the first semiconductor substrate (120). An opening (610) is placed in the portion of the resist (609) that forms an annular groove (127) (Fig. 34b). Next, the surface side of the first semiconductor substrate (120) is etched using the resist (609) as a mask to form an annular groove (127). This can be done, for example, by dry etching. By this process, a protrusion (126) can be formed on the surface side of the first semiconductor substrate (120) (Fig. 34c).

[0255] Next, an insulating layer (141) is placed in the annular groove (127) (Fig. 34d). This can be done, for example, by forming a material film of the insulating layer (141) by CVD and grinding away unnecessary parts. Next, a resist (611) is placed on the surface side of the first semiconductor substrate (120). An opening (612) is placed in the area where the gate electrode (132) is placed in the resist (611) (Fig. 34e). Next, the insulating layer (141) placed in the annular groove (127) is etched using the resist (611) as a mask to form a groove portion (613) (Fig. 34f). This can be done, for example, by anisotropic dry etching. Next, an insulating film (129) corresponding to a gate insulating film is formed on the side of the protrusion (126) and the bottom of the annular groove (127) (Fig. 34g). This can be done, for example, by thermal oxidation.

[0256] Next, a material film (614) of a gate electrode (132) is placed on the surface side of the first semiconductor substrate (120) including the groove (613) (Fig. 34h). This can be done, for example, by forming a polycrystalline silicon film by CVD. Next, a resist (615) is placed on the surface side of the first semiconductor substrate (120). An opening (616) is placed in the portion forming the annular groove (128) in this resist (615) (Fig. 34i). Next, the material film (614) is etched using the resist (615) as a mask. At this time, the etching is stopped at the point where the gate electrode (132) in the portion adjacent to the channel region (124) becomes a desired width (Fig. 34j). This etching can be performed, for example, by dry etching. By doing so, the annular groove (128) can be formed. Next, an insulating layer (141) is placed in the annular groove (128), and the resist (615) is removed (Fig. 34k). Next, the material film (614) on the surface side of the first semiconductor substrate (120) is removed. By this process, a gate electrode (132) can be formed (Fig. 34l). Next, an insulating layer (141) is placed on the surface side of the first semiconductor substrate (120), and a through electrode (253) and an electrode (143) are placed (Fig. 34m). By the above process, a charge transfer unit (102) can be formed.

[0257] [Variation Example]

[0258] FIG. 35 is a drawing illustrating a first modified example of the configuration of a charge transfer unit according to the ninth embodiment of the present disclosure. FIG. 35 is a schematic cross-sectional view showing a modified example of the configuration of a charge transfer unit (102). The charge transfer unit (102) of FIG. 33 differs from the charge transfer unit (102) of FIG. 33 in that the annular groove (127) is configured in a roughly vertical cross section.

[0259] FIGS. 36a to 36e are drawings illustrating a second variation of the configuration of a charge transfer unit according to the ninth embodiment of the present disclosure. FIGS. 36a to 36e are plan views showing variations of the configuration of a charge transfer unit (102).

[0260] FIG. 36a is a drawing showing an example of a charge transfer unit (102) configured in a circular shape when viewed from a planar view. In addition, in the same drawing, the charge holding unit (103) can also be configured in a circular shape when viewed from a planar view. Since the gate electrode (132), etc., is configured in a circular shape without corners, the concentration of the electric field can be relieved.

[0261] FIGS. 36b to 36e illustrate an example of reducing the gate electrode (132) adjacent to the channel region (124) of the charge transfer unit (102). The gate electrode (132) can be configured in any shape that does not surround the channel region (124). By reducing the gate electrode (132), the charge transfer unit (102) can be miniaturized. Additionally, by reducing the gate electrode (132), the capacitance between the gate electrode (132) and the channel region (124) can be reduced. The input capacitance of the charge transfer unit (102) is reduced, thereby allowing the charge transfer unit (102) to be accelerated.

[0262] The configuration of the imaging device (1) other than that is the same as the configuration of the imaging device (1) in the eighth embodiment of the present disclosure, so the description is omitted.

[0263] In this way, the imaging device (1) of the ninth embodiment of the present disclosure can miniaturize the charge transfer unit (102) by providing a charge transfer unit (102) composed of a vertical MOS transistor.

[0264] (10. 10th Embodiment)

[0265] In the imaging device (1) of the ninth embodiment described above, wiring for transmitting a control signal of the charge transmission unit (102) was arranged for each pixel sharing unit (539). In contrast, the imaging device (1) of the tenth embodiment of the present disclosure differs from the ninth embodiment described above in that wiring for transmitting a control signal of the charge transmission unit (102) is shared between adjacent pixel sharing units (539).

[0266] [Composition of Pixel Sharing Unit]

[0267] FIG. 37 is a drawing illustrating an example of the configuration of a pixel sharing unit according to the 10th embodiment of the present disclosure. Like FIG. 32, FIG. 37 is a plan view showing an example of the configuration of a pixel sharing unit (539). The pixel sharing unit (539) of FIG. 32 differs from the pixel sharing unit (539) of FIG. 32 in that it is equipped with a charge transmission unit wiring (144).

[0268] The charge transfer unit wiring (144) is a signal line that is commonly placed in adjacent pixel sharing units (539) to transmit control signals of the charge transfer unit (102). The charge transfer unit wiring (144) is described using the pixel sharing units (539E and 539F) described in the drawing. The gate electrodes (132) of the four charge transfer units (102) of the pixel sharing unit (539E) and the gate electrodes (132) of the corresponding charge transfer units (102) of the pixel sharing unit (539F) are each connected by the charge transfer unit wiring (144A to 144D). Specifically, the gate electrode (131A) of the charge transfer unit (102A) in the pixel (541A) of the pixel sharing unit (539E) and the gate electrode (131) of the charge transfer unit (102A) in the pixel (541A) of the pixel sharing unit (539F) are connected by a charge transfer unit wiring (144A). Likewise, the gate electrodes (132) of the charge transfer unit (102) of the pixels (541B to 541D) are each connected by charge transfer unit wiring (144B to 144D). A through electrode (253) is disposed in each of these charge transfer unit wirings (144A to 144D).

[0269] In this way, by sharing a signal line that transmits a control signal between adjacent pixel sharing units (539), the number of through electrodes (253) that transmit this control signal can be reduced.

[0270] In addition, in the pixel sharing units (539E and 539F) of the same drawing, an inverted U-shaped charge holding wiring (142) is arranged.

[0271] If through electrodes are placed for each charge holding unit (103) and charge transfer unit (102) without using charge holding unit wiring (142) and charge transfer unit wiring (144), eight through electrodes (253), etc. are required for each pixel sharing unit (539). On the other hand, by using charge holding unit wiring (142) and charge transfer unit wiring (144), the number of through electrodes (253 and 254) per pixel sharing unit (539) can be reduced to three. The opening area of ​​the through hole (262) of the second semiconductor substrate (220) for placing through electrodes (253), etc. can be reduced.

[0272] The configuration of the imaging device (1) other than that is the same as the configuration of the imaging device (1) in the ninth embodiment of the present disclosure, so the description is omitted.

[0273] In this way, the imaging device (1) of the 10th embodiment of the present disclosure can reduce the number of penetrating electrodes (253) by arranging the charge transmission unit wiring (144) and sharing the control signal between adjacent pixel sharing units (539).

[0274] (11. Application Example)

[0275] FIG. 38 shows an example of a schematic configuration of an imaging system equipped with an imaging device according to the above embodiment and a variation thereof.

[0276] The imaging system (7) is an electronic device, such as an imaging device like a digital still camera or a video camera, or a portable terminal device like a smartphone or a tablet terminal. The imaging system (7) is equipped with, for example, an imaging device (1), a DSP circuit (743), a frame memory (744), a display unit (745), a memory unit (746), an operation unit (747), and a power supply unit (748) according to the above embodiment and its variations. In the imaging system (7), the imaging device (1), the DSP circuit (743), the frame memory (744), the display unit (745), the memory unit (746), the operation unit (747), and the power supply unit (748) according to the above embodiment and its variations are connected to each other through a bus line (749).

[0277] The imaging device (1) according to the above embodiment and its variation outputs image data according to incident light. The DSP circuit (743) is a signal processing circuit that processes a signal (image data) output from the imaging device (1) according to the above embodiment and its variation. The frame memory (744) temporarily holds the image data processed by the DSP circuit (743) in frame units. The display unit (745) includes a panel-type display device, such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, for example, and displays a moving image or a still image captured by the imaging device (1) according to the above embodiment and its variation. The memory unit (746) records the image data of the moving image or a still image captured by the imaging device (1) according to the above embodiment and its variation on a recording medium such as a semiconductor memory or a hard disk. The control unit (747) issues operation commands regarding various functions of the imaging system (7) according to operation by the user. The power supply unit (748) appropriately supplies various power sources to the supply targets, which serve as operating power sources for the imaging device (1), DSP circuit (743), frame memory (744), display unit (745), memory unit (746), and control unit (747) according to the above embodiment and its variations.

[0278] Next, the imaging procedure in the imaging system (7) will be explained.

[0279] FIG. 39 shows an example of a flowchart of an imaging operation in an imaging system. The user instructs the start of imaging by operating the control unit (747) (step S101). Then, the control unit (747) transmits an imaging command to the imaging device (1) (step S102). When the imaging device (1) (specifically the system control circuit (36)) receives the imaging command, it performs imaging in a predetermined imaging method (step S103).

[0280] The imaging device (1) outputs image data obtained by imaging to the DSP circuit (743). Here, image data refers to data of the entire pixel portion of a pixel signal generated based on charges temporarily held in a floating diffusion (FD). The DSP circuit (743) performs a predetermined signal processing (e.g., noise reduction processing) based on the image data input from the imaging device (1) (step S104). The DSP circuit (743) stores the image data, on which the predetermined signal processing has been performed, in the frame memory (744), and the frame memory (744) stores the image data in the memory unit (746) (step S105). In this way, imaging is performed in the imaging system (7).

[0281] In this application example, the imaging device (1) according to the above embodiment and its variation is applied to the imaging system (7). By doing so, the imaging device (1) can be made smaller or more precise, thereby providing a small or more precise imaging system (7).

[0282] (12. Examples of Applications to Moving Objects)

[0283] The technology of the present disclosure (the technology) can be applied to various products. For example, the technology of the present disclosure may be realized as a device mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, an automatic two-wheeled vehicle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0284] FIG. 40 is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology of the present disclosure may be applied.

[0285] The vehicle control system (12000) is equipped with a plurality of electronic control units connected via a communication network (12001). In the example illustrated in FIG. 40, the vehicle control system (12000) is equipped with a drive system control unit (12010), a body system control unit (12020), an out-of-vehicle information detection unit (12030), an in-vehicle information detection unit (12040), and an integrated control unit (12050). Additionally, as a functional configuration of the integrated control unit (12050), a microcomputer (12051), a voice-image output unit (12052), and a vehicle-mounted network interface (12053) are illustrated.

[0286] The drivetrain control unit (12010) controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit (12010) functions as a control device for a driving force generating device for generating the driving force of a vehicle, such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating the braking force of the vehicle.

[0287] The body control unit (12020) controls the operation of various devices equipped on the vehicle body according to various programs. For example, the body control unit (12020) functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlights, taillights, brake lights, turn signals, or fog lamps. In this case, radio waves transmitted from a portable device that replaces a key or signals from various switches may be input to the body control unit (12020). The body control unit (12020) receives the input of such radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0288] The outside information detection unit (12030) detects information outside the vehicle equipped with the vehicle control system (12000). For example, an imaging unit (12031) is connected to the outside information detection unit (12030). The outside information detection unit (12030) captures an image of the outside of the vehicle with the imaging unit (12031) and receives the captured image. Based on the received image, the outside information detection unit (12030) may perform object detection processing, such as people, vehicles, obstacles, signs, or text on the road surface, or distance detection processing.

[0289] The imaging unit (12031) is a light sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit (12031) may output the electrical signal as an image or as distance measurement information. In addition, the light received by the imaging unit (12031) may be visible light or non-visible light such as infrared light.

[0290] The in-vehicle information detection unit (12040) detects information inside the vehicle. The in-vehicle information detection unit (12040) is connected to, for example, a driver state detection unit (12041) that detects the driver's state. The driver state detection unit (12041) includes, for example, a camera that captures the driver, and the in-vehicle information detection unit (12040) may calculate the driver's fatigue level or concentration level based on detection information input from the driver state detection unit (12041), or determine whether the driver is dozing off.

[0291] The microcomputer (12051) can calculate a control target value for a driving force generating device, a steering mechanism, or a braking device based on information inside and outside the vehicle obtained from an outside information detection unit (12030) or an inside information detection unit (12040), and output a control command to the drive system control unit (12010). For example, the microcomputer (12051) can perform cooperative control aimed at realizing functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0292] Additionally, the microcomputer (12051) can perform cooperative control for the purpose of autonomous driving without driver operation by controlling a driving force generating device, a steering mechanism, or a braking device based on information around the vehicle obtained from an outside information detection unit (12030) or an inside information detection unit (12040).

[0293] Additionally, the microcomputer (12051) can output a control command to the body system control unit (12020) based on information from outside the vehicle obtained from the outside information detection unit (12030). For example, the microcomputer (12051) can perform cooperative control aimed at achieving illumination, such as switching the high beam to the low beam, by controlling the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the outside information detection unit (12030).

[0294] The voice-image output unit (12052) transmits an output signal of at least one of voice and image to an output device capable of notifying information visually or audibly to a occupant of the vehicle or outside the vehicle. In the example of FIG. 40, an audio speaker (12061), a display unit (12062), and an instrument panel (12063) are exemplified as output devices. The display unit (12062) may include, for example, at least one of an onboard display and a head-up display.

[0295] FIG. 41 is a drawing illustrating an example of the installation location of the imaging unit (12031).

[0296] In FIG. 41, as an imaging unit (12031), it has imaging units (12101, 12102, 12103, 12104, 12105).

[0297] The imaging units (12101, 12102, 12103, 12104, 12105) are provided at locations such as, for example, the front nose, side mirrors, rear bumpers, back doors, and the upper part of the front glass inside the vehicle (12100). The imaging unit (12101) provided on the front nose and the imaging unit (12105) provided on the upper part of the front glass inside the vehicle mainly acquire a front image of the vehicle (12100). The imaging units (12102, 12103) provided on the side mirrors mainly acquire a side image of the vehicle (12100). The imaging unit (12104) provided on the rear bumper or back door mainly acquires a rear image of the vehicle (12100). The imaging unit (12105) provided on the upper part of the front glass inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, signals, traffic signs, or lanes.

[0298] Additionally, FIG. 41 illustrates an example of the shooting range of the imaging units (12101 to 12104). The imaging range (12111) represents the imaging range of the imaging unit (12101) provided on the front nose, the imaging ranges (12112, 12113) represent the imaging ranges of the imaging units (12102, 12103) provided on the side mirrors, respectively, and the imaging range (12114) represents the imaging range of the imaging unit (12104) provided on the rear bumper or back door. For example, by overlapping image data captured by the imaging units (12101 to 12104), an overhead view image of the vehicle (12100) viewed from above is obtained.

[0299] At least one of the imaging units (12101 to 12104) may have a function for acquiring distance information. For example, at least one of the imaging units (12101 to 12104) may be a stereo camera including a plurality of imaging elements, or an imaging element having a pixel for phase difference detection.

[0300] For example, the microcomputer (12051) can determine the distance to each object within the imaging range (12111 to 12114) and the temporal change of this distance (relative speed with respect to the vehicle (12100)) based on distance information obtained from the imaging unit (12101 to 12104), and can extract as the leading vehicle the closest object on the vehicle (12100) that is traveling at a predetermined speed (e.g., 0 km / h or higher) in approximately the same direction as the vehicle (12100). In addition, the microcomputer (12051) can set a distance between vehicles to be secured in advance in front of the leading vehicle and perform automatic brake control (including follow-up stop control) or automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of autonomous driving, such as driving autonomously without following the driver's operation.

[0301] For example, the microcomputer (12051) can classify and extract object data regarding objects based on distance information obtained from the imaging unit (12101 to 12104), such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other objects, and use this for automatic avoidance of obstacles. For example, the microcomputer (12051) identifies surrounding obstacles of the vehicle (12100) into obstacles visible to the driver of the vehicle (12100) and obstacles that are difficult to see. Then, the microcomputer (12051) determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is greater than a set value and there is a possibility of a collision, it can provide driving support for collision avoidance by outputting an alarm to the driver through the audio speaker (12061) or display unit (12062), or by performing forced deceleration or evasive steering through the drive system control unit (12010).

[0302] At least one of the imaging units (12101 to 12104) may be an infrared camera that detects infrared rays. For example, a microcomputer (12051) can recognize a pedestrian by determining whether a pedestrian exists in the image captured by the imaging units (12101 to 12104). This recognition of a pedestrian is performed by a procedure of extracting feature points from the image captured by the imaging units (12101 to 12104), for example, as an infrared camera, and a procedure of determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of an object. When the microcomputer (12051) determines that a pedestrian exists in the image captured by the imaging units (12101 to 12104) and recognizes the pedestrian, the voice image output unit (12052) controls the display unit (12062) to superimpose a rectangular outline for emphasis on the recognized pedestrian. Additionally, the voice and image output unit (12052) may control the display unit (12062) to display an icon representing a pedestrian, etc., at a desired location.

[0303] The above describes an example of a vehicle control system to which the technology of the present disclosure may be applied. The technology of the present disclosure may be applied to the imaging unit (12031) among the configurations described above. Specifically, the imaging device (1) of FIG. 1 may be applied to the imaging unit (12031). By applying the technology of the present disclosure to the imaging unit (12031), the imaging unit (12031) can be miniaturized.

[0304] (13. Application Examples in Endoscopic Surgical Systems)

[0305] The technology of the present disclosure (the technology) can be applied to various products. For example, the technology of the present disclosure may be applied to endoscopic surgical systems.

[0306] FIG. 42 is a drawing illustrating an example of a schematic configuration of an endoscopic surgical system to which the technology of the present disclosure (the present technology) can be applied.

[0307] In FIG. 42, a surgeon (doctor) (11131) is shown performing surgery on a patient (11132) on a patient bed (11133) using an endoscopic surgery system (11000). As illustrated, the endoscopic surgery system (11000) is composed of an endoscope (11100), other surgical tools (11110) such as a retractable tube (11111) or an energy treatment device (11112), a support arm device (11120) that supports the endoscope (11100), and a cart (11200) equipped with various devices for endoscopic surgery.

[0308] The endoscope (11100) is composed of a tube (11101) into which a predetermined length of area from the tip is inserted into the body cavity of a patient (11132), and a camera head (11102) connected to the base of the tube (11101). In the illustrated example, the endoscope (11100) is configured as a so-called rigid endoscope having a rigid tube (11101), but the endoscope (11100) may be configured as a so-called flexible endoscope having a flexible tube.

[0309] An opening into which an objective lens is inserted is provided at the tip of the tube (11101). A light source device (11203) is connected to the endoscope (11100), and light generated by the light source device (11203) is guided to the tip of the tube by a light guide that extends inside the tube (11101), and is directed toward an object of observation inside the body cavity of a patient (11132) through the objective lens. Additionally, the endoscope (11100) may be a direct-viewing endoscope, a strabismus endoscope, or a lateral-viewing endoscope.

[0310] An optical system and an image element are provided inside the camera head (11102), and reflected light (observation light) from the object to be observed is collected by the optical system and directed to the image element. The observation light is converted by photoelectricity by the image element, and an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image, is generated. The image signal is transmitted as RAW data to the camera control unit (CCU: Camera Control Unit) (11201).

[0311] The CCU (11201) is composed of a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit) and comprehensively controls the operation of the endoscope (11100) and the display device (11202). In addition, the CCU (11201) receives an image signal from the camera head (11102) and performs various image processing on the image signal to display an image based on the image signal, such as development processing (demosaic processing).

[0312] The display device (11202) displays an image based on an image signal for which image processing has been performed by the CCU (11201) under control from the CCU (11201).

[0313] The light source device (11203) is composed of a light source such as an LED (light emitting diode) and supplies illumination light to the endoscope (11100) when photographing the surgical site, etc.

[0314] The input device (11204) is an input interface for the endoscopic surgery system (11000). Through the input device (11204), the user can input various information or instructions to the endoscopic surgery system (11000). For example, the user inputs instructions such as changing the imaging conditions (type of illumination light, magnification, focal length, etc.) by the endoscope (11100).

[0315] The treatment device control device (11205) controls the operation of the energy treatment device (11112) for tissue cauterization, incision, or sealing of blood vessels. The inflating device (11206) releases gas into the body cavity through the inflating tube (11111) to inflate the body cavity of the patient (11132) for the purpose of securing a field of view by the endoscope (11100) and securing a workspace for the surgeon. The recorder (11207) is a device capable of recording various information regarding the surgery. The printer (11208) is a device capable of printing various information regarding the surgery in various formats such as text, images, or graphs.

[0316] Additionally, the light source device (11203) that supplies illumination light when photographing the surgical site with the endoscope (11100) can be composed of, for example, a white light source composed of an LED, a laser light source, or a combination thereof. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device (11203). In addition, in this case, it is also possible to capture images corresponding to each RGB in time division by irradiating laser light from each of the RGB laser light sources onto the object of observation in time division and controlling the driving of the imaging element of the camera head (11102) in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter in the imaging element.

[0317] Additionally, the light source device (11203) may be controlled to change the intensity of the light output at predetermined intervals. By controlling the driving of the imaging element of the camera head (11102) in synchronization with the timing of the change in the light intensity to acquire images in time division and synthesizing the images, a high dynamic range image without so-called black defects and white holes can be generated.

[0318] Additionally, the light source device (11203) may be configured to supply light of a predetermined wavelength band corresponding to special light observation. In special light observation, for example, so-called Narrow Band Imaging is performed by utilizing the wavelength dependence of light absorption in body tissues to irradiate a narrow band of light compared to the irradiation light (i.e., white light) used in normal observations, thereby capturing a predetermined tissue, such as blood vessels in the surface layer of a mucous membrane, with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image by irradiating an excitation light to obtain an image of fluorescence generated by irradiating an excitation light. In fluorescence observation, irradiating an excitation light to body tissues to observe fluorescence from said body tissues (autofluorescence observation), or locally injecting a reagent such as indocyanine green (ICG) into said body tissues and irradiating an excitation light corresponding to the fluorescence wavelength of said reagent to said body tissues to obtain a fluorescence image, etc. The light source device (11203) may be configured to supply narrowband light and / or excitation light corresponding to such special light observation.

[0319] FIG. 43 is a block diagram illustrating an example of the functional configuration of the camera head (11102) and CCU (11201) shown in FIG. 42.

[0320] The camera head (11102) has a lens unit (11401), an imaging unit (11402), a driving unit (11403), a communication unit (11404), and a camera head control unit (11405). The CCU (11201) has a communication unit (11411), an image processing unit (11412), and a control unit (11413). The camera head (11102) and the CCU (11201) are connected to communicate with each other by a transmission cable (11400).

[0321] The lens unit (11401) is an optical system provided at the connection point with the lens barrel (11101). Observation light introduced from the tip of the lens barrel (11101) is guided to the camera head (11102) and enters the lens unit (11401). The lens unit (11401) is composed of a combination of multiple lenses, including a zoom lens and a focus lens.

[0322] The imaging element constituting the imaging unit (11402) may be one (so-called single-plate type) or multiple (so-called multi-plate type). When the imaging unit (11402) is configured as a multi-plate type, for example, an image signal corresponding to each RGB may be generated by each imaging element, and a color image may be obtained by combining them. Alternatively, the imaging unit (11402) may be configured to have a pair of imaging elements to acquire image signals for the right eye and the left eye, respectively, corresponding to a 3D (dimensional) display. By performing a 3D display, the surgeon (11131) can more accurately determine the depth of the biological tissue in the surgical area. In addition, when the imaging unit (11402) is configured as a multi-plate type, multiple lens units (11401) may also be provided in a system corresponding to each imaging element.

[0323] Additionally, the imaging unit (11402) does not necessarily have to be provided in the camera head (11102). For example, the imaging unit (11402) may be provided inside the lens barrel (11101), immediately behind the objective lens.

[0324] The driving unit (11403) is configured by an actuator and, under control from the camera head control unit (11405), moves the zoom lens and focus lens of the lens unit (11401) by a predetermined distance along the optical axis. By doing so, the magnification and focus of the image captured by the imaging unit (11402) can be appropriately adjusted.

[0325] The communication unit (11404) is configured by a communication device for transmitting and receiving various information between the CCU (11201) and the CCU (11404). The communication unit (11404) transmits an image signal obtained from the imaging unit (11402) as RAW data to the CCU (11201) through the transmission cable (11400).

[0326] Additionally, the communication unit (11404) receives a control signal from the CCU (11201) to control the driving of the camera head (11102) and supplies it to the camera head control unit (11405). The control signal includes information regarding imaging conditions, such as information for specifying the frame rate of the captured image, information for specifying the exposure value during imaging, and / or information for specifying the magnification and focus of the captured image.

[0327] In addition, the above-mentioned imaging conditions, such as frame rate, exposure value, magnification, and focus, may be appropriately specified by the user or may be automatically set by the control unit (11413) of the CCU (11201) based on the acquired image signal. In the latter case, so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function are equipped in the endoscope (11100).

[0328] The camera head control unit (11405) controls the driving of the camera head (11102) based on a control signal from the CCU (11201) received through the communication unit (11404).

[0329] The communication unit (11411) is configured by a communication device for transmitting and receiving various information with the camera head (11102). The communication unit (11411) receives an image signal transmitted from the camera head (11102) through a transmission cable (11400).

[0330] Additionally, the communication unit (11411) transmits a control signal to the camera head (11102) to control the driving of the camera head (11102). The image signal or the control signal can be transmitted via electrical communication or optical communication, etc.

[0331] The image processing unit (11412) performs various image processing on the image signal, which is RAW data transmitted from the camera head (11102).

[0332] The control unit (11413) performs various controls regarding the imaging of the surgical area, etc. by the endoscope (11100) and the display of the image obtained by the imaging of the surgical area, etc. For example, the control unit (11413) generates a control signal to control the driving of the camera head (11102).

[0333] Additionally, the control unit (11413) displays an image of a surgical site, etc., on a display device (11202) based on an image signal in which image processing has been performed by the image processing unit (11412). At this time, the control unit (11413) may recognize various objects within the image using various image recognition technologies. For example, the control unit (11413) may recognize surgical tools such as forceps, specific biological parts, bleeding, mist when using an energy treatment device (11112), etc. by detecting the edge shape or color of an object included in the image. When the control unit (11413) displays the image on the display device (11202), it may use the recognition results to superimpose various surgical support information onto the image of the surgical site. By displaying surgical support information in an overlapping manner and presenting it to the surgeon (11131), the burden on the surgeon (11131) is reduced, or it becomes possible for the surgeon (11131) to proceed with the surgery reliably.

[0334] The transmission cable (11400) connecting the camera head (11102) and the CCU (11201) is an electric signal cable corresponding to the communication of electric signals, an optical fiber corresponding to optical communication, or a composite cable thereof.

[0335] In the example illustrated here, communication was performed via a wired connection using a transmission cable (11400), but communication between the camera head (11102) and the CCU (11201) may be performed wirelessly.

[0336] The above describes an example of an endoscopic surgical system to which the technology of the present disclosure may be applied. The technology of the present disclosure may be applied to the endoscope (11100) or the imaging unit (11402) of the camera head (11102) among the configurations described above. Specifically, the imaging device (1) of FIG. 1 may be applied to the imaging unit (11402). By applying the technology of the present disclosure to the imaging unit (11402), the imaging unit (11402) can be miniaturized.

[0337] In addition, although an endoscopic surgical system has been described herein as an example, the technology of the present disclosure may be applied to other systems, such as microscopic surgical systems.

[0338] In addition, the configuration of the seventh embodiment of the present disclosure may be applied to other embodiments. Specifically, the separator (173) of FIG. 29a and the separator (174) of FIG. 29b may be applied to the second to sixth and eighth to tenth embodiments of the present disclosure.

[0339] (effect)

[0340] The imaging device (1) has a pixel (541), a pixel circuit (210), a separation unit (171), embedded electrodes (embedded electrodes (161 and 162)), and a connection unit (through electrodes (251 and 252)). The pixel (541) is disposed on a first semiconductor substrate (120) and comprises a photoelectric conversion unit (101) that performs photoelectric conversion of incident light, a charge holding unit (103) that holds a charge generated by photoelectric conversion, and a charge transfer unit (102) that transfers the charge from the photoelectric conversion unit (101) to the charge holding unit (103). The pixel circuit (210) is disposed on a second semiconductor substrate (220) that is stacked on the surface side of the first semiconductor substrate (120) and generates an image signal based on the retained charge. The separation unit (171) is disposed at the boundary of the pixel (541). The embedded electrodes (embedded electrodes (161 and 162)) are embedded and disposed on the surface side of the first semiconductor substrate (120) at the boundary of the pixel (541) that overlaps with the separation portion (171), and are connected to the first semiconductor substrate (120). The connecting portion (through electrodes (251 and 252)) is connected to the embedded electrodes (embedded electrodes (161 and 162)). By doing so, the embedded electrodes that transmit signals, etc., are disposed at the boundary of the pixel. The pixel size can be reduced.

[0341] Additionally, boundary wiring (boundary wiring (163 and 164)) may also be provided, which is disposed at the boundary of the pixel (541) and connected to the buried electrode (buried electrode (161 and 162)). By doing so, the buried electrodes can be connected to each other at the boundary of the pixel (541).

[0342] Additionally, the boundary wiring (boundary wiring (163)) may be embedded and arranged in the first semiconductor substrate (120).

[0343] Additionally, the boundary wiring (boundary wiring (164)) may be arranged adjacent to the surface side of the first semiconductor substrate (120).

[0344] Additionally, the connection portion (through electrode (251 and 252)) may be connected to the buried electrode (buried electrode (161 and 162)) through the boundary portion wiring (boundary portion wiring (163 and 164)). By doing so, the placement location of the connection portion can be expanded.

[0345] Additionally, the buried electrode (buried electrode (161)) is connected to a well region of the first semiconductor substrate (120), and the connection portion (through electrode (251)) may supply a reference potential. By doing so, a reference potential can be supplied through the buried electrode (buried electrode (161)).

[0346] Additionally, the buried electrode (buried electrode (161)) may be configured in a shape that surrounds the pixel (541). By doing so, the buried electrode (buried electrode (161)) can be made low-resistance in the direction of the semiconductor substrate.

[0347] Additionally, a plurality of the above pixels (541) may be disposed on the first semiconductor substrate (120).

[0348] Additionally, the buried electrode (buried electrode (161)) may be commonly connected to the well region of each pixel (541) of a pixel group (538) composed of two or more pixels (541) among the plurality of pixels (541). By doing so, the buried electrode (buried electrode (161)) can be shared among the pixels (541) placed in the pixel group (538).

[0349] Additionally, the above connection part (through electrode (251)) may be placed for each pixel group (538). By doing so, the number of connection parts can be reduced.

[0350] Additionally, the connection portion (through electrode (251)) may be placed on the first semiconductor substrate (120) outside the plurality of pixels (541). By doing so, the number of connection portions can be reduced.

[0351] Additionally, the pixel circuit (210) may be placed in each pixel sharing unit (539) composed of two or more pixels (541) among the plurality of pixels (541). By doing so, the pixel circuit (210) can be shared among the plurality of pixels placed in the pixel sharing unit (639).

[0352] Additionally, the device further comprises an electrode (143) connected to the charge holding portion (103) and a charge holding portion wiring (142) disposed between the first semiconductor substrate (120) and the second semiconductor substrate (220) and commonly connected to the electrode (143) of each of the plurality of pixels (541) included in the pixel sharing unit (539), and the charge holding portion wiring (142) may be connected to the pixel circuit (210). By doing so, the number of connection portions penetrating the second semiconductor substrate (220) can be reduced.

[0353] Additionally, there may also be a charge transfer unit wiring (144) disposed between the first semiconductor substrate (120) and the second semiconductor substrate (220) to transmit a control signal to the charge transfer unit (102) and to be commonly connected to the charge transfer unit (102) of another pixel sharing unit (539), and an electrode (143) connected to the charge transfer unit wiring to supply the control signal. By doing so, the number of connection units penetrating the second semiconductor substrate (220) can be reduced.

[0354] Additionally, the above connection portion (through electrode (251)) may be connected to a well region in which an element of the pixel circuit (210) is placed on the second semiconductor substrate (220). By doing so, the well potential can be made common in the first semiconductor substrate (120) and the second semiconductor substrate (220).

[0355] Additionally, the buried electrode (buried electrode (162)) may be connected to the charge holding portion (103), and the connection portion (through electrode (252)) may be connected to the pixel circuit (210). By doing so, the potential of the charge holding portion (103) can be transmitted through the electrode (buried electrode (162)).

[0356] Additionally, a plurality of the pixels (541) may be disposed on the first semiconductor substrate (120), and the pixel circuit (210) may be disposed in each pixel sharing unit (539) composed of two or more pixels (541) among the plurality of pixels (541). By doing so, the pixel circuit (210) can be shared among the plurality of pixels (541) disposed in the pixel sharing unit (539).

[0357] Additionally, the buried electrode (buried electrode (162)) may be commonly connected to the charge holding portion (103) of each pixel (541) in the pixel sharing unit (539). By doing so, the buried electrode (buried electrode (162)) can be shared among a plurality of pixels (541) arranged in the pixel sharing unit (539).

[0358] Additionally, the buried electrode (buried electrode (162)) may be configured in a shape that protrudes from the first semiconductor substrate (120), and the charge transfer unit (102) may be configured by a MOS transistor having a gate electrode (131) having a height less than or equal to the protrusion height of the buried electrode (buried electrode (162)) from the first semiconductor substrate (120). By doing so, the parasitic capacitance of the charge holding unit (103) to which the buried electrode (buried electrode (162)) is connected can be reduced.

[0359] Additionally, the connection portion (through electrode (251)) may be connected to the well region through a semiconductor region (123), which is a semiconductor region with a high impurity concentration formed on the first semiconductor substrate (120). By doing so, the connection resistance between the connection portion (through electrode (251)) and the first semiconductor substrate (120) can be reduced.

[0360] In addition, the buried electrode (buried electrode (161 and 162)) may be composed of silicon. By doing so, a high-temperature process can be employed in the manufacturing process after the formation of the buried electrode (buried electrode (161 and 162)).

[0361] Additionally, the separation portion (171) may be configured to penetrate the first semiconductor substrate (120). By doing so, the separation capability can be improved.

[0362] In addition, the above separation part (171) may be composed of an insulating material.

[0363] Additionally, the above separation part (171) may be composed of a semiconductor region with a high impurity concentration.

[0364] Additionally, a third semiconductor substrate (320) may also be provided, which is stacked on a side different from the side where the first semiconductor substrate (120) is placed on the second semiconductor substrate (220) and has a circuit connected to the pixel circuit (210).

[0365] Additionally, the charge transfer unit (102) may be configured by a MOS transistor that transfers the charge in the thickness direction of the first semiconductor substrate (120) by having a channel region disposed on a protrusion (126) formed on the surface side of the first semiconductor substrate (120) and an adjacent gate electrode (132) interposed with an insulating film on the side of the protrusion (126). By doing so, the area of ​​the charge transfer unit (102) can be reduced.

[0366] Additionally, the protrusion (126) may be formed by grinding the surface side of the first semiconductor substrate (120) into the shape of an annular groove. This results in the protrusion (126) being embedded in the first semiconductor substrate (120). The surface side of the first semiconductor substrate (120) can be made flat.

[0367] Additionally, the gate electrode (132) may be configured to surround the side of the protrusion (126). By doing so, the effective channel width can be expanded.

[0368] Additionally, the charge holding portion (103) may be positioned at the end of the protrusion (126). By doing so, wiring between the charge transmission portion (102) and the charge holding portion (103) can be omitted.

[0369] Additionally, the gate electrode (132) may be spaced apart from the charge holding portion (103) in the thickness direction of the first semiconductor substrate (120). By doing so, the electric field between the gate electrode (132) and the charge holding portion (103) can be reduced.

[0370] In addition, the channel region may be configured with a conductivity type different from that of the well region of the first semiconductor substrate (120). By doing so, a depletion type MOS transistor can be configured.

[0371] The imaging device (1) has a pixel (541), a pixel circuit (210), a separation unit (171), an embedded electrode (embedded electrode (161 and 162)), a connection unit (through electrode (251 and 252)), and a thermal signal processing unit (550). The pixel (541) is disposed on a first semiconductor substrate (120) and comprises a photoelectric conversion unit (101) that performs photoelectric conversion of incident light, a charge holding unit (103) that holds a charge generated by photoelectric conversion, and a charge transfer unit (102) that transfers the charge from the photoelectric conversion unit (101) to the charge holding unit (103). The pixel circuit (210) is disposed on a second semiconductor substrate (220) that is stacked on the surface side of the first semiconductor substrate (120) and generates an image signal based on the retained charge. The separation unit (171) is disposed at the boundary of the pixel (541). The embedded electrodes (embedded electrodes (161 and 162)) are embedded and disposed on the surface side of the first semiconductor substrate (120) at the boundary of the pixel (541) that overlaps with the separation portion (171), and are connected to the first semiconductor substrate (120). The connection portion (through electrodes (251 and 252)) is connected to the embedded electrodes (embedded electrodes (161 and 162)). The thermal signal processing portion (550) processes the generated image signal. This brings about the effect of placing the embedded electrodes that transmit signals, etc. at the boundary of the pixel. The pixel size can be reduced.

[0372] Furthermore, the effects described in this specification are merely examples and are not limited thereto, and other effects may also be present.

[0373] In addition, the present technology may also take the following configuration.

[0374] (1) A pixel having a photoelectric conversion unit disposed on a first semiconductor substrate and performing photoelectric conversion of incident light, a charge holding unit that holds a charge generated by the photoelectric conversion, and a charge transfer unit that transfers the charge from the photoelectric conversion unit to the charge holding unit, and

[0375] A pixel circuit disposed on a second semiconductor substrate stacked on the surface side of the first semiconductor substrate and generating an image signal based on the retained charge, and

[0376] A separation portion disposed at the boundary of the pixel, and

[0377] A buried electrode that is embedded and disposed on the surface side of the first semiconductor substrate at the boundary of the pixel overlapping with the above separation portion and connected to the first semiconductor substrate, and

[0378] A connection part connected to the above-mentioned buried electrode

[0379] An imaging element having.

[0380] (2) A picture element described in (1) having a boundary wiring that is placed at the boundary of the pixel and connected to the buried electrode.

[0381] (3) The boundary wiring described above is an imaging element described in (2) that is embedded and disposed in the first semiconductor substrate.

[0382] (4) The boundary wiring described above is an imaging element described in (2) that is positioned adjacent to the surface side of the first semiconductor substrate.

[0383] (5) The above connection part is an imaging element described in (2) that is connected to the buried electrode through the boundary part wiring.

[0384] (6) The above-mentioned embedded electrode is connected to a well region of the first semiconductor substrate, and

[0385] The above connection part is an imaging element described in any one of (1) to (5) that supplies a reference potential.

[0386] (7) The above-described imaging element described in (6), which is configured such that the above-described embedded electrode is configured to surround the pixel.

[0387] (8) An imaging element described in (6), wherein a plurality of the above pixels are disposed on the first semiconductor substrate.

[0388] (9) The above-described imaging element described in (8) is commonly connected to the well region of each pixel of a pixel group composed of two or more pixels among the plurality of pixels.

[0389] (10) The above connection part is an imaging element described in (9) that is arranged for each pixel group.

[0390] (11) The above connection portion is an imaging element described in (8) that is disposed on the first semiconductor substrate outside the plurality of pixels.

[0391] (12) The pixel circuit described above is an imaging element described in (8) that is arranged in each pixel sharing unit composed of two or more pixels among the plurality of pixels.

[0392] (13) A second connection part connected to the charge holding part above, and

[0393] A charge holding portion wiring disposed between the first semiconductor substrate and the second semiconductor substrate and commonly connected to the second connection portion of each of the plurality of pixels included in the pixel sharing unit

[0394] Have more,

[0395] The above charge holding portion wiring is an imaging element described in (12) that is connected to the pixel circuit.

[0396] (14) A charge transfer unit wiring disposed between the first semiconductor substrate and the second semiconductor substrate, which transmits a control signal to the charge transfer unit and is commonly connected to the charge transfer unit of another pixel sharing unit, and

[0397] A second connection unit connected to the above charge transmission unit wiring and supplying the control signal

[0398] An imaging element described in (12) above, having additional features.

[0399] (15) The above connection portion is an imaging element described in any one of (6) to (14) that is connected to a well region in which the element of the pixel circuit on the second semiconductor substrate is placed.

[0400] (16) The above-described embedded electrode is configured as a strip when viewed from a planar view, an imaging element described in (6) to (14).

[0401] (17) The above-mentioned buried electrode is connected to the above-mentioned charge holding part, and

[0402] The above connection part is an imaging element described in (1) that is connected to the pixel circuit.

[0403] (18) A plurality of the above pixels are disposed on the first semiconductor substrate, and

[0404] The pixel circuit described above is an imaging element described in (17) that is arranged in each pixel sharing unit composed of two or more pixels among the plurality of pixels.

[0405] (19) The above-described embedded electrode is an imaging element described in (18) that is commonly connected to the charge holding portion of each pixel in the pixel sharing unit.

[0406] (20) The above-mentioned embedded electrode is configured to protrude from the first semiconductor substrate, and

[0407] The above-described image element described in any one of (17) to (19) is configured by a MOS transistor having a gate electrode having a height less than or equal to the protrusion height of the buried electrode from the first semiconductor substrate.

[0408] (21) The above connection portion is an imaging element described in any one of (6) to (20) that is connected to the well region through a high-concentration impurity region, which is a semiconductor region with a high impurity concentration formed on the first semiconductor substrate.

[0409] (22) The above-mentioned embedded electrode is an imaging element described in any one of (1) to (21), comprising silicon.

[0410] (23) The above-mentioned separation part is configured to have a shape penetrating the first semiconductor substrate, and is an imaging element described in any one of (1) to (22).

[0411] (24) The above separation part is an imaging element described in any one of (1) to (23), which is composed of an insulating material.

[0412] (25) The above separation part is an imaging element described in any one of (1) to (23), which is composed of a semiconductor region with a high impurity concentration.

[0413] (26) An imaging element described in any one of (1) to (25), having a third semiconductor substrate having a circuit connected to the pixel circuit and stacked on a side different from the side on which the first semiconductor substrate is placed in the second semiconductor substrate.

[0414] (27) The charge transfer unit is configured by a MOS transistor that transfers the charge in the thickness direction of the first semiconductor substrate by having a channel region disposed on a protrusion formed on the surface side of the first semiconductor substrate and an adjacent gate electrode with an insulating film interposed on the side of the protrusion. (1) to (26) The image element described in any one of (1) to (26).

[0415] (28) The above protrusion is formed by grinding the surface side of the first semiconductor substrate into the shape of an annular groove, the imaging element described in (27).

[0416] (29) The gate electrode is configured to surround the side of the protrusion, the imaging element described in (27).

[0417] (30) The charge holding portion is an imaging element described in any one of (27) to (29) that is disposed at the end of the protrusion.

[0418] (31) The gate electrode is spaced apart from the charge holding portion in the thickness direction of the first semiconductor substrate and is an imaging element described in (30).

[0419] (32) An imaging element described in any one of (27) to (31), wherein the channel region is configured with a conductivity type different from that of the well region of the first semiconductor substrate.

[0420] (33) A pixel having a photoelectric conversion unit disposed on a first semiconductor substrate and performing photoelectric conversion of incident light, a charge holding unit that holds a charge generated by the photoelectric conversion, and a charge transfer unit that transfers the charge from the photoelectric conversion unit to the charge holding unit, and

[0421] A pixel circuit disposed on a second semiconductor substrate stacked on the surface side of the first semiconductor substrate and generating an image signal based on the retained charge, and

[0422] A separation portion disposed at the boundary of the pixel, and

[0423] A buried electrode that is embedded and disposed on the surface side of the first semiconductor substrate at the boundary of the pixel overlapping with the above separation portion and connected to the first semiconductor substrate, and

[0424] A connection part connected to the above-mentioned buried electrode, and

[0425] A processing circuit that processes the above-mentioned generated image signal

[0426] Imaging device having Explanation of the symbols

[0427] 1: Imaging device 100S, 200S, 300S: Semiconductor layer 100T, 200T, 300T: Wiring layer 101, 101A, 101B: Photovoltaic converter 102, 102A, 102B: Charge transfer unit 103, 103A, 103B: Charge retention unit 120: First semiconductor substrate 123, 123A, 123B: Semiconductor region 124: Channel area 126: Protrusion 128: Circular groove 129: Insulating film 132: Gate electrode 134: Separation 142: Charge holding part wiring 143: Electrode 144, 144A, 144B, 144C, 144D: Charge transfer section wiring 161, 162, 165, 166: Buried electrodes 163, 164: Boundary wiring 171, 173, 174: Separator 179: Groove 210: Pixel circuit 220: Second semiconductor substrate 251 to 254: Through electrodes 320: Third semiconductor substrate 538: Pixel group 539, 539A, 539B, 539E, 539F: Pixel sharing unit 540: Pixel array section 541, 541A, 541B, 541C, 541D: Pixels 550: Thermal signal processing unit 11402, 12031, 12101 to 12105: Imaging unit

Claims

Claim 1 An imaging element comprising: a pixel having a photoelectric conversion unit disposed on a first semiconductor substrate and performing photoelectric conversion of incident light, a charge holding unit having a charge generated by the photoelectric conversion, and a charge transfer unit having a charge transfer unit having a charge from the photoelectric conversion unit to the charge holding unit; a pixel circuit disposed on a second semiconductor substrate stacked on the surface side of the first semiconductor substrate and generating an image signal based on the retained charge; a separation unit disposed at the boundary of the pixel; a buried electrode disposed on the surface side of the first semiconductor substrate at the boundary of the pixel overlapping with the separation unit and connected to the first semiconductor substrate; and a connection unit connected to the buried electrode, wherein the width of the separation unit is the same as the width of the buried electrode. Claim 2 An imaging element according to claim 1, further comprising a boundary wiring disposed at the boundary of the pixel and connected to the embedded electrode. Claim 3 In paragraph 2, the boundary wiring is an imaging element that is embedded and disposed in the first semiconductor substrate. Claim 4 In paragraph 2, the boundary wiring is an imaging element disposed adjacent to the surface side of the first semiconductor substrate. Claim 5 In paragraph 2, the connection portion is an imaging element connected to the embedded electrode through the boundary portion wiring. Claim 6 In claim 1, the embedded electrode is connected to a well region of the first semiconductor substrate, and the connection portion supplies a reference potential, forming an imaging element. Claim 7 In claim 6, the above-mentioned embedded electrode is configured in a shape that surrounds the pixel, an imaging element. Claim 8 An imaging element according to claim 6, wherein a plurality of the pixels are disposed on the first semiconductor substrate. Claim 9 In claim 8, the embedded electrode is an imaging element that is commonly connected to the well region of each pixel of a pixel group composed of two or more pixels among the plurality of pixels. Claim 10 In claim 9, the connection portion is an imaging element arranged for each pixel group. Claim 11 In claim 8, the connection portion is an imaging element disposed on the first semiconductor substrate outside the plurality of pixels. Claim 12 In claim 8, the pixel circuit is an imaging element disposed in each pixel sharing unit composed of two or more pixels among the plurality of pixels. Claim 13 In claim 12, the imaging element further comprises a second connection portion connected to the charge holding portion, and a charge holding portion wiring disposed between the first semiconductor substrate and the second semiconductor substrate and commonly connected to the second connection portion of each of the plurality of pixels included in the pixel sharing unit, wherein the charge holding portion wiring is connected to the pixel circuit. Claim 14 An imaging element according to claim 12, further comprising a charge transmission unit wiring disposed between the first semiconductor substrate and the second semiconductor substrate and connected in common to the charge transmission unit of another pixel sharing unit while transmitting a control signal to the charge transmission unit, and a second connection unit connected to the charge transmission unit wiring and supplying the control signal. Claim 15 In claim 6, the connection portion is an imaging element connected to a well region where an element of the pixel circuit on the second semiconductor substrate is disposed. Claim 16 In claim 6, the embedded electrode is an imaging element configured in a strip shape when viewed from a planar perspective. Claim 17 An imaging element according to claim 1, wherein the embedded electrode is connected to the charge holding portion, and the connection portion is connected to the pixel circuit. Claim 18 An imaging element according to claim 17, wherein a plurality of the pixels are disposed on the first semiconductor substrate, and the pixel circuit is disposed for each pixel sharing unit composed of two or more pixels among the plurality of pixels. Claim 19 In claim 18, the above-mentioned embedded electrode is an imaging element that is commonly connected to the charge holding portion of each pixel in the pixel sharing unit. Claim 20 In claim 17, the embedded electrode is configured to have a shape protruding from the first semiconductor substrate, and the charge transfer unit is configured by a MOS transistor having a gate electrode having a height less than or equal to the protrusion height of the embedded electrode from the first semiconductor substrate. Claim 21 In claim 6, the above connection portion is an imaging element connected to the well region through a high-concentration impurity region, which is a semiconductor region with a high impurity concentration formed on the first semiconductor substrate. Claim 22 In claim 1, the embedded electrode is an imaging element composed of silicon. Claim 23 In claim 1, the separating part is configured in a shape penetrating the first semiconductor substrate, an imaging element. Claim 24 In claim 1, the separation part is an imaging element composed of an insulating material. Claim 25 In claim 1, the separation part is an imaging element composed of a semiconductor region with a high impurity concentration. Claim 26 An imaging element according to claim 1, further comprising a third semiconductor substrate having a circuit connected to the pixel circuit and stacked on a side different from the side where the first semiconductor substrate is disposed on the second semiconductor substrate. Claim 27 An imaging device according to claim 1, wherein the charge transfer unit comprises a MOS transistor that transfers the charge in the thickness direction of the first semiconductor substrate by having a channel region disposed on a protrusion formed on the surface side of the first semiconductor substrate and an adjacent gate electrode interposed with an insulating film on the side of the protrusion. Claim 28 In claim 27, the above-mentioned protrusion is formed by grinding the surface side of the first semiconductor substrate into the shape of an annular groove, forming an imaging element. Claim 29 In claim 27, the imaging element, wherein the gate electrode is configured in a shape that surrounds the side of the protrusion. Claim 30 In claim 27, the charge holding portion is an imaging element disposed at the end of the protrusion. Claim 31 In claim 30, the gate electrode is an imaging element spaced apart from the charge holding portion in the thickness direction of the first semiconductor substrate. Claim 32 In claim 27, the above channel region is configured with a conductivity type different from that of the well region of the first semiconductor substrate, an imaging element. Claim 33 An imaging device comprising: a pixel having a photoelectric conversion unit disposed on a first semiconductor substrate and performing photoelectric conversion of incident light, a charge holding unit that holds a charge generated by the photoelectric conversion, and a charge transfer unit that transmits the charge from the photoelectric conversion unit to the charge holding unit; a pixel circuit disposed on a second semiconductor substrate stacked on the surface side of the first semiconductor substrate and generating an image signal based on the held charge; a separation unit disposed at the boundary of the pixel; an embedded electrode disposed on the surface side of the first semiconductor substrate at the boundary of the pixel overlapping with the separation unit and connected to the first semiconductor substrate; a connection unit connected to the embedded electrode; and a processing circuit that processes the generated image signal, wherein the width of the separation unit is the same as the width of the embedded electrode.

Images