Deterministic communication and precise time synchronization system

Abstract

A deterministic communication and precision time synchronization system for ensuring time consistency between heterogeneous data is disclosed. The deterministic communication and precision time synchronization system according to the present invention is a deterministic communication and precision time synchronization system for ensuring time consistency between a plurality of heterogeneous data including an analog signal, a digital signal, and a communication signal, and comprises: a clock generation unit for generating a master clock; a global time counter configured to increase a counter value according to the master clock; and an FPGA-based processing unit configured to detect an event related to each of the plurality of heterogeneous data, generate a time tag using the counter value at the time when the event is detected, and align each of the plurality of heterogeneous data according to the same time standard based on the time tag.

Description

Technology Field

[0001] The present invention relates to a deterministic communication and precision time synchronization system for ensuring time consistency between heterogeneous data. Background Technology

[0002] Recently, the importance of technologies that ensure time consistency for different types of data is steadily increasing in various fields, such as industrial automation systems, test and measurement systems, robot control systems, and communication-based control systems. For example, in these systems, different forms of data, such as analog sensor data, digital input signals, and data received through communication interfaces, can be processed simultaneously.

[0003] To perform accurate analysis or control on such multiple heterogeneous data, it is necessary to be able to compare or align the time of occurrence of each data point according to the same time standard. In other words, it is crucial to secure accurate time information regarding the occurrence times of different data points.

[0004] However, conventional data collection systems often faced the problem of difficulty in ensuring accurate time consistency regarding the timing of data occurrence, as data is frequently input through different paths or subject to varying processing delays. In particular, heterogeneous data such as analog data, digital event data, and communication data are difficult to align their occurrence times to a single standard time because their respective processing methods and interface characteristics differ.

[0005] As a solution to these problems, methods such as increasing the sampling rate to improve the temporal resolution of the data are sometimes used. However, such methods can cause issues such as increased data throughput, increased consumption of system resources, and increased processing delays, and in particular, in systems that need to process large amounts of data, a problem of significantly increased system load may occur.

[0006] In addition, while some systems perform inter-system time synchronization using network-based time synchronization technology, this method has limitations, such as failing to accurately reflect the actual time of data occurrence or the potential for time errors due to internal system processing delays.

[0007] Therefore, there is a need for a new data processing technology that can ensure accurate time consistency based on the time of event occurrence without relying on high sampling rates for multiple heterogeneous data such as analog signals, digital signals, and communication signals.

[0008] Related prior art documents include Korean Published Patent Application No. 10-2011-0056087 (Title of invention: Time synchronization method and apparatus, Date of publication: May 26, 2011) and Korean Published Patent Application No. 10-2016-0073601 (Title of invention: Launch vehicle system integrated test facility system, Date of publication: June 27, 2016). Prior art literature

[0009] Republic of Korea Published Patent Application No. 10-2011-0056087 (May 26, 2011) Republic of Korea Published Patent Application No. 10-2016-0073601 (June 27, 2016) The problem to be solved

[0010] The objective of the present invention is to provide a deterministic communication and precise time synchronization system that can secure precise time alignment between data without relying on a high sampling rate by generating a time tag using the counter value of a global time counter at the time of occurrence of an event associated with each of a plurality of heterogeneous data, such as analog signals, digital signals, and communication signals, and aligning the plurality of heterogeneous data according to the same time standard based on the time tag. means of solving the problem

[0011] The above objective is achieved by a deterministic communication and precision time synchronization system for ensuring time consistency of a plurality of heterogeneous data including analog signals, digital signals, and communication signals, according to one embodiment of the present invention, comprising: a clock generation unit for generating a master clock; a global time counter configured to increase a counter value according to the master clock; and an FPGA-based processing unit configured to detect an event associated with each of the plurality of heterogeneous data, generate a time tag using the counter value at the time when the event is detected, and align each of the plurality of heterogeneous data according to the same time standard based on the time tag.

[0012] Preferably, the global time counter can be configured so that the counter value increases every clock cycle according to the master clock.

[0013] Preferably, the FPGA-based processing unit can generate the time tag by capturing the counter value of the global time counter at the time the event is detected.

[0014] Preferably, the FPGA-based processing unit can generate the time tag by adding a correction value corresponding to the internal system delay time to the counter value at the time when the event is detected.

[0015] Preferably, the FPGA-based processing unit may include a buffer for arranging data corresponding to the time tag in chronological order.

[0016] Preferably, the FPGA-based processing unit may include a clock domain crossing circuit for converting data generated by different clock signals into a signal synchronized with the master clock.

[0017] Preferably, the clock domain crossing circuit may include an asynchronous FIFO (First-In-First-Out).

[0018] Preferably, the asynchronous FIFO can synchronize the write pointer and the read pointer using a Gray code method.

[0019] The above FPGA-based processing unit may be configured to perform communication data processing by a hardware state machine inside the FPGA.

[0020] Preferably, the global time counter may be composed of a counter of 64 bits or more.

[0021] Preferably, the event may occur in response to at least one of the completion of the conversion of the analog signal, the change in the state of the digital signal, and the completion of the reception of the communication signal.

[0022] Preferably, the time tag and the heterogeneous data can be combined in the form of a packet and transmitted to an external system. Effects of the invention

[0023] According to one embodiment of the present invention, by generating a time tag corresponding to the time of event occurrence using the counter value of a global time counter that increases based on a master clock, time consistency based on the same time standard can be secured for a plurality of heterogeneous data, such as analog signals, digital signals, and communication signals.

[0024] According to one embodiment of the present invention, by directly capturing the global time counter value at the time of event detection in an FPGA-based processing unit to generate a time tag, the time of event occurrence can be accurately recorded while minimizing the impact of processing delay or transmission delay that may occur during the data collection process.

[0025] According to one embodiment of the present invention, by arranging a plurality of heterogeneous data in chronological order based on time tags, the timing of occurrence between data collected from different data generation paths can be accurately compared or analyzed, thereby improving the temporal consistency of data throughout the system.

[0026] According to one embodiment of the present invention, by including a clock domain crossing circuit in an FPGA-based processing unit to synchronize data generated in different clock domains based on a master clock, meta-stability issues that may occur during the data transfer process between clock domains can be mitigated and stable data processing can be performed.

[0027] According to one embodiment of the present invention, by combining and transmitting data corresponding to a time tag in the form of a packet, data alignment and analysis based on the same time standard can be performed in external systems as well, thereby improving data interoperability between systems.

[0028] According to one embodiment of the present invention, by expressing the time of event occurrence based on a global time counter, precise time information regarding the time of data occurrence can be provided without relying on a high sampling rate, thereby enabling efficient utilization of system resources and precise time synchronization. Brief explanation of the drawing

[0029] FIG. 1 is a block diagram showing the overall configuration of a deterministic communication and precision time synchronization system according to one embodiment of the present invention. FIG. 2 is a timing diagram for explaining the event-based time tag generation process according to one embodiment of the present invention. FIG. 3 is a block diagram showing the internal configuration of an FPGA-based processing unit according to one embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of a clock domain crossing circuit according to one embodiment of the present invention. FIG. 5 is a block diagram showing a time tag-based data packet structure according to one embodiment of the present invention. FIG. 6 is a flowchart illustrating the processing process of a deterministic communication and precise time synchronization method according to one embodiment of the present invention. Specific details for implementing the invention

[0030] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, in describing the present invention, descriptions of already known configurations or functions will be omitted to clarify the gist of the present invention.

[0031] The terms used herein are for describing specific embodiments and are not intended to limit the invention. Additionally, the singular form in this specification may include the plural form unless the context clearly indicates otherwise.

[0032] The attached drawings are intended solely to facilitate an understanding of the concept of the present invention and should not be interpreted as limiting the scope of the invention. Additionally, relative thicknesses, lengths, or sizes in the drawings may be exaggerated for convenience and clarity of explanation.

[0033] FIG. 1 is a block diagram showing the overall configuration of a deterministic communication and precision time synchronization system according to one embodiment of the present invention.

[0034] Referring to FIG. 1, a deterministic communication and precision time synchronization system (100) according to one embodiment of the present invention may include a clock generation unit (110), a global time counter (120), and an FPGA-based processing unit (130).

[0035] The clock generation unit (110) may be configured to generate a master clock that serves as the operating reference of the system. The master clock may be used as a common time reference within the system and may be provided as an operating reference signal for the global time counter (120). The clock generation unit (110) may be configured to include at least one of a crystal oscillator, a temperature-compensated crystal oscillator (TCXO), an oven-controlled crystal oscillator (OCXO), a phase-locked loop (PLL) based clock generator, or an external reference clock receiving circuit.

[0036] The clock generation unit (110) may directly generate a single clock according to the precision required by the system, or it may be configured to generate multiple internal operation clocks through division or multiplication after generating a reference clock.

[0037] For example, the clock generation unit (110) can generate a master clock of 100 MHz and allow each function block within the FPGA-based processing unit (130) to operate based on the master clock. As another example, the clock generation unit (110) may be configured to generate an internal master clock after aligning the phase with a reference clock provided from an external test device or a higher-level controller.

[0038] The global time counter (120) can be configured to increase its counter value according to the master clock generated by the clock generation unit (110). For example, the global time counter (120) can be configured to increase its counter value according to the period of the master clock and can provide a time reference commonly used throughout the system. The global time counter (120) can be configured to operate as a free-running counter and can form a single time axis for the entire system by maintaining a counter value that increases continuously after a reset.

[0039] The global time counter (120) can have a width of 64 bits or more, and accordingly, the time of event occurrence can be reliably identified while minimizing the impact of counter overflow even in a long-term operation environment. For example, when a master clock of 100 MHz is applied, the global time counter (120) can provide a time resolution of 10 ns, and can provide sufficient time identification precision even in a high-speed control environment with a control cycle of 1 kHz to 5 kHz.

[0040] The global time counter (120) is not merely a means of indicating the passage of time, but can function as key reference information for arranging heterogeneous data input from different paths on the same time axis by being used as a reference value for generating time tags as described later.

[0041] The FPGA-based processing unit (130) may be configured to receive a plurality of heterogeneous data, such as analog signals, digital signals, and communication signals. The FPGA-based processing unit (130) may detect an event associated with each of the plurality of heterogeneous data, and may generate a time tag using the counter value of the global time counter (120) at the time the event is detected.

[0042] Specifically, the FPGA-based processing unit (130) can detect an event corresponding to the completion of ADC conversion in relation to an analog signal, and can detect an event corresponding to a state change such as a rising edge, a falling edge, a level change, a pulse generation, or a trigger input in relation to a digital signal, and can detect an event corresponding to a frame start, frame end, specific header detection, packet reception completion, or valid data interval detection in relation to a communication signal.

[0043] That is, the FPGA-based processing unit (130) may be configured to define the time of completion of acquisition, the time of effective change, or the time of completion of communication processing for each data of different nature as an event reference point, and to generate a time tag by referencing the counter value of the same global time counter (120) for each reference point.

[0044] At this time, the FPGA-based processing unit (130) can be configured to perform event detection and time tag generation by internal FPGA logic circuits without the intervention of the central processing unit or operating system scheduling, thereby reducing the impact of interrupt delay, buffer copy delay, or task scheduling delay that may occur in a software-based structure.

[0045] The FPGA-based processing unit (130) can be configured to sort multiple heterogeneous data according to the same time standard based on the generated time tag. This allows data of different forms to be sorted based on the time of occurrence, and ensures time consistency of the data throughout the system.

[0046] Meanwhile, the analog signal, digital signal, and communication signal may be input from different data generation paths or devices, and the FPGA-based processing unit (130) may detect an event corresponding to each signal and generate a time tag for the corresponding data.

[0047] For example, the analog signal may be a sensor signal related to pressure, temperature, acceleration, voltage, current, displacement, flow rate, or vibration, the digital signal may be a switch input, relay status, interlock signal, pulse signal, threshold exceedance signal, or fault detection signal, and the communication signal may be frame data transmitted and received through serial communication, industrial fieldbus communication, a dedicated communication protocol, or a test equipment interface.

[0048] In addition, the communication signal may be processed according to a communication protocol such as SDLC, in which case the FPGA-based processing unit (130) can generate a time tag corresponding to the end of the frame or the completion of reception while performing frame processing based on a hardware state machine. Accordingly, the deterministic communication and precise time synchronization system (100) according to one embodiment of the present invention is not limited to a simple data collection device, but can be applied to various fields such as a test and measurement system, a control system, an aerospace weapon system test system, a HILS (Hardware-In-the-Loop Simulation) system, an industrial automation system, a robot control system, a vehicle electronics test system, or a multiple sensor fusion system.

[0049] The FPGA-based processing unit (130) may be configured to internally include at least one of an event detection unit, a time tag generation unit, a data alignment unit, a delay correction unit, a buffer management unit, a communication processing unit, a state machine unit, and a clock domain crossing circuit.

[0050] For example, the event detection unit can detect the edge of an input signal or the end of a frame, the time tag generation unit can generate a time tag by capturing the global time counter value at the time of event detection, and the delay correction unit can calculate a more accurate time tag by adding a correction value corresponding to the internal processing delay time. As another example, the data sorting unit can store the data corresponding to the generated time tag in a buffer and then rearrange it according to chronological order, and the communication processing unit can perform interpretation of the communication frame and extraction of packet-unit data.

[0051] These detailed blocks may be implemented as a single integrated logic circuit or separated into independent blocks by function, and some functions may be omitted or combined with other functions as needed.

[0052] Furthermore, a deterministic communication and precision time synchronization system (100) according to one embodiment of the present invention may further include a clock domain crossing circuit (see "340" in FIG. 3) to reliably process data generated by different clock signals. In this case, the clock domain crossing circuit may be configured to include at least one of a synchronization flip-flop, an asynchronous FIFO (First-In-First-Out), a pointer synchronization circuit, a Gray code conversion circuit, or a metastability relaxation circuit.

[0053] For example, the ADC may operate in the first clock domain, the communication interface may operate in the second clock domain, and the alignment logic of the FPGA-based processing unit (130) may operate in the master clock domain. In this case, the clock domain crossing circuit may be configured to safely transmit data generated in each domain based on the master clock. Through this, the deterministic communication and precision time synchronization system (100) of the present invention can stably integrate and process multiple heterogeneous data sources while maintaining a single time reference.

[0054] Meanwhile, a deterministic communication and precision time synchronization system (100) according to one embodiment of the present invention may be configured to combine heterogeneous data corresponding to a time tag into a packet form and output it to an external system. In this case, the packet may include at least one of a time tag field, a data type field, a data field, a status field, a channel identifier field, an error detection field, or a sequence number field.

[0055] For example, even if pressure sensor data, ignition trigger signal, and communication response frame data generated in the same test section are collected independently, they are provided to an external system in the form of packets containing time tags corresponding to each data, so that the external system can reconstruct the data on a single time axis during the post-processing stage.

[0056] In addition, the deterministic communication and precise time synchronization system (100) according to one embodiment of the present invention can secure precise time consistency without an excessive increase in the amount of processing data by adopting a structure that generates a time tag based on a global time counter value at the time of event occurrence, rather than a method of unconditionally increasing a high sampling rate.

[0057] For example, instead of excessively increasing the sampling rate of analog channels to obtain the same temporal resolution, the system can be configured to generate time tags at the time of actual event occurrence, thereby reducing memory bandwidth, storage capacity, and processing load while still securing the necessary temporal resolution. This enables the coexistence of efficient operation of system resources and time alignment accuracy, particularly in test and measurement environments or high-speed control loop environments.

[0058] In addition, the deterministic communication and precision time synchronization system (100) according to one embodiment of the present invention can provide a basis for numerically analyzing and reproducing the time relationship between different heterogeneous data, going beyond merely verifying whether a function is operating. For example, the delay between the time of transmission of a specific control command and the time of occurrence of an actual analog response, the correlation between the time of arrival of a communication response frame after the generation of a digital interlock signal, or the order of occurrence of abnormal signs among multiple sensors can all be analyzed based on the same time standard.

[0059] Accordingly, the deterministic communication and precision time synchronization system (100) according to one embodiment of the present invention is not a simple data collection system, but can be implemented as a time-matching-based data processing platform that can contribute to improving test reliability, improving the precision of fault cause analysis, improving the precision of control performance verification, and improving the accuracy of determining event causality.

[0060] FIG. 2 is a timing diagram for explaining the event-based time tag generation process according to one embodiment of the present invention.

[0061] Referring to FIGS. 1 and FIGS. 2, in the deterministic communication and precision time synchronization system (100) of the present invention, a global time counter (120) operates based on a master clock, and a time tag can be generated using the counter value at the time an event occurs.

[0062] Specifically, the clock generation unit (110) can generate a master clock that serves as a reference time signal for the system, and the global time counter (120) can operate such that the counter value increases sequentially according to the master clock. For example, as shown in FIG. 2, the value of the global time counter can increase sequentially as 0, 1, 2, 3, 4, 5, 6, 7, 8 according to each clock cycle of the master clock.

[0063] Meanwhile, the FPGA-based processing unit (130) can detect events related to the input signal. For example, the event may occur in response to the completion of the conversion of an analog signal, a change in the state of a digital signal, or the completion of the reception of a communication signal.

[0064] In the example illustrated in FIG. 2, an event signal may occur at a point in time when the value of the global time counter corresponds to 5. The FPGA-based processing unit (130) may generate a time tag by capturing the counter value of the global time counter (120) at the time the event is detected. Thus, "5," which is the counter value corresponding to the time of the event occurrence, may be generated as a time tag. The generated time tag may subsequently be stored or transmitted together with data corresponding to the event, thereby allowing the occurrence times of different data to be compared or aligned according to the same time standard.

[0065] In this way, the deterministic communication and precise time synchronization system (100) according to one embodiment of the present invention can secure precise time consistency based on the same time standard for different types of data by directly expressing the time at which an event occurs as the counter value of a global time counter.

[0066] FIG. 3 is a block diagram showing the internal configuration of an FPGA-based processing unit according to one embodiment of the present invention.

[0067] Referring to FIG. 3, the FPGA-based processing unit (130) may be configured to include an event detection unit (310), a time tag generation unit (320), a data alignment unit (330), and a clock domain crossing circuit (340).

[0068] The event detection unit (310) may be configured to detect events related to a plurality of heterogeneous data input into the system. For example, the event may occur in response to the completion of conversion of an analog signal, a change in the state of a digital signal, or the completion of reception of a communication signal. The event detection unit (310) may determine whether such an event has occurred and transmit an event occurrence signal to the time tag generation unit (320).

[0069] The time tag generation unit (320) may be configured to generate a time tag by capturing the counter value of the global time counter (120) at the time when an event is detected by the event detection unit (310). Additionally, the time tag generation unit (320) may generate a time tag by adding a correction value corresponding to the internal system delay time to the counter value as needed. Through this, more accurate time information regarding the time of event occurrence can be generated.

[0070] The data sorting unit (330) may be configured to sort a plurality of heterogeneous data according to the same time standard based on the generated time tag. For example, the data sorting unit (330) may include a buffer for storing data corresponding to the time tag in chronological order, and may sort data input from different data generation paths in chronological order using the buffer.

[0071] A clock domain crossing circuit (340) can be used to convert data generated by different clock signals into a signal synchronized with the master clock. For example, the clock domain crossing circuit (340) may include an asynchronous FIFO (First-In-First-Out), thereby mitigating metastability issues that may occur during the data transfer process between different clock domains.

[0072] In this way, the FPGA-based processing unit (130) performs event detection, time tag generation, data alignment, and clock domain synchronization functions, thereby ensuring time consistency according to the same time standard for multiple heterogeneous data such as analog signals, digital signals, and communication signals.

[0073] FIG. 4 is a block diagram showing the configuration of a clock domain crossing circuit according to one embodiment of the present invention.

[0074] Referring to FIG. 4, the clock domain crossing circuit (340) may have a structure for performing data transfer between different clock domains and may be configured to include, for example, a synchronization circuit (410) and an asynchronous FIFO (420).

[0075] Specifically, some data within the system may be generated in clock domain A, and this data needs to be transferred to clock domain B, which operates based on the master clock. In this case, since direct data transfer between different clock domains can cause metastability issues, a clock domain crossing circuit (340) may be used.

[0076] The synchronization circuit (410) is a circuit for synchronizing a signal before transmitting a signal generated in clock domain A to clock domain B, and can be configured, for example, using multiple stages of flip-flops. This can mitigate metastability problems that may occur due to asynchronously input signals.

[0077] The asynchronous FIFO (420) can be used as a buffer for transferring data between different clock domains. For example, data generated in clock domain A can be written to the asynchronous FIFO (420), and then the data can be read from clock domain B, which operates based on the master clock. Through this structure, stable data transfer between different clock domains can be made possible.

[0078] Additionally, the asynchronous FIFO (420) can manage data writing and reading operations using write pointers and read pointers, and said pointers can be synchronized using a Gray code method. Through this, errors that may occur during the pointer synchronization process can be reduced and the stability of data delivery can be improved.

[0079] In this way, the clock domain crossing circuit (340) can mitigate problems that may occur during the data transfer process between different clock domains and support stable processing of data based on the master clock throughout the system.

[0080] FIG. 5 is a block diagram showing a time tag-based data packet structure according to one embodiment of the present invention.

[0081] Referring to FIG. 5, a data packet (500) according to one embodiment of the present invention may include a time tag field (510), a data type field (520), a data field (530), and a status / control field (540).

[0082] The time tag field (510) may include time information indicating the time at which an event occurred. The time tag may be generated based on the counter value of the global time counter (120) and may have a length of, for example, 64 bits or more. The time tag field (510) enables the time at which data occurs to be identified according to a time standard commonly used throughout the system.

[0083] The data type field (520) may contain information about what kind of data the data is. For example, the data type field (520) may indicate the type of data, such as analog data, digital input data, or communication data. Through this, the receiving system can distinguish the type of data included in the data packet and perform an appropriate processing procedure.

[0084] The data field (530) may include actual measured or collected data. For example, the data field (530) may include a measurement value obtained from an analog sensor, status information of a digital input signal, or a data frame received through a communication interface.

[0085] The status / control field (540) may include status information or control information related to the data packet. For example, the status / control field (540) may include whether the data is valid, an error status, event occurrence channel information, or a packet sequence number.

[0086] The FPGA-based processing unit (130) can form a data packet (500) by combining data corresponding to a time tag generated during the event detection and time tag generation process. The data packet (500) can be transmitted to an external system, and the external system can sort or analyze multiple data according to the same time standard based on time information included in the time tag field (510).

[0087] In this way, the data packet structure according to one embodiment of the present invention is configured to include both a time tag and data, thereby enabling data alignment and analysis based on accurate time standards even for heterogeneous data generated from different data generation paths.

[0088] FIG. 6 is a flowchart illustrating the processing process of a deterministic communication and precise time synchronization method according to one embodiment of the present invention.

[0089] Referring to FIG. 6, in step (610), the clock generation unit (110) can generate a master clock that is used as a reference time signal of the system. The master clock is a reference clock that is commonly used throughout the system and can be used as a reference signal for a global time counter to increase its counter value.

[0090] Next, in step (620), the FPGA-based processing unit (130) can detect events associated with each of a plurality of heterogeneous data, such as analog signals, digital signals, and communication signals. For example, the event may occur in response to the completion of conversion of an analog signal, a change in the state of a digital signal, or the completion of reception of communication data.

[0091] Next, in step (630), the FPGA-based processing unit (130) can generate a time tag using the counter value of a global time counter that increases according to the master clock at the time when an event is detected. The time tag can be used as time information indicating the time when the event occurred.

[0092] Next, in step (640), the FPGA-based processing unit (130) can sort multiple heterogeneous data according to the same time standard based on the generated time tags. For example, the data can be sorted in chronological order by comparing the time of occurrence of the data based on the time tag corresponding to each data.

[0093] Through such a processing method, according to one embodiment of the present invention, precise time alignment based on the same time standard can be secured for different forms of data, such as analog signals, digital signals, and communication signals.

[0094] Although the present invention has been described in detail through preferred embodiments, it is obvious to those skilled in the art that the present invention is not limited to the aforementioned preferred embodiments and can be modified and varied in various ways without departing from the spirit and scope of the invention. Accordingly, such modifications or variations should be deemed to fall within the scope of the claims of the present invention. Explanation of the symbols

[0095] 110: Clock generation unit 120: Global Time Counter 130: FPGA-based processing unit 310: Event detection unit 320: Time Tag Generation Section 330: Data alignment section 340: Clock domain crossing circuit 410: Synchronizer 420: Asynchronous FIFO 500: Data packet 510: Time Tag Field 520: Data type field 530: Data field 540: Status / Control Field

Claims

Claim 1 In a deterministic communication and precision time synchronization system for ensuring time consistency of a plurality of heterogeneous data including analog signals, digital signals and communication signals, a clock generation unit for generating a master clock; and a global time counter configured such that a counter value increases according to the master clock;The system includes an FPGA-based processing unit configured to detect events related to each of the plurality of heterogeneous data, generate a time tag using the counter value at the time the event is detected, and align each of the plurality of heterogeneous data according to the same time standard based on the time tag; the global time counter is configured such that the counter value increases sequentially for each clock cycle of the master clock, and is composed of a counter of 64 bits or more to stably identify the time of event occurrence while minimizing the impact of counter overflow even in a long-term operation environment; it is used as a reference value in generating the time tag for placing the plurality of heterogeneous data input from different paths on the same time axis; the FPGA-based processing unit detects an event corresponding to the time of completion of ADC conversion in relation to analog signals, detects an event corresponding to a state change such as a rising edge, falling edge, level change, pulse generation, or trigger input in relation to digital signals, and detects an event corresponding to frame start, frame end, detection of a specific header, completion of packet reception, or detection of a valid data interval in relation to communication signals; and the FPGA-based processing unit internally within the FPGA without intervention by the central processing unit or operating system scheduling. A deterministic communication and precision time synchronization system configured to perform detection of the event and generation of the time tag by a logic circuit, wherein the FPGA-based processing unit includes a clock domain crossing circuit that converts data generated by different clock signals into a signal synchronized with the master clock so as to transmit data generated in each domain based on the master clock during the data transfer process between different clock domains. Claim 2 delete Claim 3 A deterministic communication and precision time synchronization system according to claim 1, wherein the FPGA-based processing unit captures the counter value of the global time counter at the time when the event is detected and generates the time tag. Claim 4 A deterministic communication and precise time synchronization system according to claim 1, wherein the FPGA-based processing unit generates the time tag by adding a correction value corresponding to the system internal delay time to the counter value at the time when the event is detected. Claim 5 A deterministic communication and precision time synchronization system according to claim 1, wherein the FPGA-based processing unit includes a buffer for aligning data corresponding to the time tag in chronological order. Claim 6 delete Claim 7 A deterministic communication and precision time synchronization system according to claim 1, characterized in that the clock domain crossing circuit includes an asynchronous FIFO (First-In-First-Out). Claim 8 A deterministic communication and precision time synchronization system according to claim 1, characterized in that the FPGA-based processing unit is configured to perform communication data processing by a hardware state machine inside the FPGA.

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