Support shielding structures for trench-type semiconductor devices

Abstract

A power semiconductor device comprises a semiconductor layer structure including a drift region of a first conductivity type and a gate trench extending into the drift region. The gate trench includes sidewalls and a bottom surface between them. A bottom shielding structure of a second conductivity type is provided below the bottom surface of the gate trench. The first and second supporting shielding structures of the second conductivity type extend into the drift region from opposite sides of the gate trench and are spaced apart from the sidewalls. The material composition of the bottom shielding structure, the distance of extension into the drift region relative to the surface of the semiconductor layer structure, and / or the dopant concentration may differ from those of the first and second supporting shielding structures. Related devices and manufacturing methods are also discussed.

Description

Technology Field

[0001] Claim of priority

[0002] This application claims priority to U.S. Patent Application No. 17 / 703,708 filed March 24, 2022, the disclosure of which is incorporated herein by reference.

[0003] field

[0004] The present invention relates to semiconductor devices, and more specifically, to power semiconductor devices. Background Technology

[0005] Power semiconductor devices refer to devices comprising one or more "power" semiconductor dies designed to carry large currents (e.g., tens or hundreds of amperes) and / or block high voltages (e.g., hundreds, thousands, or tens of thousands of volts). A wide variety of power semiconductor devices are known in the art, including, for example, power metal-insulator semiconductor field-effect transistors ("MISFETs"), metal-oxide semiconductor FETs ("MOSFETs"), bipolar junction transistors ("BJTs"), insulated gate bipolar transistors ("IGBTs"), junction barrier Schottky diodes, gate turn-off transistors ("GTOs"), MOS-controlled thyristors, and various other devices. These power semiconductor devices are generally fabricated from wide-bandgap semiconductor materials, for example, silicon carbide ("SiC") or group III nitride (e.g., gallium nitride ("GaN"))-based semiconductor materials. Here, a wide bandgap semiconductor material refers to a semiconductor material having a bandgap greater than about 1.40 eV, for example, greater than about 2 eV.

[0006] A conventional power semiconductor device typically has a semiconductor substrate having a first conductivity type (e.g., an n-type substrate) on which an epitaxial layer structure having a first conductivity type (e.g., an n-type) is formed. A portion of this epitaxial layer structure (which may include one or more distinct layers) functions as a drift layer or drift region of the power semiconductor device. The device typically includes an "active region" comprising one or more "unit cell" structures having a junction, e.g., a pn junction. The active region may be formed on and / or within the drift region. The active region acts as a main junction to block voltage in the reverse bias direction and provide current flow in the forward bias direction. The power semiconductor device may also have an edge termination in a termination region adjacent to the active region. One or more power semiconductor devices may be formed on the substrate, and each power semiconductor device will typically have its own edge termination. After the substrate is fully processed, the resulting structure may be diced to separate the individual edge-terminated power semiconductor devices.

[0007] Power semiconductor devices may have a unit cell configuration in which multiple individual unit cell structures in an active region are electrically connected (e.g., in parallel) to function as a single power semiconductor device. In high-power applications, such power semiconductor devices may include thousands or tens of thousands of unit cells implemented on a single chip or "die." A die or chip may comprise a small block of semiconductor material or other substrate on which electronic circuit elements are manufactured. For example, multiple individual power semiconductor devices may be formed on a relatively large semiconductor substrate (e.g., by doping selected regions with dopants, forming insulating and metal layers thereon, and growing epitaxial layers thereon), and the finished structure may then be cut into multiple individual dies (e.g., by sawing or dicing operations), each of which is a power semiconductor device.

[0008] Power semiconductor devices may have a lateral structure or a vertical structure. In a device having a lateral structure, the terminals of the device (e.g., drain, gate, and source terminals for a power MOSFET device) are on the same main surface (e.g., top or bottom) of the semiconductor layer structure. In contrast, in a device having a vertical structure, at least one terminal is provided on each main surface of the semiconductor layer structure (e.g., in a vertical MOSFET device, the source may be on the top surface of the semiconductor layer structure and the drain may be on the bottom surface of the semiconductor layer structure). The semiconductor layer structure may or may not include an underlying substrate. In this specification, the term "semiconductor layer structure" refers to a structure comprising one or more semiconductor layers, including semiconductor substrates and / or semiconductor epitaxial layers.

[0009] Vertical power semiconductor devices, such as MOSFETs or IGBTs, can have a standard gate electrode design in which the transistor's gate electrode is formed on top of the semiconductor layer structure, or alternatively, a gate electrode embedded in a trench within the semiconductor layer structure. Devices with embedded gate electrodes are typically referred to as gate trench devices. In a standard gate electrode design, the channel region of each unit cell transistor is positioned horizontally beneath the gate electrode. In contrast, in a gate trench design, the channel is positioned vertically. Gate trench devices can provide enhanced performance but typically require more complex manufacturing processes.

[0010] Power semiconductor devices are designed to block large voltages and / or currents (in forward or reverse blocking states) or pass them (in forward operating states). For example, in the blocking state, a power semiconductor device may be designed to maintain a potential of hundreds or thousands of volts. As the applied voltage approaches or exceeds the voltage level for which the device is designed to block, non-trivial levels of current (referred to as leakage current) may begin to flow through the power semiconductor device. The device's blocking capability may be a function, among other things, of the doping density / concentration and thickness of the drift region. Leakage currents may also occur due to other reasons, such as failures at the device's edge terminations and / or main junction. If the voltage applied to the device increases to a critical level beyond the breakdown voltage, the increasing electric field can lead to the generation of uncontrollable and undesirable runaway charge carriers within the semiconductor device, resulting in a condition known as avalanche breakdown.

[0011] In addition, a relatively thin gate insulating layer (e.g., a gate oxide layer) separating the gate electrode from the semiconductor layer structure can degrade when high electric field levels are applied to the gate insulating layer during on-state (conduction) or off-state (blocking) operation. This degradation of the gate insulating layer can ultimately lead to the breakdown of the gate insulating layer, at which point the gate electrode can cause a short circuit in the semiconductor layer structure, which can destroy the device. means of solving the problem

[0012] According to some embodiments, a power semiconductor device comprises: a semiconductor layer structure including a drift region of a first conductivity type; a gate trench extending into the drift region—the gate trench includes sidewalls and a bottom surface between them—; a bottom shielding structure of a second conductivity type below the bottom surface of the gate trench; and first and second supporting shielding structures of a second conductivity type extending into the drift region on opposite sides of the gate trench and spaced apart from the sidewalls.

[0013] In some embodiments, one or more of the first and second support shielding structures extend into a drift region at a depth different from the depth of the bottom shielding structure relative to the surface of the semiconductor layer structure.

[0014] In some embodiments, the first and second support shielding structures extend beyond the bottom shielding structure into the drift region by about 0.1 to about 1 μm.

[0015] In some embodiments, at least one of the bottom shielding structure, the first support shielding structure, or the second support shielding structure comprises a material different from the material of the drift area.

[0016] In some embodiments, the drift region comprises a wide bandgap semiconductor material, and at least one of the bottom shielding structure, the first support shielding structure, or the second support shielding structure comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide.

[0017] In some embodiments, at least one of the bottom shielding structure, the first support shielding structure, or the second support shielding structure further includes an injected portion of the drift area.

[0018] In some embodiments, the bottom shielding structure comprises dopants of a second conductivity type at a first concentration, and the first and second supporting shielding structures comprise dopants of a second conductivity type at a second concentration different from the first concentration.

[0019] In some embodiments, the second concentration is higher than the first concentration.

[0020] In some embodiments, the semiconductor layer structure further comprises a substrate, and the substrate comprises a drift region thereon and a second conductivity type well region on or within the drift region facing the substrate. The first and second supporting shielding structures extend through the well region and beyond the bottom shielding structure and are spaced apart from the substrate.

[0021] In some embodiments, the first and second supporting shielding structures have dopants of a second conductivity type at different concentrations from the well region.

[0022] In some embodiments, the first and second support shielding structures are spaced apart from the substrate by about 1 to about 100 μm.

[0023] In some embodiments, the bottom shielding structure extends along a portion of the bottom surface of the gate trench.

[0024] In some embodiments, the bottom shielding structure extends along the entire bottom surface of the gate trench.

[0025] According to some embodiments, a power semiconductor device comprises: a semiconductor layer structure including a drift region of a first conductivity type; a gate trench extending into the drift region—the gate trench includes sidewalls and a bottom surface between them—; a bottom shielding structure of a second conductivity type below the bottom surface of the gate trench; and first and second supporting shielding structures of a second conductivity type extending into the drift region on opposite sides of the sidewalls of the gate trench and spaced apart from the sidewalls of the gate trench. The material composition of the bottom shielding structure, the distance of extension into the drift region relative to the surface of the semiconductor layer structure, and / or the dopant concentration are different from those of the first and second supporting shielding structures.

[0026] In some embodiments, the extension distance into the drift region of one or more of the first and second support shielding structures is greater than the extension distance of the bottom shielding structure to the surface of the semiconductor layer structure.

[0027] In some embodiments, the first and second support shielding structures extend beyond the bottom shielding structure into the drift region by about 0.1 to about 1 μm.

[0028] In some embodiments, the material composition of at least one of the bottom shielding structure, the first support shielding structure, or the second support shielding structure is different from the material composition of the drift region.

[0029] In some embodiments, the drift region comprises a wide bandgap semiconductor material, and at least one of the bottom shielding structure, the first support shielding structure, or the second support shielding structure comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide.

[0030] In some embodiments, at least one of the bottom shielding structure, the first support shielding structure, or the second support shielding structure further includes an injected area of ​​the drift area.

[0031] In some embodiments, the dopant concentrations of the first and second supporting shielding structures are lower than the dopant concentration of the bottom shielding structure.

[0032] In some embodiments, the dopant concentrations of the first and second supporting shielding structures are higher than the dopant concentration of the bottom shielding structure.

[0033] In some embodiments, the semiconductor layer structure further comprises a substrate including a drift region thereon, and the first and second supporting shielding structures are spaced apart from the substrate by about 1 to about 100 μm.

[0034] According to some embodiments, a method for manufacturing a power semiconductor device comprises: providing a semiconductor layer structure including a drift region of a first conductivity type; forming first and second support shielding structures of a second conductivity type that extend into a bottom shielding structure and a drift region; and forming a gate trench that extends into the drift region and is spaced apart from the first and second support shielding structures, wherein the bottom shielding structure is below the gate trench.

[0035] In some embodiments, the step of forming the gate trench is performed after forming the bottom shielding structure.

[0036] In some embodiments, the step of forming a bottom shielding structure and first and second support shielding structures includes forming one or more of the first and second support shielding structures that extend into a drift region at a depth different from the depth of the bottom shielding structure with respect to the surface of the semiconductor layer structure.

[0037] In some embodiments, the first and second support shielding structures extend beyond the bottom shielding structure into the drift region by about 0.1 to about 1 μm.

[0038] In some embodiments, the step of forming at least one of the bottom shielding structure or the first and second support shielding structures includes the step of performing one or more etching operations to form each shielding trench in the drift region; and the step of performing one or more deposition operations to form a material different from the material of the drift region in each shielding trench.

[0039] In some embodiments, the drift region comprises a wide bandgap semiconductor material, and at least one of the bottom shielding structure or the first and second supporting shielding structures comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide.

[0040] In some embodiments, the step of forming a bottom shielding structure or at least one of the first and second support shielding structures further includes the step of performing one or more ion implantation operations to inject dopants of the second conductivity type into portions of the drift region below each shielding trench.

[0041] In some embodiments, the step of forming a bottom shielding structure or at least one of the first and second support shielding structures includes the step of performing one or more ion implantation operations to inject dopants of the second conductivity type into the drift region.

[0042] In some embodiments, in response to one or more ion implantation operations, the bottom shielding structure comprises a first concentration of dopants of a second conductivity type, and the first and second supporting shielding structures comprise a second concentration of dopants of a second conductivity type different from the first concentration. The second concentration may be higher than the first concentration.

[0043] According to some embodiments, a method for manufacturing a power semiconductor device comprises: providing a semiconductor layer structure including a drift region of a first conductivity type; forming first and second support shielding structures of a second conductivity type extending into the drift region; forming a gate trench extending into the drift region and spaced apart from the first and second support shielding structures—the gate trench includes sidewalls and a bottom surface between them—; and forming a bottom shielding structure of a second conductivity type below the bottom surface of the gate trench.

[0044] In some embodiments, the step of forming a bottom shielding structure includes, after forming a gate trench, performing one or more ion implantation and / or deposition operations to form a bottom shielding structure that extends into a drift region to a first depth with respect to the surface of the semiconductor layer structure.

[0045] In some embodiments, the material composition of the bottom shielding structure, the extension distance into the drift region on the surface of the semiconductor layer structure, and / or the dopant concentration are different from those of the first and second supporting shielding structures.

[0046] In some embodiments, the step of forming first and second support shielding structures includes forming one or more of the first and second support shielding structures that extend into a drift region up to a second depth with respect to the surface of the semiconductor layer structure before forming a gate trench, wherein the second depth is different from the first depth.

[0047] In some embodiments, the second depth is about 0.1 to about 1 μm larger than the first depth.

[0048] In some embodiments, the step of forming first and second support shielding structures includes, before forming a gate trench, performing one or more etching operations to form each shielding trench in a drift region, and performing one or more deposition operations to form each shielding trench with a material different from the material of the drift region.

[0049] In some embodiments, the drift region comprises a wide bandgap semiconductor material, and at least one of the bottom shielding structure or the first and second support shielding structures comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide.

[0050] In some embodiments, the step of forming the first and second support shielding structures further includes the step of performing one or more ion implantation operations to implant dopants of the second conductivity type into portions of the drift region under each shielding trench before forming the gate trench.

[0051] In some embodiments, the step of forming the first and second support shielding structures includes the step of performing one or more ion implantation operations to inject dopants of the second conductivity type into the drift region before forming the gate trench.

[0052] In some embodiments, in response to one or more ion implantation operations, the first and second supporting shielding structures comprise a second concentration of dopants of a second conductivity type that is different from a first concentration of dopants of a second conductivity type of the bottom shielding structure. The second concentration is higher than the first concentration.

[0053] Other devices, apparatuses, and / or methods according to some embodiments will become apparent to a person skilled in the art upon review of the following drawings and detailed description. In addition to any and all combinations of the above embodiments, all such additional embodiments are intended to be incorporated within this description, within the scope of the invention, and protected by the appended claims. Brief explanation of the drawing

[0054] FIG. 1a is a schematic cross-sectional view illustrating an exemplary unit cell of a gate trench power semiconductor device including shielded regions located below gate trenches. FIG. 1b is a schematic cross-sectional view illustrating an exemplary unit cell of a gate trench power semiconductor device including shielded regions located below and along one sidewall of the gate trenches. FIG. 2 is a schematic cross-sectional view illustrating an exemplary unit cell of a gate trench power semiconductor device according to some embodiments of the present invention, comprising bottom shielding structures below gate trenches and support shielding structures spaced apart from the sidewalls of gate trenches. FIGS. 3a, FIGS. 3b, FIGS. 3c, and FIGS. 3d are schematic cross-sectional views illustrating exemplary unit cells of gate trench power semiconductor devices comprising bottom shielding structures and supporting shielding structures in various combinations of different dopant concentrations, depths, and / or material compositions according to some embodiments of the present invention. FIGS. 4a, FIGS. 4b, FIGS. 4c, and FIGS. 4d are schematic cross-sectional views illustrating exemplary unit cells of gate trench power semiconductor devices including bottom shielding structures and support shielding structures of different dopant concentrations and different material compositions according to some embodiments of the present invention. FIGS. 5A, FIGS. 5B, FIGS. 5C, FIGS. 5D, FIGS. 5E, and FIGS. 5F are schematic cross-sectional views illustrating exemplary manufacturing operations for forming power semiconductor devices including bottom shielding structures below gate trenches and support shielding structures spaced apart from the sidewalls of gate trenches, according to some embodiments of the present invention. FIGS. 6a, FIGS. 6b, FIGS. 6c, FIGS. 6d, FIGS. 6e, FIGS. 6f, FIGS. 6g, and FIGS. 6h are schematic cross-sectional views illustrating exemplary manufacturing operations for forming power semiconductor devices including bottom shielding structures below gate trenches and support shielding structures spaced apart from the sidewalls of gate trenches, according to additional embodiments of the present invention. FIGS. 7a, FIGS. 7b, FIGS. 7c, FIGS. 7d, FIGS. 7e, FIGS. 7f, FIGS. 7g, and FIGS. 7h are schematic cross-sectional views illustrating exemplary manufacturing operations for forming power semiconductor devices including bottom shielding structures below gate trenches and support shielding structures spaced apart from the sidewalls of gate trenches, according to other embodiments of the present invention. FIGS. 8a, FIGS. 8b, FIGS. 8c, FIGS. 8d, FIGS. 8e, FIGS. 8f, FIGS. 8g, and FIGS. 8h are schematic cross-sectional views illustrating exemplary manufacturing operations for forming power semiconductor devices including bottom shielding structures below gate trenches and support shielding structures spaced apart from the sidewalls of gate trenches, according to other embodiments of the present invention. Specific details for implementing the invention

[0055] Some embodiments of the present invention relate to improvements in power semiconductor devices (e.g., MOSFETs, IGBTs, and other gate-controlled power devices). Many power semiconductor devices include so-called deep or 'buried' shielded semiconductor regions, also referred to as shielding structures, which have a different conductivity type from the layer(s) of semiconductor material beneath the well regions and / or gate electrodes of the device. For example, in devices having gate electrodes and gate insulating layers formed within trenches of a semiconductor layer structure, high electric fields can degrade the gate insulating layer over time and eventually lead to device failure. Therefore, deep shielding structures may be provided beneath the gate trenches to reduce electric field levels in the gate insulating layer, particularly at the corners of the gate trenches where electric field levels may be more concentrated. The shielding structures may have the same conductivity type as the well regions, opposite to the conductivity type of the drift regions.

[0056] Deep shielding structures may typically include highly doped semiconductor regions having the same conductivity type as the channel region. Methods for doping a semiconductor material with n-type and / or p-type dopants include (1) doping the semiconductor material during growth, (2) diffusing the dopants into the semiconductor material, and (3) using ion implantation to selectively implant the dopants into the semiconductor material. When silicon carbide is doped during epitaxial growth, the dopants tend to accumulate non-uniformly, and thus the dopant concentration can vary, for example, by + / -15%, which can have a negative impact on device operation and / or reliability. Additionally, doping by diffusion may not be selectable in silicon carbide, gallium nitride, and various wide bandgap semiconductor devices because n-type and p-type dopants tend not to diffuse well (or at all) in these materials even at high temperatures.

[0057] From the above perspective, ion implantation is often used to dope broad-bandgap semiconductor materials such as silicon carbide. However, in gate-trench vertical power devices (also referred to herein as trench-type vertical power devices or trench-type gate devices), it may be desirable to form deep shielding structures beneath the well regions of the device and / or the gate electrodes, and these deep shielding structures often extend into the device to depths of about 1-3 μm or more. The depth to which ions are implanted is directly related to the energy of the implantation, that is, ions implanted into the semiconductor layer at higher energies tend to go deeper into the layer.

[0058] Therefore, forming deep shielding structures through ion implantation may require high-energy implantation. However, when dopant ions are implanted into a semiconductor layer, they damage the crystal lattice of the semiconductor layer. This lattice damage can typically be repaired only partially by thermal annealing processes. In other words, lattice damage caused by the ion implantation process may not be fully repaired. Furthermore, the amount of lattice damage can also be directly related to the implantation energy, and higher-energy implantations tend to cause more lattice damage than lower-energy implantations. The uniformity of dopant concentration also tends to decrease as the implantation depth increases.

[0059] Various approaches can be used to form trench-type vertical power semiconductor devices. Figures 1a and 1b schematically illustrate two examples of these different approaches.

[0060] FIGS. 1A and 1B are schematic cross-sectional views illustrating exemplary unit cells of trench-type vertical power devices (exemplified as power MOSFETs (100a and 100b), respectively) comprising deep buried P-type shielded regions (140a, 140b). As shown in FIGS. 1A and 1B, each of the power MOSFETs (100a, 100b) is highly doped (e.g., N + ) includes a first conductivity type (e.g., n-type) substrate (110). Low concentration doped (e.g., N - A first conductivity type drift layer or region (120) is provided on a substrate (110), for example, by epitaxial growth. In some embodiments, the drift region (120) may be a wide bandgap semiconductor material (such as silicon carbide (SiC)). For example, the substrate (110) may be a 4H-SiC substrate, and the drift region (120) may be a 4H-SiC n-type epitaxial layer formed on the substrate (110). A portion of the drift region (120) may include a first conductivity type current diffusion layer ("CSL") (185) having a higher dopant concentration than the lower portions of the drift region (120). A medium-concentration doped second conductivity type (e.g., p-type) layer is formed on or within the drift region (120) (e.g., by epitaxial growth or injection) and acts as well regions (e.g., "P-wells") (170) for the device (100a, 100b). A high-concentration doped second conductivity type (e.g., P + Regions (174) are formed in the well regions (170), for example, through ion implantation. Transistor channels or conduction paths (178) may be formed in the medium-concentration doped regions of the P-wells (170). The medium-concentration doped layer forming the substrate (110), the drift region (120) (including the current diffusion layer (185)), and the P-wells (170) is included in the semiconductor layer structure (106) of the MOSFETs (100a, 100b), along with various regions / patterns formed therein.

[0061] Referring still to FIGS. 1a and 1b, trenches (180) are formed in the semiconductor layer structure (106) as ‘stripe-type’ gate trench layouts in which the trenches (180) extend continuously parallel to each other in the longitudinal direction. The trenches (180) are spaced laterally intersecting (e.g. perpendicular thereto) the longitudinal direction and extend vertically into the drift region (120) toward the substrate (110). The trenches (180) (where the gate electrodes (184) are formed) may be formed to extend through a medium-concentration doped layer (170) to form each P-well. A high-concentration doped (e.g., P + ) Second conductivity type shielding structures (140a, 140b) are formed in the drift region (120), for example, by ion implantation. The shielding structures (140a, 140b) can be electrically connected to the P-wells (170). A gate insulating layer (182) (e.g., gate oxide) is formed conformally on the bottom surface and sidewalls of each trench (180). Although otherwise illustrated, the corners of the gate trench (180) and the gate insulating layer (182) above it may be rounded.

[0062] A gate electrode (184) (or "gate") is formed on each gate insulating layer (182) to fill each gate trench (180). A portion of the drift region (120) below and / or adjacent to the gate electrode (184) may be referred to as a "JFET region" (175). Vertical transistor channel regions (conduction (178) is shown by dashed arrows) are formed in well regions (170) adjacent to the gate insulating layer (182). A first conductivity type (e.g., N + High-concentration doped source regions (160) of ) are formed in the upper portions of the P-wells (170), for example, through ion implantation. A second conductivity type (e.g., P +The highly doped regions (174) of the well regions (170) are in contact with the well regions (170). Source contacts (190) are formed on the source regions (160), on the highly doped regions (174), and on the deep shielding structures (140b) (in FIG. 1b). The source contacts (190) may be ohmic metals in some embodiments. Drain contacts (192) are formed on the lower surface of the substrate (110). Gate contacts (not shown) may be electrically connected to each gate electrode (184) by, for example, a conductive gate bus (not shown). An intermetallic dielectric layer (186) may be formed on the gates (184), and a metal (e.g., aluminum) layer (196) may be formed on the intermetallic dielectric layer (186) to contact the source contacts (190). The source contacts (190) may extend onto an intermetallic dielectric layer (186) in some embodiments and may include, for example, diffusion barriers and / or adhesive layers.

[0063] As previously mentioned, some devices may be susceptible to premature oxide breakdown due to electric field concentration effects near the corners of the gate trench (180). In the examples of FIGS. 1a and 1b, deep buried semiconductor regions or shielding patterns (140a, 140b) of opposite conductivity type to the drift region (120) are configured to prevent degradation of the trench MOSFET (100a, 100b) in high electric fields. In particular, in the exemplary devices (100a and 100b), the shielding patterns (140a, 140b) at the bottom (in FIG. 1a) of the gate trenches (180) or along one sidewall (in FIG. 1b) are configured to provide an electric field (e.g., voltage and / or current) that is blocked by connections to each source contact (190) connected to ground. The shielded connection patterns may be connected to source contacts (190) at the top of the device (100a, 100b) to allow the deep shielded patterns (140a, 140b) to be electrically grounded (or otherwise connected to the deep shielded patterns (140a, 140b)).

[0064] The shielding patterns (140a, 140b) may extend from the bottom surfaces of the gate trenches (180) to one lower corner region (in FIG. 1b) or both lower corner regions (in FIG. 1a). Since the gate insulation layer (182) may be particularly vulnerable to destruction in the corner regions, the shielding patterns (140a, 140b) may help protect the gate insulation layer (182) in the lower corner region(s) of the gate trenches (180) from high electric fields during reverse blocking operation.

[0065] FIG. 1a illustrates a bottom-gating shielding (BPS_TMOS) configuration of a shielding pattern (140a) that allows for aggressive cell pitch reduction and increased sidewall conductivity utilization. In particular, in FIG. 1a, conduction (178) (indicated by dashed arrows) occurs along both sides of a channel within the device (100a). However, the structure of the device (100a) illustrated in FIG. 1a may be difficult to manufacture due to masking and / or other operations required to block or protect the sidewalls of the trench (180) during the injection process used to form the shielding pattern (140a).

[0066] For more reliable on- and off-state performance and / or improved robustness, FIG. 1b illustrates a contact method having an asymmetric shielding (APS_TMOS) configuration, wherein the shielding pattern (140b) extends along only one sidewall of the trench (180) and thus, there is no shielding pattern (140b) on the other sidewall of the trench (180). However, this configuration may limit the active conductive area of ​​the device (100b) by blocking conduction (178) on one side of the channel.

[0067] Embodiments of the present invention relate to power semiconductor devices comprising layouts and design arrangements that further improve reliability by forming a shielded region (240a, 340a, 340a') (also referred to herein as bottom shielded structure (240a, 340a, 340a')) at the bottom of the gate trench (180) in combination with additional supporting shielding structures or regions (240b, 340b, 340b') that are on opposite sides of the sidewalls of the gate trench (180) and spaced apart therefrom. The shielding structures (240a / 240b, 340a / 340b, 340a' / 340b') are opposite to or second to the first conductivity type (e.g., n-type) of the drift region (120) or second conductivity type (e.g., p-type). Although the present specification has been described and illustrated by reference to regions of specific first and second conductivity types (i.e., n-type and p-type), it will be understood that the conductivity types of the regions in any of the illustrated examples may be reversed (i.e., p-type and n-type) according to embodiments of the present invention. Likewise, although the present specification has been described primarily by reference to MOSFET implementations, it will be understood that the same techniques may be used in other vertical power semiconductor devices, such as insulated gate bipolar transistors (IGBTs), and / or other related power devices utilizing trench-type structures.

[0068] In some embodiments, support shielding structures or regions are provided adjacent to the JFET portions (175) of the drift region (120) below the gate trench (180) and / or adjacent thereto. FIG. 2 is a schematic cross-sectional view illustrating an exemplary unit cell of a power semiconductor device (200) according to some embodiments of the present invention, comprising bottom shielding structures (240a) below the gate trenches (180) and support shielding structures (240b) spaced apart from the sidewalls of the gate trenches (180). Elements, layers, or regions similar to those of the semiconductor layer structure (106) described herein are indicated by similar numbers.

[0069] As illustrated in FIG. 2, in a trench-type vertical power semiconductor device (200), the JFET region (175) may include upper portions of the drift region (120) adjacent to the gate trenches (180) and below the well regions. A main bottom shielding structure (240a) is provided below the bottom surface of the gate trench (180), and first and second supporting shielding structures (240b) are provided on opposite sides of the sidewalls of the gate trench (180) and spaced apart therefrom, so that the JFET regions (175) extend at least partially between each supporting shielding structure (240b) and the bottom shielding structure (240a). The bottom and supporting shielding structures (240a and 240b) (collectively referred to as shielding structures) extend beyond the gate trench (180) toward the substrate (110) (i.e., extend closer to the substrate (110) than to the gate trench (180)). Shielding connection patterns may be connected to the shielding structures (240a, 240b) and source contacts (190) (e.g., at the top of the device (200)), or the source contacts (190) may be connected to the shielding structures (240a, 240b) in a different way to allow the shielding structures (240a, 240b) to be electrically grounded.

[0070] Support shielding structures (240b) may differ from bottom shielding structures (240a) (e.g., in material composition, extension distance or depth from the surface (S) of the semiconductor layer structure (106) toward the substrate (110), and / or dopant concentration) to provide greater protection for the gate insulation layer (182) along the gate trench (180) (e.g., at the corners of the bottom surface of the gate trench (180)) by providing a lower resistance current path under avalanche breakdown conditions. In some embodiments, the support shielding structures (240b) may extend toward the substrate (110) to a depth (D2) substantially equal to the depth (D1) of the bottom shielding structures (240a) (i.e., where D2=D1). In some embodiments, the supporting shielding structures (240b) may extend toward the substrate (110) to a depth (D2) greater than the depth (D1) of the bottom shielding structures (240a). For example, the supporting shielding structures (240b) may extend toward the substrate (110) beyond the bottom shielding structures (240a) by a depth (ΔD) of about 0.1 μm to about 1 μm (e.g., about 0.3 μm to about 0.7 μm, e.g., about 0.5 μm). That is, the difference (ΔD) between the depth (D2) of the supporting shielding structures (240b) and the depth (D1) of the bottom shielding structures (D1) may be about 0.1 μm to about 1 μm. The depths or distances of extension into the drift region (120) as described in this specification may exist along the vertical direction in the drawings and may be relative to the (top) surface (S) of the semiconductor layer structure (106). The depth D2 of the support shielding structures (240b) may be sufficient to reduce or prevent avalanche destruction at the bottom of the gate trench (180).In some embodiments, the support shielding structures (240b) may extend from the surface (S) of the semiconductor layer structure (106) toward the substrate (110) to a depth (D2) of about 1 μm to about 10 μm (e.g., about 3 μm to about 7 μm, e.g., about 5 μm).

[0071] Additionally, in some embodiments, the shapes of the support shielding structures (240b) may differ from those of the bottom shielding structures (240a) and / or the trenches (180). For example, the widths of the support shielding structures (240b) (along the horizontal or lateral direction) may differ from the widths of the trenches (180) (and / or the bottom shielding structures (240a) extending below the trenches (180). That is, while the widths are exemplified as substantially similar, the first and second support shielding structures (240b) may be wider or narrower than the gate trenches (180) in some embodiments.

[0072] Support shielding structures (240b) can form a pn junction (e.g., a body diode) with the drift region (120). The gap (T) between the support shielding structures (240b) and the substrate (110) (e.g., formed by a portion of the drift region (120) between them) can correspond to the breakdown voltage of the device (200). For example, the support shielding structures (240b) and / or the bottom shielding structures (240a) can be separated from the substrate (110) by a gap T of about 1 μm to about 100 μm (e.g., about 30 μm to about 70 μm, e.g., about 50 μm). The gap (T) can vary, for example, based on the materials and / or dopant concentrations of the shielding structures (240a, 240b).

[0073] In some embodiments, the support shielding structures (240b) may have lower resistance than the bottom shielding structures (240a). For example, the support shielding structures (240b) may contact the source contact (190) over a greater length (e.g., along the direction into the page) than the bottom shielding structures (240a), which may be connected only to the source intermittently along its length, thereby reducing resistance. The support shielding structures (240b) may be formed of the same or different material as the bottom shielding structures (240a) and / or with a similar or different dopant concentration. In some embodiments, the shielding structures (240a, 240b) may be formed by one or more injection processes having a substantially uniform concentration or stepwise or continuous grading, and may be extended to contact the source contact (190) for connection to the electrical ground within the unit cell. The support shielding structures (240b) are approximately 1 x 10 17 to about 1 x 10 20 cm -3 , for example, about 5 x 10 17 Up to about 5 x 10 19 cm -3 , or about 1 x 10 18 to about 1 x 10 19 cm -3 The concentration of dopants of the second conductivity type may be included. The dopant concentration of the support shielding structures (240b) may be higher than the dopant concentration of the well regions (170) (e.g., more than about 10 times higher; e.g., more than about 100 times higher), and may be similar to or higher than the dopant concentration of the bottom shielding structures (240a). The dopant concentrations of the shielding structures (240a, 240b) may vary based on the implementation of the manufacturing process and / or device design, for example, as illustrated in the shielding structures (340a, 340b) of the method embodiments of FIGS. 5a to 5f and FIGS. 6a to 6h.

[0074] In some embodiments, the shielding structures (240a, 240b) may be formed of materials different from the drift region (120), for example, semiconductor materials having a lower resistance than the semiconductor material of the drift region (120). For example, in embodiments where the drift region (120) is an n-type material (e.g., SiC), the supporting shielding structures (240b) and / or the bottom shielding structures (240a) may be p-type material(s) (e.g., nickel oxide (p-NiO), polysilicon (poly-Si), gallium nitride (p-GaN), gallium oxide (p-Ga2O3)). In embodiments where the drift region (120) is a p-type material, the supporting shielding structures (240b) and / or the bottom shielding structures (240a) may be n-type material(s) (e.g., n-SiC, n-Si, n-GaN). Accordingly, forming shielding structures (240a and / or 240b) of different materials of opposite conductivity type with the drift region (120) can form each pn heterojunction or body diode within the drift region (120).

[0075] Shielding structures formed of different material(s) forming heterojunctions with the drift region (120) may also have different ability to withstand repeated failure events (compared to injected shielding structures). For example, heterojunction-based shielding structures (also described herein with reference to shielding structures (340a' and 340b')) may be formed to provide lower resistance and / or extend to greater depths than injection-based shielding structures (e.g., shielding structures (340a and 340b) in this specification) to increase effectiveness. That is, compared to injection-based shielding regions, heterojunction-based shielding structures may provide advantages with respect to resistance and / or depth control (i.e., may be formed to have lower resistance and / or greater depth than injection-based shielding structures).

[0076] Additionally or alternatively, the supporting shielding structures (240b) may be formed of materials different from the bottom shielding structures (240a). For example, as illustrated in the shielding structures (340a, 340b and 340a', 340b') of the device embodiments of FIGS. 3c through 3d and FIGS. 4a through 4d, the bottom shielding structures (240a) may be the injected regions of the drift region (120) (and thus may be the same material), whereas the supporting shielding structures (240b) may be formed of a material different from the drift region (120), or vice versa. Forming shielding structures (240a and / or 240b) of different materials may provide improved protection of the gate insulation layer (182). For example, forming support shielding structures (240b) of different materials of the second conductivity type (e.g., p-NiO, p-poly-Si, p-GaN, p-Ga2O3) is the second conductivity type (e.g., P + Some of the injected bottom shielding structures (240a) of the regions may have lower resistance (in some cases, several orders of magnitude lower), and thus provide a lower resistance current path under avalanche breakdown conditions. That is, the shielding structures (240a, 240b) may be formed of materials different from and / or different from the drift region (120).

[0077] The shape and / or depth of the supporting shielding structures (240b) may also allow variations in the shape and / or depth of the bottom shielding structures (240a) while still providing the desired avalanche destruction characteristics. For example, in some embodiments, due to the greater protection of the gate oxide (182) provided by the supporting shielding structures (240b), the bottom shielding structure (240a) may extend along only a portion of the bottom surface of the gate trench (180) (i.e., it may be narrower), which may increase the available area for conduction (178) at the bottom corners of the gate trench (180) (so that the JFET region (175) may extend below the outer edges of the gate trench (180) in addition to following the trench sidewalls). In contrast, in some embodiments, the bottom shielding structure (240a) may extend along the entire bottom surface of the gate trench (180) (or extend laterally or more widely thereover), and the dopant concentration of the JFET region (175) may be increased to maintain the desired conduction (178). The width of the bottom shielding structure (240a) (i.e., the width along the bottom of the gate trench (180)) may be changed based on the masking, injection, deposition, and / or other manufacturing operations used to form the shielding structures (240a and 240b).

[0078] More generally, the supporting shielding structures (240b) may be formed with a different depth, dopant concentration, and / or material than the bottom shielding structures (240a), and one or more of these may be configured to reduce or prevent avalanche destruction at the bottom of the gate trench (180). Exemplary unit cells of power semiconductor devices (300a-300d and 400a-400d) comprising various combinations of bottom shielding structures (340a, 340a') and supporting shielding structures (340b, 340b') are illustrated in FIGS. 3a to 3d and FIGS. 4a to 4d.

[0079] In the examples of FIGS. 3a through 3d and FIGS. 4a through 4d, a simplified semiconductor layer structure (106) (e.g., without JFET regions (175), CSL (185), etc.) is illustrated for convenience of illustration, but it can be understood that these and other well-known elements are present, although not specifically illustrated. Likewise, elements, layers, and / or regions of devices (300a-300d and 400a-400d) similar to those discussed above are indicated by similar numbers, and descriptions of these elements, layers, and / or regions may be omitted for brevity. Bottom shielding structures (340a, 340a') and supporting shielding structures (340b, 340b') may each include characteristics similar to those of bottom shielding structures (240a) and supporting shielding structures (240b), respectively, unless otherwise noted.

[0080] In particular, as illustrated in FIG. 3a, the power semiconductor device (300a) includes bottom shielding structures (340a) and supporting shielding structures (340b) provided by injected regions of a second conductivity type (e.g., p-type) in a first conductivity type drift region (120) (e.g., n-type). The supporting shielding structures (340b) may differ from the bottom shielding structures (340a) (e.g., in extension depth toward the substrate (110) and / or dopant concentration) depending on the manufacturing processes used. For example, a first ion implantation process may be performed to form bottom shielding structures (340a) having a first depth (D1) and a first concentration of second conductivity type dopants, and a second ion implantation process may be performed to form supporting shielding structures (340b) having a second depth (D2) (e.g., greater than the first depth (D1)) and a second concentration of second conductivity type dopants (e.g., less than the first concentration). In embodiments where the supporting shielding structures (340b) are implanted regions (as in FIG. 3a, FIG. 3c and FIG. 4a), the supporting shielding structures (340b) can effectively provide high-concentration doped regions (174) of the second conductivity type that can be omitted. In FIG. 3a, the bottom shielding structure (340a) is illustrated as being narrower than the bottom surface of the gate trench (180) (i.e., extending only partially along it), but depending on the manufacturing processes used, it may be the same as or wider than the bottom surface of the gate trench (180). Methods for manufacturing a device (300a) including the injected bottom shielding structures (340a) and supporting shielding structures (340b) are discussed below with reference to FIGS. 5a through 5f and FIGS. 6a through 6h.

[0081] As illustrated in FIG. 3b, the power semiconductor device (300b) includes supporting shielding structures (340b') of one or more different materials from the bottom shielding structures (340a') and the drift region (120). In particular, the bottom shielding structures (340a') and the supporting shielding structures (340b') include materials of a second conductivity type (e.g., p-type) and thereby form respective heterojunctions with the first conductivity type drift region (120) (e.g., n-type). For example, the drift region (120) may be formed of an n-type material (e.g., SiC), and the bottom shielding structures (340a') and the supporting shielding structures (340b') may be formed of p-type materials (e.g., p-NiO, p-poly-Si, p-GaN, p-Ga2O3) using one or more deposition operations. The supporting shielding structures (340b') may differ from the bottom shielding structures (340a') (e.g., in the extension depth toward the substrate (110) and / or material composition) depending on the manufacturing processes used. For example, in some embodiments, the bottom shielding structures (340a') may be formed from a first material having a first depth (D1) using a first etching and deposition process, and the supporting shielding structures (340b') may be formed from a second material having a second depth (D2) (e.g., greater than the first depth (D1)) using a second etching and deposition process (e.g., identical or different from the first material), so that the shielding structures (340a' and 340b) may be formed from different materials and / or different depths (e.g., the bottom shielding structures (340a') may be p-poly-Si and the supporting shielding structures (340b') may be p-NiO).In embodiments where supporting shielding structures (340b') form heterojunctions with a drift region (120) (as in FIG. 3b, FIG. 3d, and FIG. 4b, FIG. 4c, and FIG. 4d), the supporting shielding structures (340b'), the high-concentration doped regions (174), and the source regions (160) may each have a contact (e.g., an ohmic contact) with a source contact (190). Methods for manufacturing a device (300b) comprising bottom shielding structures (340a') and supporting shielding structures (340b') forming heterojunctions with a drift region (120) are discussed below with reference to FIG. 7a through 7f and FIG. 8a through 8h.

[0082] FIG. 3c illustrates a power semiconductor device (300c) comprising supporting shielding structures (340b) provided by injected regions of a second conductivity type (e.g., p-type) in combination with bottom shielding structures (340a') of a second conductivity type material(s) different from a first conductivity type drift region (120) (e.g., n-type), and thus, a material(s) different from the injected supporting shielding structures (340b). The bottom shielding structures (340a') form heterojunctions with the drift region (120) below the bottom surfaces of the gate trenches (180'). Support shielding structures (340b) and bottom shielding structures (340a') can be formed using different manufacturing operations (e.g., ion implantation and deposition, respectively), and thus the depth D2 of the support shielding structures (340b) may be the same as or different from the depth D1 of the bottom shielding structures (340a') depending on each manufacturing process used.

[0083] FIG. 3d illustrates a power semiconductor device (300d) comprising bottom shielding structures (340a) provided by injected regions of a second conductivity type (e.g., p-type) in combination with supporting shielding structures (340b') of a second conductivity type material(s) different from a first conductivity type drift region (120) (e.g., n-type). The supporting shielding structures (340b') are on opposite sides of the sidewalls of the gate trench (180) and form heterojunctions with the drift region (120) spaced apart from the sidewalls. Support shielding structures (340b') and bottom shielding structures (340a) can be formed using different manufacturing operations (e.g., deposition and ion implantation, respectively), and thus, the depth D2 of the support shielding structures (340b') may be the same as or different from the depth D1 of the bottom shielding structures (340a), depending on the respective manufacturing processes used. In FIG. 3d, the bottom shielding structure (340a) is illustrated as being wider than the bottom surface of the gate trench (180) (i.e., extending laterally beyond it), but depending on the manufacturing processes used, it may be the same as or narrower than the bottom surface of the gate trench (180).

[0084] FIG. 4a illustrates a power semiconductor device (400a) comprising support shielding structures (340b) provided by implanted regions of a second conductivity type (e.g., p-type), first bottom shielding structure portions (340a) provided by implanted regions of the second conductivity type, and second bottom shielding structure portions (340a') of a second conductivity type material(s) different from the drift region (120). The second bottom shielding structure portions (340a') form heterojunctions with the drift region (120) below the bottom surfaces of the gate trenches (180'). The support shielding structures (340b) and the second bottom shielding structure portions (340a') may be formed using different manufacturing operations (e.g., ion implantation and deposition, respectively). Support shielding structures (340b) and first bottom shielding structure portions (340a) may be formed using the same or different injection operations. As such, the depth D2 and / or dopant concentration of the support shielding structures (340b) may be the same as or different from the depth D1 and / or dopant concentration of the first bottom shielding structure portions (340a), depending on the manufacturing processes used. Likewise, in FIG. 4a, the first bottom shielding structure portions (340a) are illustrated as being narrower than the bottom surfaces of the gate trenches (180'), for example, but may be the same as or wider than the bottom surfaces of the gate trenches (180') depending on the manufacturing processes used.

[0085] FIG. 4b illustrates a power semiconductor device (400b) comprising first support shielding structure portions (340b) provided by second conductivity type injected regions. The second support shielding structure portions (340b') as well as the bottom shielding structures (340a') comprise a second conductivity type material(s) different from the first conductivity type drift region (120). The bottom shielding structures (340a') and the second support shielding structure portions (340b') form heterojunctions with the drift region (120) (subordinate to the bottom surfaces of the gate trenches (180') and laterally spaced from the opposing sidewalls of the gate trenches (180'), respectively). The lower shielding structures (340a') and the second supporting shielding structure portions (340b') may be formed using the same or different manufacturing operations (e.g., the same or different deposition steps), and thus, depending on the manufacturing processes used, they may be the same or different from each other (e.g., in the extension depth toward the substrate (110) and / or in the material composition). The first supporting shielding structure portions (340b) may be formed using manufacturing operations different from the shielding structures (340a', 340b'), (e.g., one or more ion implantation processes). The depth (D2) of the first supporting shielding structure portions (340b) may be the same or different from the depth (D1) of the lower shielding structures (340a'), depending on the manufacturing processes used.

[0086] FIG. 4c illustrates a power semiconductor device (400c) comprising bottom shielding structures and supporting shielding structures, each comprising injected and heterojunction regions. In particular, each of the bottom shielding structures and supporting shielding structures comprises first portions (340a and 340b) provided by injected regions of a second conductivity type, and second portions (340a' and 340b') of a second conductivity type material(s) different from the drift region (120). The second portions (340a' and 340b') form heterojunctions with the drift region (120) (subordinate to the bottom surfaces of the gate trench (180') and laterally spaced from the opposing sidewalls of the gate trench (180')). The first portions (340a and 340b) extend from the second shielding structure portions (340a' and 340b') toward the substrate (110) to depths (D1 and D2), respectively. The first portions (340a and 340b) may be formed using the same or different manufacturing operations (e.g., the same or different ion implantation processes), and thus, depending on the manufacturing processes used, they may be the same or different from each other (e.g., in the depth of extension toward the substrate (110) and / or dopant concentration). The second portions (340a' and 340b') may be formed using the same or different manufacturing operations (e.g., the same or different deposition steps), and thus, depending on the manufacturing processes used, they may be the same or different from each other (e.g., in the depth of extension toward the substrate (110) and / or material composition). In this way, the depth (D2) of the first and second parts (340b and 340b') of the support shielding structures may be the same as or different from the depth (D1) of the first and second parts (340a and 340a') of the bottom shielding structures.In FIG. 4c, the first portion (340a) of the bottom shielding structures is illustrated as being wider than the bottom surface of the gate trench (180') (i.e. extending laterally beyond it), but depending on the manufacturing processes used, it may be the same as or narrower than the bottom surface of the gate trench (180').

[0087] FIG. 4d illustrates a power semiconductor device (400d) comprising bottom shielding structures (340a) provided by injected regions of a second conductivity type (e.g., p-type). First supporting shielding structure portions (340b) are provided by injected regions of the second conductivity type, and second supporting shielding structure portions (340b') are formed of a second conductivity type material(s) different from the first conductivity type drift region (120). The second supporting shielding structure portions (340b') form heterojunctions with the drift region (120) which is laterally spaced from the opposing sidewalls of the gate trenches (180). The bottom shielding structures (340a) and the first support shielding structure portions (340b) may be formed using the same or different manufacturing operations (e.g., the same or different ion implantation processes), and thus, depending on the manufacturing processes used, they may be the same or different from each other (e.g., in the extension depth toward the substrate (110) and / or dopant concentration). The second support shielding structure portions (340b') may be formed using manufacturing operations different from the shielding structures (340a, 340b) (e.g., one or more ion implantation processes). The depth (D2) of the first and second support shielding structure portions (340b and 340b') may be the same or different from the depth (D1) of the bottom shielding structure (340a).

[0088] FIGS. 5a through 5f are schematic cross-sectional views illustrating exemplary manufacturing operations for forming power semiconductor devices including bottom shielding structures below gate trenches and support shielding structures spaced apart from the sidewalls of gate trenches, according to some embodiments of the present invention. In particular, FIGS. 5a through 5f illustrate methods for forming shielding structures (340a, 340b) as injected regions, wherein the bottom shielding structure (340a) is formed before forming the gate trench (180), which may be referred to herein as a pre-trench shielding injection process.

[0089] As illustrated in FIG. 5a, a semiconductor layer structure (106) is provided. The semiconductor layer structure (106) includes, as previously described, a drift region (120) of a first conductivity type (e.g., n-type), a current diffusion layer (185), a JFET region (175), a well region (170), and a source region (160). Highly doped regions (174) of a second conductivity type are exemplified but may be omitted in embodiments where supporting shielding structures (340b) are formed as injected regions. The semiconductor layer structure (106) may include a substrate (110) and / or other layers. A mask layer (501) is formed on the surface (S) of the semiconductor layer structure (106), and a patterning layer (502) is formed on the mask layer (501).

[0090] In FIG. 5b, the mask layer (501) is patterned (e.g., by photolithography) using a patterning layer (502) to form an injection mask pattern (501') that includes openings therein that expose portions of the surface (S) of the semiconductor layer structure (106). In FIG. 5c, one or more ion implantation processes (500) are performed to form shielding structures (340a and 340b) that extend into the drift region (120) toward the substrate (100) by injecting dopants of a second conductivity type (e.g., p-type) into the exposed portions of the surface (S) using the mask pattern (501') as an injection mask. The injection amount and / or injection energy of the injection process(s) (500) can be controlled to form shielding structures (340a and 340b) having desired dopant concentrations and / or depths (e.g., D1 and D2) for the surface (S) (e.g., having higher injection energies resulting in greater depths). The dopant concentrations of the shielding structures (340a and / or 340b) can be substantially uniform or graded (e.g., stepwise or continuous).

[0091] Examples of FIGS. 5a through 5c illustrate a single mask (501') and a high-energy ion implantation process (500) for forming bottom shielding structures (340a) and supporting shielding structures (340b) simultaneously or in the same process step so that the shielding structures (340a, 340b) can have the same dopant concentrations and / or the same depths (i.e., D1 = D2) with respect to the surface (S) of the semiconductor layer structure (106). However, it will be understood that the embodiments described herein are not limited to a single masking and / or injection process, and that multiple masking and injection operations may be performed sequentially with different mask shapes to expose different parts of the surface (S), different injection energies, and / or different injection amounts (e.g., one or more of FIG. 5a, FIG. 5b, or FIG. 5c may be repeated or repeated), and thus the bottom shielding structures (340a) and supporting shielding structures (340b) may have different shapes, different depths (i.e., D1 ≠ D2), and / or different dopant concentrations.

[0092] In FIG. 5d, the mask (501') is removed, and an etching mask layer (503) (e.g., an oxide layer) is formed on the surface (S) of the semiconductor layer structure (106), and a patterning layer (504) is formed on the etching mask layer (503). In FIG. 5e, the etching mask layer (503) is patterned using the patterning layer (504) to form an etching mask pattern (503') that contains openings that expose portions of the surface (S) of the semiconductor layer structure (106) between the support shielding structures (340b). In FIG. 5f, an etching process (550) is performed to selectively etch portions of the surface (S) exposed by an etching mask pattern (503'), thereby forming gate trenches (180) that extend into and are spaced apart from the drift region (120) between the supporting shielding structures (340b). The bottom shielding structures (340a) extend below the bottom surface of the gate trenches (180) and at least partially along it. The mask pattern (503') is removed, and a gate oxide layer (182), a gate electrode (184), source contacts (190), an intermetallic dielectric (186), and a metal layer (196) are subsequently formed to provide the device (300a) of FIG. 3a.

[0093] In the exemplary operations of FIGS. 5a through 5f, the support shielding structures (340b) and the bottom shielding structures (340a) are formed using the same injection process(s) (500) before forming the gate trenches (180). Thus, the support shielding structures (340b) and the bottom shielding structures (340a) may have the same or substantially similar depths and dopant concentrations. However, due to the etching of the gate trench (180) into the bottom shielding structure (340a) formed by the pre-trench injection process, the distribution of dopants within the bottom shielding structure (340a) (from the bottom surface of the trench (180) toward the substrate (110)) may be more abrupt than that of the support shielding structures (340b) (from the surface S toward the substrate (110)).

[0094] FIGS. 6a through 6h are schematic cross-sectional views illustrating exemplary manufacturing operations for forming power semiconductor devices including bottom shielding structures below gate trenches and support shielding structures spaced apart from the sidewalls of the gate trenches, according to further embodiments of the present invention. In particular, FIGS. 6a through 6h illustrate methods for forming shielding structures (340a, 340b) as injected regions formed after the gate trench (180), wherein the bottom shielding structure (340a) is formed, which may be referred to herein as a post-trench shielding injection process.

[0095] As illustrated in FIG. 6a, a semiconductor layer structure (106) is provided. The semiconductor layer structure (106) includes, as previously described, a drift region (120) of a first conductivity type (e.g., n-type), a current diffusion layer (185), a JFET region (175), a well region (170), and a source region (160). Highly doped regions (174) of a second conductivity type are exemplified but may be omitted in embodiments where supporting shielding structures (340b) are formed as injected regions. The semiconductor layer structure (106) may include a substrate (110) and / or other layers. A mask layer (601) is formed on the surface (S) of the semiconductor layer structure (106), and a patterning layer (602) is formed on the mask layer (601).

[0096] In FIG. 6b, the mask layer (601) is patterned (e.g., by photolithography) using a patterning layer (602) to form an injection mask pattern (601') that includes openings therein that expose portions of the surface (S) of the semiconductor layer structure (106). In FIG. 6c, one or more ion implantation processes (600) are performed to form support shielding structures (340b) that extend into the drift region (120) toward the substrate (100) by injecting dopants of a second conductivity type (e.g., p-type) into the exposed portions of the surface (S) using the mask pattern (601') as an injection mask. The injection amount and / or injection energy of the implantation process(s) (600) can be controlled to form support shielding structures (340b) having desired dopant concentrations and / or desired depths (e.g., D2) for the surface (S). The dopant concentrations of the support shielding structures (340b) can be substantially uniform or graded (e.g., stepwise or continuous).

[0097] In FIG. 6d, the mask (601') is removed, and an etching mask layer (603) (e.g., an oxide layer) is formed on the surface (S) of the semiconductor layer structure (106), and a patterning layer (604) is formed on the etching mask layer (603). In FIG. 6e, the etching mask layer (603) is patterned using the patterning layer (604) to form an etching mask pattern (603') that includes openings therein that expose portions of the surface (S) of the semiconductor layer structure (106) between the support shielding structures (340b). In FIG. 6f, an etching process (650) is performed to selectively etch parts of the surface (S) exposed by the etching mask pattern (603'), thereby forming gate trenches (180) that extend into and are spaced apart from the drift region (120) between the support shielding structures (340b).

[0098] In FIG. 6g, a mask (655) (e.g., an oxide mask) is formed on the sidewalls of the gate trenches (180) and on the bottom surface. For example, the trenches (180) may be oxidized and / or a coating may be deposited along the sidewalls and bottom surface of the gate trenches (180) to form the mask (655). In some embodiments, portions of the mask (655) on the sidewalls may be formed thicker than portions of the mask (655) on the bottom surface of the gate trenches (180) to protect the conductive sidewalls of the trenches (180) from an injection process to form a shielding structure (340a).

[0099] In FIG. 6h, one or more ion implantation processes (600') are performed to form bottom shielding structures (340a) extending below and at least partially along the bottom surface of the gate trenches (180) by injecting dopants of a second conductivity type into the bottom surface of the trenches (180) using a mask (655) as an injection mask. The injection amount and / or injection energy of the implantation process(s) (600') can be controlled to form bottom shielding structures (340a) having desired dopant concentrations and / or desired depths (e.g., D1) with respect to the surface (S) and / or substantially uniform or graded dopant concentrations. The mask (655) is removed, and a gate oxide layer (182), a gate electrode (184), source contacts (190), an intermetallic dielectric (186), and a metal layer (196) are subsequently formed to provide the device (300a) of FIG. 3a.

[0100] In the exemplary operations of FIGS. 6a through 6h, a first high-energy injection (600) is used to form supporting shielding structures (340b) before forming gate trenches (180), and bottom shielding structures (340a) are formed using a second high-energy injection (600'). The injection amount and / or injection energy of the second injection (600') may be the same as or different from that of the first injection (600). Thus, the operations illustrated in FIGS. 6a through 6h may be advantageous in terms of ease of forming supporting shielding structures (340b) having depths, concentrations, and / or materials different from those of the bottom shielding structures (340a). For example, the use of multiple injection processes (600 and 600') may allow for the selection of different injection energies and / or dopant profiles for each of the first and second injection processes to form supporting shielding structures (340b) that extend to a greater depth and / or different dopant concentrations than, for example, the bottom shielding structures (340a). For example, the bottom shielding structures (340a) may be formed individually with a dopant concentration similar to or lower than that of the supporting shielding structures (340b). The formation of the bottom shielding structure (340a) after the formation of the gate trench (180) may also result in a similar (e.g., Gaussian) distribution of dopants across the depths of the shielding structures (340a and 340b) (from the bottom surface of the trench (180) toward the substrate (110) and from the surface (S) toward the substrate (110), respectively).

[0101] FIGS. 7a through 7h are schematic cross-sectional views illustrating exemplary manufacturing operations for forming power semiconductor devices including bottom shielding structures below gate trenches and support shielding structures spaced apart from the sidewalls of gate trenches, according to other embodiments of the present invention. In particular, FIGS. 7a through 7h illustrate methods for forming shielding structures (340a', 340b') of a material different from the drift region (120), wherein the bottom shielding structure (340a') is formed before forming the gate trench (180'), which may be referred to herein as a pre-trench heterojunction shielding process.

[0102] As illustrated in FIG. 7a, the semiconductor layer structure (106) is provided as described with reference to any of the above embodiments. A mask layer (701) is formed on the surface (S) of the semiconductor layer structure (106), and a patterning layer (702) is formed on the mask layer (701). In FIG. 7b, the mask layer (701) is patterned (e.g., by photolithography) using the patterning layer (702) to form a first etching mask pattern (701') that includes openings therein that expose portions of the surface (S) of the semiconductor layer structure (106).

[0103] In FIG. 7c, one or more etching processes (700) are performed using a first mask pattern (701') as an etching mask to form shielding trenches (780) into exposed portions of the surface (S). The etching processes (700) can be controlled to provide shielding trenches (780) having desired depths (e.g., D1, D2). In FIG. 7d, one or more deposition processes are performed to form a second conductivity type (e.g., p-type) material in the shielding trenches (780), and the second conductivity type material can be removed from the surface (S) of the semiconductor layer structure (106) (e.g., by one or more planarization processes) thereby forming shielding structures (340a' and 340b') that extend into the drift region (120) toward the substrate (100). For example, the drift region (120) can be formed of an n-type material (e.g., SiC), and the shielding structures (340a' and 340b') can be formed of one or more p-type materials (e.g., p-NiO, p-poly-Si, p-GaN, p-Ga2O3).

[0104] Examples of FIGS. 7a through 7d illustrate a single mask (701'), an etching process (700), and a deposition process for forming bottom shielding structures (340a') and supporting shielding structures (340b') simultaneously or in the same process step, so that shielding structures (340a', 340b') can be formed with the same material(s) and / or have the same depths (i.e., D1 = D2) with respect to the surface (S) of the semiconductor layer structure (106). However, it will be understood that the embodiments described herein are not limited to a single masking and / or etching process, and that a number of masking and etching operations may be performed sequentially with different mask shapes to expose different parts of the surface (S), with different etching processes to form shielding trenches (780) of different depths, and / or different deposition processes (e.g., one or more of FIG. 7a, FIG. 7b, FIG. 7c, or FIG. 7d may be repeated or repeated), and thus, the bottom shielding structures (340a') and the supporting shielding structures (340b') may have different shapes, different depths (i.e., D1 ≠ D2), and / or may be formed of different materials (e.g., the bottom shielding structures (340a') may be p-poly-Si and the supporting shielding structures (340b') may be p-NiO).

[0105] In FIG. 7e, a mask layer (703) (e.g., an oxide layer) is formed on the surface (S) of the semiconductor layer structure (106), and a patterning layer (704) is formed on the mask layer (703). In FIG. 7f, the mask layer (703) is patterned using the patterning layer (704) to form a second etching mask pattern (703') that includes openings therein that expose portions of the surface (S) of the semiconductor layer structure (106) (including the surfaces of the lower shielding structures (340a') between the support shielding structures (340b'). In FIG. 7g, an etching process (750) is performed to selectively etch portions of the surface (S) exposed by the etching mask pattern (503'), thereby forming gate trenches (180) that extend into and are spaced apart from the drift region (120) between the supporting shielding structures (340b'). The bottom shielding structures (340a') are maintained below the bottom surface of the gate trenches (180) and at least partially along it. In FIG. 7h, the mask pattern (503') is removed. To provide the device (300b) of FIG. 3b, a gate oxide layer (182), a gate electrode (184), source contacts (190), an intermetallic dielectric (186), and a metal layer (196) may subsequently be formed.

[0106] FIGS. 8a through 8h are schematic cross-sectional views illustrating exemplary manufacturing operations for forming power semiconductor devices including bottom shielding structures below gate trenches and support shielding structures spaced apart from the sidewalls of gate trenches, according to other embodiments of the present invention. In particular, FIGS. 8a through 8h illustrate methods for forming shielding structures (340a', 340b') of a material different from the drift region (120), wherein the bottom shielding structure (340a') is formed after the gate trench (180') and may be referred to herein as a post-trench heterojunction shielding process.

[0107] As illustrated in FIG. 8a, a semiconductor layer structure (106) is provided as described in any of the embodiments above. A mask layer (801) is formed on a surface (S) of the semiconductor layer structure (106), and a patterning layer (802) is formed on the mask layer (801). In FIG. 8b, the mask layer (801) is patterned (e.g., by photolithography) using the patterning layer (802) to form a first etching mask pattern (801') that includes openings therein that expose portions of the surface (S) of the semiconductor layer structure (106).

[0108] In FIG. 8c, one or more etching processes (800) are performed using a first mask pattern (801') as an etching mask to form support shielding trenches (880) extending into exposed portions of the surface (S). The etching processes (800) can be controlled to form support shielding trenches (880) having a desired depth (e.g., D2) with respect to the surface (S). In FIG. 8d, one or more deposition processes are performed to form a material of a second conductivity type (e.g., p-type) in the support shielding trenches (880), and the material of the second conductivity type is removed from the surface (S) (e.g., by one or more planarization processes) to form support shielding structures (340b') extending into a drift region (120) toward the substrate (100). For example, the drift region (120) can be formed of an n-type material (e.g., SiC), and the supporting shielding structures (340b') can be formed of p-type materials (e.g., p-NiO, p-poly-Si, p-GaN, p-Ga2O3).

[0109] In FIG. 8e, an etching mask layer (803) (e.g., an oxide layer) is formed on the surface (S) of the semiconductor layer structure (106), and a patterning layer (804) is formed on the etching mask layer (803). In FIG. 8f, the etching mask layer (803) is patterned using the patterning layer (804) to form a second etching mask pattern (803') that includes openings therein that expose portions of the surface (S) of the semiconductor layer structure (106) between the support shielding structures (340b').

[0110] In FIG. 8g, an etching process (850) is performed to selectively etch parts of the surface (S) exposed by an etching mask pattern (803'), thereby forming gate trenches (180') that extend into and are spaced apart from the drift region (120) between the support shielding structures (340b'). The etching process(s) (850) can be controlled to form support gate trenches (180') having a desired depth (e.g., D1) with respect to the surface (S), which may be the same as or different from the depth (D2) of the support shielding trenches (880).

[0111] In FIG. 8h, one or more optional deposition processes are performed to form a material of a second conductivity type (e.g., p-type) in the gate trenches (180'), thereby forming bottom shielding structures (340a') that extend into the drift region (120) toward the substrate (100). The bottom shielding structures (340a') can partially fill the gate trenches (180'), and thus, the depth of the gate trenches (180') can form the depth D1 of the bottom shielding structures (340a'). Different deposition processes can be performed so that the bottom shielding structures (340a') and the supporting shielding structures (340b') can have different shapes, different depths (i.e., D1 ≠ D2), and / or can be formed from different materials. The second mask pattern (803') is removed, and a gate oxide layer (182), a gate electrode (184), source contacts (190), an intermetallic dielectric (186), and a metal layer (196) are subsequently formed to provide the device (300b) of FIG. 3b.

[0112] In the exemplary operations of FIGS. 8a through 8h, a first etching and deposition process is used to form supporting shielding structures (340b') before forming gate trenches (180'), and a second etching and deposition process is used to form bottom shielding structures (340a') to fill a portion of the gate trenches (180'). Accordingly, the operations illustrated in FIGS. 8a through 8h may be advantageous in terms of ease of forming supporting shielding structures (340b') having different depths and / or materials from the bottom shielding structures (340a'). For example, the use of multiple etching processes (800, 850) and / or multiple deposition processes may allow for the selection of different depths and / or materials so that the supporting shielding structures (340b') extend to a greater depth than the bottom shielding structures (340a') and / or are formed of a lower resistance material.

[0113] It will be understood that any of the operations illustrated in FIGS. 5a through 8h may be combined in various embodiments of this specification. For example, one or more of the pre-trench shielding injection operations of FIGS. 5a through 5f may be performed between one or more of the pre-trench heterojunction shielding operations of FIGS. 7a through 7h, or vice versa. Likewise, one or more of the post-trench shielding injection operations of FIGS. 6a through 6h may be performed between one or more of the post-trench heterojunction shielding operations of FIGS. 8a through 8h, or vice versa. More generally, the manufacturing operations illustrated in FIGS. 5a through 8h are illustrated by reference to forming the injected shielding regions (340a, 340b) of FIG. 3a or the heterojunction shielding regions (340a', 340b) of FIG. 3b, but it will be understood that any of the illustrated operations may be used in combination to provide any desired combination of injected and heterojunction shielding regions, such as any of the structures illustrated in FIGS. 3c through 4d, having similar or different shapes, similar (i.e., D1 = D2) or different (i.e., D1 ≠ D2) depths, and / or having the same or different materials.

[0114] Accordingly, the embodiments described herein illustrate various examples of different combinations of bottom shielding structures (e.g., 240a, 340a, 340a') and supporting shielding structures (e.g., 240b, 340b, 340b') according to the present invention, which may be particularly beneficial for protecting the gate oxide (182) at the bottom surface and edges / corners of the gate trench (180, 180'). However, it will be understood that the embodiments of the present invention may include any and all combinations of the features described herein and are not limited to the examples illustrated. The embodiments of the present invention may be used in trench-type vertical semiconductor power transistors, including but not limited to MOSFETs, IGBTs, or other power devices including transistor terminals within a trench region.

[0115] In the above description, each exemplary embodiment is described with reference to regions of specific conductivity types. It will be understood that in each of the above embodiments, devices of opposite conductivity types can be formed by simply reversing the conductivity of the n-type and p-type layers. Accordingly, it will be understood that the present invention covers both n-channel and p-channel devices for each different device structure (e.g., MOSFET, IGBT, etc.).

[0116] The present invention has been discussed above primarily in relation to silicon carbide-based power semiconductor devices. However, it will be understood that silicon carbide is used as an example in this specification, and that the devices discussed herein can be formed in any suitable broadbandgap semiconductor material system. For example, gallium nitride-based semiconductor materials (e.g., gallium nitride, aluminum gallium nitride, etc.) may be used instead of silicon carbide in any of the aforementioned embodiments. More generally, although discussed with reference to silicon carbide devices, embodiments of the present invention are not so limited and may be applicable to devices formed using other broadbandgap semiconductor materials, e.g., gallium nitride, zinc selenide, or any other II-VI or III-V broadbandgap compound semiconductor materials.

[0117] Embodiments of the present invention have been described above with reference to the accompanying drawings. However, it will be understood that the present invention can be embodied in many different forms and should not be interpreted as being limited to the embodiments described above. Rather, these embodiments are provided to ensure that the disclosure is thorough and complete and will fully convey the scope of the invention to those skilled in the art. Similar numbers refer to similar elements throughout.

[0118] It will be understood that although terms such as first, second, etc. are used throughout this specification to describe various elements, these elements are not to be limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0119] The terms used herein are merely for describing specific embodiments and are not intended to limit the invention. As used herein, singular forms (“a,” “an,” and “the”) are intended to include plural forms unless the context otherwise clearly indicates. It will be further understood that the terms “comprises,” “comprising,” “includes,” and / or “including,” when used herein, specify the presence of the mentioned features, integers, steps, actions, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, components, and / or groups thereof.

[0120] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "on" another element, it will be understood that it may be directly on or extending directly above another element, or that intervening elements may also exist. In contrast, when an element is referred to as being "on" or extending "directly above" another element, no intervening elements exist. When an element is referred to as being "connected" or "combined" to another element, it will also be understood that it may be directly connected or combined to another element, or that intervening elements may exist. In contrast, when an element is referred to as being "directly connected" or "directly combined" to another element, no intervening elements exist.

[0121] Relative terms such as "below," "above," "upper," "lower," "top," or "bottom" may be used herein to describe the relationship between one element, layer, or region and another element, layer, or region, as illustrated in the drawings. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientations illustrated in the drawings.

[0122] Embodiments of the present invention are described herein with reference to cross-sectional examples, which are schematic examples of ideal embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations in the shapes of the examples are expected, for example, as a result of manufacturing techniques and / or tolerances. Embodiments of the present invention are also described with reference to manufacturing operations. It will be understood that the steps illustrated in the manufacturing operations do not need to be performed in the illustrated order.

[0123] Some embodiments of the present invention are described with reference to semiconductor layers and / or regions characterized by having a conductivity type, such as n-type or p-type, which designates the majority carrier concentration in the layer and / or region. Thus, n-type materials have a majority equilibrium concentration of negatively charged electrons, whereas p-type materials have a majority equilibrium concentration of positively charged holes. Some materials may be designated as "+" or "-" (as in n+, n-, p+, p-, n++, n-, p++, p-, etc.) to indicate majority carriers with a relatively larger ("+") or smaller ("-") concentration compared to other layers or regions. However, such notation does not imply the presence of a specific concentration of majority or minority carriers in the layer or region.

[0124] In the drawings and specification, typical embodiments of the invention are disclosed, and specific terms are used, but are used only in a general and descriptive sense and not for limiting purposes, and the scope of the invention is set forth in the following claims.

Claims

Claim 1 A power semiconductor device comprising: a semiconductor layer structure including a drift region of a first conductivity type; a gate trench extending into the semiconductor layer structure, wherein the gate trench includes sidewalls and a bottom surface between them; a bottom shielding structure of a second conductivity type below the bottom surface of the gate trench; and first and second support shielding structures of the second conductivity type extending into the semiconductor layer structure from opposite sides of the gate trench and spaced apart from the sidewalls, wherein the bottom shielding structure comprises dopants of the second conductivity type at a first concentration, and the first and second support shielding structures comprise dopants of the second conductivity type at a second concentration different from the first concentration. Claim 2 A power semiconductor device according to claim 1, wherein one or more of the first and second support shielding structures extend into the semiconductor layer structure at a depth different from the depth of the bottom shielding structure with respect to the surface of the semiconductor layer structure. Claim 3 A power semiconductor device according to paragraph 2, wherein the first and second support shielding structures extend 0.1 to 1 μm into the semiconductor layer structure beyond the bottom shielding structure. Claim 4 A power semiconductor device according to any one of claims 1 to 3, wherein at least one of the bottom shielding structure, the first support shielding structure, or the second support shielding structure comprises a material different from the material of the drift region. Claim 5 A power semiconductor device according to claim 4, wherein the drift region comprises a widebandgap semiconductor material, and at least one of the bottom shielding structure, the first support shielding structure, or the second support shielding structure comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide. Claim 6 A power semiconductor device according to claim 4, wherein at least one of the lower shielding structure, the first support shielding structure, or the second support shielding structure further comprises an injected portion of the drift region. Claim 7 delete Claim 8 A power semiconductor device according to claim 1, wherein the second concentration is higher than the first concentration. Claim 9 A power semiconductor device according to any one of claims 1 to 3, wherein the semiconductor layer structure further comprises a substrate, the substrate comprises a drift region above the substrate and a second conductivity type well region on or within the drift region facing the substrate, and the first and second support shielding structures extend through the well region and beyond the bottom shielding structure and are spaced apart from the substrate. Claim 10 A power semiconductor device according to claim 9, wherein the first and second support shielding structures have dopants of the second conductivity type at a concentration different from that of the well region. Claim 11 A power semiconductor device according to claim 9, wherein the first and second support shielding structures are spaced apart from the substrate by 1 to 100 μm. Claim 12 A power semiconductor device according to any one of claims 1 to 3, wherein the bottom shielding structure extends along a portion of the bottom surface of the gate trench. Claim 13 A power semiconductor device according to any one of claims 1 to 3, wherein the lower shielding structure extends along the entire lower surface of the gate trench. Claim 14 delete Claim 15 A method for manufacturing a power semiconductor device, comprising: providing a semiconductor layer structure including a drift region of a first conductivity type; forming first and second support shielding structures and a bottom shielding structure of a second conductivity type extending into the semiconductor layer structure, wherein the bottom shielding structure comprises dopants of the second conductivity type of a first concentration, and the first and second support shielding structures comprise dopants of the second conductivity type of a second concentration different from the first concentration; and, after forming the bottom shielding structure, forming a gate trench extending into the semiconductor layer structure and spaced apart from the first and second support shielding structures, wherein the bottom shielding structure is located below the gate trench. Claim 16 delete Claim 17 A method for manufacturing a power semiconductor device, comprising: providing a semiconductor layer structure including a drift region of a first conductivity type; forming first and second support shielding structures of a second conductivity type extending into the semiconductor layer structure; after forming the first and second support shielding structures, forming a gate trench extending into the semiconductor layer structure and spaced apart from the first and second support shielding structures, wherein the gate trench includes sidewalls and a bottom surface between them; and forming a bottom shielding structure of the second conductivity type below the bottom surface of the gate trench, wherein the bottom shielding structure includes dopants of the second conductivity type at a first concentration, and the first and second support shielding structures include dopants of the second conductivity type at a second concentration different from the first concentration. Claim 18 In claim 17, the step of forming the bottom shielding structure comprises, after forming the gate trench, performing at least one of an ion implantation operation or a deposition operation to form the bottom shielding structure extending into the semiconductor layer structure to a first depth relative to the surface of the semiconductor layer structure. Claim 19 delete Claim 20 delete Claim 21 delete Claim 22 delete Claim 23 delete Claim 24 delete Claim 25 delete Claim 26 delete Claim 27 delete Claim 28 delete Claim 29 delete Claim 30 delete Claim 31 delete Claim 32 delete Claim 33 delete Claim 34 delete Claim 35 delete Claim 36 delete Claim 37 delete Claim 38 delete Claim 39 delete Claim 40 delete Claim 41 delete Claim 42 delete Claim 43 delete

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