Display apparatus

Abstract

One embodiment of the present invention provides a display device comprising: a substrate; a driving thin-film transistor disposed on the substrate and having a driving semiconductor layer and a driving gate electrode; a scan line disposed on the substrate and extending in a first direction; a data line extended in a second direction intersecting the first direction; a node connection line disposed on the same layer as the scan line; and a shielding conductive layer disposed between the data line and the node connection line, wherein one end of the node connection line is connected to the driving gate electrode through a first node contact hole.

Description

Technology Field

[0001] Embodiments of the present invention relate to a display device, and more specifically, to a display device for high-quality implementation. Background Technology

[0002] A display device is a device that visually displays data. Such a display device includes a substrate divided into a display area and a peripheral area. In the display area, scan lines and data lines are formed with mutual insulation and a plurality of pixels are included. Additionally, the display area is equipped with a thin-film transistor and a pixel electrode electrically connected to the thin-film transistor, corresponding to each of the pixels. Furthermore, the display area may be equipped with a counter electrode that is common to the pixels. The peripheral area may be equipped with various wirings that transmit electrical signals to the display area, a scan driver, a data driver, a control unit, etc.

[0003] The applications of such display devices are becoming increasingly diverse. Furthermore, as display devices become thinner and lighter, their range of use is expanding. To achieve high quality and high resolution in display devices, the design of pixel circuits included in the pixels is becoming more diverse. The problem to be solved

[0004] Embodiments of the present invention aim to provide a display device that implements high-quality images. However, these objectives are exemplary and do not limit the scope of the present invention. means of solving the problem

[0005] One embodiment of the present invention provides a display device comprising: a substrate; a driving thin-film transistor disposed on the substrate and having a driving semiconductor layer and a driving gate electrode; a scan line disposed on the substrate and extending in a first direction; a data line disposed between the scan line and an insulating layer and extending in a second direction intersecting the first direction; a node connection line disposed on the same layer as the scan line; and a shielding conductive layer disposed between the data line and the node connection line; wherein one end of the node connection line is connected to the driving gate electrode through a first node contact hole.

[0006] In one embodiment, the device further comprises a storage capacitor having a lower electrode and an upper electrode that overlaps with the driving thin-film transistor; and the shielding conductive layer may extend from the upper electrode.

[0007] In one embodiment, the lower electrode may be provided integrally with the driving gate electrode of the driving thin-film transistor.

[0008] In one embodiment, it further includes a driving voltage line extending in the second direction and disposed on the same layer as the data line; and the shielding conductive layer can receive a DC voltage from the driving voltage line.

[0009] In one embodiment, the device further comprises a compensation thin-film transistor connected to the scan line and having a compensation semiconductor layer and a compensation gate electrode; and a semiconductor connection line extending from the compensation semiconductor layer, wherein the other end of the node connection line can be connected to the semiconductor connection line through a second node contact hole.

[0010] In one embodiment, the shielding conductive layer and the semiconductor connecting line may include a portion extending in the second direction.

[0011] In one embodiment, the resistivity value of the scan line may be smaller than the resistivity value of the driving gate electrode.

[0012] In one embodiment, the storage capacitor further comprises a driving gate electrode as a lower electrode and an upper electrode having a storage opening in the shape of a closed curve that is overlapped with the lower electrode, wherein the first node contact hole may be disposed inside the storage opening.

[0013] In one embodiment, the size of the storage opening may be larger than the size of the first node contact hole.

[0014] In one embodiment, the light-emitting control thin film transistor disposed on the substrate and having a light-emitting control semiconductor layer and a light-emitting control gate electrode; and a light-emitting control line that transmits a light-emitting control signal to the light-emitting control gate electrode; further comprising, wherein the light-emitting control gate electrode may be provided as a part of the light-emitting control line.

[0016] Another embodiment of the present invention provides a display device comprising: a substrate; a driving thin-film transistor disposed on the substrate and having a driving gate electrode disposed between a driving semiconductor layer and a first gate insulating layer; a second gate insulating layer covering the driving gate electrode; a shielding conductive layer disposed on the second gate insulating layer; an interlayer insulating layer covering the shielding conductive layer; a node connecting line disposed on the interlayer insulating layer and connected to the driving gate electrode through a first node contact hole penetrating the interlayer insulating layer and the second gate insulating layer; a scan line disposed on the same layer as the node connecting line and extended in a first direction; a via layer covering the scan line and the node connecting line; and a data line disposed on the via layer and extended in a second direction intersecting the first direction; wherein the shielding conductive layer extends in the second direction between the data line and the node connecting line.

[0017] In one embodiment, the resistivity value of the scan line may be smaller than the resistivity value of the driving gate electrode.

[0018] In one embodiment, the device further comprises a storage capacitor having a lower electrode and an upper electrode that overlaps with the driving thin-film transistor; wherein the shielding conductive layer may extend in a second direction from the upper electrode.

[0019] In one embodiment, the lower electrode may be provided integrally with the driving gate electrode of the driving thin-film transistor.

[0020] In one embodiment, the upper electrode has a closed curve storage opening, and the first node contact hole may be disposed within the storage opening.

[0021] In one embodiment, the driving semiconductor layer may be formed in a curved shape.

[0022] In one embodiment, it further includes a driving voltage line extending in the second direction and disposed on the same layer as the data line; and the shielding conductive layer can receive a DC voltage from the driving voltage line.

[0023] In one embodiment, the device further comprises a compensation thin-film transistor connected to the scan line and having a compensation semiconductor layer and a compensation gate electrode; and a semiconductor connection line extending from the compensation semiconductor layer, wherein the other end of the node connection line can be connected to the semiconductor connection line through a second node contact hole.

[0024] In one embodiment, the shielding conductive layer and the semiconductor connecting line may include a portion extending in the second direction.

[0025] In one embodiment, a light-emitting control thin-film transistor disposed on the substrate and having a light-emitting control semiconductor layer and a light-emitting control gate electrode; and an organic light-emitting diode connected to the light-emitting control thin-film transistor may be further provided. Effects of the invention

[0026] As described above, in the embodiments of the present invention, a shielding conductive layer extending from one electrode of a storage capacitor is disposed between a node connection line and a data line connecting a driving thin-film transistor, thereby reducing crosstalk phenomena caused by parasitic capacitance.

[0027] In addition, by using a scan line with lower resistance than the gate electrode of the switching thin-film transistor, the RC delay phenomenon can be prevented.

[0028] Of course, the scope of the present invention is not limited by these effects. Brief explanation of the drawing

[0029] FIG. 1 is a schematic diagram showing a display device according to one embodiment of the present invention. FIG. 2 is a block diagram schematically showing a display device according to one embodiment of the present invention. Figure 3 is an equivalent circuit diagram of a single pixel provided in the display device of Figure 1. FIG. 4 is a schematic layout diagram showing the positions of a plurality of thin-film transistors and a capacitor included in a pixel circuit according to one embodiment of the present invention. Figure 5 is a layout diagram showing only a portion of the configuration of Figure 4, focusing on the shielding conductive layer. Figure 6 shows a partial configuration of a cross-sectional view of Figure 4 cut along the line I-I'. Figure 7 shows a configuration in which organic light-emitting diodes are arranged in a cross-sectional view of Figure 4 cut along the lines II-II' and III-III'. Specific details for implementing the invention

[0030] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0031] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0032] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0033] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0034] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0035] In the following embodiments, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of another part, but also cases where another film, region, or component is interposed in between.

[0036] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is illustrated.

[0037] In the following embodiments, when it is stated that a membrane, region, component, etc. is connected, it includes not only cases where the membrane, region, or component is directly connected, but also cases where other membranes, regions, or components are interposed between them to form an indirect connection. For example, when it is stated in this specification that a membrane, region, component, etc. is electrically connected, it includes not only cases where the membrane, region, or component, etc. are directly electrically connected, but also cases where other membranes, regions, or components are interposed between them to form an indirect electrical connection.

[0038] A display device is a device for displaying images and may be a liquid crystal display, an electrophoretic display, an organic light-emitting display, an inorganic light-emitting display, a field emission display, a surface-conduction electron-emitter display, a plasma display, a cathode ray display, etc.

[0039] In the following description, an organic light-emitting display device is used as an example of a display device according to one embodiment of the present invention, but the display device of the present invention is not limited thereto, and various types of display devices may be used.

[0040] FIG. 1 is a schematic diagram showing a display device according to one embodiment of the present invention.

[0041] Referring to FIG. 1, the display device includes a display area (DA) and a non-display area, which is a peripheral area (PA). Pixels (PX) equipped with organic light-emitting devices (OLEDs) are arranged in the display area (DA) to provide a predetermined image. The peripheral area (PA) is an area that does not provide an image and includes a scan driving unit and a data driving unit that provide electrical signals to be applied to the pixels (PX) of the display area (DA), and power lines that provide power such as a driving voltage and a common voltage.

[0042] FIG. 2 is a block diagram schematically showing a display device according to one embodiment of the present invention.

[0043] An organic light-emitting display device according to one embodiment of the present invention includes a display unit (10) comprising a plurality of pixels (PX), a scan driving unit (20), a data driving unit (30), a light-emitting control driving unit (40), and a control unit (50).

[0044] The display unit (10) is positioned in a display area and includes a plurality of pixels (PX) arranged in a roughly matrix form, located at the intersection of a plurality of scan lines (SL1 to SLn+1, scanning line), a plurality of data lines (DL1 to DLm), and a plurality of light emission control lines (EL1 to ELn). The plurality of scan lines (SL1 to SLn+1) and the plurality of light emission control lines (EL1 to ELn) extend in a second direction, which is the row direction, and the plurality of data lines (DL1 to DLm) and the driving voltage line (ELVDDL) extend in a first direction, which is the column direction. In one pixel line, the n value of the plurality of scan lines (SL1 to SLn+1) may be different from the n value of the plurality of light emission control lines (EL1 to ELn).

[0045] Each pixel (PX) is connected to three of the plurality of scan lines (SL1 to SLn+1) transmitted to the display unit (10). The scan driving unit (20) generates and transmits three scan signals to each pixel (PX) through the plurality of scan lines (SL1 to SLn+1). That is, the scan driving unit (20) sequentially supplies scan signals to the scan lines (SL2 to SLn), the previous scan lines (SL1 to SLn-1), or the subsequent scan lines (SL3 to SLn+1).

[0046] The initialization voltage line (IL) can receive an initialization voltage from an external power source (VINT) and supply it to each pixel (PX).

[0047] In addition, each pixel (PX) is connected to one of the data lines (DL1 to DLm) connected to the display unit (10) and one of the light emission control lines (EL1 to ELn) connected to the display unit (10).

[0048] The data driving unit (30) transmits a data signal to each pixel (PX) through a plurality of data lines (DL1 to DLm). The data signal is supplied to the pixel (PX) selected by the scan signal whenever a scan signal is supplied through the scan lines (SL2 to SLn).

[0049] The light emission control driving unit (40) generates and transmits a light emission control signal to each pixel through a plurality of light emission control lines (EL1 to ELn). The light emission control signal controls the light emission time of the pixel (PX). The light emission control driving unit (40) may be omitted depending on the internal structure of the pixel (PX).

[0050] The control unit (50) converts multiple image signals (IR, IG, IB) transmitted from the outside into multiple image data signals (DR, DG, DB) and transmits them to the data driving unit (30). Additionally, the control unit (50) receives a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), and a clock signal (MCLK), generates control signals to control the operation of the scan driving unit (20), the data driving unit (30), and the light emission control driving unit (40), and transmits them to each. That is, the control unit (50) generates and transmits a scan driving control signal (SCS) for controlling the scan driving unit (20), a data driving control signal (DCS) for controlling the data driving unit (30), and a light emission driving control signal (ECS) for controlling the light emission control driving unit (40), respectively.

[0051] Each of the multiple pixels (PX) receives an external driving power voltage (ELVDD) and a common power voltage (ELVSS). The driving power voltage (ELVDD) may be a predetermined high-level voltage, and the common power voltage (ELVSS) may be a voltage lower than the driving power voltage (ELVDD) or a ground voltage. The driving power voltage (ELVDD) is supplied to each pixel (PX) through a driving voltage line (ELVDDL).

[0052] Each of the multiple pixels (PX) emits light of a predetermined brightness by a driving current supplied to a light-emitting element according to a data signal transmitted through multiple data lines (DL1 to DLm).

[0053] Figure 3 is an equivalent circuit diagram of a single pixel provided in the display device of Figure 1.

[0054] Referring to FIG. 3, the pixel (PX) includes signal lines (121, 131, 132, 133, 151), a plurality of thin-film transistors (T1, T2, T3, T4, T5, T6, T7) connected to the signal lines, a capacitor (Cst), an initialization voltage line (123), a driving voltage line (152), and an organic light-emitting diode (OLED).

[0055] FIG. 3 illustrates a case in which signal lines (121, 131, 132, 133, 151), an initialization voltage line (123), and a driving voltage line (152) are provided for each pixel (PX), but the present invention is not limited thereto. As another embodiment, at least one of the signal lines (121, 131, 132, 133, 151), or / and the initialization voltage line (123) may be shared among neighboring pixels.

[0056] The thin-film transistor may include a driving thin-film transistor (T1), a switching thin-film transistor (T2), a compensation thin-film transistor (T3), a first initialization thin-film transistor (T4), an operation control thin-film transistor (T5), a light emission control thin-film transistor (T6), and a second initialization thin-film transistor (T7).

[0057] The signal line includes a scan line (131) that transmits a scan signal (Sn), a previous scan line (132) that transmits a previous scan signal (Sn-1) to a first initialization thin film transistor (T4), a subsequent scan line (133) that transmits a subsequent scan signal (Sn+1) to a second initialization thin film transistor (T7), a light emission control line (121) that transmits a light emission control signal (En) to an operation control thin film transistor (T5) and a light emission control thin film transistor (T6), and a data line (151) that intersects with the scan line (131) and transmits a data signal (Dm). The driving voltage line (152) transmits a driving voltage (ELVDD) to a driving thin film transistor (T1), and the initialization voltage line (123) transmits an initialization voltage (Vint) that initializes the driving thin film transistor (T1) and the pixel electrode.

[0058] The driving gate electrode (G1) of the driving thin-film transistor (T1) is connected to the lower electrode (Cst1) of the storage capacitor (Cst), the driving source electrode (S1) of the driving thin-film transistor (T1) is connected to the driving voltage line (152) via the operation control thin-film transistor (T5), and the driving drain electrode (D1) of the driving thin-film transistor (T1) is electrically connected to the pixel electrode of the organic light-emitting diode (OLED) via the light-emitting control thin-film transistor (T6). The driving thin-film transistor (T1) receives a data signal (Dm) according to the switching operation of the switching thin-film transistor (T2) and transmits a driving current (I) to the organic light-emitting diode (OLED). OLED supplies ).

[0059] The switching gate electrode (G2) of the switching thin-film transistor (T2) is connected to the scan line (131), the switching source electrode (S2) of the switching thin-film transistor (T2) is connected to the data line (151), and the switching drain electrode (D2) of the switching thin-film transistor (T2) is connected to the driving source electrode (S1) of the driving thin-film transistor (T1) and is connected to the driving voltage line (152) via the operation control thin-film transistor (T5). The switching thin-film transistor (T2) is turned on according to the scan signal (Sn) received through the scan line (131) and performs a switching operation to transmit the data signal (Dm) transmitted through the data line (151) to the driving source electrode (S1) of the driving thin-film transistor (T1).

[0060] The compensation gate electrode (G3) of the compensation thin film transistor (T3) is connected to the scan line (131), and the compensation source electrode (S3) of the compensation thin film transistor (T3) is connected to the driving drain electrode (D1) of the driving thin film transistor (T1) and is connected to the pixel electrode of the organic light-emitting diode (OLED) via the light-emitting control thin film transistor (T6). The compensation drain electrode (D3) of the compensation thin film transistor (T3) is connected to the lower electrode (Cst1) of the storage capacitor (Cst), the first initialization drain electrode (D4) of the first initialization thin film transistor (T4), and the driving gate electrode (G1) of the driving thin film transistor (T1). The compensation thin film transistor (T3) is turned on according to the scan signal (Sn) received through the scan line (131) to electrically connect the driving gate electrode (G1) and the driving drain electrode (D1) of the driving thin film transistor (T1), thereby diode-connecting the driving thin film transistor (T1).

[0061] The first initialization gate electrode (G4) of the first initialization thin film transistor (T4) is connected to the previous scan line (132), the first initialization drain electrode (D4) of the first initialization thin film transistor (T4) is connected to the second initialization drain electrode (D7) of the second initialization thin film transistor (T7) and the initialization voltage line (123), and the first initialization source electrode (S4) of the first initialization thin film transistor (T4) is connected to the lower electrode (Cst1) of the storage capacitor (Cst), the compensation drain electrode (D3) of the compensation thin film transistor (T3), and the driving gate electrode (G1) of the driving thin film transistor (T1). The first initialization thin film transistor (T4) is turned on according to the previous scan signal (Sn-1) received through the previous scan line (132) and transmits the initialization voltage (Vint) to the driving gate electrode (G1) of the driving thin film transistor (T1) to perform an initialization operation that initializes the voltage of the driving gate electrode (G1) of the driving thin film transistor (T1).

[0062] The operation control gate electrode (G5) of the operation control thin film transistor (T5) is connected to the light emission control line (121), the operation control source electrode (S5) of the operation control thin film transistor (T5) is connected to the driving voltage line (152), and the operation control drain electrode (D5) of the operation control thin film transistor (T5) is connected to the driving source electrode (S1) of the driving thin film transistor (T1) and the switching drain electrode (D2) of the switching thin film transistor (T2).

[0063] The light-emitting control gate electrode (G6) of the light-emitting control thin film transistor (T6) is connected to the light-emitting control line (121), and the light-emitting control source electrode (S6) of the light-emitting control thin film transistor (T6) is connected to the driving drain electrode (D1) of the driving thin film transistor (T1) and the compensation source electrode (S3) of the compensation thin film transistor (T3), and the light-emitting control drain electrode (D6) of the light-emitting control thin film transistor (T6) is electrically connected to the second initialization source electrode (S7) of the second initialization thin film transistor (T7) and the pixel electrode of the organic light-emitting diode (OLED). The light-emitting control gate electrode (G6) may be provided as part of the light-emitting control line (121).

[0064] The operation control thin-film transistor (T5) and the light emission control thin-film transistor (T6) are simultaneously turned on according to the light emission control signal (En) received through the light emission control line (121), so that the driving voltage (ELVDD) is transmitted to the organic light-emitting diode (OLED) and the driving current (I) to the organic light-emitting diode (OLED) OLED Make ) flow.

[0065] The second initialization gate electrode (G7) of the second initialization thin film transistor (T7) is subsequently connected to the scan line (133), and the second initialization source electrode (S7) of the second initialization thin film transistor (T7) is connected to the light-emitting control drain electrode (D6) of the light-emitting control thin film transistor (T6) and the pixel electrode of the organic light-emitting diode (OLED), and the second initialization drain electrode (D7) of the second initialization thin film transistor (T7) is connected to the first initialization source electrode (S4) of the first initialization thin film transistor (T4) and the initialization voltage line (123). The second initialization thin film transistor (T7) is subsequently turned on according to the scan signal (Sn+1) received through the scan line (133) to initialize the pixel electrode of the organic light-emitting diode (OLED).

[0066] FIG. 3 illustrates a case where the first initialization thin-film transistor (T4) and the second initialization thin-film transistor (T7) are connected to the previous scan line (132) and the subsequent scan line (133), respectively, but the present invention is not limited thereto. As another embodiment, the first initialization thin-film transistor (T4) and the second initialization thin-film transistor (T7) may both be connected to the previous scan line (122) and driven according to the previous scan signal (Sn-1). Meanwhile, the positions of the source electrodes (S1~S7) and drain electrodes (D1~D4) in FIG. 3 may be interchanged depending on the type of transistor (p-type or n-type).

[0067] The specific operation of each pixel (PX) according to one embodiment is as follows.

[0068] During the initialization period, when a previous scan signal (Sn-1) is supplied through the previous scan line (132), the first initialization thin film transistor (T4) is turned on in response to the previous scan signal (Sn-1), and the driving thin film transistor (T1) is initialized by the initialization voltage (Vint) supplied from the initialization voltage line (123).

[0069] During the data programming period, when a scan signal (Sn) is supplied through the scan line (131), the switching thin-film transistor (T2) and the compensation thin-film transistor (T3) are turned on in response to the scan signal (Sn). At this time, the driving thin-film transistor (T1) is diode-connected to the turned-on compensation thin-film transistor (T3) and is forward-biased.

[0070] Then, a compensation voltage (Dm+Vth, where Vth is a negative value) that is reduced by the threshold voltage (Vth) of the driving thin-film transistor (T1) from the data signal (Dm) supplied from the data line (151) is applied to the driving gate electrode (G1) of the driving thin-film transistor (T1).

[0071] A driving voltage (ELVDD) and a compensation voltage (Dm+Vth) are applied across the storage capacitor (Cst), and a charge corresponding to the voltage difference across the storage capacitor (Cst) is stored.

[0072] During the light emission period, the operation control thin film transistor (T5) and the light emission control thin film transistor (T6) are turned on by the light emission control signal (En) supplied from the light emission control line (121). The driving current (I) depends on the voltage difference between the voltage of the gate electrode of the driving thin film transistor (T1) and the driving voltage (ELVDD). OLED ) is generated, and a driving current (I) is generated through the light-emitting control thin-film transistor (T6). OLED ) is supplied to organic light-emitting diodes (OLEDs).

[0073] The display device according to the present embodiment has a shielding conductive layer (141) extending from the upper electrode (Cst2) of a storage capacitor connected to a driving voltage line (152). The shielding conductive layer (141) is intended to block parasitic capacitance that may occur between part A, where the data line (151) is arranged, and part B, which connects the driving thin-film transistor (T1) and the compensation thin-film transistor.

[0074] Hereinafter, a display device according to an embodiment of the present invention will be described in more detail with reference to the layout and cross-sectional views of FIGS. 4 to 7.

[0075] FIG. 4 is a schematic layout diagram showing the positions of a plurality of thin-film transistors and a capacitor included in a pixel circuit according to an embodiment of the present invention. FIG. 5 is a layout diagram showing only a portion of the configuration of FIG. 4, centered on the shielding conductive layer. FIG. 6 shows a portion of the configuration of a cross-sectional view taken along the line I-I' of FIG. 4. FIG. 7 shows a configuration in which an organic light-emitting diode is arranged in a cross-sectional view taken along the lines II-II' and III-III' of FIG. 4.

[0076] As illustrated in FIGS. 4 and 5, a display device according to one embodiment of the present invention includes a scan line (131) extended in a first direction, a previous scan line (132), a subsequent scan line (133), a horizontal driving voltage line (134), a light emission control line (121), and an initialization voltage line (123), and includes a data line (151) and a driving voltage line (152) extended in a second direction that intersects the first direction.

[0077] In this embodiment, the scan line (131), previous scan line (132), subsequent scan line (133), and horizontal driving voltage line (134) may be placed on the same layer using the same material. The scan line (131), previous scan line (132), and subsequent scan line (133) are placed on a different layer from the gate electrodes (G1~G7) of the thin-film transistors (T1~T7) and may be provided with a resistance smaller than that of the gate electrodes (G1~G7). That is, the resistivity value of the scan line (131) may have a value smaller than the resistivity value of the gate electrodes (G1~G7). Accordingly, the RC delay phenomenon caused by the application of the scan signal can be prevented or minimized.

[0078] For example, the scan line (131), previous scan line (132), and subsequent scan line (133) may be disposed on the interlayer insulating layer (114) and may include a conductive material including aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), etc., and may be formed as a multilayer or single layer including the above materials. As an example, the scan line (131), previous scan line (132), and subsequent scan line (133) may be formed as a multilayer structure of Ti / Al / Ti.

[0079] Gate electrodes (G1 to G7) can be disposed on the first gate insulating layer (112) and may be composed of a single layer or multiple layers, including molybdenum (Mo), titanium (Ti), etc. For example, the gate electrode (G1) may be a single layer of Mo.

[0080] A second gate insulating layer (113) and an interlayer insulating layer (114) may be disposed between the scan line (131) and the gate electrodes (G1 to G7). That is, the scan line (131), the previous scan line (132), and the subsequent scan line (133) are disposed on a different layer from the gate electrodes (G1 to G7) connected to them, so that the scan line (131), the previous scan line (132), and the subsequent scan line (133) can be connected to the gate electrodes (G1 to G7) through contact holes.

[0081] Meanwhile, the light-emitting control line (121) can be placed in the first gate insulating layer (112), which is the same layer as the gate electrodes (G1 to G7), using the same material.

[0082] The data line (151) and the driving voltage line (152) may be positioned between the scan line (131) and the via layer (115). The data line (151) and the driving voltage line (152) may have a resistivity value similar to that of the scan line (131). For example, the data line (151) and the driving voltage line (152) may include a conductive material including aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), etc., and may be formed as a multilayer or single layer including the above materials. As an example, the data line (151) and the driving voltage line (152) may be formed as a multilayer structure of Ti / Al / Ti.

[0083] A horizontal driving voltage line (134) extended in the first direction is placed on another layer and connected to a driving voltage line (152) extended in the second direction through a contact hole. Accordingly, the horizontal driving voltage line (134) and the driving voltage line (152) can form a mesh structure.

[0084] Additionally, a display device according to one embodiment of the present invention includes a driving thin-film transistor (T1), a switching thin-film transistor (T2), a compensation thin-film transistor (T3), a first initialization thin-film transistor (T4), an operation control thin-film transistor (T5), a light emission control thin-film transistor (T6), and a storage capacitor (Cst).

[0085] The driving semiconductor layer (A1) of the driving thin-film transistor (T1), the switching semiconductor layer (A2) of the switching thin-film transistor (T2), the compensation semiconductor layer (A3) of the compensation thin-film transistor (T3), the first initialization semiconductor layer (A4) of the first initialization thin-film transistor (T4), the operation control semiconductor layer (A5) of the operation control thin-film transistor (T5), the light emission control semiconductor layer (A6) of the light emission control thin-film transistor (T6), and the second initialization semiconductor layer (A7) of the second initialization thin-film transistor (T7) are arranged in the same layer and contain the same material. For example, the semiconductor layers (A1 to A7) may be formed of polycrystalline silicon or amorphous silicon. Alternatively, the semiconductor layers (A1 to A7) may comprise an oxide semiconductor material comprising an oxide of at least one material selected from the group comprising indium (In), gallium (Ga), stannium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). The semiconductor layers (A1 to A7) may be connected to each other and may be bent into various shapes.

[0086] The semiconductor layers (A1 to A7) may include a channel region, source regions and drain regions on both sides of the channel region. For example, the source region and drain region may be doped with impurities, and the impurities may include N-type impurities or P-type impurities. The source region and drain region correspond to the source electrode and drain electrode, respectively. Hereinafter, the terms source region and drain region will be used instead of source electrode or drain electrode.

[0087] The driving thin-film transistor (T1) includes a driving semiconductor layer (A1), a driving gate electrode (G1), a driving source region (S1), and a driving drain region (D1). The driving semiconductor layer (A1) is curved. A storage capacitor (Cst) is formed on top of the driving thin-film transistor (T1) so as to overlap it.

[0088] The driving semiconductor layer (A1) includes a driving channel region, driving source regions (S1) on both sides of the driving channel region, and a driving drain region (D1). The driving semiconductor layer has a curved shape and can be formed longer than other semiconductor layers (A2 to A7). For example, by having the driving semiconductor layer (A1) have a shape that is folded multiple times, such as an omega or the letter "S", a long channel length can be formed within a narrow space. Since the driving semiconductor layer (A1) is formed long, the driving range of the gate voltage applied to the driving gate electrode (G1) is widened, allowing for more precise control of the gradation of light emitted from the organic light-emitting diode (OLED) and improving display quality.

[0089] The storage capacitor (Cst) includes a lower electrode (Cst1) and an upper electrode (Cst2) positioned with the second gate insulating layer (113) in between. Here, the driving gate electrode (G1) also serves as the lower electrode (Cst1). That is, the driving gate electrode (G1) is formed integrally with the lower electrode (Cst). The second gate insulating layer (113) functions as a dielectric for the storage capacitor (Cst), and the storage capacitance is determined by the charge accumulated in the storage capacitor (Cst) and the voltage between the two electrodes (Cst1, Cst2).

[0090] The lower electrode (Cst1) is formed as a floating electrode in the shape of an island and is formed on the same layer with the same material as the light emission control line (121), switching gate electrode (G2), compensation gate electrode (G3), first initialization gate electrode (G4), operation control gate electrode (G5), light emission control gate electrode (G6), and second initialization gate electrode (G7).

[0091] The upper electrode (Cst2) is positioned on the second gate insulating layer (113). The upper electrode (Cst2) is positioned to overlap the entire lower electrode (Cst1) and is provided with a storage opening (SOP). The storage opening (SOP) is provided to overlap the lower electrode (Cst1). The storage opening (SOP) may have the shape of a single closed curve penetrating the upper electrode (Cst2). Here, a single closed curve refers to a closed shape, such as a polygon or a circle, where the starting point and the ending point are the same when a point is placed on a straight line or curve. The upper electrode (Cst2) is connected to the driving voltage line (152) through a contact hole and receives the driving power supply voltage (ELVDD).

[0092] The switching thin-film transistor (T2) includes a switching semiconductor layer (A2) and a switching gate electrode (G2). The switching semiconductor layer (A2) includes a switching source region (S2) and a switching drain region (D2) on both sides of the switching channel region. The switching drain region (D2) is connected to the driving source region (S1).

[0093] The compensation thin-film transistor (T3) includes a compensation semiconductor layer (A3) and a compensation gate electrode (G3). The compensation semiconductor layer (A3) includes a compensation source region (S3) and a compensation drain region (D3) on both sides of the compensation channel region. The compensation thin-film transistor (T3) formed on the compensation semiconductor layer (A3) is a dual thin-film transistor having two compensation channel regions, and the region between the compensation channel regions is an impurity-doped region that locally corresponds to the source region of one of the dual thin-film transistors and the drain region of the other. The compensation drain region (D3) can be connected to the lower electrode (Cst1) through a node connection line (135). The compensation gate electrode (G3) can prevent leakage current by forming a separate dual gate electrode.

[0094] The first initialization thin-film transistor (T4) includes a first initialization semiconductor layer (A4) and a first initialization gate electrode (G4). The first initialization semiconductor layer (A4) includes a first initialization source region (S4) and a first initialization drain region (D4) on both sides of the first initialization channel region. The first initialization thin-film transistor (T4) formed on the first initialization semiconductor layer (A4) is a dual thin-film transistor having two first initialization channel regions, and the region between the first initialization channel regions is an impurity-doped region that locally corresponds to the source region of one of the dual thin-film transistors and the drain region of the other. The first initialization drain region (D4) can be connected to the lower electrode (Cst1) through a node connection line (135). The initialization source region (S4) can be connected to the initialization voltage line (123).

[0095] The operation control thin-film transistor (T5) includes an operation control semiconductor layer (A5) and an operation control gate electrode (G5). The operation control semiconductor layer (A5) includes an operation control source region (S5) and an operation control drain region (D5) on both sides of the operation control channel region. The operation control drain region (D5) can be connected to the driving source region (S1).

[0096] The light-emitting control thin film transistor (T6) includes a light-emitting control semiconductor layer (A6) and a light-emitting control gate electrode (G6). The light-emitting control semiconductor layer (AS6) includes a light-emitting control source region (S6) and a light-emitting control drain region (D6) on both sides of the light-emitting control channel region. The light-emitting control source region (S6) can be connected to a driving drain region (D1).

[0097] The second initialization thin film transistor (T7) includes a second initialization semiconductor layer (A7) and a second initialization gate electrode (G7). The second initialization semiconductor layer (A7) includes a second initialization source region (S7) and a second initialization drain region (D7) on both sides of the second initialization channel region.

[0098] The initialization voltage line (123) may be placed in the same layer as the semiconductor layers (A1 to A7) using the same material. The initialization voltage line (123) may be connected to the first initialization drain region (D4) of the first initialization thin film transistor (T4) and the second initialization drain region (D7) of the second initialization thin film transistor (T7).

[0099] One end of the driving semiconductor layer (A1) of the driving thin-film transistor (T1) is connected to the switching semiconductor layer (A2) and the operation control semiconductor layer (A5), and the other end of the driving semiconductor layer (A1) is connected to the compensation semiconductor layer (A3) and the light emission control semiconductor layer (A6). Accordingly, the driving source electrode (S1) is connected to the switching drain electrode (D2) and the operation control drain electrode (D5), and the driving drain electrode (D1) is connected to the compensation source electrode (S3) and the light emission control source electrode (S6).

[0100] The lower electrode (Cst1) of the storage capacitor (Cst) is connected to the compensation thin-film transistor (T3) and the initialization thin-film transistor (T4) through a node connection line (135). This node connection line (135) is formed on the same layer as the scan line (131). One end of the node connection line (135) is connected to the lower electrode (Cst1) through a first node contact hole (CNT1) formed in the second gate insulating layer (113) and the interlayer insulating layer (114). Here, the first node contact hole (CNT1) is provided to be placed within the storage opening (SOP) of the upper electrode (Cst2). The size of the storage opening (SOP) is provided to be larger than the size of the first node contact hole (CNT1), so that the first node contact hole (CNT1) can be connected to the lower electrode (Cst1) without contacting the upper electrode (Cst2).

[0101] The other end of the node connection line (135) is connected together with the compensation drain region (D3) and the first initialization drain region (D4) through the second node contact hole (CNT2) formed in the first gate insulation layer (112), the second gate insulation layer (113), and the interlayer insulation layer (114).

[0102] The upper electrode (Cst2) of the storage capacitor (Cst) is connected to the driving voltage line (152) through a contact hole in the interlayer insulation layer (114), and receives the driving power supply voltage (ELVDD) from the driving voltage line (152).

[0103] Meanwhile, the switching thin-film transistor (T2) is used as a switching element to select the pixel to be emitted. The switching gate electrode (G2) is connected to a scan line (131) placed on another layer through a contact hole, the switching source region (S2) is connected to a data line (151) through a contact hole, and the switching drain region (S3) is connected to a driving thin-film transistor (T1) and an operation control thin-film transistor (T5).

[0104] And, the light-emitting control drain electrode (D6) of the light-emitting control thin film transistor (T6) can be directly connected to the pixel electrode of the organic light-emitting diode (OLED) through a via hole (Via) formed in the via layer (115) and the planarization layer (116).

[0105] The display device according to the present embodiment is provided with a shielding conductive layer (141) for reducing parasitic capacitance. The shielding conductive layer (141) may be provided extending from the upper electrode (Cst2) of the storage capacitor (Cst). That is, the shielding conductive layer (141) can be understood as being formed integrally with the upper electrode (Cst2). The shielding conductive layer (141) may be provided protruding in a second direction from one side of the upper electrode (Cst2). The shielding conductive layer (141) is connected to the driving voltage line (152) through a contact hole, and thus can receive a driving power supply voltage (ELVDD), which is a DC voltage.

[0106] Referring to FIG. 5, which shows only the configuration around the shielding conductive layer (141), and FIG. 6, which is a cross-sectional view around the shielding conductive layer (141), in top view, the shielding conductive layer (141) is positioned between the data line (151) and the node connection line (135), and / or between the data line (151) and the semiconductor connection line (125). The semiconductor connection line (125) can be understood as part of the compensation drain region (D3) as wiring connected to the compensation thin film transistor (T3).

[0107] If the shielding conductive layer (141) is not provided, parasitic capacitance is formed between the data line (151) and the node connection line (135), or between the data line (151) and the semiconductor connection line (125), and the characteristics of the driving thin-film transistor (T1), etc., may change depending on the signal supply of the data line (151).

[0108] However, the display device according to the present embodiment is provided with a shielding conductive layer (141) so as to prevent the occurrence of parasitic capacitance. In addition, the shielding conductive layer (141) receives a driving power supply voltage (ELVDD), which is a DC voltage, and maintains a constant voltage, thereby minimizing the coupling effect caused by the signal of the data line (151).

[0109] Meanwhile, the node connecting line (135) and the semiconductor connecting line (125) are wirings that connect the compensation thin-film transistor (T3) and the driving thin-film transistor (T1). The node connecting line (135) is placed on the interlayer insulating layer (114) which is in the same layer as the scan line (31), and the semiconductor connecting line (125) is placed on the buffer layer (111) which is in the same layer as the semiconductor layers (A1 to A7). That is, the data line (151) is placed further away from the semiconductor connecting line (125) than from the node connecting line (135). Therefore, in order to minimize parasitic capacitance, it is desirable to minimize the length of the node connecting line (135).

[0110] Accordingly, in some embodiments, the semiconductor connecting line (125) may have a portion extending in a second direction that is in the same direction as the shielding conductive layer (141).

[0111] Hereinafter, with reference to FIG. 7, the configuration included in the display device of the present invention will be described in the stacking order. FIG. 7 shows a configuration in which organic light-emitting diodes are arranged in a cross-sectional view taken along the lines II-II' and III-III' of FIG. 4.

[0112] The substrate (110) may include a glass material, a ceramic material, a metal material, or a material having flexible or bendable properties. If the substrate (110) has flexible or bendable properties, the substrate (110) may include a polymer resin such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP). The substrate (110) may have a single layer or a multilayer structure of the material, and in the case of a multilayer structure, may further include an inorganic layer. In some embodiments, the substrate (110) may have an organic / inorganic / organic structure.

[0113] The buffer layer (111) is positioned on the substrate (110) to reduce or block the penetration of foreign matter, moisture, or outside air from the bottom of the substrate (110) and to provide a flat surface on the substrate (110). The buffer layer (111) may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite, and may be composed of a single layer or a multilayer structure of inorganic and organic materials.

[0114] A barrier layer (not shown) may be further included between the substrate (110) and the buffer layer (111). The barrier layer may serve to prevent or minimize the penetration of impurities from the substrate (110), etc., into the semiconductor layers (AS1 to AS7). The barrier layer may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite, and may be composed of a single layer or a multilayer structure of inorganic and organic materials.

[0115] A semiconductor layer (A1, A3, A6) may be disposed on the buffer layer (111). The semiconductor layer (A1, A3, A6) may include amorphous silicon or polysilicon. In another embodiment, the semiconductor layer (A1) may include an oxide of at least one material selected from the group comprising indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). In some embodiments, the semiconductor layer (A1) may be formed of a Zn oxide-based material, such as Zn oxide, In-Zn oxide, Ga-In-Zn oxide, etc. In another embodiment, the semiconductor layer (A1) may be an IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O) semiconductor containing metals such as indium (In), gallium (Ga), and tin (Sn) in ZnO. The semiconductor layer (A1, A3, A6)) may include a channel region and source and drain regions disposed on both sides of the channel region. The semiconductor layer (A1, A3, A6)) may be composed of a single layer or a multilayer.

[0116] On the semiconductor layers (A1, A3, A6), a first gate insulating layer (112) is placed between the gate electrodes (G1, G3, G6) so as to overlap at least partially with the semiconductor layers (A1, A3, A6). The gate electrodes (G1, G3, G6) include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be composed of a single layer or multiple layers. As an example, the gate electrodes (G1, G3, G6) may be a single layer of Mo.

[0117] The first gate insulating layer (112) is silicon oxide (SiO2) or silicon nitride (SiN xIt may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0118] A second gate insulating layer (113) may be provided to cover the gate electrodes (G1, G3, G6). The second gate insulating layer (113) may be silicon oxide (SiO2) or silicon nitride (SiN x It may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0119] The lower electrode (Cst1) of the storage capacitor (Cst) can overlap with the thin-film transistor (T1). For example, the driving gate electrode (G1) of the driving thin-film transistor (T1) can function as the lower electrode (Cst1) of the storage capacitor (Cst).

[0120] The upper electrode (Cst2) of the storage capacitor (Cst) overlaps with the lower electrode (Cst1) with the second gate insulating layer (113) in between. In this case, the second gate insulating layer (113) can function as a dielectric layer of the storage capacitor (Cst). The upper electrode (Cst2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials.

[0121] An interlayer insulating layer (114) may be provided to cover the upper electrode (Cst2) of the storage capacitor (Cst). The interlayer insulating layer (114) may be silicon oxide (SiO2) or silicon nitride (SiN x It may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0122] Scan lines (131) and node connecting lines (135) are placed on the interlayer insulating layer (114). Scan lines (131) and node connecting lines (135) may include a conductive material including aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. For example, the source electrode (S1) and drain electrode (D1) may be formed as a multilayer structure of Ti / Al / Ti.

[0123] One end of the node connecting line (135) is connected to the driving gate electrode (G1) through a first node contact hole (CNT1) penetrating the interlayer insulating layer (114) and the second gate insulating layer (113), and the other end of the node connecting line (135) can be connected to the semiconductor connecting line (125) through a second node contact hole (CNT2) penetrating the interlayer insulating layer (114), the second gate insulating layer (113), and the first gate insulating layer (112). The semiconductor connecting line (125) may be a wire extending from the compensation drain region (D3) of the compensation thin film transistor (T3).

[0124] The scan line (131) is connected to the compensation gate electrode (G3) through a contact hole penetrating the interlayer insulation layer (114) and the second gate insulation layer (113). The connection electrode (136) can be connected to the light-emitting control drain region (D6) of the light-emitting control transistor (T6) through a contact hole penetrating the interlayer insulation layer (114), the second gate insulation layer (113), and the first gate insulation layer (112).

[0125] A via layer (115) is located on the scan line (131), node connection line (135), and connection electrode (136), and a data line (151) and a driving voltage line (152) may be located on the via layer (115).

[0126] The via layer (115) may include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA), or polystylene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof. The via layer (115) may include inorganic materials. Such via layer (115) may include silicon oxide (SiO2) or silicon nitride (SiN x It may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc. If the via layer (115) is provided with an inorganic material, chemical planarization polishing may be performed depending on the case. Meanwhile, the via layer (115) may include both organic and inorganic materials.

[0127] A flattening layer (116) is located on the data line (151) and the driving voltage line (152). The flattening layer (116) may include organic materials such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane). Alternatively, the flattening layer (116) may include inorganic materials. The flattening layer (116) may serve to generally flatten the upper surface of the protective film covering the thin-film transistors (T1 to T7). The flattening layer (116) may be provided as a single layer or a multilayer.

[0128] An organic light-emitting diode (OLED) having a pixel electrode (210), a counter electrode (230), and an intermediate layer (220) interposed between them and including a light-emitting layer may be positioned on the flattening layer (116).

[0129] The pixel electrode (210) is connected to the connecting electrode (136) through a via hole penetrating the flattening layer (116) and the via layer (115), and is connected to the light-emitting control drain region (D6) of the light-emitting control thin film transistor (T6) by the connecting electrode (136).

[0130] A pixel defining film (117) may be disposed on the upper portion of the flattening layer (116). This pixel defining film (117) serves to define pixels by having openings corresponding to each subpixel, that is, openings that expose at least the central portion of the pixel electrode (210). Additionally, the pixel defining film (117) serves to prevent arcs from occurring at the edge of the pixel electrode (210) by increasing the distance between the edge of the pixel electrode (210) and the opposing electrode (230) above the pixel electrode (210). Such a pixel defining film (117) may be formed from an organic material such as polyimide or HMDSO (hexamethyldisiloxane).

[0131] The intermediate layer (220) of the organic light-emitting diode (OLED) may include low-molecular-weight or high-molecular-weight materials. When including low-molecular-weight materials, the structure may have a stacked structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) are stacked in a single or composite structure, and may include various organic materials including copper phthalocyanine (CuPc), N,N-di(naphthalene-1-yl)-N,N'-diphenyl-benzidine (NPB), and tris-8-hydroxyquinoline aluminum (Alq3). These layers may be formed by a vacuum deposition method.

[0132] When the intermediate layer (220) includes a polymer material, it may generally have a structure including a hole transport layer (HTL) and an emitting layer (EML). In this case, the hole transport layer may include PEDOT, and the emitting layer may include polymer materials such as PPV (Poly-Phenylenevinylene) and Polyfluorene. Such an intermediate layer (220) can be formed by screen printing, inkjet printing, or laser induced thermal imaging (LITI).

[0133] Of course, the intermediate layer (220) is not necessarily limited to this and may have various structures. Also, the intermediate layer (220) may include a layer that is integral across a plurality of pixel electrodes (210), or may include a layer patterned to correspond to each of the plurality of pixel electrodes (210).

[0134] The counter electrode (230) is positioned above the display area (DA), and can be positioned to cover the display area (DA) as shown in FIG. 10. That is, the counter electrode (230) is formed as a single unit in a plurality of organic light-emitting elements and can correspond to a plurality of pixel electrodes (210).

[0135] Since these organic light-emitting diodes (OLEDs) can be easily damaged by external moisture or oxygen, a thin film encapsulation layer (300) can cover these organic light-emitting elements to protect them. The thin film encapsulation layer (300) covers the display area (DA) and can extend to the outside of the display area (DA). This thin film encapsulation layer (300) may include a first inorganic encapsulation layer (310), an organic encapsulation layer (320), and a second inorganic encapsulation layer (330).

[0136] The first inorganic sealing layer (310) covers the counter electrode (230) and may include ceramic, metal oxide, metal nitride, metal carbide, metal oxynitride, indium oxide (In2O3), tin oxide (SnO2), indium tin oxide (ITO), silicon oxide, silicon nitride and / or silicon oxynitride, etc. Of course, other layers such as a capping layer may be interposed between the first inorganic sealing layer (310) and the counter electrode (230) as needed. Since this first inorganic sealing layer (310) is formed along the underlying structure, the upper surface of the first inorganic sealing layer (310) is not flat.

[0137] The organic encapsulation layer (320) covers the first inorganic encapsulation layer (310), and unlike the first inorganic encapsulation layer (310), its upper surface can be made approximately flat. Specifically, the organic encapsulation layer (320) can have its upper surface made approximately flat in the portion corresponding to the display area (DA). The organic encapsulation layer (320) may include one or more materials selected from the group consisting of acrylic, methacrylic, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane.

[0138] The second inorganic encapsulation layer (330) covers the organic encapsulation layer (320) and may include ceramic, metal oxide, metal nitride, metal carbide, metal oxynitride, indium oxide (In2O3), tin oxide (SnO2), indium tin oxide (ITO), silicon oxide, silicon nitride and / or silicon oxynitride, etc.

[0139] In this way, the thin film encapsulation layer (300) includes a first inorganic encapsulation layer (310), an organic encapsulation layer (320), and a second inorganic encapsulation layer (330). Through this multilayer structure, even if a crack occurs within the thin film encapsulation layer (300), such cracks can be prevented from connecting between the first inorganic encapsulation layer (310) and the organic encapsulation layer (320), or between the organic encapsulation layer (320) and the second inorganic encapsulation layer (330). This prevents or minimizes the formation of a path for moisture or oxygen from the outside to penetrate into the display area (DA).

[0140] Although not shown, a spacer for preventing mask imprinting may be further included on the pixel definition film (117), and various functional layers such as a polarizing layer for reducing external light reflection, a black matrix, a color filter, and / or a touchscreen layer equipped with a touch electrode may be provided on the thin film encapsulation layer (300).

[0141] Although the above description refers to the embodiments illustrated in the drawings, this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0142] 110: Substrate 111: Buffer layer 112: First gate insulating layer 113: Second gate insulation layer 114: Interlayer insulation layer 115: Via layer 115, Via layer: There is a via layer on top 116: Leveling layer 117: Pixel definition membrane 141: Shielding conductive layer 151: Data line 152: Driving voltage line 210: Pixel electrode 220: Middle layer 230: Counter electrode 300: Thin film encapsulation layer

Claims

Claim 1 A display device comprising: a substrate; a driving thin-film transistor disposed on the substrate and having a driving semiconductor layer and a driving gate electrode; a capacitor having a lower electrode and an upper electrode that overlaps with the driving thin-film transistor; a scan line disposed on the substrate and extended in a first direction; a data line disposed in the same layer as the scan line and extending in a second direction intersecting the first direction, insulated from the scan line by an insulating layer; a node connection line disposed in the same layer as the scan line; and a shielding conductive layer disposed between the data line and the node connection line; wherein the shielding conductive layer extends in the second direction from one side of the upper electrode. Claim 2 A display device according to claim 1, wherein the data line overlaps at least partially with the upper electrode. Claim 3 A display device according to claim 1, wherein the shielding conductive layer does not overlap with the data line. Claim 4 A display device according to claim 1, wherein the first end of the node connection line is connected to the driving gate electrode through the first node contact hole. Claim 5 A display device according to claim 4, further comprising: a compensation thin-film transistor connected to the scan line and including a compensation semiconductor layer and a compensation gate electrode; and a semiconductor connection line extending from the compensation semiconductor layer, wherein the second end of the node connection line is connected to the semiconductor connection line through a second node contact hole. Claim 6 A display device according to claim 5, wherein the semiconductor connecting line includes a portion extended in the second direction. Claim 7 A display device according to claim 4, wherein the upper electrode has an opening, and the first node contact hole is disposed in a planar manner inside the opening of the upper electrode. Claim 8 A display device according to claim 1, wherein the lower electrode of the capacitor is integrally formed with the driving gate electrode. Claim 9 A display device according to claim 1, wherein the node connecting line is positioned below the data line and the shielding conductive layer is positioned below the node connecting line. Claim 10 A display device according to claim 1, further comprising a driving voltage line extending in the second direction and disposed in the same layer as the data line, wherein the shielding conductive layer overlaps at least partially with the driving voltage line. Claim 11 A display device comprising: a substrate; a driving thin-film transistor disposed on the substrate and including a driving semiconductor layer and a driving gate electrode; a capacitor having a lower electrode and an upper electrode that overlaps with the driving thin-film transistor; a data line and a driving voltage line disposed on the substrate and extending in the longitudinal direction; and a shielding conductive layer extending in the longitudinal direction from one side of the upper electrode; wherein the shielding conductive layer does not overlap with the data line in a planar manner. Claim 12 In paragraph 11, the display device wherein the data line overlaps at least partially with the upper electrode. Claim 13 A display device according to claim 11, wherein the shielding conductive layer overlaps at least partially with the driving voltage line. Claim 14 A display device according to claim 11, further comprising a node connecting line connected through the driving gate electrode and the first node contact hole, wherein the shielding conductive layer is disposed in a planar position between the data line and the node connecting line. Claim 15 A display device according to claim 14, wherein the node connecting line is positioned below the data line and the shielding conductive layer is positioned below the node connecting line. Claim 16 A display device according to claim 14, further comprising: a compensation thin-film transistor including a compensation semiconductor layer and a compensation gate electrode; and a semiconductor connection line extending from the compensation semiconductor layer, wherein one end of the node connection line is connected to the semiconductor connection line through a second node contact hole. Claim 17 In claim 16, the semiconductor connecting line comprises a portion extended in the vertical direction, a display device. Claim 18 In claim 11, the upper electrode of the capacitor is provided with an opening in the display device. Claim 19 In claim 11, the lower electrode of the capacitor is integrally formed with the driving gate electrode, in a display device. Claim 20 A display device according to claim 11, further comprising: a light-emitting control thin film transistor disposed on the substrate and comprising a light-emitting control semiconductor layer and a light-emitting control gate electrode; and an organic light-emitting diode connected to the light-emitting control thin film transistor. Claim 21 A display device comprising: a substrate; a thin-film transistor disposed on the substrate and having a semiconductor layer and a gate electrode; a first wiring disposed on the same layer as the gate electrode and extending in a first direction; a horizontal wiring disposed on a different layer from the first wiring and extending in the first direction; and a vertical wiring disposed on a different layer from the first wiring and the horizontal wiring and extending in a second direction intersecting the first direction; wherein the gate electrode is provided as part of the first wiring, and a first region of the semiconductor layer is connected to the horizontal wiring. Claim 22 In claim 21, the above horizontal wiring is connected to the above vertical wiring through a contact hole, a display device. Claim 23 In claim 21, the second region of the semiconductor layer is a display device connected to a driving thin-film transistor. Claim 24 A display device according to claim 21, further comprising a scan line extended in the first direction; wherein the scan line is disposed on the same layer as the horizontal wiring. Claim 25 A display device according to claim 21, wherein the first wiring is positioned closer to the upper surface of the substrate than the horizontal wiring. Claim 26 A display device according to claim 21, wherein the first wiring is positioned closer to the upper surface of the substrate than the vertical wiring. Claim 27 A display device according to claim 21, wherein the horizontal wiring is positioned closer to the upper surface of the substrate than the vertical wiring. Claim 28 A display device comprising: a substrate; a thin-film transistor having a semiconductor layer and a gate electrode disposed on the substrate; a first insulating layer disposed between the semiconductor layer and the gate electrode; a first wiring disposed on the first insulating layer; a second insulating layer covering the gate electrode and the first wiring; a third insulating layer disposed on the second insulating layer; a horizontal wiring disposed on the third insulating layer and extending in a first direction; a fourth insulating layer disposed on the horizontal wiring; and a vertical wiring disposed on the fourth insulating layer and extending in a second direction intersecting the first direction; wherein the gate electrode is provided as part of the first wiring, and a first region of the semiconductor layer is connected to the horizontal wiring. Claim 29 A display device according to claim 28, wherein the vertical wiring is connected to the horizontal wiring through a contact hole defined in the fourth insulating layer. Claim 30 In paragraph 28, the second region of the semiconductor layer is a display device connected to a driving thin-film transistor. Claim 31 In paragraph 28, the first wiring is a display device that extends in the first direction. Claim 32 A display device according to claim 28, further comprising a scan line extended in the first direction; wherein the scan line is disposed on the same layer as the horizontal wiring. Claim 33 A display device comprising: a substrate; a driving thin-film transistor disposed on the substrate and having a first semiconductor layer and a driving gate electrode; a storage capacitor including a lower electrode formed integrally with the driving gate electrode and an upper electrode disposed on the lower electrode; a scan line disposed on a layer different from the driving gate electrode and extending in a first direction; a horizontal line disposed on a layer different from the lower electrode and the upper electrode and extending in a first direction; and a vertical line disposed on a layer different from the horizontal line and extending in a second direction intersecting the first direction; wherein the vertical line is connected to the horizontal line through a contact hole, and the vertical line is connected to the upper electrode. Claim 34 delete Claim 35 A display device according to claim 33, wherein the horizontal wiring is positioned closer to the upper surface of the substrate than the vertical wiring. Claim 36 In paragraph 33, the above scan line is a display device placed on the same layer as the above horizontal wiring. Claim 37 A display device according to claim 33, further comprising a first wiring extending in a first direction and disposed on the same layer as the driving gate electrode. Claim 38 A display device further comprising a conductive layer protruding from an upper electrode in paragraph 33. Claim 39 In paragraph 38, the above conductive layer is superimposed with the above scan line, a display device. Claim 40 In paragraph 39, the above scan line is a display device placed on the same layer as the horizontal wiring.

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