DRAM with two vertical channel transistors

Abstract

A DRAM is provided. The DRAM comprises a first signal line extending in a first direction on a substrate, a first interlayer insulating film disposed on the first signal line, and a second signal line extending in a second direction intersecting the first signal line on the first interlayer insulating film. A storage node electrode is disposed within a lower opening that penetrates the second signal line and the first interlayer insulating film, and in which the second signal line is exposed within a sidewall and the first signal line is exposed within a bottom surface. Between the storage node electrode and the sidewall and bottom surface of the lower opening, a read semiconductor layer is disposed that is electrically connected to the second signal line exposed within the sidewall of the lower opening and the first signal line exposed within the bottom surface of the lower opening. A read gate insulating film is disposed between the storage node electrode and the read semiconductor layer. A second interlayer insulating film is disposed on the storage node electrode, a third signal line extending in a third direction is disposed on the second interlayer insulating film, and a third interlayer insulating film is disposed on the third signal line. A write semiconductor layer is disposed within an upper opening that penetrates the third interlayer insulating film, the third signal line, and the second interlayer insulating film, and in which the third signal line is exposed within a sidewall and the storage node electrode is exposed within a bottom surface, and which is electrically connected to the storage node electrode exposed within the bottom surface of the upper opening. A write gate insulating film is disposed between the write semiconductor layer and the third signal line exposed within the sidewall of the upper opening. A fourth signal line is disposed on the third interlayer insulating film, extending in a fourth direction intersecting the third signal line and being electrically connected to the write semiconductor layer.

Description

Technology Field

[0001] The present invention relates to a semiconductor device, and specifically to a DRAM. Background Technology

[0002] Electronic products are becoming increasingly smaller in size while requiring high-speed and high-capacity data processing. Accordingly, there is a need to reduce the volume of memory chips used in these products while increasing their performance and integration density.

[0003] Dynamic Random Access Memory (DRAM), a type of memory device, has a 1T1C structure in which each unit consists of one transistor and one capacitor. As the integration density of the device continues to increase, the area occupied by the transistor and capacitor must be reduced. However, a reduction in the area occupied by the capacitor can lead to a decrease in capacitance; therefore, to avoid a decrease in capacitance despite the reduction in area, development is underway on ultrathin dielectric materials that possess high dielectric constants while having low leakage current. However, since materials with high dielectric constants generally tend to have small band gap energies or large dielectric losses, there is a fundamental trade-off between the high dielectric constant of the capacitor and leakage current. The problem to be solved

[0004] The problem that the present invention aims to solve is to overcome the limitations of a DRAM having a 1T1C structure by providing a 4F having two vertical channel transistors without a capacitor. 2 It is to provide a DRAM of (F = feature size).

[0005] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] To achieve the above objective, one aspect of the present invention provides a DRAM. The DRAM comprises a first signal line extending in a first direction on a substrate, a first interlayer insulating film disposed on the first signal line, and a second signal line extending in a second direction that intersects the first signal line on the first interlayer insulating film. A storage node electrode is disposed within a lower opening that penetrates the second signal line and the first interlayer insulating film, and in which the second signal line is exposed within a sidewall and the first signal line is exposed within a bottom surface. Between the storage node electrode and the sidewall and bottom surface of the lower opening, a read semiconductor layer is disposed that is electrically connected to the second signal line exposed within the sidewall of the lower opening and the first signal line exposed within the bottom surface of the lower opening. A read gate insulating film is disposed between the storage node electrode and the read semiconductor layer. A second interlayer insulating film is disposed on the storage node electrode, a third signal line extending in a third direction is disposed on the second interlayer insulating film, and a third interlayer insulating film is disposed on the third signal line. A write semiconductor layer is disposed within an upper opening that penetrates the third interlayer insulating film, the third signal line, and the second interlayer insulating film, and in which the third signal line is exposed within a sidewall and the storage node electrode is exposed within a bottom surface, and which is electrically connected to the storage node electrode exposed within the bottom surface of the upper opening. A write gate insulating film is disposed between the write semiconductor layer and the third signal line exposed within the sidewall of the upper opening. A fourth signal line extending in a fourth direction intersecting the third signal line and being electrically connected to the write semiconductor layer is disposed on the third interlayer insulating film.

[0007] The storage node electrode may have a read gate electrode disposed within the lower opening and a write source electrode disposed on the read gate electrode.

[0008] The first direction and the fourth direction may be X-axis directions, and the second direction and the third direction may be Y-axis directions. Either one of the first signal line and the second signal line may be a read bit line and the other may be a read word line, the third signal line may be a write word line, and the fourth signal line may be a write bit line.

[0009] The above-mentioned reading semiconductor layer is conformally formed on the bottom surface and side wall of the lower opening, the above-mentioned reading gate insulating film is conformally formed on the above-mentioned reading semiconductor layer, and the above-mentioned storage node electrode fills the remaining area of ​​the lower opening where the above-mentioned reading semiconductor layer and the above-mentioned reading gate insulating film are formed, and may have an upper surface at a level higher than the second signal line.

[0010] The writing semiconductor layer is conformally formed on the bottom surface and side wall of the upper opening, and a filler insulating film that fills the remaining area of ​​the upper opening where the writing gate insulating film and the writing semiconductor layer are formed may be disposed below the fourth signal line. The filler insulating film may be an aluminum oxide film.

[0011] The above-mentioned writing semiconductor layer may be a metal oxide semiconductor layer, specifically an IGO (Indium Gallium Oxide) layer. The above-mentioned reading semiconductor layer may be a metal oxide semiconductor layer, specifically an IGO (Indium Gallium Oxide) layer. Both the above-mentioned writing semiconductor layer and the above-mentioned reading semiconductor layer are IGO (Indium Gallium Oxide) layers, and the above-mentioned reading semiconductor layer may have a higher indium content than the above-mentioned writing semiconductor layer.

[0012] The above-mentioned read gate insulating film and the above-mentioned write gate insulating film may both be insulating films with a dielectric constant higher than that of a silicon oxide film. The above-mentioned read gate insulating film may be an insulating film with a dielectric constant higher than that of a write gate insulating film. The above-mentioned read gate insulating film may be a hafnium oxide film, and the above-mentioned write gate insulating film may be an aluminum oxide film.

[0013] To achieve the above objective, another aspect of the present invention provides a method for manufacturing a DRAM. First, a first signal line extending in a first direction is formed on a substrate. A first interlayer insulating film is formed on the first signal line. A second signal line extending in a second direction that intersects the first signal line is formed on the first interlayer insulating film. A lower opening is formed within the second signal line and the first interlayer insulating film, penetrating them, so that the second signal line is exposed within a sidewall and the first signal line is exposed within a bottom surface. A read semiconductor layer electrically connected to the second signal line exposed within the sidewall of the lower opening and the first signal line exposed within the bottom surface of the lower opening, and a read gate insulating film are conformally formed on top of the same within the lower opening. A storage node electrode is formed on the read gate insulating film to fill the remaining area of ​​the lower opening. A second interlayer insulating film is formed disposed on the storage node electrode, a third signal line extending in a third direction is formed on the second interlayer insulating film, and a third interlayer insulating film is formed on the third signal line. An upper opening is formed within the third interlayer insulating film, the third signal line, and the second interlayer insulating film, penetrating them such that the third signal line is exposed within the sidewall and the storage node electrode is exposed within the bottom surface. A write gate insulating film is formed covering the third signal line exposed on the sidewall of the upper opening. A write semiconductor layer is formed on the write gate insulating film disposed on the sidewall of the upper opening, which is electrically connected to the storage node electrode exposed within the bottom surface of the upper opening. A fourth signal line is formed on the third interlayer insulating film, which extends in a fourth direction intersecting the third signal line and is electrically connected to the write semiconductor layer.

[0014] The above storage node electrode may include a read gate electrode that fills the lower opening and a write source electrode disposed on the read gate electrode.

[0015] The first direction and the fourth direction may be X-axis directions, and the second direction and the third direction may be Y-axis directions. Either one of the first signal line and the second signal line may be a read bit line and the other may be a read word line, the third signal line may be a write word line, and the fourth signal line may be a write bit line.

[0016] The above-mentioned write semiconductor layer is conformally formed on the bottom surface and side wall of the above-mentioned upper opening, and before forming the fourth signal line, a filler insulating film can be formed to fill the remaining area of ​​the above-mentioned upper opening where the write gate insulating film and the write semiconductor layer are formed. The filler insulating film may be an aluminum oxide film.

[0017] The above-mentioned writing semiconductor layer may be a metal oxide semiconductor layer, specifically an IGO (Indium Gallium Oxide) layer. The above-mentioned reading semiconductor layer may be a metal oxide semiconductor layer, specifically an IGO (Indium Gallium Oxide) layer. Both the above-mentioned writing semiconductor layer and the above-mentioned reading semiconductor layer are IGO (Indium Gallium Oxide) layers, and the above-mentioned reading semiconductor layer may have a higher indium content than the above-mentioned writing semiconductor layer.

[0018] The above-mentioned read gate insulating film and the above-mentioned write gate insulating film may both be insulating films with a dielectric constant higher than that of a silicon oxide film. The above-mentioned read gate insulating film may be an insulating film with a dielectric constant higher than that of a write gate insulating film. The above-mentioned read gate insulating film may be a hafnium oxide film, and the above-mentioned write gate insulating film may be an aluminum oxide film. Effects of the invention

[0019] According to embodiments of the present invention, 4F 2 It is possible to provide a DRAM that has a unit cell area while exhibiting excellent operating speed and data retention time.

[0020] However, the effects of the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description below. Brief explanation of the drawing

[0021] FIG. 1 is a circuit diagram showing a part of a DRAM cell array having two transistors according to one embodiment of the present invention. FIG. 2 is a layout diagram showing a part of a DRAM cell array having two transistors according to one embodiment of the present invention. FIG. 3 is a perspective view showing part of the Direm cell array shown in FIG. 2. FIGS. 4a, FIGS. 5a, FIGS. 6a, FIGS. 7a, and FIGS. 8a are cross-sectional views taken at each process step along the cutting line II′ of FIG. 2. FIGS. 4b, FIGS. 5b, FIGS. 6b, FIGS. 7b, and FIGS. 8b are cross-sectional views taken at each process step along the cutting line Ⅱ-Ⅱ′ of FIG. 2. Figure 9 is a photograph showing a planar structure 2T0C DRAM fabricated for characteristic evaluation, and Figure 10 is a schematic diagram showing a cross-section thereof. Figures 11a and 11b are graphs showing the voltage of the storage node over time after a write operation when the gate insulating films of the transistors in a 2T0C DRAM fabricated as in Figures 9 and 10 are formed with Al2O3 and HfO2 films, respectively. FIG. 12 is a graph showing the transfer characteristics of a read transistor when the gate insulating film of the read transistor shown in FIG. 9 and FIG. 10 is formed with an Al2O3 film and an HfO2 film. Figure 13 is a graph showing the transfer characteristics of a read transistor according to the composition of the semiconductor layer of the read transistor shown in Figures 9 and 10. Specific details for implementing the invention

[0022] Hereinafter, preferred embodiments according to the present invention will be described in more detail with reference to the accompanying drawings in order to explain the present invention more specifically. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. In the drawings, where a layer is referred to as being "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed between them. In these embodiments, "first," "second," or "third" are not intended to impose any limitations on the components, but should be understood merely as terms to distinguish the components.

[0023] Parts indicated by the same reference number throughout the specification represent the same components.

[0025] FIG. 1 is a circuit diagram showing a part of a DRAM cell array having two transistors according to one embodiment of the present invention.

[0026] Referring to FIG. 1, a plurality of mutually parallel write word lines (WWL) and a plurality of mutually parallel write bit lines (WBL) intersecting therein may be arranged. Additionally, a plurality of mutually parallel read word lines (RWL) and a plurality of mutually parallel read bit lines (RBL) intersecting therein may be arranged. The read word lines (RWL) may be arranged parallel to the write word lines (WWL), and the read bit lines (RBL) may be arranged parallel to the write bit lines (WBL).

[0027] Unit cells (UC) may be placed in the intersection areas of the write word lines (WWL) and the write bit lines (WBL), respectively. The intersection areas of the read word lines (RWL) and the read bit lines (RBL) may overlap with the intersection areas of the write word lines (WWL) and the write bit lines (WBL). Accordingly, it may be said that the unit cells (UC) are placed in the intersection areas of the read word lines (RWL) and the read bit lines (RBL), respectively.

[0028] The unit cell (UC) may be equipped with a write thin-film transistor (WTr) and a read thin-film transistor (RTr). Both the write thin-film transistor (WTr) and the read thin-film transistor (RTr) may be N-type thin-film transistors. However, not limited thereto, in one example, both the write thin-film transistor (WTr) and the read thin-film transistor (RTr) may be P-type thin-film transistors, or in another example, one of the write thin-film transistor (WTr) and the read thin-film transistor (RTr) may be an N-type thin-film transistor and the other a P-type thin-film transistor.

[0029] The gate electrode of the write thin-film transistor (WTr) may be electrically connected to the write word line (WWL), and the drain electrode of the write thin-film transistor (WTr) may be electrically connected to the write bit line (WBL). The source electrode of the write thin-film transistor (WTr) may be electrically connected to the gate electrode of the read thin-film transistor (RTr), the source electrode of the read thin-film transistor (RTr) may be electrically connected to the read word line (RWL), and the drain electrode of the read thin-film transistor (RTr) may be electrically connected to the read bit line (RBL). The source electrode of the write thin-film transistor (WTr) and the gate electrode of the read thin-film transistor (RTr) may form a storage node (N).

[0030] In this DRAM writing operation, a ground voltage, for example 0V, is applied to the read word lines (RWL) and read bit lines (RBL); one of the write word lines (WWL) is selected to provide a first switch signal, and one of the write bit lines (WBL) is selected to provide a first level signal, so that the write thin-film transistor (WTr) of the selected unit cell at the intersection point is turned on to store the first level signal in the storage node (N). Meanwhile, a second level signal is provided to the selected write bit line (WBL) to store the second level signal in the storage node (N). A first level signal stored in the storage node (N) can turn on the read thin-film transistors (RTr), and a second level signal stored in the storage node (N) can turn off the read thin-film transistors (RTr), but when ground voltage is applied to both the read word line (RWL) and the read bit line (RBL), current detection may not occur in the read bit line (RBL).

[0031] When a second switch signal is provided to the write word line (WWL), the write thin-film transistor (WTr) connected to the gate is turned off, so the information stored in the storage node (N) can be maintained. However, since the information stored in the storage node (N) may be lost due to channel leakage current and / or gate leakage current of the write thin-film transistor (WTr), a refresh operation to store information in the storage node (N) again can be performed periodically.

[0032] Afterwards, the operation of reading information stored in the storage node (N) is performed by providing a second switch signal to the write word line (WWL) so that the write thin-film transistor (WTr), to which the gate is connected, is turned off, and applying a ground voltage, for example 0V, to the read word lines (RWL), and applying a third level signal, which is a voltage higher than the ground voltage, to the read bit line (RBL), so that the current value detected in the read bit line (RBL) may differ depending on the on or off state of the read thin-film transistor (RTr), and this can be detected as logic information. Specifically, when a first level signal is stored in the storage node (N) and the read thin-film transistor (RTr) is in the on state, a high current is detected in the read bit line (RBL), and the first level signal stored in the storage node (N) can be detected as logic information "1". Meanwhile, when a second level signal is stored in the storage node (N) and the read thin-film transistor (RTr) is in the off state, a small current is detected in the read bit line (RBL), and the second level signal stored in the storage node (N) can be detected as logic information "0".

[0033] Since such a DRAM has two transistors but no capacitor, it can be named a 2TOC DRAM.

[0035] FIG. 2 is a layout diagram showing a part of a DRAM cell array having two transistors according to an embodiment of the present invention, FIG. 3 is a perspective view showing a part of the DRAM cell array shown in FIG. 2, FIG. 4a, FIG. 5a, FIG. 6a, FIG. 7a, and FIG. 8a are cross-sectional views taken at each process step along the cutting line II' of FIG. 2, FIG. 4b, FIG. 5b, FIG. 6b, FIG. 7b, and FIG. 8b are cross-sectional views taken at each process step along the cutting line II-II' of FIG. 2.

[0036] Referring to FIGS. 2, FIGS. 3, FIGS. 4a, and FIGS. 4b, a base insulating film (not shown) may be disposed on a substrate (10). The substrate (10) may be a semiconductor substrate such as a silicon substrate or a GaAs substrate, an insulating substrate such as a glass substrate or sapphire, or a polymer substrate. The base insulating film may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, but is not limited thereto. In one example, the substrate (10) may be a silicon substrate and the base insulating film may be a silicon oxide film. In one example, other elements may be disposed within the base insulating film.

[0037] A first electrode layer can be formed on a base insulating film and patterned to form first signal lines (110) parallel to each other. The first signal lines (110) may extend in the X-axis direction as an example of a first direction. The first signal lines (110) may be read bit lines (RBL of FIG. 1).

[0038] A first interlayer insulating film (20) covering the first signal lines (110) can be formed on the first signal lines (110). The first interlayer insulating film (20) can be flattened, specifically by chemical mechanical polishing (CMP). A second electrode layer can be formed on the first interlayer insulating film (20) and patterned to form second signal lines (120) parallel to each other. The second signal lines (120) can extend in the Y-axis direction, as an example of a second direction. The second signal lines (120) may be read word lines (RWL in FIG. 1). However, not limited thereto, the first signal lines (110) may be read word lines (RWL in FIG. 1), and the second signal lines (120) may be read bit lines (RBL in FIG. 1).

[0039] A first inter-wire insulating film (30) covering the second signal lines (120) can be formed on the second signal lines (120). The first inter-wire insulating film (30) can be flattened, specifically by CMP. In one example, as illustrated, the first inter-wire insulating film (30) can be flattened until the second signal lines (120) are exposed. However, it is not limited thereto, and the first inter-wire insulating film (30) may remain on the second signal lines (120).

[0040] 2 signal lines (120) If the first inter-wire insulating film (30) remains on the upper side, lower openings (35) can be formed to expose the first signal lines (110) within the first inter-wire insulating film (30), the second signal lines (120), and the first inter-layer insulating film (20). The lower openings (35) can be formed in the intersection areas where the second signal lines (120) and the first signal lines (110) intersect. The intersection areas where the second signal lines (120) and the first signal lines (110) intersect can each be defined as unit cell areas (UC).

[0041] Referring to FIGS. 2, FIGS. 3, FIGS. 5a, and FIGS. 5b, a read semiconductor layer (130) and a read gate insulating film (140) can be conformally formed in sequence on the bottom surface and side wall of each lower opening (35) that exposes the first signal line (110). To this end, both the read semiconductor layer (130) and the read gate insulating film (140) can be formed using atomic layer deposition (ALD). The remaining area of ​​the lower opening (35), where the bottom surface and side wall are coated with the read gate insulating film (140), can be filled with a read gate electrode layer. A write source electrode layer can be disposed on the read gate electrode layer.

[0042] Afterwards, the writing source electrode layer, the reading gate electrode layer, the reading gate insulating film (140), and the reading semiconductor layer (130) can be patterned using photolithography so that the reading semiconductor layer (130), the reading gate insulating film (140), the reading gate electrode (150), and the writing source electrode (210) are positioned separately within each unit cell region (UC).

[0043] In the above description, the read gate electrode (150) and the write source electrode (210) were described as separate layers, but they are not limited thereto and can be formed as a single electrode to simultaneously perform the roles of the read gate electrode (150) and the write source electrode (210). The read gate electrode (150) and the write source electrode (210) may also be named as storage node electrodes or storage node (N in FIG. 1).

[0044] Referring to FIGS. 2, FIGS. 3, FIGS. 6a, and FIGS. 6b, after forming a second inter-wire insulating film (40) covering the storage node, specifically the write source electrode (210), the second inter-wire insulating film (40) can be flattened, specifically CMP, until the upper surface of the write source electrode (210) is exposed. As a result, the upper surface of the second inter-wire insulating film (40) can be formed to be at the same level as the upper surface of the storage node, specifically the write source electrode (210).

[0045] A second interlayer insulating film (50) can be formed on a storage node specifically, a write source electrode (210), exposed by the second interlayer insulating film (40). A third electrode layer can be formed on the second interlayer insulating film (50) and patterned to form third signal lines (250) parallel to each other. The third signal lines (250) can be extended in the Y-axis direction, as an example of a third direction. The third signal lines (250) can be write word lines (WWL in FIG. 1). The third signal lines (250) can be formed to be aligned with the second signal lines (120), extend in the same direction, and have the same width.

[0046] A third interlayer insulating film (60) covering the third signal lines (250) can be formed on the third signal lines (250). The upper surface of the third interlayer insulating film (60) can be flattened, specifically by CMP.

[0047] Upper openings (65) that expose a storage node, specifically a write source electrode (210), can be formed in the third interlayer insulating film (60), the third signal lines (250), and the second interlayer insulating film (50), respectively.

[0048] Referring to FIGS. 2, FIGS. 3, FIGS. 7a, and FIGS. 7b, after conformally forming a write gate insulating film on the bottom surface and side wall of each upper opening (65), the write gate insulating film can be anisotropically etched to leave a write gate insulating film (240) on the side wall of the upper opening (65) while exposing a storage node, specifically a write source electrode (210), on the bottom surface of the upper opening (65).

[0049] Afterwards, a writing source electrode (210) is exposed on the bottom surface and a writing gate insulating film (240) is formed on the side wall of the upper opening (65), and a writing semiconductor layer (230) can be conformally formed on the bottom surface and the side wall. Both the writing gate insulating film (240) and the writing semiconductor layer (230) can be formed using ALD.

[0050] Afterward, the writing semiconductor layer (230) can be patterned so that the writing semiconductor layer (230) has a shape that extends partially around the upper opening (65). In another example, the procedure for patterning the writing semiconductor layer (230) may be omitted.

[0051] Referring to FIGS. 2, FIGS. 3, FIGS. 8a, and FIGS. 8b, a filler insulating film (70) is formed on a writing semiconductor layer (230), and the remaining area of ​​the upper opening (65) where the writing semiconductor layer (230) is formed on the sidewall and bottom surface can be filled with the filler insulating film (70, filler dielectric). Afterwards, the filler insulating film (70) can be flattened, specifically CMP, until the upper surface of the writing semiconductor layer (230) or the third interlayer insulating film (60) is exposed. If the above procedure for patterning the writing semiconductor layer (230) is omitted, or if the filler insulating film (70) is flattened until the third interlayer insulating film (60) is exposed during the CMP process, the writing semiconductor layer (230) may be limited within the upper opening (65).

[0052] A fourth electrode layer can be formed on a flattened filler insulating film (70) and patterned to form fourth signal lines (220) that are parallel to each other while connected to the upper surface of the writing semiconductor layers (230) of the unit cells. The fourth signal lines (220) may extend in the X-axis direction as an example of a fourth direction. The fourth signal lines (220) may be formed to be aligned with the first signal lines (110), extend in the same direction, and have the same width as the first signal lines (110). The fourth signal lines (220) may be writing bit lines (WBL of FIG. 1).

[0054] With reference to FIGS. 1, 2, 3, 8a, and 8b, the unit cell structure of a DRAM cell array according to one embodiment of the present invention will be described once again.

[0055] First signal lines (110) extending in a first direction and parallel to each other, second signal lines (120) extending in a second direction and intersecting the first signal lines (110) above the first signal lines (110), third signal lines (250) extending in a third direction and parallel to each other above the second signal lines (120), and fourth signal lines (220) extending in a fourth direction and intersecting the third signal lines (250) above the third signal lines (250) may be arranged. Areas where the first signal lines (110) and the second signal lines (120) intersect may each be located vertically below the areas where the third signal lines (250) and the fourth signal lines (220) intersect, and these areas may be defined as unit cell areas (UC).

[0056] In the drawing, the first and fourth directions are indicated as the X-axis, and the second and third directions are indicated as the Y-axis, but are not limited thereto. As an example, the areas where the third signal lines (250) and the fourth signal lines (220) intersect are above the areas where the first signal lines (110) and the second signal lines (120) intersect, and the extension directions of the signal lines can be freely selected as long as they can be aligned and overlapped with each of them from the vertical upper side. As an example, when the first signal lines (110) are extended in the X-axis direction and the second signal lines (120) are extended in the Y-axis direction, the third signal lines (250) may be extended to have a positive slope in the XY plane, and the fourth signal lines (220) may be extended to have a negative slope in the XY plane.

[0057] The first signal lines (110) may be read bit lines (RBL in FIG. 1) and the second signal lines (120) may be read word lines (RWL in FIG. 1). However, not limited thereto, the first signal lines (110) may be read word lines (RWL in FIG. 1) and the second signal lines (120) may be read bit lines (RBL in FIG. 1). The third signal lines (250) may be write word lines (WWL in FIG. 1). The fourth signal lines (220) may be write bit lines (WBL in FIG. 1).

[0058] A first interlayer insulating film (20) may be disposed between the first signal lines (110) and the second signal lines (120). Specifically, an interlayer insulating film (40) and a second interlayer insulating film (50) may be disposed between the second signal lines (120) and the third signal lines (250). A third interlayer insulating film (60) may be disposed between the third signal lines (250) and the fourth signal lines (220).

[0059] As previously explained, the areas where the first signal lines (110) and the second signal lines (120) intersect can each be defined as unit cell areas, and within each unit cell area, an area where the third signal lines (250) and the fourth signal lines (220) intersect can be placed.

[0060] Read transistors (RTr) may be disposed in the areas where the first signal lines (110) and the second signal lines (120) intersect, i.e., in the unit cell areas. Specifically, in each unit cell area, the first signal line (110) may be the first read source / drain electrode of the read transistor (RTr), and the second signal line (120) may be the second read source / drain electrode of the read transistor (RTr). However, not limited thereto, the read transistor (RTr) may further include a separate first read source / drain electrode connected to the first signal line (110) and / or a separate second read source / drain electrode connected to the second signal line (120). In this case, the source / drain electrodes may be distinguished and named as a source electrode and a drain electrode depending on their role during DRAM operation.

[0061] As previously described, a first interlayer insulating film (20) is disposed between the first signal lines (110) and the second signal lines (120), and in each unit cell region (UC), a lower opening is formed within the second signal line (120) and the first interlayer insulating film (20) to penetrate them and expose the first signal line (110), and the read transistor (RTr) may include a storage node electrode disposed within the lower opening as a read gate electrode or may include a separate read gate electrode (150). The storage node electrode, specifically the read gate electrode (150), may have an upper surface at a higher level than the upper surface of the second signal line (120) around the lower opening, and further extend onto the second signal line (120) around the lower opening within the unit cell region.

[0062] The read transistor (RTr) may further include a read semiconductor layer (130) between the storage node electrode, specifically the read gate electrode (150), and the sidewall and bottom surface of the lower opening. The read semiconductor layer (130) may be extended onto the second signal line (120) within a unit cell region when the read gate electrode (150) extends onto the second signal line (120) around the lower opening, and may be disposed between the read gate electrode (150) and the second signal line (120) in this region as well. This read semiconductor layer (130) may be connected to the second signal line (120) exposed within the sidewall of the lower opening and to the first signal line (110) exposed on the bottom of the lower opening. When the reading semiconductor layer (130) is extended onto the second signal line (120), it may be connected to the second signal line (120) in this region as well, but is not limited thereto, and an insulating film (30) between the wires may be located between the reading semiconductor layer (130) and the second signal line (120) in this region.

[0063] The read transistor (RTr) may further include a read gate insulating film (140) disposed between the storage node electrode, specifically the read gate electrode (150) and the read semiconductor layer (130).

[0064] This read transistor (RTr) can be named a vertical channel transistor because the read semiconductor layer (130) is positioned vertically with respect to the substrate (10) on the side wall of the lower opening, and can also be named a channel-all-around (CAA) thin-film transistor because the read semiconductor layer (130) surrounds the read gate electrode (150) within the lower opening.

[0065] Write transistors (WTr) may be disposed in each of the areas where the third signal lines (250) and the fourth signal lines (220) intersect, i.e., unit cell areas. Specifically, in each unit cell area (UC), the storage node electrode may serve as the write source electrode of the write transistor (WTr), or the write transistor (WTr) may include a separate write source electrode (210) connected to the read gate electrode (150). In this case, the storage node electrode may include the read gate electrode (150) and the write source electrode (210). Additionally, in each unit cell area, the third signal line (250) may be the write gate electrode of the write transistor (WTr), and the fourth signal line (220) may be the write drain electrode of the write transistor (WTr). However, not limited thereto, the write transistor (WTr) may further include a separate write gate electrode connected to the third signal line (250) and / or a separate write drain electrode connected to the fourth signal line (220).

[0066] A second interlayer insulating film (50) is disposed between the storage node electrode, specifically the writing source electrode (210), and the third signal line (250), and a third interlayer insulating film (60) is disposed between the third signal line (250) and the fourth signal line (220). An upper opening may be formed by penetrating the third interlayer insulating film (60), the third signal line (250), and the second interlayer insulating film (50) so that the third signal line (250) is exposed within the side wall and the storage node electrode, specifically the writing source electrode (210), is exposed on the bottom.

[0067] A write transistor (WTr) may include a write semiconductor layer (230) that is connected to a storage node electrode, specifically a write source electrode (210), exposed at the bottom of the upper opening within the upper opening, and extends over the sidewall of the upper opening. The write semiconductor layer (230) may also extend over a third interlayer insulating film (60) around the upper opening. The write transistor (WTr) may include a write gate insulating film (240) between the third signal line (250) and the write semiconductor layer (230). The upper opening, with its bottom and sidewall coated by the write semiconductor layer (230), may be filled by a filler insulating film (70). A fourth signal line (220), which is a write drain electrode, may be connected to the write semiconductor layer (230).

[0068] This writing transistor (WTr) can be named a vertical channel transistor because the writing semiconductor layer (230) is positioned vertically with respect to the substrate (10) on the side wall of the upper opening, and also a gate-all-around (GAA) thin film transistor because the third signal line (250), which is the writing gate electrode, surrounds the writing semiconductor layer (230).

[0069] In this way, by stacking a GAA thin-film transistor, wherein a storage node electrode, specifically a write source electrode (210), is disposed on the lower side of a CAA thin-film transistor, wherein a storage node electrode, specifically a read gate electrode (150), is exposed on the upper side, when the signal lines (110, 120, 250, 220) each have a minimum line width and minimum spacing of 1F (Feature size), the X-axis length of the unit cell (UC) becomes 2F and the Y-axis length becomes 2F, and the area of ​​the unit cell (UC) becomes 4F 2It can be. As such, considering that a traditional DRAM consisting of one transistor and one capacitor (1T1C) has a 6F² structure, it can be seen that the unit cell area is significantly reduced in the DRAM having a 2TOC structure with two transistors and zero capacitors according to the present invention.

[0070] In addition, by configuring the write transistor (WTr) with a GAA thin-film transistor having excellent gate channel controllability, the channel leakage current of the write transistor (WTr) can be suppressed, thereby increasing the data retention time of the 2TOC DRAM. In addition, by configuring the read transistor (RTr) with a CAA thin-film transistor exhibiting a relatively high on-current, the operating speed of the 2TOC DRAM can be improved.

[0071] Meanwhile, the signal lines (110, 120, 250, 220), the read gate electrode (150), and the write source electrode (210) may include, independently of each other, a conductive metal such as platinum (Pt), ruthenium (Ru), iridium (Ir), silver (Ag), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), silicon (Si), copper (Cu), nickel (Ni), cobalt (Co), or molybdenum (Mo), or an alloy thereof; or a conductive metal oxide film such as ITO (Indium Tin Oxide), but are not limited thereto. In one example, the first signal lines (110) may be a double layer of ITO / W, the second to fourth signal lines (120, 250, 220) may be a W layer, the read gate electrode (150) may be a W layer, and the write source electrode (210) may be an ITO layer.

[0072] The reading semiconductor layer (130) and the writing semiconductor layer (230) may be metal oxide semiconductor layers, specifically oxide semiconductor layers containing at least two metals among indium, gallium, tin, and zinc, specifically IGZO (Indium Gallium Zinc Oxide), ZTO (Zinc Tin Oxide), IZO (Indium Zinc Oxide), or IGO (Indium Gallium Oxide). In one embodiment, both the reading semiconductor layer (130) and the writing semiconductor layer (230) may be IGO (Indium Gallium Oxide), in which case the reading semiconductor layer (130) may be formed of IGO having a higher indium content than the writing semiconductor layer (230). Specifically, the reading semiconductor layer (130) may contain indium at 70 at% or more, specifically 72 at% or more, more specifically 75 at% or more, as an example, 80 at% relative to the total number of atoms of indium and gallium. On the other hand, the writing semiconductor layer (230) may contain less than 70 at% of indium relative to the total number of atoms of indium and gallium, specifically 65 at% or less, as an example, 63 at%. In this case, the reading transistor (RTr) exhibits a higher on-current and higher charge mobility compared to the writing transistor (WTr), thereby improving the operating speed of the 2TOC DRAM.

[0073] The reading semiconductor layer (130) and the writing semiconductor layer (230) may have a thickness of about 3 to 10 nm.

[0074] In one embodiment, the read gate insulating film (140) and the write gate insulating film (240) may both be insulating films with a dielectric constant higher than that of a silicon oxide film. Furthermore, the read gate insulating film (140) may be an insulating film with a dielectric constant higher than that of a write gate insulating film (240). In one example, the read gate insulating film (140) may be an HfO2 film as an example of a hafnium oxide film, and the write gate insulating film (240) may be an Al2O3 film as an example of an aluminum oxide film. In this case, the read transistor (RTr) may exhibit a higher on-current and higher charge mobility compared to the write transistor (WTr) to improve the operating speed of the 2TOC DRAM, and the write transistor (WTr) may exhibit a lower gate leakage current compared to the read transistor (RTr) to increase the data retention time of the 2TOC DRAM.

[0075] The filler insulating film (70) may be an aluminum oxide film (e.g., Al2O3). In this case, when forming the filler insulating film (70), the writing semiconductor layer (230) is passivated so that the threshold voltage of the writing transistor (WTr) can be shifted in a positive direction, specifically to a positive value. In this case, the writing transistor (WTr) can be in a "normally off" state, and as the channel leakage current is lowered, the data retention time of the 2TOC DRAM can be increased. Additionally, the aluminum oxide film prevents hydrogen from diffusing into the writing semiconductor layer (230) during subsequent processes, thereby suppressing changes in the characteristics of the writing transistor (WTr).

[0076] The aluminum oxide film (e.g., Al2O3) formed as a filler insulating film (70) can be formed using an ALD process using an aluminum precursor (e.g., trimethylaluminum) and oxygen as an oxidizing agent, and can be formed using an oxygen partial pressure of 5 to 15 vol% when oxygen is supplied.

[0077] The insulating films (20, 30, 40, 50, 60) may be silicon oxide, silicon nitride, or silicon oxynitride films regardless of one another, but are not limited thereto.

[0079] FIG. 9 is a photograph showing a planar 2T0C DRAM fabricated for characteristic evaluation, and FIG. 10 is a schematic diagram showing a cross-section thereof. Here, SN means storage node.

[0080] Figures 11a and 11b are graphs showing the voltage of the storage node over time after a write operation when the gate insulating films of the transistors in a 2T0C DRAM fabricated as in Figures 9 and 10 are formed with Al2O3 and HfO2 films, respectively.

[0081] Referring to Figures 11a and 11b, it can be seen that the voltage of the storage node remains constant with almost no change when the gate insulating film is an Al2O3 film, whereas it decreases rapidly when the gate insulating film is an HfO2 film.

[0082] The decrease in voltage at the storage node electrode is caused by leakage current of the write transistor, and from these results, it can be seen that the data retention time of the 2T0C DRAM increases when the gate insulating film of the write transistor is formed with an Al2O3 film.

[0084] FIG. 12 is a graph showing the transfer characteristics of a read transistor when the gate insulating film of the read transistor illustrated in FIG. 9 and 10 is formed with an Al2O3 film and an HfO2 film. In FIG. 11, the right Y-axis represents the charge mobility (μ LIN , cm 2 / Vs) represents.

[0085] Referring to Figure 12, it can be seen that when the gate insulating film is an HfO2 film compared to an Al2O3 film, the transistor can exhibit higher charge mobility and higher on-current characteristics.

[0086] Accordingly, if the gate insulating film of the read transistor is formed with an HfO2 film, the operating speed of the 2T0C DRAM can be increased.

[0087] FIG. 13 is a graph showing the transfer characteristics of a read transistor according to the composition of the semiconductor layer of the read transistor illustrated in FIG. 9 and FIG. 10. The semiconductor layer was formed as an IGO layer using ALD, and In oxide (InO₂) included in the ALD unit cycle x Subcycle for ) manufacturing and Ga oxide (GaO x The IGO layer was manufactured by varying the subcycle ratio to 6:3, 9:3, and 12:3. When the subcycle ratio was 6:3, the IGO layer contained 63% indium relative to the total number of indium and gallium atoms; when the subcycle ratio was 9:3, the IGO layer contained 72% indium relative to the total number of indium and gallium atoms; and when the subcycle ratio was 12:3, the IGO layer contained 80% indium relative to the total number of indium and gallium atoms. At this time, the gate insulating film was an Al2O3 film.

[0088] Referring to FIG. 13, it can be seen that the on-current increases as the indium content in the IGO semiconductor layer increases. Specifically, it can be seen that for an increase in on-current, the semiconductor layer of the reading transistor contains 70 at% or more of indium, specifically 75 at% or more, as an example, 80 at% or more, relative to the total number of atoms of indium and gallium.

[0089] Meanwhile, as the indium content in the IGO semiconductor layer decreases, the threshold voltage (V TH It can be seen that ) moves in the positive direction. In the case of a write transistor, the threshold voltage (V THConsidering that the off-current, i.e., leakage current, is lower the more positive the direction, it can be seen that it is desirable for the writing semiconductor layer to contain less than 70 at%, specifically 65 at% or less, as an example, 63 at% or less relative to the total number of atoms of indium and gallium.

[0091] FIG. 14 is a graph showing the transfer characteristics of a write transistor when the write transistor is formed as a Gate-All-Around (GAA) thin-film transistor as shown in FIG. 8a and 8b, but the write semiconductor layer is formed under the IGO (6:3) conditions of FIG. 13 and the filler insulating film is formed as an Al2O3 film.

[0092] At this time, the Al2O3 film was formed using ALD with an aluminum precursor (trimethylaluminum) and oxygen, with the oxygen partial pressure at 10 vol% (90 vol% is argon) when oxygen was supplied.

[0093] Referring to Figure 14, it can be seen that the threshold voltage of the write transistor has a positive value of 0.58V. As such, when aluminum oxide is applied as a filler insulating film in a write transistor having a GAA structure, the threshold voltage can be made positive, allowing the write transistor to be turned "normally off".

[0094] Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications and changes are possible by those skilled in the art within the technical spirit and scope of the present invention.

Claims

Claim 1 A first signal line extending in a first direction on a substrate; a first interlayer insulating film disposed on the first signal line; a second signal line extending in a second direction intersecting the first signal line on the first interlayer insulating film; a storage node electrode disposed within a lower opening through which the second signal line and the first interlayer insulating film penetrate, and the second signal line is exposed within a sidewall and the first signal line is exposed within a bottom surface; a reading semiconductor layer disposed between the storage node electrode and the sidewall and bottom surface of the lower opening, and electrically connected to the second signal line exposed within the sidewall of the lower opening and the first signal line exposed within the bottom surface of the lower opening; a reading gate insulating film disposed between the storage node electrode and the reading semiconductor layer; a second interlayer insulating film disposed on the storage node electrode, a third signal line extending in a third direction disposed on the second interlayer insulating film, and a third interlayer insulating film disposed on the third signal line; the third interlayer insulating film, the third signal line, and the second interlayer insulating film A DRAM comprising: a write semiconductor layer electrically connected to the storage node electrode exposed within the bottom surface of the upper opening, wherein the third signal line is exposed within the side wall and the storage node electrode is exposed within the bottom surface of the upper opening, the write semiconductor layer; a write gate insulating film disposed between the write semiconductor layer and the third signal line exposed within the side wall of the upper opening; and a fourth signal line extending in a fourth direction intersecting the third signal line on the third interlayer insulating film and electrically connected to the write semiconductor layer. Claim 2 The DRAM according to claim 1, wherein the storage node electrode comprises a read gate electrode disposed within the lower opening and a write source electrode disposed on the read gate electrode. Claim 3 A DRAM according to claim 1, wherein the first direction and the fourth direction are X-axis directions, and the second direction and the third direction are Y-axis directions. Claim 4 A DRAM according to claim 1, wherein either of the first signal line and the second signal line is a read bit line and the other is a read word line, the third signal line is a write word line, and the fourth signal line is a write bit line. Claim 5 A DRAM according to claim 1, wherein the read semiconductor layer is conformally formed on the bottom surface and side wall of the lower opening, the read gate insulating film is conformally formed on the read semiconductor layer, the storage node electrode fills the remaining area of ​​the lower opening where the read semiconductor layer and the read gate insulating film are formed, and has an upper surface at a level higher than the second signal line. Claim 6 A DRAM according to claim 1, wherein the write semiconductor layer is conformally formed on the bottom surface and side wall of the upper opening, and further comprises a filler insulating layer disposed below the fourth signal line, filling the remaining area of ​​the upper opening where the write gate insulating layer and the write semiconductor layer are formed. Claim 7 In claim 6, the filler insulating film is an aluminum oxide film in the DRAM. Claim 8 A DRAM according to claim 1 or claim 6, wherein the writing semiconductor layer is a metal oxide semiconductor layer. Claim 9 A DRAM according to claim 8, wherein the metal oxide semiconductor layer is an IGO (Indium Gallium Oxide) layer. Claim 10 In claim 1, the reading semiconductor layer is a metal oxide semiconductor layer in the DRAM. Claim 11 A DRAM according to claim 10, wherein the metal oxide semiconductor layer is an IGO (Indium Gallium Oxide) layer. Claim 12 A DRAM according to claim 1, wherein both the write semiconductor layer and the read semiconductor layer are IGO (Indium Gallium Oxide) layers, and the read semiconductor layer has a higher indium content than the write semiconductor layer. Claim 13 A DRAM according to claim 1, wherein the read gate insulating film and the write gate insulating film are both insulating films with a dielectric constant higher than that of a silicon oxide film. Claim 14 In claim 13, the read gate insulating film is a DRAM in which the dielectric constant is higher than that of the write gate insulating film. Claim 15 A DRAM according to claim 14, wherein the read gate insulating film is a hafnium oxide film and the write gate insulating film is an aluminum oxide film. Claim 16 A step of forming a first signal line extending in a first direction on a substrate; a step of forming a first interlayer insulating film on the first signal line; a step of forming a second signal line extending in a second direction intersecting the first signal line on the first interlayer insulating film; a step of forming a lower opening that penetrates the second signal line and the first interlayer insulating film, wherein the second signal line is exposed within a sidewall and the first signal line is exposed within a bottom surface; a step of conformally forming a read semiconductor layer that is electrically connected to the second signal line exposed within the sidewall of the lower opening and the first signal line exposed within the bottom surface of the lower opening, and a read gate insulating film on top thereof within the lower opening; a step of forming a storage node electrode that fills the remaining area of ​​the lower opening on the read gate insulating film. A method for manufacturing a DRAM comprising: forming a second interlayer insulating film disposed on the storage node electrode, forming a third signal line extending in a third direction on the second interlayer insulating film, and forming a third interlayer insulating film on the third signal line; forming an upper opening within the third interlayer insulating film, the third signal line, and the second interlayer insulating film, penetrating them such that the third signal line is exposed within a sidewall and the storage node electrode is exposed within a bottom surface; forming a write gate insulating film covering the third signal line exposed on the sidewall of the upper opening; forming a write semiconductor layer electrically connected to the storage node electrode exposed within the bottom surface of the upper opening on the write gate insulating film disposed on the sidewall of the upper opening; and forming a fourth signal line extending in a fourth direction intersecting the third signal line on the third interlayer insulating film and electrically connected to the write semiconductor layer. Claim 17 A method for manufacturing a DRAM according to claim 16, wherein the storage node electrode comprises a read gate electrode filling the lower opening and a write source electrode disposed on the read gate electrode. Claim 18 A method for manufacturing a DRAM according to claim 16, wherein the first direction and the fourth direction are X-axis directions, and the second direction and the third direction are Y-axis directions. Claim 19 A method for manufacturing a DRAM according to claim 16, wherein either of the first signal line and the second signal line is a read bit line and the other is a read word line, the third signal line is a write word line, and the fourth signal line is a write bit line. Claim 20 A method for manufacturing a DRAM according to claim 16, wherein the write semiconductor layer is conformally formed on the bottom surface and side wall of the upper opening, and further comprising the step of forming a filler insulating film that fills the remaining area of ​​the upper opening where the write gate insulating film and the write semiconductor layer are formed before forming the fourth signal line. Claim 21 A method for manufacturing a DRAM according to claim 20, wherein the filler insulating film is an aluminum oxide film. Claim 22 A method for manufacturing a DRAM according to claim 16 or claim 21, wherein the writing semiconductor layer is a metal oxide semiconductor layer. Claim 23 A method for manufacturing a DRAM according to claim 22, wherein the metal oxide semiconductor layer is an IGO (Indium Gallium Oxide) layer. Claim 24 A method for manufacturing a DRAM according to claim 16, wherein the reading semiconductor layer is a metal oxide semiconductor layer. Claim 25 A method for manufacturing a DRAM according to claim 24, wherein the metal oxide semiconductor layer is an IGO (Indium Gallium Oxide) layer. Claim 26 A method for manufacturing a DRAM according to claim 16, wherein the writing semiconductor layer and the reading semiconductor layer are both IGO (Indium Gallium Oxide) layers, and the reading semiconductor layer has a higher indium content than the writing semiconductor layer. Claim 27 A method for manufacturing a DRAM according to claim 16, wherein the read gate insulating film and the write gate insulating film are both insulating films with a dielectric constant higher than that of a silicon oxide film. Claim 28 A method for manufacturing a DRAM according to claim 27, wherein the read gate insulating film is an insulating film with a higher dielectric constant than the write gate insulating film. Claim 29 A method for manufacturing a DRAM according to claim 28, wherein the read gate insulating film is a hafnium oxide film and the write gate insulating film is an aluminum oxide film.

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