Copper Iodide Semiconductor Material, P-type Transistor, and Their Manufacturing Methods

Abstract

The present invention discloses a Cd ion-doped copper iodide semiconductor material, a p-type transistor, and a method for manufacturing the same. The Cd ion-doped copper iodide semiconductor material of the present invention can provide high air stability, and by using the copper iodide semiconductor material together with a SiOx encapsulation material, surface defects of the copper iodide semiconductor material can be de-passivated, thereby providing a transistor with significantly improved performance.

Description

Technology Field

[0001] The present invention relates to a copper iodide semiconductor material, a p-type transistor, and a method for manufacturing the same. More specifically, it relates to a Cd2+ cation-doped copper iodide semiconductor material, a p-type transistor, and a method for manufacturing the same, which can be utilized in the fields of electronics, energy, and display. Background Technology

[0002] Copper iodide (CuI) has been studied as a next-generation transparent p-type semiconductor material due to its wide bandgap of 3.1 eV and high hole conductivity. In particular, the valence band composed of widely dispersed iodine (I) 5p orbitals allows CuI to have a low hole effective mass of 0.3 me. The high hole mobility resulting from this has been the impetus for researchers to attempt to develop thin-film transistors using CuI as a p-type semiconductor material.

[0003] However, due to the low hole formation energy of Copper (Cu) at 0.085 eV / atom, it is necessary to lower the hole concentration through extrinsic metal ion doping to use it as a semiconductor material. Accordingly, Professor Yong-Young Noh's group at POSTECH has successfully fabricated a p-type thin-film transistor by doping CuI with ZnI2 via a solution process. The thin-film transistor is 5 cm 2 High saturation mobility at the / Vs level and 10 7It operated with a high switching ratio. However, although CMOS circuits were successfully constructed using CuI:Zn thin films and indium-gallium-zinc oxide (IGZO), subsequent papers revealed that oxygen reacts with CuI:Zn thin films even in environments containing trace amounts of oxygen, altering or degrading the performance of thin-film transistors. Furthermore, to process air-sensitive CuI:Zn thin films, the process was carried out using a special photoresist that does not react with the CuI:Zn thin film inside a glove box in an inert atmosphere, but this process method is disadvantageous for industrial application. The problem to be solved

[0004] Therefore, in order to carry out effective miniaturization processes using CuI thin films as p-type transparent semiconductors, it is necessary to develop CuI thin films with higher air stability and corresponding process technologies.

[0005] One objective of the present invention is Cd 2+ The invention provides a copper iodide semiconductor material with high air stability by doping CuI with cations.

[0006] Another objective of the present invention is Cd 2+ The present invention provides a method for manufacturing a copper iodide semiconductor material capable of controlling the hole conductivity of the copper iodide semiconductor material by doping cations into CuI.

[0007] Another objective of the present invention is to provide a method for manufacturing a p-type transistor with high safety so that no damage occurs during the manufacturing process when it is used as a device in various fields.

[0008] Another objective of the present invention is to provide a p-type transistor that can be applied to inverters, ring oscillators, etc. means of solving the problem

[0009] A copper iodide semiconductor material for one purpose of the present invention is Cd 2+ It contains copper iodide doped with cations.

[0010] In one embodiment, the Cd 2+ The doping concentration of the ions can be 1.0 mol% to 10.0 mol%.

[0011] A method for manufacturing a copper iodide semiconductor material for another purpose of the present invention comprises a copper iodide solution and Cd 2+ It includes a precursor solution preparation step of preparing a precursor solution mixed with a cation solution containing cations, and a spin coating step of spin-coating the precursor solution onto a substrate.

[0012] In one embodiment, the cation solution may be a cadmium iodide (CdI2) solution.

[0013] In one embodiment, the volume ratio of the cadmium iodide solution and the copper iodide solution may be 10 μL to 110 μL per 1 ml of copper iodide solution.

[0014] A method for manufacturing a p-type transistor for another purpose of the present invention is Cd 2+ A step of forming a copper iodide semiconductor thin film doped with cations and a SiO₂ on the semiconductor thin film x (However, 1 < x < 2) includes the step of forming a thin film.

[0015] In one embodiment, the copper iodide semiconductor thin film is a copper iodide solution and Cd 2+ It may include a precursor solution preparation step of preparing a precursor solution mixed with a cation solution containing cations, and a spin coating step of spin coating the precursor solution.

[0016] In one embodiment, the cation solution may be a cadmium iodide (CdI2) solution.

[0017] In one embodiment, the volume ratio of the cadmium iodide solution and the copper iodide solution may be 10 μL to 110 μL per 1 ml of copper iodide solution.

[0018] A p-type transistor for another purpose of the present invention is Cd 2+ A copper iodide semiconductor thin film doped with cations and SiO formed on the copper iodide semiconductor thin film x (where 1 < x < 2) includes a thin film.

[0019] In one embodiment, the Cd of the semiconductor thin film 2+ The doping concentration of the ions can be 1.0 mol% to 10.0 mol%.

[0020] In one embodiment, the thickness of the SiOx thin film may be 45 to 55 nm. Effects of the invention

[0021] According to the present invention, a semiconductor material having superior air stability compared to conventional technology can be provided. Specifically, even if the semiconductor material deteriorates when exposed to air, it has the advantage of being able to reversibly recover its physical properties through low-temperature heat treatment in an inert atmosphere.

[0022] In addition, according to the present invention, Cd 2+ The hole conductivity of copper iodide semiconductor materials can be easily controlled through cation doping.

[0023] In addition, according to the present invention, a transparent transistor capable of a miniaturization process can be provided.

[0024] In addition, according to the present invention, since a stable semiconductor material is used, the semiconductor material is not damaged in subsequent processes, which has the advantage of being effectively applicable in fields such as inverters and ring oscillators. Brief explanation of the drawing

[0025] FIG. 1 is a diagram for comparing a copper iodide semiconductor material according to an embodiment of the present invention with a copper iodide semiconductor material of the prior art. Here, FIG. 1(a) is a Zn of the prior art. 2+Figure 1(b) is a drawing showing a copper iodide semiconductor material doped with iodide, and Figure 1(b) is a drawing showing a copper iodide semiconductor material according to one embodiment of the present invention. FIG. 2 is a diagram illustrating a method for manufacturing a copper iodide semiconductor material of the present invention. FIG. 3 is a Cd according to an embodiment of the present invention. 2+ This is a diagram showing (a) X-ray diffraction pattern, (b) transmittance, (c) Fermi level, and (d) band structure of CuI:Cd thin films prepared according to cation doping concentration, respectively. FIG. 4 is a diagram analyzing the stability of a CuI:Cd thin film according to an embodiment of the present invention, showing the Cd M5N when a CuI:Cd + 4.0% thin film is exposed to air and when heat treatment is performed in an inert atmosphere. 45 N 45 This is a diagram showing the Auger electron spectrum results. Figure 5 is a diagram showing the transfer characteristics of a thin-film transistor fabricated using CuI:Cd + 4.0% according to one embodiment of the present invention. Figure 6 is a diagram showing the output characteristics of a thin-film transistor fabricated using CuI:Cd + 4.0% according to one embodiment of the present invention. FIG. 7 is a diagram showing the trend of changes in transfer characteristics when a thin film transistor fabricated using CuI:Cd + 4.0% according to one embodiment of the present invention undergoes a repetitive air exposure-inert atmosphere heat treatment process five times. FIG. 8 shows a CuI:Cd thin film and SiO according to an embodiment of the present invention. x This shows a cross-sectional view of an inverter fabricated through a lithography process incorporating encapsulation material. FIG. 9 is SiO according to an embodiment of the present invention. x This is a diagram illustrating the interfacial passivation of a CuI:Cd thin film using a packaging material thin film. FIG. 10 is SiO according to an embodiment of the present invention. xThis is a diagram showing the negative voltage load reliability results of a p-type thin-film transistor using a CuI:Cd thin film with an introduced encapsulation material. FIG. 11 shows an optical microscope image of an actual 7-stage ring oscillator fabricated according to one embodiment of the present invention. FIG. 12 is a diagram showing the reduction in propagation delay and the increase in oscillation frequency as the supply voltage of a 7-stage ring oscillator according to one embodiment of the present invention increases. FIG. 13 is a diagram showing a radio signal generated when the supply terminal voltage is -30 V in a 7-stage ring oscillator according to one embodiment of the present invention. Specific details for implementing the invention

[0026] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed content is thorough and complete and to ensure that the concept of the present invention is sufficiently conveyed to those skilled in the art.

[0027] In this specification, when a component is described as being on another component, it means that it may be formed directly on the other component or that a third component may be interposed between them. Additionally, in the drawings, the thicknesses of the films and regions are exaggerated for the effective description of the technical content.

[0028] Additionally, although terms such as first, second, third, etc., have been used to describe various components in the various embodiments of this specification, these components should not be limited by such terms. These terms are used merely to distinguish one component from another. Accordingly, what is referred to as the first component in one embodiment may be referred to as the second component in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiment. Furthermore, in this specification, "and / or" is used to mean including at least one of the components listed before and after it.

[0029] In the specification, singular expressions include plural expressions unless the context clearly indicates otherwise. Furthermore, terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, components, or combinations thereof described in the specification, and should not be understood as excluding the existence or addition of one or more other features, numbers, steps, components, or combinations thereof. Additionally, in this specification, "connection" is used to include both indirectly connecting multiple components and directly connecting them.

[0030] Furthermore, in describing the present invention below, if it is determined that a detailed description of related known functions or configurations could unnecessarily obscure the essence of the invention, such detailed description will be omitted.

[0032] Copper iodide (CuI) exhibits excellent conductivity due to its low hole effective mass and high hole mobility, but there is a problem in that it is difficult to control conductivity due to the excessively high hole mobility. To solve this problem, the present invention provides a metal ion-doped semiconductor material capable of effectively controlling hole concentration and realizing stable semiconductor performance in CuI-based semiconductor materials and devices.

[0034] Copper iodide semiconductor material and method for manufacturing the same

[0035] The copper iodide semiconductor material of the present invention is Cd 2+ It is characterized by being doped with cations. The above Cd 2+ Cations have a low polarization, and by doping them, the semiconductor material of the present invention can secure excellent air stability. This high air stability facilitates additional processes (e.g., miniaturization processes) when applying the semiconductor material in the fields of electronic devices, energy devices, and optical devices. The present invention can be applied to various industrial fields as a transparent p-type transparent semiconductor material.

[0036] Preferably, the above Cd 2+ The doping concentration of cations can be 1.0 mol% to 10.0 mol%. As the doping concentration increases, the work function and Fermi level of the copper iodide semiconductor material increase, which is Cd 2+ Ions can introduce electrons, causing an n-doping effect in which the hole concentration decreases and the electron concentration increases within copper iodide. Therefore, Cd 2+ The doping concentration of the cation should not exceed 5.0 mol%, and if it exceeds this, n-type characteristics may appear excessively.

[0038] Hereinafter, with reference to FIG. 1, a copper iodide semiconductor material according to one embodiment of the present invention and a conventional copper iodide semiconductor material will be specifically described by comparison.

[0039] FIG. 1 is a diagram for comparing a copper iodide semiconductor material according to an embodiment of the present invention with a copper iodide semiconductor material of the prior art. Here, FIG. 1(a) is a Zn of the prior art. 2+ Figure 1(b) is a drawing showing a copper iodide semiconductor material doped with iodide, and Figure 1(b) is a drawing showing a copper iodide semiconductor material according to one embodiment of the present invention.

[0040] First, referring to FIG. 1 (a), the prior art Zn 2+ The copper iodide semiconductor material doped with Zn 2+ It can be confirmed that due to the high charge density and low polarization of ions, water and oxygen are easily adsorbed (strong bonding), leading to a problem where the performance of the semiconductor thin film is permanently degraded.

[0041] On the other hand, referring to FIG. 1(b), the present invention relates to Zn 2+ Cd having a lower polarization degree 2+ By providing a cation-doped copper iodide semiconductor material, it can be confirmed that oxygen and moisture molecules adsorbed on the surface can be effectively removed through low-temperature heat treatment (80°C annealing) in an inert atmosphere.

[0042] Preferably, in the present invention, the temperature range of the low-temperature heat treatment may be 80°C to 100°C. Furthermore, the low-temperature heat treatment refers to heat treatment in a low temperature range of 200°C or lower. If the temperature of the low-temperature heat treatment exceeds 100°C, the generation of iodine vacancies increases, causing a problem in which the physical properties of the semiconductor are lost.

[0043] Therefore, when manufacturing devices utilizing copper iodide semiconductor materials, the present invention enables the easy removal of air molecules adsorbed on the surface without degradation of physical properties even when exposed to air, which inevitably occurs during the integration process, thereby enhancing the stability of the semiconductor material. Furthermore, unlike conventional technologies that result in permanent damage, the present invention has the advantage of reversibly restoring physical properties through low-temperature heat treatment.

[0045] FIG. 2 is a diagram illustrating a method for manufacturing a copper iodide semiconductor material of the present invention.

[0046] Referring to FIG. 2, the method for manufacturing a copper iodide semiconductor material of the present invention comprises a copper iodide solution and Cd 2+ It includes a precursor solution preparation step (S10) for preparing a precursor solution mixed with a cation solution containing cations, and a spin coating step (S20) for spin-coating the precursor solution onto a substrate.

[0047] In the step (S10) of preparing the precursor solution, the copper iodide solution can be prepared by dissolving copper iodide powder in a solvent. The cation solution may be a solution in which cadmium iodide (CdI2) is dissolved in a solvent. The solvent may be an organic solvent, and preferably, it may be a solvent comprising one or more of acetonitrile, dimethylsulfoxide, dimethylformamide, and γ-butyrolactone. In one embodiment, the copper iodide solution may be prepared at a concentration of 100 mg / ml, and the cation solution at a concentration of 96 mg / ml.

[0048] The above precursor solution may be a mixed solution of a copper iodide solution and a cation solution. In one embodiment, the volume ratio of the cadmium iodide solution and the copper iodide solution may be 10 μL to 110 μL per 1 ml of copper iodide solution.

[0049] The substrate may be a semiconductor substrate, a glass substrate, etc., and the material is not particularly limited. In addition, the substrate may be a structure in which various material layers are stacked, rather than a single layer.

[0050] In the spin coating step (S20) above, the spin coating can be used as a conventional spin coating method suitable for the purpose of the ball invention, so it is not particularly limited.

[0052] p-type transistor and method of manufacturing the same

[0053] The p-type transistor of the present invention CD 2+ It is characterized by including a copper iodide semiconductor thin film doped with cations. By including the semiconductor thin film, the p-type transistor can have high stability against oxygen and moisture in the air, and has the effect of enabling performance recovery after degradation.

[0054] Cd of the above semiconductor thin film 2+ The doping concentration of the cation can be 1 mol% to 10 mol%. Cd 2+ If the doping concentration of cations becomes too high, an n-doping phenomenon may occur in which the hole concentration of copper iodide actually decreases.

[0055] The above p-type transistor is a SiO formed on the copper iodide semiconductor thin film. x (However, 1 < x < 2) additional thin films may be included.

[0056] The above SiO x The thin film serves as an encapsulation material and can protect the semiconductor thin film from the solvent of the photoresist and the developer for the lithography process, thereby providing a higher level of integration than conventional technology. In addition, the SiO x The thin film can improve the performance of a p-type transistor by passivating surface defects of the semiconductor thin film. In one embodiment, the SiO xThe thickness of the thin film may be 45 to 55 nm. Preferably, the SiO x The thickness of the thin film can be 50 nm. The above SiO x The thin film was deposited on a CuI:Cd thin film using an electron beam evaporator, and the deposition rate can be 0.2 Å / s to 1.0 Å / s.

[0058] The method for manufacturing a p-type transistor of the present invention is Cd 2+ It includes the step of forming a copper iodide semiconductor thin film doped with cations. Since the above step is identical to the method for manufacturing the copper iodide semiconductor material of the present invention described above, a detailed description thereof will be omitted.

[0059] The above method for manufacturing a p-type transistor involves, after the step of forming the semiconductor thin film, SiO on the semiconductor thin film. x (wherein, 1 < x < 2) includes performing a step of forming a thin film. The SiO x Thin films can be formed using the electron beam deposition method.

[0061] Below, comparative examples and embodiments are prepared, and the present invention is described in more detail through the analysis of their characteristics.

[0063] Comparative Examples and Examples

[0064] In the present invention, CuI solution and CdI2 solution were mixed in various volume ratios (0 μL to 110 μL per 1 ml of CuI solution) to prepare CuI:Cd solutions having different Cd concentrations, and CuI:Cd thin films were formed by spin-coating the CuI:Cd solutions onto a substrate.

[0065] Specifically, CuI and CdI2 solutions were prepared such that the concentration of the CuI solution was 100 mg / ml and the concentration of the CdI2 solution was 96 mg / ml, and the CuI:Cd solution was prepared by mixing the solutions in an appropriate volume ratio.

[0066] Thin films were formed from the prepared solutions through a spin coating process. Depending on the requirements, the thin films were spin-coated onto various substrates, such as Si, Al2O3, and glass. The spin coating was performed for 30 seconds at a rotational speed of 5,000 rpm, with an acceleration time of 5 seconds to reach the maximum speed, for a total spin coating duration of 35 seconds. After spin coating, a heat treatment process was performed at a low temperature of 80 to 100 ℃ to induce the evaporation of residual solvent and thin film growth.

[0067] For the fabrication and patterning process of p-type thin-film transistors using CuI:Cd, an Al2O3 substrate or an Al2O3 substrate with electrode patterns is fabricated, and a CuI:Cd solution is spin-coated. For the CuI:Cd patterning process, SiO2 is deposited onto the CuI:Cd thin film formed by spin coating via electron beam deposition. x A thin film must be deposited as a sealing layer. SiO x The deposition of the thin film protects CuI:Cd from the photoresist solvent, developer, and cleaning solution during the patterning process using commercial photoresist. After transferring the pattern onto the photoresist through a conventional lithography process, channels for the p-type thin-film transistor were patterned using a dry etching process with argon gas.

[0069] The comparative example is a thin film in which CuI is not doped with Cd ions, and is named "CuI-ref" in the present invention.

[0070] Example 1 is a CuI:Cd solution in which 1.0 mol% of CdI2 solution is added relative to the total solution, and is named "Cd + 1.0%" and "CuI:Cd + 1.0%" in the present invention.

[0071] Example 2 is a CuI:Cd solution in which 2.5 mol% of CdI2 solution is added relative to the total solution, and is named "Cd + 2.5%" and "CuI:Cd + 2.5%" in the present invention.

[0072] Example 3 is a CuI:Cd solution in which 4.0 mol% of CdI2 solution is added relative to the total solution, and is named "CuI:Cd + 4.0%" in the present invention.

[0073] Example 4 is a CuI:Cd solution in which 5.0 mol% of CdI2 solution is added relative to the total solution, and is named "Cd + 5.0%" and "CuI:Cd + 5.0%" in the present invention.

[0074] Example 5 is a CuI:Cd solution in which 10.0 mol% of CdI2 solution is added relative to the total solution, and is named "Cd + 10.0%" and "CuI:Cd + 10.0%" in the present invention.

[0076] Characteristic analysis

[0077] CD 2+ Analysis of semiconductor material characteristics according to doping concentration

[0078] FIG. 3 is a Cd according to an embodiment of the present invention. 2+ This is a diagram analyzing the characteristics of semiconductor materials according to cation doping concentration, showing (a) X-ray diffraction pattern, (b) transmittance, (c) Fermi level, and (d) band structure of each fabricated CuI:Cd thin film.

[0079] Referring to Fig. 3(a), analysis of the X-ray diffraction pattern revealed that only the CuI (111) peak was observed at CuI-ref, Cd+ 1.0%, and Cd+ 2.5%, whereas the impurity phase Cu2CdI4 (002) peak was observed at Cd+ 5.0% and Cd+ 10.0%. This indicates that as the amount of Cd ions doped increases, impurity phases are detected, and performance may actually deteriorate. Meanwhile, referring to Fig. 3(b), it can be confirmed that the CuI:Cd thin film has a transmittance of over 80% in the visible light wavelength range of 400 nm to 800 nm, regardless of the Cd concentration. Additionally, Fig. 3(c) shows that the Fermi level increases as the Cd doping concentration increases. Meanwhile, in FIG. 3(d), the band structure of the CuI:Cd thin film was examined using the results obtained from the aforementioned UV-Visible-Near-Infrared spectroscopy and UV-Photoelectron spectroscopy. It was confirmed that as the doping concentration increased, the work function and the Fermi level of the CuI:Cd thin film increased. These results demonstrate that the semiconductor thin film of the present invention can exhibit an n-doping phenomenon in which the hole concentration of CuI decreases through Cd doping.

[0080] Through this, it can be seen that the appropriate Cd doping concentration of the copper iodide semiconductor thin film of the present invention is 4.0%, which is less than 5.0%.

[0082] Semiconductor material stability analysis through surface characteristic analysis

[0083] FIG. 4 is a diagram analyzing the stability of a CuI:Cd thin film according to an embodiment of the present invention, showing the Cd M5N when a CuI:Cd + 4.0% thin film is exposed to air and when heat treatment is performed in an inert atmosphere. 45 N 45 This is a diagram showing the Auger electron spectrum results.

[0084] Referring to Fig. 4, Cd M5N 45 N 45When comparing Auger electron spectra, it can be confirmed that the Cd-OH2 formed on the surface of the CuI:Cd + 4.0% thin film exposed to air disappears through heat treatment in an inert atmosphere, and that Cd-I bonds are formed. In other words, it can be seen that when heat treatment is performed in an inert atmosphere using Cd-OH2, water molecules adsorbed on the surface of CuI:Cd are desorbed. Therefore, it can be seen that the semiconductor material of the present invention has high air stability.

[0086] Based on this, a p-type transistor was fabricated using a CuI:Cd (CuI:Cd + 4.0%) thin film doped with 4.0% Cd obtained, and the results of the analysis are shown in Figures 5 to 7.

[0088] Figure 5 is a diagram showing the transfer characteristics of a thin-film transistor fabricated using CuI:Cd + 4.0% according to one embodiment of the present invention.

[0089] Referring to Fig. 5, the CuI:Cd+ 4.0% thin film has a maximum of 5.61 cm 2 It can be confirmed that it operates with a high saturation mobility of / Vs.

[0091] Figure 6 is a diagram showing the output characteristics of a thin-film transistor fabricated using CuI:Cd + 4.0% according to one embodiment of the present invention.

[0092] Referring to Fig. 6, it can be seen that stable output characteristics can be provided even under various voltage conditions.

[0094] FIG. 7 is a diagram showing the trend of changes in transfer characteristics when a thin film transistor fabricated using CuI:Cd + 4.0% according to one embodiment of the present invention undergoes a repetitive air exposure-inert atmosphere heat treatment process five times.

[0095] Referring to Fig. 7, it can be seen that the material operates with constant performance without changes in physical properties even during repeated exposure to air and heat treatment in an inert atmosphere. In particular, it can be seen that the material returns to its original electrical characteristics through heat treatment in an inert atmosphere even after being exposed to external air for a long period of 24 hours, which is a characteristic that is impossible with conventional technology.

[0097] Subsequently, an inverter and a 7-stage ring oscillator were fabricated by additionally depositing a SiOx thin film on the semiconductor thin film of the secured p-type transistor and performing a lithography process. The SiOx thin film was deposited to a thickness of approximately 50 nm via electron beam deposition. The results of the analysis are shown in Figures 8 to 13.

[0099] FIG. 8 shows a CuI:Cd thin film and SiO according to an embodiment of the present invention. x This shows a cross-sectional view of an inverter fabricated through a lithography process incorporating encapsulation material.

[0100] Referring to FIG. 8, an inverter according to one embodiment of the present invention forms a Cr / Au electrode layer on a substrate (glass). The Cr / Au electrode layer may be formed on the substrate with a spaced interval from one another. An Al2O3 layer may be formed to cover a part or all of the substrate and the Cu / Au electrode. An electrode layer formed of Au may be formed on the Al2O3 layer, which may be formed to cover a part of the Al2O3. A CuI:Cd thin film of the present invention may be formed to cover a part of the Al2O3 layer and the Au layer. On the CuI:Cd thin film, SiO2 capable of protecting the CuI:Cd thin film is formed. x A layer can be formed. SiO x It can passivate the CuI:Cd thin film and protect the CuI:Cd thin film in subsequent processes.

[0102] FIG. 9 is SiO according to an embodiment of the present invention. xThis is a diagram illustrating the interfacial passivation of a CuI:Cd thin film using a packaging material thin film.

[0103] Referring to Fig. 9, adsorbed oxygen and surface defects present on the CuI:Cd surface are SiO₂ x It can be confirmed that passivation is achieved by the thin film. Through this passivation, CuI:Cd can be maintained more stably for a longer period of time.

[0105] FIG. 10 is SiO according to an embodiment of the present invention. x This is a diagram showing the negative voltage load reliability results of a p-type thin-film transistor using a CuI:Cd thin film with an introduced encapsulation material.

[0106] Referring to Fig. 10, a small voltage shift of 1.9 V was observed during a voltage load of 3600 seconds in the negative voltage load reliability measurement. These results are consistent with the SiO2 explained earlier. x It can be interpreted that this appears because it is formed on the surface of the CuI:Cd thin film and passivates the CuI:Cd thin film.

[0108] FIG. 11 shows an optical microscope image of an actual 7-stage ring oscillator fabricated according to one embodiment of the present invention.

[0109] Referring to Fig. 11, it can be seen that a 7-stage ring oscillator composed of 14 p-type thin-film transistors using CuI:Cd thin films was formed through a lithography process. This result indicates that CuI:Cd thin films can be patterned through a lithography process, which means that direct integration through a miniaturization process is possible.

[0111] FIG. 12 is a diagram showing the reduction in propagation delay and the increase in oscillation frequency as the supply voltage of a 7-stage ring oscillator according to one embodiment of the present invention increases.

[0112] Referring to Figure 12, the fabricated ring oscillator showed a tendency for the oscillation frequency to increase with the supply voltage, and the Delay (μs) value to decrease.

[0114] FIG. 13 is a diagram showing a radio signal generated when the supply terminal voltage is -30 V in a 7-stage ring oscillator according to one embodiment of the present invention.

[0115] Referring to Fig. 13, it was shown that oscillation occurred at a frequency of 65.01 kHz when the supply voltage was -30 V.

[0117] With reference to FIGS. 8 to 13, the present invention relates to a CuI:Cd material having high air stability and SiO₂ therewith. x It was proven that by introducing an encapsulation material, CuI:Cd integration can be performed without changes in physical properties, and devices utilizing this can operate stably.

[0119] Although the present invention has been described in detail using preferred embodiments, the scope of the invention is not limited to specific embodiments and should be interpreted by the appended claims. Furthermore, those skilled in the art will understand that many modifications and variations are possible without departing from the scope of the invention.

Claims

Claim 1 CD 2+ A step of forming a copper iodide semiconductor thin film doped with cations; and SiO on the semiconductor thin film x (wherein, 1 < x < 2) the step of forming a thin film is included, wherein the step of forming the copper iodide semiconductor thin film comprises a copper iodide solution and the Cd 2+ The method comprises: a precursor solution preparation step of preparing a precursor solution by mixing a cadmium iodide solution containing cations; a spin coating step of spin-coating the precursor solution onto a substrate; and a heat treatment step of heat-treating at 80°C to 100°C after spin-coating, wherein the precursor solution preparation step prepares the precursor solution by mixing 10 μL to 110 μL of the cadmium iodide solution per 1 ml of the copper iodide solution, and the step of forming the SiOx thin film involves depositing the SiOx thin film on the semiconductor thin film at a deposition rate of 0.2 to 1.0 Å / s to 1.0 Å / s using an electron beam depositor, and the copper iodide semiconductor thin film is the Cd 2+ Method for manufacturing a p-type transistor doped with cations at a concentration of 4 to 5 mol%. Claim 2 In claim 1, the above SiO x A method for manufacturing a p-type transistor, wherein the thickness of the thin film is 45 to 55 nm. Claim 3 delete Claim 4 delete Claim 5 delete Claim 6 delete Claim 7 delete Claim 8 delete Claim 9 delete Claim 10 delete Claim 11 delete Claim 12 delete

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