Vertical field effect transistors and methods of fabrication thereof

Abstract

A vertical field-effect transistor is disclosed. The vertical field-effect transistor comprises: a substrate; a drain electrode disposed on the substrate; a source electrode disposed on the substrate intersecting the drain electrode; and a semiconductor thin film disposed between the drain electrode and the source electrode and coupled to the drain electrode and the source electrode by van der Waals interaction.

Description

Technology Field

[0001] The present invention relates to a vertical field effect transistor and a method for manufacturing the same, and more specifically, to a vertical field effect transistor capable of preventing leakage current with a short channel length and a method for manufacturing the same. Background Technology

[0002] Research and development for the miniaturization of transistors are actively underway due to various factors, including increased switching speed, reduced power consumption, improved integration density, cost reduction, and advancements in lithography technology as well as new semiconductor materials and process technologies.

[0003] Meanwhile, research on reducing transistor size by minimizing channel length has a long history alongside the advancement of semiconductor technology, and is continuously being conducted in accordance with technological developments and the introduction of new processes, such as Vertical Field Effect Transistors (VFETs), Fin Field-Effect Transistors (FinFETs), Gate-All-Around Field Effect Transistors (GAAFETs), nanosheet-type channels, and ultra-fine processes using EUV lithography.

[0004] A Vertical Field Effect Transistor (VFET) is a semiconductor device that improves performance by arranging the transistor structure in a vertical direction. Unlike traditional planar transistors, it features a vertically arranged structure, which enables high integration density and improved performance.

[0005] However, due to the shortened channel length between the source and drain electrodes, electrical control between the channel and electrodes can become difficult, which leads to increased leakage current and severe screening effects on the electrodes.

[0006] Therefore, research is required to resolve the aforementioned problems. The problem to be solved

[0007] The present invention provides a vertical field-effect transistor having a channel length of sub-nanometer length.

[0008] In addition, the present invention provides a vertical field-effect transistor capable of controlling leakage current with a short channel length.

[0009] In addition, the present invention provides a vertical field-effect transistor having high performance and stability. means of solving the problem

[0010] A vertical field-effect transistor according to the present invention may include a substrate; a drain electrode disposed on the substrate; a source electrode disposed on the substrate intersecting the drain electrode; and a semiconductor thin film disposed between the drain electrode and the source electrode and coupled to the drain electrode and the source electrode by van der Waals interaction.

[0011] In addition, the semiconductor thin film can make ohmic contact with each of the drain electrode and the source electrode.

[0012] Additionally, the semiconductor thin film may include a first region in contact with the drain electrode and the source electrode; a second region located on one side of the first region and in contact with the substrate; and a third region located on the other side of the first region and in contact with the substrate.

[0013] In addition, the semiconductor thin film may have a thickness of 0.6 to 0.7 nm.

[0014] In addition, the semiconductor thin film may have a thickness of 0.65 nm.

[0015] In addition, the semiconductor thin film may be provided as at least one of zinc oxide (ZnO), molybdenum disulfide (MoS2), tungsten diselenide (WSe2), tungsten disulfide (WS2), molybdenum diselenide (MoSe2), black phosphorus (BP), silicon (Si), and germanium (Ge).

[0016] In addition, the drain electrode and the source electrode may be provided as carbon nanotubes or metal nanowires.

[0017] In addition, an insulating film is formed on the upper surface of the substrate, and the insulating film may be provided as any one of silicon dioxide (SiO2), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), polycrystalline boron nitride, and metal oxide.

[0018] A method for manufacturing a vertical field-effect transistor according to the present invention comprises the steps of: forming a drain electrode on a substrate; forming a semiconductor thin film on the substrate on which the drain electrode is formed; and forming a source electrode on the substrate in a direction intersecting the drain electrode, wherein the semiconductor thin film can be coupled to the drain electrode and the source electrode by van der Waals interaction.

[0019] Additionally, the semiconductor thin film may include a first region in contact with the drain electrode and the source electrode; a second region located on one side of the first region and in contact with the substrate; and a third region located on the other side of the first region and in contact with the substrate.

[0020] In addition, the semiconductor thin film may have a thickness of 0.6 to 0.7 nm.

[0021] In addition, the semiconductor thin film may be selected from at least one of zinc oxide (ZnO), molybdenum disulfide (MoS2), tungsten diselenide (WSe2), tungsten disulfide (WS2), molybdenum diselenide (MoSe2), black phosphorus (BP), silicon (Si), and germanium (Ge).

[0022] In addition, the step of forming the semiconductor thin film can be performed by any one of the following methods: CVD method, MOCVD method, wet transfer method, dry transfer method, and ALD method.

[0023] In addition, the drain electrode and the source electrode may be provided as carbon nanotubes or metal nanowires.

[0024] In addition, an insulating film is formed on the upper surface of the substrate, and the insulating film may be provided as any one of silicon dioxide (SiO2), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), polycrystalline boron nitride, and metal oxide. Effects of the invention

[0025] According to the present invention, a semiconductor thin film of sub-nanometer length can be formed by a method for manufacturing a vertical field-effect transistor according to one embodiment.

[0026] In addition, according to the present invention, as the vertical field-effect transistor is provided in a vertical structure with a sub-nanometer channel length, the gate voltage is effectively controlled from the outside to the inside, and leakage current can be controlled as the current flow between the drain electrode and the source electrode is effectively controlled.

[0027] In addition, according to the present invention, the semiconductor thin film is coupled to the drain electrode and source electrode by van der Waals interaction, and as the metal gap state on the materials is eliminated, it can have high performance and stability. Brief explanation of the drawing

[0028] FIG. 1 is a drawing showing a vertical field-effect transistor according to an embodiment of the present invention. Figure 2 is a cross-sectional view of Figure 1 viewed from the X-axis direction. Figure 3 is a cross-sectional view showing the gate potential direction of the vertical electric field transistor of Figure 1. FIG. 4 is a flowchart illustrating a method for manufacturing a vertical field-effect transistor according to an embodiment of the present invention. FIG. 5 is a diagram showing the process of growing a semiconductor thin film of a two-dimensional transition metal dichalcogenide (TMD) material as a method for manufacturing a vertical electric field effect transistor according to an embodiment of the present invention. Figure 6 is an image of a cross-section of a vertical field-effect transistor formed with a molybdenum sulfide semiconductor thin film according to an embodiment of the present invention, observed with an electron microscope. Figure 7 is a graph showing the IV (current-voltage) transfer curve of the vertical field-effect transistor of Figure 5. Figure 8 is a graph showing the IV output curve of the vertical field-effect transistor of Figure 5. Specific details for implementing the invention

[0029] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed content is thorough and complete and to ensure that the concept of the present invention is sufficiently conveyed to those skilled in the art.

[0030] In this specification, when a component is described as being on another component, it means that it may be formed directly on the other component or that a third component may be interposed between them. Additionally, in the drawings, the thicknesses of the films and regions are exaggerated for the effective description of the technical content.

[0031] Additionally, although terms such as first, second, third, etc., have been used to describe various components in the various embodiments of this specification, these components should not be limited by such terms. These terms are used merely to distinguish one component from another. Accordingly, what is referred to as the first component in one embodiment may be referred to as the second component in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiment. Furthermore, in this specification, "and / or" is used to mean including at least one of the components listed before and after it.

[0032] In the specification, singular expressions include plural expressions unless the context clearly indicates otherwise. Furthermore, terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, components, or combinations thereof described in the specification, and should not be understood as excluding the existence or addition of one or more other features, numbers, steps, components, or combinations thereof. Additionally, in this specification, "connection" is used to include both indirectly connecting multiple components and directly connecting them.

[0033] Furthermore, in describing the present invention below, if it is determined that a detailed description of related known functions or configurations could unnecessarily obscure the essence of the invention, such detailed description will be omitted.

[0035] FIG. 1 is a drawing showing a vertical field effect transistor (10) according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of FIG. 1 viewed from the X-axis direction, and FIG. 3 is a cross-sectional view showing the gate potential direction of the vertical field effect transistor of FIG. 1.

[0036] Referring to FIGS. 1 to 3, a vertical field effect transistor (10) according to an embodiment of the present invention has a stacked structure comprising a drain electrode (130), a semiconductor thin film (140), and a source electrode (150), so that the gate field potential can be effectively modulated from the outside in the heterogeneous structure, and the vertical current flow between the source electrode (150) and the drain electrode (130) can be effectively modulated through the semiconductor thin film (140). In addition, the vertical field effect transistor (10) according to an embodiment of the present invention has the gate field potential effectively controlled so that on / off switching can be precisely controlled.

[0037] A vertical field effect transistor (10) according to an embodiment of the present invention includes a substrate (110), a drain electrode (130), a source electrode (150), and a semiconductor thin film (140).

[0038] The substrate (110) is made of a conductive material and is provided as a gate electrode. According to an embodiment, the substrate (110) may be a silicon (Si) substrate.

[0039] A cut-out film (120) is formed on the upper surface of the substrate (110). The insulating film (120) can be formed from any one of polygonal boron nitride and metal oxides such as silicon dioxide (SiO2), hafnium dioxide (HfO2), zirconium dioxide (ZrO2).

[0040] A drain electrode (130) is laminated on a substrate (110) on which an insulating film (120) is formed. The drain electrode (130) is formed in one direction on the substrate (110). The drain electrode (130) can be made of carbon nanotubes (CNT) or metal nanowires.

[0041] A source electrode (150) is laminated on a substrate (110) on which a drain electrode (130) and an insulating film (120) are formed. The source electrode (150) is formed in a direction intersecting the drain electrode (130). The source electrode (150) has a central region positioned intersecting the drain electrode (130), and the remaining region is laminated on the substrate (110) on which the insulating film (120) is formed. The source electrode (150) can be made of carbon nanotubes (CNT) or metal nanowires.

[0042] A semiconductor thin film (140) is stacked between a drain electrode (130) and a source electrode (150). After the semiconductor thin film (140) is stacked over a predetermined area on a substrate (110) on which the drain electrode (130) and an insulating film (120) are formed, the source electrode (150) is stacked.

[0043] The semiconductor thin film (140) includes a first region (141), a second region (142), and a third region (143).

[0044] The first region (141) is a central region of the semiconductor thin film (140) and is in contact with the drain electrode (130) and the source electrode (150) between the drain electrode (130) and the source electrode (150).

[0045] The first region (141) is coupled at its lower end to the drain electrode (130) and at its upper end to the source electrode (150) by van der Waals interaction.

[0046] The second region (142) extends in one direction from the first region (141) and is located on one side of the drain electrode (130). The second region (142) is laminated to one region of the substrate (110) on which the insulating film (120) is formed.

[0047] The third region (143) extends in the other direction from the first region (141) and is located on the other side of the drain electrode (130). The third region (143) is laminated on the other region of the substrate (110) on which the insulating film (120) is formed.

[0048] The semiconductor thin film (140) has a first region (141) disposed on the drain electrode (130), and a second region (142) and a third region (143) in contact with the substrate (110) on which the insulating film (120) is formed, so that the center protrudes.

[0049] The semiconductor thin film (140) is provided with a thickness of sub-nanometers. According to an embodiment, the semiconductor thin film (140) may have a thickness of 0.6 to 0.7 nm. Preferably, the semiconductor thin film (140) is provided with a thickness of 0.65 nm.

[0050] The semiconductor thin film (140) can be made of a semiconductor thin film material, a two-dimensional material, or an oxide semiconductor having a tunable Fermi energy level.

[0051] According to an embodiment, the semiconductor thin film (140) can be made of at least one material among zinc oxide (ZnO), molybdenum disulfide (MoS2), tungsten diselenide (WSe2), tungsten disulfide (WS2), molybdenum diselenide (MoSe2), black phosphorus (BP), silicon (Si), and germanium (Ge).

[0052] The vertical field-effect transistor (10) described above has a drain electrode (130) and a source electrode (150) arranged alternately on a substrate (110), and a semiconductor thin film (140) arranged between the drain electrode (130) and the source electrode (150). The semiconductor thin film (140) is coupled to the drain electrode (130) and the source electrode (150) by van der Waals interaction. As the semiconductor thin film (140) is coupled to the drain electrode (130) and the source electrode (150) by van der Waals interaction, the vertical field-effect transistor (10) can modulate the vertical current flow between the source electrode (150) and the drain electrode (130) through electric field control.

[0054] FIG. 4 is a flowchart showing a method for manufacturing a vertical field-effect transistor (10) according to an embodiment of the present invention.

[0055] Referring to FIG. 4, a method for manufacturing a vertical field-effect transistor according to an embodiment of the present invention includes the steps of preparing a substrate, forming a drain electrode, forming a semiconductor thin film, and forming a source electrode.

[0056] The step (S10) of preparing the substrate forms an insulating film (120) on the upper surface of the silicon substrate (110). The insulating film (120) formed on the upper surface of the substrate (110) can be formed from any one of polygonal boron nitride, metal oxide, such as silicon dioxide (SiO2), hafnium dioxide (HfO2), zirconium dioxide (ZrO2).

[0057] The drain electrode formation step (S20) forms a drain electrode (130) on a substrate (110) on which an insulating film (120) is formed. The drain electrode formation step (S10) forms the drain electrode (130) on the substrate (110) in one direction.

[0058] According to one embodiment, the drain electrode forming step (S20) may form the drain electrode (130) with carbon nanotubes. According to another embodiment, the drain electrode forming step (S20) may form the drain electrode (130) with metal nanowires.

[0059] According to one embodiment, the drain electrode formation step (S20) may form a drain electrode (130) by transferring the materials onto the substrate (110). The drain electrode formation step (S20) may form a drain electrode (130) on the substrate (110) through wet transfer or dry transfer.

[0060] According to another embodiment, the drain electrode forming step (S20) may form a drain electrode (130) by synthesizing the materials on the substrate (110). In the case where carbon nanotubes are synthesized directly on the substrate (110), a precursor solution of carbon nanotubes is applied to the edge of the substrate (110), and then hydrogen (H₂) is synthesized at a temperature of 1,000°C for 35 minutes. 2) A gas mixed with methane (CH4) is supplied. In this way, carbon nanotubes of a specific length can be grown on the substrate (110).

[0061] The semiconductor thin film formation step (S30) forms a semiconductor thin film (140) on the upper surface of a substrate (110) on which a drain electrode (130) and an insulating film (120) are formed. The semiconductor thin film formation step (S30) forms the semiconductor thin film (140) with a predetermined area on the substrate (110) on which the drain electrode (130) and the insulating film (120) are formed.

[0062] According to an embodiment, the semiconductor thin film (140) can be formed by selecting at least one material from zinc oxide (ZnO), molybdenum disulfide (MoS2), tungsten diselenide (WSe2), tungsten disulfide (WS2), molybdenum diselenide (MoSe2), black phosphorus (BP), silicon (Si), and germanium (Ge).

[0063] According to one embodiment, the semiconductor thin film formation step (S30) may form a semiconductor thin film (140) on a substrate (110) on which the drain electrode (130) and insulating film (120) are formed using a CVD method (CVD, Chemical Vapor Deposition).

[0064] According to another embodiment, the semiconductor thin film formation step (S30) may form a semiconductor thin film (140) on a substrate (110) on which the drain electrode (130) and insulating film (120) are formed using the MOCVD method (Metal-Organic Chemical Vapor Deposition).

[0065] According to another embodiment, the semiconductor thin film formation step (S30) may form a semiconductor thin film (140) on a substrate (110) on which the drain electrode (130) and insulating film (120) are formed using a transfer method. The transfer method may be a wet transfer method or a dry transfer method.

[0066] According to another embodiment, the semiconductor thin film formation step (S30) may form a semiconductor thin film (140) on a substrate (110) on which the drain electrode (130) and insulating film (120) are formed using an ALD (Atomic Layer Deposition) method.

[0067] The source electrode formation step (S40) forms a source electrode (150) on a substrate (110) on which a semiconductor thin film (140) and an insulating film (120) are formed. The source electrode formation step (S40) forms the source electrode (150) in a direction intersecting the drain electrode (130). In the source electrode formation step (S40), the source electrode (150) is positioned such that its central region intersects the drain electrode (130), and the remaining region is laminated on the substrate (110) on which the insulating film (120) is formed.

[0068] According to one embodiment, the source electrode forming step (S40) may form the source electrode (150) with carbon nanotubes. According to another embodiment, the source electrode forming step (S40) may form the source electrode (150) with metal nanowires.

[0069] According to one embodiment, the source electrode formation step (S40) may form a source electrode (150) by transferring the materials onto a substrate (110) on which the semiconductor thin film (140) and insulating film (120) are formed. The source electrode formation step (S40) may form a source electrode (150) on a substrate (110) on which the semiconductor thin film (140) and insulating film (120) are formed through wet transfer or dry transfer.

[0070] According to another embodiment, the source electrode formation step (S40) may form a source electrode (150) by synthesizing the materials on a substrate (110) on which a semiconductor thin film (140) and an insulating film (120) are formed. When carbon nanotubes are directly synthesized on a substrate (110) on which a semiconductor thin film (140) and an insulating film (120) are formed, a precursor solution of carbon nanotubes is applied to the edge of the substrate (110), and then hydrogen (H₂) is synthesized at a temperature of 1,000°C for 35 minutes. 2)A gas mixed with methane (CH4) is supplied. In this way, carbon nanotubes of a specific length can be grown on a substrate (110) on which a semiconductor thin film (140) and an insulating film (120) are formed.

[0072] By the method described above, a vertical field-effect transistor (10) can be manufactured in which a drain electrode (130), a semiconductor thin film (140), and a source electrode (150) are vertically stacked. The semiconductor thin film (140) is placed between the drain electrode (130) and the source electrode (150) and can be coupled to the drain electrode (130) and the source electrode (150) by van der Waals interactions. By coupling the semiconductor thin film (140) between the drain electrode (130) and the source electrode (150), the interface between the semiconductor thin film (140) and the two electrodes (130, 150) can be maintained and kept clean. In addition, the undamaged drain electrode (130), semiconductor thin film (140), and source electrode (150) formed through van der Waals interactions can effectively eliminate Metal-Induced Gap States (MIGS) and prevent Fermi level fixation. As a result, efficient gate modulation of the drain electrode (130), semiconductor thin film (140), and source electrode (150) is possible through an external electric field.

[0074] FIG. 5 is a diagram showing the process of growing a semiconductor thin film (140) of a two-dimensional transition metal dichalcogenide (TMDs) material as a method for manufacturing a vertical electric field effect transistor according to an embodiment of the present invention.

[0075] Referring to FIG. 5, a semiconductor thin film (140) of a single-layer two-dimensional transition metal dichalcogenide (TMD) material can be grown by a CVD method on a substrate (110) on which a drain electrode (130) and an insulating film (120) are formed by the manufacturing method of the vertical field-effect transistor of FIG. 4.

[0076] Specifically, an insulating film (120) is formed on the upper surface of a silicon substrate (110), whichever of a polygonal boron nitride such as silicon dioxide (SiO2), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), or a metal oxide is formed. A drain electrode (130) is formed on the substrate (110) on which the insulating film (120) is formed by transferring or synthesizing a material whichever of a carbon nanotube or a metal nanowire. In this process, the drain electrode (130) is formed in one direction of the substrate (110). A precursor solution mixed with vanadium (V) and tungsten (W) is spin-coated on the upper surface of the substrate (110) on which the drain electrode (130) and the insulating film (120) are formed. The substrate (110) coated with the precursor solution is heated to a temperature of 400°C to 600°C. According to an example, a substrate (110) coated with a precursor solution is heated to a temperature of 500°C. Afterward, the substrate (110) is placed in a chamber, and then a mixed gas of hydrogen (H2) and nitrogen (N2) and a sulfur compound are supplied into the chamber.

[0077] By the method described above, a vanadium-tungsten sulfide semiconductor thin film is formed on a substrate (110) on which a drain electrode (130) and an insulating film (120) are formed. The vanadium-tungsten sulfide semiconductor thin film consists of a single atomic layer and has a flake structure. The semiconductor thin film has a thin thickness of 0.65 nm.

[0078] In addition, two-dimensional transition metal dichalgogenide materials such as molybdenum sulfide (MoS2), tungsten selenide (WSe2), tungsten sulfide (WS2), and molybdenum selenide (MoSe2) can be formed into a semiconductor thin film (140) through a CVD or MOCVD process.

[0080] In addition to the method of forming a semiconductor thin film (140) through the CVD method described above, a semiconductor thin film (140) can be formed on a substrate (110) on which a drain electrode (130) and an insulating film (120) are formed by any one of the MOCVD method, wet transfer method, dry transfer method, and ALD method.

[0081] Hereinafter, a process for forming a semiconductor thin film (140) using an ALD method and a dry transfer method is described in the step of forming a semiconductor thin film (140) of a vertical electric field effect transistor (10) according to an embodiment of the present invention.

[0082] When depositing a zinc oxide (ZnO) semiconductor thin film (140) using the ALD method, a carbon nanotube is transferred in one direction with a thickness of 250 nm to 350 nm as a drain electrode (130) on a substrate (110) on which an insulating film (120) is formed according to the manufacturing method of the vertical field effect transistor (10) described above. According to an embodiment, the carbon nanotube can be transferred with a thickness of 300 nm. Then, a zinc oxide film of less than 1 nm is deposited on the substrate (110) on which the drain electrode (130) is formed using diethyl zinc (DEZn) (Sigma-Aldrich) and H2O at 100°C using the ALD method to form a zinc oxide semiconductor thin film (140).

[0083] Afterward, carbon nanotubes are transferred onto the zinc oxide semiconductor thin film (140) using a source electrode (150). At this time, the source electrode (150) is transferred so as to intersect in a direction perpendicular to the drain electrode (130). The zinc oxide semiconductor thin film (140) can be deposited at a rate of 1 period / Å.

[0085] When growing a black phosphorus (BP) semiconductor thin film (140) using a dry transfer method, first, as a preparation process for transferring black phosphorus into a semiconductor thin film (140), a process of peeling off the black phosphorus in bulk form grown by CVT into a single crystal may be performed. Black phosphorus consists of atomic layers arranged in a honeycomb structure, and each layer is fixed together by van der Waals forces, so the layers can be easily peeled off into a thin sheet.

[0086] According to the manufacturing method of the vertical field-effect transistor (10), a carbon nanotube is transferred in one direction with a thickness of 300 nm as a drain electrode (130) on a substrate (110) on which an insulating film (120) is formed. Then, on the substrate (110) on which the drain electrode (130) is formed, black phosphorus flakes of less than 1 nm prepared through the black phosphorus peeling process are peeled onto a polydimethylsiloxane film and transferred to the drain electrode (130) using a dry transfer technique to form a black phosphorus semiconductor thin film (140). Subsequently, a carbon nanotube is transferred as a source electrode (150) on the black phosphorus semiconductor thin film (140). At this time, the source electrode (150) is transferred so as to intersect in a direction perpendicular to the drain electrode (130).

[0088] FIG. 6 is an image of a cross-section of a vertical field-effect transistor (10) in which a molybdenum sulfide semiconductor thin film (140) is formed according to an embodiment of the present invention, observed with an electron microscope.

[0089] Referring to FIG. 6, the semiconductor thin film (140) made of molybdenum sulfide has a thickness of 0.65 nm. A van der Waals gap (vdW Gap) is formed between the molybdenum sulfide semiconductor thin film (140) and the drain electrode (130).

[0090] According to the manufacturing method of a vertical field-effect transistor (10) according to an embodiment of the present invention, an insulating film (120) of any one of polygonal boron nitride, metal oxide, silicon dioxide (SiO2), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), etc., was formed on the upper surface of a silicon substrate (110). A carbon nanotube with a thickness of 300 nm was transferred in one direction as a drain electrode (130) on the substrate (110) on which the insulating film (120) was formed. Then, a single layer of molybdenum sulfide (MoS2) with a thickness of 0.65 nm was transferred on the substrate (110) on which the drain electrode (130) and the insulating film (120) were formed using a wet transfer technique to form a single layer of molybdenum sulfide semiconductor film (140). Subsequently, carbon nanotubes were transferred as source electrodes (150) onto a substrate (110) on which a single layer molybdenum sulfide semiconductor thin film (140) and an insulating film (120) were formed. The source electrodes (150) were transferred so as to intersect in a direction perpendicular to the drain electrodes (130).

[0091] The vertical field-effect transistor (10) manufactured according to the embodiment is shown to have a molybdenum sulfide semiconductor thin film (140) having a thickness of 0.65 nm and formed as a single atomic layer. Additionally, it is observed that a van der Waals gap is formed between the drain electrode (130) and the molybdenum sulfide semiconductor thin film (140). Through the van der Waals gap formed between the drain electrode (130) and the molybdenum sulfide semiconductor thin film (140), it can be confirmed that the drain electrode (130) and the molybdenum sulfide semiconductor thin film (140) are bonded while maintaining a layered structure in the vertical direction.

[0092] The vertical field-effect transistor (10) of the present invention has a structure in which a drain electrode (130), a semiconductor thin film (140), and a source electrode (150) are stacked in a vertical direction, and the semiconductor thin film (140) is provided with a length of 0.65 nm (sus nanometer), enabling high-density integration. In addition, through van der Waals interactions, the semiconductor thin film (140) is coupled with the drain electrode (130) and the source electrode (150), thereby maintaining an interface between the semiconductor thin film (140) and the electrodes and eliminating Metal-Induced Gap States (MIGS), which can prevent Fermi Energy Convergence. As a result, the vertical field-effect transistor (10) can effectively modulate the vertical current flow between the source electrode (150) and the drain electrode (130) through the semiconductor thin film (140).

[0094] Figure 7 is a graph showing the IV (current-voltage) transfer curve of the vertical field-effect transistor (10) of Figure 5.

[0095] Referring to Fig. 7, the vertical field-effect transistor of Fig. 5 shows that the drain current increases rapidly in the on state, and the difference between the on and off states is large.

[0096] A conductive pad is provided to measure the electrical characteristics of the vertical field-effect transistor (10). The conductive pad is provided at the respective ends of the drain electrode (130) and the source electrode (150). The electrode pad can be made by selecting at least one of gold (Au), aluminum (Al), silver (Ag), chromium (Cr), nickel (Ni), titanium (Ti), platinum (Pt), palladium (Pd), and copper (Cu).

[0097] The vertical field-effect transistor (10) is based on a semiconductor thin film (140) of 0.65 nm and is approximately 10 6 of It can operate with an on / off current ratio. Since the gate voltage effectively controls charge transfer and mitigates tunneling current from the source electrode to the drain electrode, the vertical field effect transistor (10) of the present invention can induce a low off current using a short channel length of 0.65 nm.

[0099] Figure 8 is a graph showing the IV output curve of the vertical field-effect transistor (10) of Figure 5.

[0100] Referring to FIG. 8, the IV output curve of the vertical field-effect transistor (10) of FIG. 5 shows that the voltage and current increased linearly with a constant slope. Through this, it can be seen that an ohmic contact is formed between the semiconductor thin film (140), the source electrode (150), and the drain electrode (130). In the vertical field-effect transistor (10), the ohmic contact between the semiconductor thin film (140), the source electrode (150), and the drain electrode (130) lowers the resistance between the drain electrode (130) and the source electrode (150), and the resistance generated when current flows from the source electrode (150) to the drain electrode (130) can be minimized. Through this, the vertical field-effect transistor (10) can efficiently transmit current.

[0102] As described above, the vertical field-effect transistor (10) of the present invention has a short channel length formed by a semiconductor thin film (140) having a vertical structure with a sub-nanometer length. As the channel length is provided in a vertical structure with a sub-nanometer length, the gate field potential can be effectively controlled from the outside to the inside of the heterojunction, which eliminates the screening effect caused by the electrode and allows for efficient control of the current flow between the drain electrode (130) and the source electrode (150). In addition, high performance and safety can be achieved by eliminating the metal-induced gap state between the semiconductor thin film (140), the drain electrode (130), and the source electrode (150) interface through van der Waals interaction, whereby the semiconductor thin film (140) is coupled to the drain electrode (130) and the sub-electrode.

[0104] Although the present invention has been described in detail using preferred embodiments, the scope of the invention is not limited to specific embodiments and should be interpreted by the appended claims. Furthermore, those skilled in the art will understand that many modifications and variations are possible without departing from the scope of the invention. Explanation of the symbols

[0105] 10: Vertical Field Effect Transistor 110: Substrate 120: Insulating film 130: Drain electrode 140: Semiconductor thin film 141: First Zone 142: Second Zone 143: The Third Area 150: Source electrode S10: Step of preparing the substrate S20: Drain electrode formation step S30: Semiconductor thin film formation step S40: Source electrode formation step

Claims

Claim 1 A vertical field-effect transistor comprising: a substrate having an insulating film formed thereon; a drain electrode stacked on the insulating film; a source electrode having a central region intersecting the drain electrode and a remaining region stacked on the insulating film; and a semiconductor thin film having a central region disposed between the drain electrode and the source electrode and coupled to the drain electrode and the source electrode by van der Waals interaction, and an edge region in contact with the insulating film, wherein the thickness of the semiconductor thin film is 0.6 to 0.7 nm, and the semiconductor thin film comprises: a first region in which the lower part is coupled to the drain electrode and the upper part is coupled to the source electrode by van der Waals interaction; a second region extending in one direction from the first region and stacked on a region where the insulating film is formed on one side of the drain electrode; and a third region extending in the other direction from the first region and stacked on a region where the insulating film is formed on the other side of the drain electrode. Claim 2 delete Claim 3 delete Claim 4 delete Claim 5 In claim 1, the semiconductor thin film is a vertical field-effect transistor having a thickness of 0.65 nm. Claim 6 A vertical field-effect transistor according to claim 1, wherein the semiconductor thin film is provided as at least one of zinc oxide (ZnO), molybdenum disulfide (MoS2), tungsten diselenide (WSe2), tungsten disulfide (WS2), molybdenum diselenide (MoSe2), black phosphorus (BP), silicon (Si), and germanium (Ge). Claim 7 In claim 1, the drain electrode and the source electrode are provided as carbon nanotubes or metal nanowires in a vertical field-effect transistor. Claim 8 A vertical field-effect transistor according to claim 1, wherein the insulating film is provided as any one of silicon dioxide (SiO2), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), polygonal boron nitride, and metal oxide. Claim 9 The steps include: stacking a drain electrode on an insulating film formed on a substrate; forming a semiconductor thin film on the insulating film on which the drain electrode is stacked; and forming a source electrode on the insulating film in a direction intersecting the drain electrode, wherein the source electrode has a central region intersecting the drain electrode and a remaining region stacked on the insulating film, and the semiconductor thin film comprises: a first region in which the lower part is coupled to the drain electrode and the upper part is coupled to the source electrode by van der Waals interaction; and a second region extending in one direction from the first region and stacked on a region on one side of the drain electrode where the insulating film is formed. A method for manufacturing a vertical field-effect transistor, comprising a third region extending in a different direction from the first region and stacked on a different region where the insulating film is formed on the other side of the drain electrode, wherein the semiconductor thin film has a central region disposed between the drain electrode and the source electrode and coupled with the drain electrode and the source electrode by van der Waals interaction, an edge region in contact with the insulating film, and a thickness of 0.6 to 0.7 nm. Claim 10 delete Claim 11 delete Claim 12 A method for manufacturing a vertical field-effect transistor according to claim 9, wherein the semiconductor thin film is selected from at least one of zinc oxide (ZnO), molybdenum disulfide (MoS2), tungsten diselenide (WSe2), tungsten disulfide (WS2), molybdenum diselenide (MoSe2), black phosphorus (BP), silicon (Si), and germanium (Ge). Claim 13 In claim 9, the step of forming the semiconductor thin film is a method for manufacturing a vertical field-effect transistor in which the semiconductor thin film is formed by any one of the CVD method, MOCVD method, wet transfer method, dry transfer method, and ALD method. Claim 14 A method for manufacturing a vertical field-effect transistor according to claim 9, wherein the drain electrode and the source electrode are provided as carbon nanotubes or metal nanowires. Claim 15 A method for manufacturing a vertical field-effect transistor according to claim 9, wherein an insulating film is formed on the upper surface of the substrate, and the insulating film is provided as any one of silicon dioxide (SiO2), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), polygonal boron nitride, and metal oxide.

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