Semiconductor devices and methods of manufacturing semiconductor devices

Abstract

In one example, the semiconductor device comprises a first steering diode and a second steering diode on the upper side of a region of semiconductor material, a first Zener diode embedded within a region of semiconductor material, and a second Zener diode on the lower side of a region of semiconductor material. The semiconductor device is configured as a bidirectional electrostatic discharge (ESD) structure. The first Zener diode and the first steering diode are configured to respond to a positive ESD pulse, and the second Zener diode and the second steering diode are configured to respond to a negative ESD pulse. The steering diode is configured to have low capacitance, and the Zener diode is configured to provide enhanced ESD protection. Other related examples and methods are disclosed herein.

Description

Technology Field

[0001] Cross-reference of related applications

[0002] Not applicable.

[0003] Technology field

[0004] The present invention generally relates to electronic devices, and more specifically to a semiconductor device structure and a method for forming a semiconductor device. Background Technology

[0005] Previous semiconductor devices and methods for forming semiconductor devices are inadequate and result, for example, in excessive cost, improper integration, reduced reliability, relatively low performance, or excessively large dimensions.

[0006] For example, previous low-capacitance electrostatic discharge (ESD) protection devices, in which current flows vertically through the first die, were composed of unidirectional devices. To make the ESD protection device bidirectional, a second die was added in series to the first die, requiring two inputs / outputs (I / O). In other configurations, two I / Os were used as a single unit in series using two bond wires. Having two separate dies or two I / Os reduces the effectiveness of ESD protection, uses more semiconductor die area, and increases assembly costs. Furthermore, previous approaches to single-die bidirectional ESD protection devices were unsatisfactory, including poor ESD survival and high capacitance.

[0007] Therefore, there is a need for a structure and method for a bidirectional ESD device that improves performance and reduces package size and manufacturing costs without increasing capacitance.

[0008] Additional limitations and disadvantages of the conventional and traditional approach will become apparent to those skilled in the art through comparison with the present disclosure and reference to the drawings. Brief explanation of the drawing

[0009] Figure 1 schematically illustrates a part of the circuit representation of a semiconductor device configured as an electrostatic discharge (ESD) device according to the present description. FIG. 2a illustrates a cross-sectional view of a semiconductor device according to the present description. FIGS. 2B and 2C illustrate partial cross-sectional views of the semiconductor device of FIG. 2A in a manufacturing step including an alternative embodiment according to the present description. Figure 3 illustrates a cross-sectional view of a semiconductor device according to the present description. Figure 4 illustrates a cross-sectional view of a semiconductor device according to the present description. Figure 5 illustrates a cross-sectional view of a semiconductor device according to the present description. Figure 6 illustrates a cross-sectional view of a semiconductor device according to the present description. The following discussion provides various examples of semiconductor devices and methods for manufacturing semiconductor devices. These examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "examples" and "for example" are non-limiting. For the sake of brevity and clarity of the examples, elements within the drawings are not necessarily drawn to scale, and identical reference numerals in different drawings represent identical elements. Additionally, for the sake of brevity, descriptions and details of well-known steps and elements are omitted. For the sake of clarity in the drawings, specific regions of the device structure, such as doping regions or dielectric regions, may generally be depicted as having straight edges and precise angled corners. However, those skilled in the art understand that due to the diffusion and activation of the dopant or the formation of layers, the edges of these regions may generally not be straight, and the corners may not be precise angles. Although the semiconductor device has been described herein with specific N-type conductive regions and specific P-type conductive regions, those skilled in the art understand that the conductive type can be reversed and is also possible according to this description by considering any necessary polarity reversal of voltage, reversal of transistor type and / or current direction, etc. Furthermore, the terms used herein are intended to describe specific examples only and are not intended to limit the disclosure. As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise. As used herein, "current-carrying electrode" refers to an element of a device that carries current through the device, such as the source or drain of a MOS transistor, the emitter or collector of an anode transistor, or the cathode or anode of a diode, and "control electrode" refers to an element of a device that controls current through the device, such as the gate of a MOS transistor or the base of an anode transistor. When used with semiconductor regions, wafers, or substrates, the term "principal surface" refers to the surface of a semiconductor region, wafer, or substrate that forms an interface with other materials, such as dielectrics, insulators, conductors, or polycrystalline semiconductors. The principal surface may have a topography that varies in the x, y, and z directions. The terms “constitute,” “constituting,” “include,” and / or “include,” when used in this description, are open terms that specify the presence of the stated features, numbers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or groups thereof. The term "or" means any one or more of the items in the list combined by "or". For example, "x or y" means any element of the 3-element set {(x), (y), (x, y)}. As another example, "x, y, or z" means any element of the 7-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. Terms “first,” “second,” etc., may be used herein to describe various members, elements, regions, layers, and / or sections, but these members, elements, regions, layers, and / or sections should not be limited by these terms. These terms are used merely to distinguish one member, element, region, layer, and / or section from another. Accordingly, for example, the first member, first element, first region, first layer, and / or first section discussed below may be referred to as the second member, second element, second region, second layer, and / or second section without departing from the teachings of the present disclosure. With respect to circuit operation, the terms "during," "during," and "when" as used herein are not precise terms implying that an operation occurs immediately upon the initiation operation, and it will be recognized by those skilled in the art that there may be some small but reasonable delay, such as propagation delay, between the response initiated by the initial operation. Furthermore, the term "during" implies that a specific operation occurs at least within some part of the duration of the initiation operation. The use of the words "about," "approximately," or "considerably" implies that the value of an element is expected to be close to the mentioned value or location. However, as is well known in the art, there are always minor variations that prevent the value or location from being stated precisely. Unless otherwise specified, as used herein, the words “on” or “on” include an orientation, arrangement, or relationship in which a particular element may be in direct or indirect physical contact. Unless otherwise specified, as used herein, “overlapping” includes orientations, arrangements, or relationships in which certain elements may coincide or be aligned at least partially or wholly in the same or different planes. It is further understood that the examples exemplified and described below may be practiced without any elements that may and / or are not specifically disclosed herein. Specific details for implementing the invention

[0010] Generally, the present invention relates to a method for manufacturing a semiconductor device, such as an electrostatic discharge (ESD) device, and a semiconductor device structure utilizing a large-area Zener diode provided on the back side of a semiconductor substrate in series with a low-capacitance steering diode on the upper side of the semiconductor substrate. This combination is parallel to another low-capacitance steering diode in series with the large-area lower-surface Zener diode. The two structures provide a bidirectional ESD device within a single semiconductor die. By minimizing the area of ​​the steering diode, the capacitance of the ESD structure can be kept low, and by independently maximizing the areas of the two Zener diodes, ESD performance can be enhanced. Furthermore, the structure and method reduce manufacturing complexity and cost by reducing die area, reducing package size, and reducing I / O requirements. In some examples, the Zener diode can be formed on the back side of the semiconductor substrate using double-sided photolithography masking techniques, ion implantation, and localized annealing.

[0011] In one example, the semiconductor device includes a first terminal and a second terminal. The first PN diode has an anode and a cathode coupled to the first terminal. The first Zener diode is coupled in series with the first PN diode and has a cathode and an anode coupled to the cathode of the first PN diode. The second PN diode is coupled in parallel with the series combination of the first PN diode and the first Zener diode, and the second PN diode has a cathode and an anode coupled to the first terminal. The second Zener diode has a cathode and an anode coupled to the second terminal, and the anode of the second Zener diode is coupled to the anode of the second PN diode and is coupled to the anode of the first Zener diode. The semiconductor device is approximately 1.0 x 10⁻⁶ 19It includes a semiconductor substrate of a first conductive type having a first peak dopant concentration of atomic / cm³ or greater. The semiconductor device includes a first semiconductor region of a second conductive type opposite to the first conductive type and having approximately a first peak dopant concentration, wherein the first semiconductor region forms a first PN junction with the semiconductor substrate, and the first PN junction forms a junction of a first Zener diode. The semiconductor device includes a second semiconductor region of a second conductive type on the first semiconductor region, wherein the second semiconductor region has a second peak dopant concentration smaller than the first peak dopant concentration. The semiconductor device includes a first doping region of a first conductive type located within the second semiconductor region and on top of the first semiconductor region. The semiconductor device includes a third semiconductor region laterally adjacent to the first semiconductor region and having a first conductive type and a third peak dopant concentration. The semiconductor device includes a fourth semiconductor region of a first conductive type located on the third semiconductor region and having a fourth peak dopant concentration smaller than the third peak dopant concentration. The semiconductor device includes a second doping region of a second conductive type located within a fourth semiconductor region and positioned over a third semiconductor region. The semiconductor device includes a third doping region of a second conductive type located on the lower side of the semiconductor substrate and having an approximate first peak dopant concentration, thereby providing a second PN junction with the semiconductor substrate, wherein the second PN junction forms a junction of a second Zener diode.

[0012] In one example, the semiconductor device comprises a semiconductor substrate of a first conductive type having a first peak dopant concentration, an upper side, and a lower side opposite to the upper side. A first semiconductor region of a second conductive type opposite to the first conductive type is located in a first portion of the upper side, where the first semiconductor region has approximately a first peak dopant concentration and forms a first PN junction with the semiconductor substrate, and the first PN junction forms a junction of a first Zener diode. A second semiconductor region of the second conductive type lies over the first semiconductor region and has a second peak dopant concentration smaller than the first peak dopant concentration. A first doping region of the first conductive type is located within the second semiconductor region and lies over the first semiconductor region, where the first doping region forms a second PN junction with the second semiconductor region. A third semiconductor region in the second portion of the upper side is laterally adjacent to the first semiconductor region and has a first conductive type and a third peak dopant concentration. A fourth semiconductor region of the first conductive type is positioned over a third semiconductor region and has a fourth peak dopant concentration smaller than the third peak dopant concentration. A second doping region of the second conductive type is located in the fourth semiconductor region and is positioned over the third semiconductor region, where the second doping region forms a third PN junction with the fourth semiconductor region. A third doping region of the second conductive type is located on the lower side of the semiconductor substrate and has approximately the first peak dopant concentration, and the third doping region forms a fourth PN junction with the semiconductor substrate, where the fourth PN junction forms a junction of the second Zener diode. A first conductor is coupled to the first doping region and the second doping region on the upper side. A second conductor is coupled to the second Zener diode on the lower side of the semiconductor substrate.

[0013] In one example, a method for forming a semiconductor device comprises the step of providing a semiconductor substrate of a first conductive type having a first peak dopant concentration, an upper side, and a lower side opposite to the first side. The method comprises the step of providing a first semiconductor region of a second conductive type opposite to the first conductive type in a first portion of the upper side, wherein the first semiconductor region has approximately the first peak dopant concentration and forms a first PN junction with the semiconductor substrate, and the first PN junction forms a junction of a first Zener diode. The method comprises the step of providing a second semiconductor region of a first conductive type laterally adjacent to the first semiconductor region having a second peak dopant concentration in a second portion of the side. The method comprises the step of providing a third semiconductor region of a second conductive type placed over the first semiconductor region and a fourth semiconductor region of a first conductive type placed over the second semiconductor region, wherein the third semiconductor region has a third peak dopant concentration smaller than the first peak dopant concentration, and the fourth semiconductor region has a fourth peak dopant concentration smaller than the second peak dopant concentration. The above method provides a first doping region of a first conductive type positioned within a third semiconductor region and on top of a first semiconductor region, wherein the first doping region forms a second PN junction with the third semiconductor region. The above method provides a second doping region of a second conductive type positioned within a fourth semiconductor region and on top of a second semiconductor region, wherein the second doping region forms a third PN junction with the fourth semiconductor region. The above method includes the step of providing a first conductor coupled to the first doping region and the second doping region. The above method provides a third doping region of a second conductive type having an approximate first peak dopant concentration on the lower side of a semiconductor substrate and provides a fourth PN junction with the semiconductor substrate, wherein the fourth PN junction forms a junction of a second Zener diode.The above method includes the step of providing a second conductor coupled to a second Zener diode on the lower side of a semiconductor substrate.

[0014] Other examples are incorporated into the present disclosure. Such examples may be found in the drawings, claims, or description of the present disclosure.

[0015] FIG. 1 schematically illustrates a semiconductor device (10) as an embodiment of an electrostatic discharge (ESD) protection device (10) or an ESD device (10). According to the present description, the semiconductor device (10) is a bidirectional device having low capacitance and a fast response time. The semiconductor device (10) includes two terminals, a first terminal (11) and a second terminal (12). In some examples, terminal (11) is an input terminal, and terminal (12) is generally an output terminal connected to another element (not shown) that is protected by the semiconductor device (10). For example, terminal (11) may be connected to the high side of a regulated power supply (e.g., a 5-volt (V) supply). According to the present description, the semiconductor device (10) is configured to have low capacitance between terminals (11 and 12). The semiconductor device (10) is also formed to limit the maximum voltage formed between terminals (11 and 12) to the clamp voltage of the semiconductor device (10). The sharp breakdown voltage characteristic (or sharp knee) of the semiconductor device (10) helps to accurately control the value of the clamp voltage. Low capacitance helps to provide a fast response time to the semiconductor device (10).

[0016] According to the present description, the semiconductor device (10) comprises a first PN junction diode (13) configured as a first steering diode, a first Zener diode (14) connected in series with the first PN diode (13), and a second PN junction diode (17) configured as a second steering diode. The second PN junction diode (17) is coupled in parallel with the series combination of diodes (13 and 14). According to the present description, the device (10) further comprises a second Zener diode (18) coupled in series with diodes (13 and 14) and coupled in series with diode (17).

[0017] In exemplary normal operation, the semiconductor device (10) is biased to a voltage between approximately 1 volt (1V) and the Zener voltage of the diode (14) by applying a normal operating voltage, such as about 1 volt (1V) to terminal (11) and a ground reference voltage to terminal (12). Due to the characteristics of the semiconductor device (10) described below, the capacitance of the device (10) remains low as the voltage between terminals (11 and 12) varies over this normal operating voltage. However, the capacitance of the ESD device is typically specified as 0 volts applied across the entire device. This zero voltage condition is generally referred to as a zero bias condition. As will be further known below, under this zero bias condition, the low capacitance characteristics of the semiconductor device (10) described below form very low capacitance values ​​for the diodes (13 and 17). Since the capacitance of the capacitors connected in series is smaller than the capacitance of the smallest capacitor, the capacitance generated from the diodes (13 and 14) under these zero-bias conditions is smaller than the capacitance of either diode (13 or 14). The capacitance of the semiconductor device (10) is the equivalent capacitance of the diodes (13 and 14) plus the sum of the capacitance of the diode (17), and the equivalent capacitance of the sum of the equivalent capacitance of the diode (18). As further indicated below, since the capacitance of the diode (17) is also very small, the total capacitance of the semiconductor device (10) is very small under these zero-bias conditions.

[0018] When a positive ESD event is received on terminal (11), terminal (11) is forced to a large positive voltage with respect to terminal (12). Since the anode of diode (13) is connected to terminal (11) and the cathode is connected to the cathode of diode (14), the large positive voltage forward-biases diode (13) and reverse-biases diode (14). When the voltage between terminals (11 and 12) reaches the positive threshold voltage of the semiconductor device (10) (forward voltage of diode (13) + Zener voltage of diode (14) + forward voltage of diode (18)), a positive current (Ip) flows from terminal (11) to terminal (12) through diodes (13, 14, and 18). The diode (14) clamps the maximum voltage applied to terminal (12) to approximately the Zener voltage of the diode (14) (+ the forward voltage of the diode (13) and the forward voltage of the diode (18). The sharp knee of the diode (14) causes the diode (14) to quickly clamp the maximum voltage between terminals (11 and 12) to the Zener voltage of the diode (14). The Zener voltage of the diode (14) is generally about 2.5 to 80 volts (2.5V to 80V), and preferably about 5 volts (5V).

[0019] When a negative ESD event is received on terminal (11), terminal (11) is forced to a large negative voltage relative to terminal (12). Since the cathode of diode (17) is connected to terminal (11) and the anode is connected to the anode of diode (18), the large negative voltage forward-biases diode (17) and reverse-biases diode (18). When the voltage between terminals (11 and 12) reaches the negative threshold voltage of the device (10) (forward voltage of diode (17) + Zener voltage of diode (18)), a negative current (I N) flows from terminal (12) to terminal (11) through diodes (18 and 17). Diode (18) clamps the maximum voltage applied to terminal (11) to the approximate Zener voltage of diode (18) (+ forward voltage of diode (17). The sharp knee of diode (18) causes diode (18) to quickly clamp the maximum voltage between terminals (11 and 12) to the Zener voltage of diode (18). The Zener voltage of diode (18) is generally about 2.5 to 80 volts (2.5V to 80V), preferably about 5 volts (5V). In this way, the semiconductor device (10) is generally configured as a bidirectional ESD device. As described in this description and as will be described in more detail later, since diode (18) is larger than diode (14), the Zener voltages of diodes (14 and 18) do not need to be the same, but can be substantially similar. For example, the Zener voltages of the diodes (14 and 18) can be between several tens of volts and several volts of each other.

[0020] FIG. 2a illustrates an example cross-sectional view of a semiconductor device (10) according to the present description. The semiconductor device (10) is configured as a bidirectional ESD device. Diodes (13, 14, 17, 18) (generally referenced using arrows) are formed as part of a semiconductor substrate (21) and a semiconductor layer (27). In some examples, the semiconductor substrate (21) is a silicon substrate having a peak dopant concentration selected to provide a desired Zener voltage for a P-type conductive type and Zener diodes (14 and 18). In some examples, the peak dopant concentration of the semiconductor substrate is 1.0 x 10⁻⁶ 19 It is greater than atomic / cm³. In another example, the peak dopant concentration is 1.0 x 10⁻⁶ 19 atomic / cm³ to 1x10 21 It is an atom / cm³.

[0021] The semiconductor layer (27) may be on, placed on, or over the semiconductor substrate (21), and may be formed, for example, using an epitaxial growth technique. According to the present description, the semiconductor layer (27) is formed as an undoped or intrinsic semiconductor layer. That is, the semiconductor layer (27) is an undoped or intrinsic silicon semiconductor layer as formed. Alternatively, as described in more detail below, the semiconductor layer (27) is doped from a buried layer region provided on or over the semiconductor substrate (21) before the semiconductor layer (27) is formed. In some examples, the semiconductor substrate (21) and the semiconductor layer (27) may be referred to as a semiconductor workpiece or a semiconductor material region.

[0022] The semiconductor device (10) comprises a semiconductor region (24) and a semiconductor region (32), which are laterally adjacent to each other and are located between the semiconductor substrate (21) and the semiconductor layer (27). In this example, the semiconductor region (24) has an N-type conductive type and has a peak dopant concentration approximately equal to the peak dopant concentration of the semiconductor substrate (21). In some examples, the semiconductor region (24) has a generally small thickness ranging from about 1 micron to about 3 microns or more. Due to the small thickness and high dopant concentration of the semiconductor region (24), when the semiconductor device (10) receives a positive voltage from terminal (11) to terminal (12), the voltage causes the carrier concentration to be confined to a small, high-density area within the semiconductor region (24) and near the interface with the semiconductor substrate (21). This high carrier and dopant concentration forms a Zener diode (14) by providing Zener diode operating characteristics to the diode formed between the semiconductor substrate (21) and the semiconductor region (24). This combination also provides a Zener diode (14) having a very sharp breakdown voltage or knee, and allows for very precise control of the breakdown voltage or Zener voltage of the diode (14). The breakdown voltage or Zener voltage of the diode (14) can be adjusted by changing the carrier concentration of the semiconductor region (24) and / or the semiconductor substrate (21). The Zener breakdown voltage is much more controllable compared to devices using punch-through breakdown voltage.

[0023] In this example, the semiconductor region (32) is of the P-type conductive type and about 1.0 x 10 16 atomic / cm³ to about 1.0 x 10⁻³ 17 atoms / cm 3It has a range of peak dopant concentrations. In some examples, different concentrations may be used. In some examples, the peak dopant concentration of the semiconductor region (32) is smaller than the peak dopant concentration of the semiconductor region (24). In some examples, the dopant concentration of the semiconductor region (32) may be selected to adjust the cutoff voltage characteristics of the diode (17).

[0024] According to the present description, both the semiconductor region (24) and the semiconductor region (32) are formed on or within the semiconductor substrate (21) using masking and doping techniques known to those skilled in the art. In some examples, a first masking layer may be provided on the semiconductor substrate (21) to expose a first area for the semiconductor region (24). Then, for example, using ion implantation techniques, an N-type dopant may be provided for the semiconductor region (24). Then, a second masking layer may be provided on the semiconductor substrate (21) to expose a second area for the semiconductor region (32). Then, for example, using ion implantation techniques, a P-type dopant may be provided for the semiconductor region (32).

[0025] After a dopant is provided for both the semiconductor region (24) and the semiconductor region (32), a semiconductor layer (27) can be formed on the semiconductor region (24) and the semiconductor region (32) using an epitaxial growth technique. When the epitaxial growth technique is used to form the semiconductor layer (27), the dopants within the semiconductor region (24) and the semiconductor region (32) are externally diffused to provide a dopant source for increasing the dopant concentration of the semiconductor layer (27). That is, the semiconductor layer (27) is self-doped by the semiconductor regions (24 and 32). External diffusion of an N-type conductive dopant from the semiconductor region (24) provides an N-type conductive semiconductor region (211), and external diffusion of a P-type conductive dopant from the semiconductor region (32) provides a P-type conductive semiconductor region (212). More specifically, the semiconductor layer comprises a semiconductor region (211) and a semiconductor region (212), which are laterally adjacent to each other.

[0026] Next, isolation structures (29 and 31) are formed to isolate a portion of the semiconductor region (211) where the diode (13) is to be formed from a portion of the semiconductor region (212) where the diode (17) is to be formed. In some examples, the isolation structures (29 and 31) may be isolation trenches and may be referred to as isolation trenches (29 and 31). The isolation trenches (29 and 31) are generally formed by creating an opening from the upper side of the semiconductor layer (27) and extending through the semiconductor layer (27) and through the semiconductor regions (24 and 32) into the semiconductor substrate (21). The isolation trenches (29 and 31) may be formed using photolithography and etching techniques or other techniques known to those skilled in the art.

[0027] The configuration of the isolation trenches (29 and 31) reduces or prevents lateral conduction between the semiconductor regions (24, 32, 211 and 212) and the diodes (13, 14 and 17). The isolation trenches (29 and 31) may include a dielectric liner (30) that fills the remaining openings along the sidewalls and bottom of the trenches (29 and 31) with a dielectric or doped or undoped polysilicon. Alternatively, the dielectric liner (30) may be formed along the sidewalls rather than the bottom of the trenches (29 and 31). The isolation trench (29) preferably forms a closed polygon with a periphery having an opening that surrounds a portion of the semiconductor region (211). The isolation trench (31) preferably forms a closed polygon with a periphery having an opening that surrounds a portion of the semiconductor region (212). Each of the isolation trench (29) and isolation trench (31) can be considered as a multi-connected domain.

[0028] The semiconductor region (24) is positioned so that it extends between the outer edges of the isolation trench (29) but terminates before the outer edge of the trench (31). This configuration ensures that the semiconductor region (24) is used to form a continuous Zener diode (14) and that the semiconductor region (24) does not extend into the semiconductor region (212) or the semiconductor region (32) located below the diode (17). The semiconductor region (32) is positioned so that it extends between the outer edges of the isolation trench (31) but terminates before the outer edge of the isolation trench (29). This configuration ensures that the semiconductor region (32) does not extend into the semiconductor region (211) or the semiconductor region (24).

[0029] The semiconductor device (10) includes a doping region (33) formed on the upper side of the semiconductor layer (27) within the semiconductor region (211). The doping region (33) forms a PN junction with the semiconductor region (211) and forms a junction for the diode (13). The doping region (33) has a P-type conductive type and extends into the semiconductor region (211) and lies over the semiconductor region (24). The doping region (33) is located within the semiconductor region (211) such that an isolation trench (29) completely surrounds the doping region (33). In some examples, the isolation trench (29) is a single continuous trench isolation formed around the doping region (33). The peak dopant concentration of the doping region (33) is greater than the peak dopant concentration of the semiconductor region (211) and may be approximately equal to the peak dopant concentration of the semiconductor substrate (21). In some examples, the doping region (33) extends into the semiconductor region (211) by a distance of less than about 2 microns. In some examples, the distance is 0.1 microns to 2 microns from the upper side of the semiconductor layer (27). The large difference in dopant concentration between the doping region (33) and the semiconductor region (211), the small area, and the shallow depth of the doping region (33) help to provide a diode (13) having a very small capacitance. As previously mentioned, under zero bias conditions, the very small capacitance of the diode (13) helps to form a small zero capacitance for the semiconductor device (10).

[0030] The doping region (33) is separated from the semiconductor region (24) by a distance that helps minimize the capacitance of the diode (14). The distance is typically about 2 to 20 microns. The portion of the semiconductor region (211) between the doping region (33) and the semiconductor region (24) forms the drift portion of the diode (13). The thickness of the drift portion is typically at least about 2 microns to reduce the formation of parasitic transistor operation and to ensure that the semiconductor device (10) does not operate in the punch-through operating region.

[0031] The doping region (34) is formed within the semiconductor region (212) and has an N-type conductive type. The doping region (34) forms a PN junction with the semiconductor region (212) and provides a junction for the diode (17). The peak dopant concentration of the doping region (34) is greater than the peak dopant concentration of the semiconductor region (212) and is preferably approximately equal to the peak dopant concentration of the semiconductor substrate (21). In some examples, the doping region (34) is formed on the upper side of the semiconductor layer (27) within the semiconductor region (212) and extends into the semiconductor region (212) by a distance approximately equal to that of the doping region (33) extending into the semiconductor region (211). The doping region (34) is positioned over the semiconductor region (32) and is positioned so that the periphery of the doping region (34) on the upper side of the semiconductor layer (27) is completely surrounded by an isolation trench (31). In some examples, the isolation trench (31) is a single continuous trench. The low carrier concentration of the semiconductor region (212) and the shallow depth of the doping region (34) help to provide a diode (17) having a very small capacitance. As previously mentioned, the very small capacitance of the diode (17) under zero-bias conditions helps to form a small zero-bias capacitance for the semiconductor device (10).

[0032] The semiconductor device (10) further comprises a dielectric (36) on the upper side of the semiconductor layer (27). The dielectric (36) may be provided before the formation of the doping regions (33 and 34) and may comprise one or more dielectric layers, for example, including a field dielectric layer and a pre-ohm dielectric layer. In some examples, the dielectric (36) comprises an oxide, a nitride, a combination thereof, or other dielectrics known to those skilled in the art. The dielectric (36) may be provided using a thermal growth process or a chemical vapor deposition process. The dielectric (36) may be patterned, for example, using photolithography and etching processes to provide openings for the doping regions (33 and 34).

[0033] The semiconductor device (10) further comprises a conductor (38) on the dielectric (36) that contacts or is bonded to doped regions (33 and 34) through openings within the dielectric (36). In some examples, the conductor (38) comprises one or more metals or metal layers. In some examples, the conductor (38) may comprise an aluminum alloy, such as an aluminum (Al)-silicon (Si)-copper (Cu) alloy. In some examples, a solderable material or a sintered material is provided on the aluminum alloy. In other examples, the conductor (38) may comprise titanium (Ti), nickel (Ni), silver (Ag), or chromium (Cr), Ni, or gold (Au). The conductor (38) may be formed using evaporation, sputtering, or other deposition techniques. In some examples, the conductor (38) has a thickness of about 2 microns to 9 microns. The conductor (38) provides a terminal (11) for the semiconductor device (10) as illustrated in FIG. 1.

[0034] In a subsequent manufacturing step, a portion of the back surface of the semiconductor substrate (21) is removed to reduce the overall thickness of the semiconductor substrate (21). In some examples, a back surface grinding and etching process is used to remove a portion of the semiconductor substrate (21) from the back surface. In some examples, the thickness of the semiconductor substrate (21) and the semiconductor layer (27) after the removal process may be about 100 microns to about 200 microns. In other examples, the thickness may be less than 100 microns or greater than 200 microns.

[0035] FIGS. 2B and 2C illustrate a portion of the semiconductor substrate (21) after the semiconductor substrate (21) has its thickness reduced and after additional processing to form a doping region (22). In this example, the doping region (22) is an N-type conductive region that forms a PN junction with the semiconductor substrate (21) and provides a junction for the Zener diode (18). According to this description, a mask (59) is provided on the back surface (218) of the semiconductor substrate (21) and an opening (59A) is provided to form the doping region (22). In some examples, the mask (59) may be a photoresist layer or other deposited masking material. The mask (59) may be provided using a double-sided alignment photolithography tool that effectively aligns the opening (59A) of the mask (59) with a structure on the upper side of the semiconductor layer (27). In this way, the dopant used to form the doping region (22) is aligned with the semiconductor regions (24 and 32). In some examples, the thickness of the mask (59) is selected to block the dopant used to form the doping region (22).

[0036] In some examples, one or more low-energy ion implants (typically indicated by arrow (63)) are used to form an implanted region (22A) in the back surface (218) within the opening (59A), as typically illustrated in FIG. 2b. According to the present description, the ion implantation dose is selected such that the peak dopant concentration in the doping region (22) is approximately equal to the peak dopant concentration in the semiconductor substrate (21). In some examples, an N-type dopant is ion-implanted into the back surface (218) at an ion implantation energy of 100 keV or higher. In some embodiments, phosphorus or arsenic is about 1.0 x 10⁻⁶ 15 atomic / cm² to 1.0 x 10⁻⁶ 16Ion implantation is performed at a dose greater than atomic / cm². In some examples, different doses and / or implantation energies may be used in multiple ion implantation processes. After the dopant is implanted, the mask (59) may be removed, and a heat treatment may be used to activate the N-type dopant and diffuse it into the semiconductor substrate (21) to form a doping region (22). In some examples, a laser annealing process may be used to activate and diffuse the N-type dopant to form a doping region (22). In some examples, the doping region (22) extends a distance of about 0.2 microns to about 3 microns or more into the semiconductor substrate after the heat treatment. Due to the small thickness of the doping region (22) and the high dopant concentration, when the semiconductor device (10) receives a negative voltage from terminal (11) to terminal (12), the voltage causes the carrier concentration to be confined to a small, high-density area within the doping region (22) and near the interface with the semiconductor substrate (21). These high carrier and dopant concentrations form a Zener diode (18) by providing Zener diode operating characteristics to the diode formed between the semiconductor substrate (21) and the doping region (22). This combination also provides a Zener diode (18) having a very sharp breakdown voltage or knee, and allows for very precise control of the breakdown voltage or Zener voltage of the diode (18). The breakdown voltage or Zener voltage of the diode (18) can be adjusted by changing the carrier concentration of the doping region (22) and / or the semiconductor substrate (21). As previously described, the Zener breakdown voltage is much more controllable compared to devices using punch-through breakdown voltage.

[0037] According to the present description, the doping region (22) is a patterned region inserted inward from or laterally spaced from the edge of the semiconductor device (10), as illustrated in FIGS. 2a through 2c. That is, the doping region (22) does not extend completely laterally to the edge of the semiconductor substrate (21). In some examples, a mask (59) may be held in place on the back surface (218) of the semiconductor substrate (21) to provide additional isolation of the doping region (22). The doping region (22) is placed beneath both the semiconductor region (24) and the semiconductor region (32) and is separated from the semiconductor region (24) and the semiconductor region (32) by the semiconductor substrate (21). According to the present description, the doping region (22) has a width greater than the width of the semiconductor region (24), as illustrated in FIG. 2a.

[0038] The semiconductor device (10) further comprises a conductor (39) formed on a rear surface (218) adjacent to a doping region (22). In some examples, the conductor (39) may comprise Al-Ni-vanadium(V)-Au and may be formed by evaporation, sputtering, or other deposition techniques as known to those skilled in the art. In other examples, Ti-Ni-Ag, Al-Ni-Ag, or Cr-Ni-Au may be used. In some examples, the conductor (39) has a thickness in the range of about 1 micron to about 4 microns. The conductor (39) provides a terminal (12) for the semiconductor device (10), as illustrated in FIG. 1.

[0039] In some examples, the conductor (39) has a width smaller than the doping region (22), as shown in FIG. 2a. That is, the conductor (39) can be inserted along the edge of the doping region (22). In this way, the conductor (39) does not short-circuit the PN junction forming the Zener diode (18). This is further illustrated in the left portion of FIG. 2c. In other examples, the mask (59) may remain in place to isolate the PN junction forming the Zener diode (18), and the conductor (39) may be extended to overlap at least a portion of the mask (59), as shown in the right portion of FIG. 2c. In some examples, where the mask (59) is held over the back surface (218) of the semiconductor substrate (21), the mask (59) may be an organic polymer film, such as polyimide or other materials known to those skilled in the art. The conductor (39) may be formed using double-sided photolithography technology. In some examples, the conductor (39) is a patterned conductor on the back surface (218) of the semiconductor device (10).

[0040] According to the description, the diodes (13 and 17) may have low capacitance to provide overall low capacitance for the semiconductor device (10). The Zener diodes (14 and 18) may be larger area diodes to sustain positive and negative ESD events. More specifically, it is advantageous for the area of ​​the Zener diode (18) (which is the patterned back diode of the semiconductor device (10)) to be close to the area of ​​the semiconductor device (10) to provide enhanced ESD protection for a selected size of the semiconductor device (10). During a positive ESD pulse, the diode (13) regulates the positive pulse through the embedded Zener diode (14). The diode (17) blocks the positive pulse. The Zener diode (18) adds a forward voltage drop to the breakdown voltage of the Zener diode (14). During a negative ESD pulse, the diode (17) regulates the negative pulse through the Zener diode (18). The diode (13) blocks the negative pulse.

[0041] Among other things, the semiconductor device (10) provides a bidirectional ESD device within a single semiconductor die having a smaller die size compared to a previous device requiring two dies, which supports a smaller package. Additionally, the semiconductor device (10) reduces the number of required packaging interconnects, for example, from two interconnects to one interconnect. The semiconductor device (10) provides additional design freedom without significantly increasing capacitance and improves the negative aspects of ESD performance. Furthermore, the breakdown voltage of the negative aspects of the semiconductor device (10) can be adjusted based on the dopant concentration of the semiconductor substrate (21) and the doping region (22). This is an improvement over the previous ESD device.

[0042] FIG. 3 illustrates a cross-sectional view of a semiconductor device (30) configured as a bidirectional ESD device within a single semiconductor die according to the present description. The semiconductor device (30) is similar to the device (10), and only the differences between the devices are described. The semiconductor device (30) includes a semiconductor layer (210) interposed between a semiconductor layer (27) and a semiconductor substrate (21). In this example, semiconductor regions (24 and 32) are formed within the semiconductor layer (210). In some examples, the semiconductor layer (210) may have the same conductivity type as the semiconductor substrate (21) (in this example, P-type conductivity) and may have a peak dopant concentration different from the peak dopant concentration of the semiconductor substrate (21). In some examples, the peak dopant concentration of the semiconductor layer (210) is smaller than the peak dopant concentration of the semiconductor substrate (21). In some examples, the semiconductor layer (210) is formed using epitaxial growth technology and may have a selected thickness such that the semiconductor regions (24 and 32) do not extend into the semiconductor substrate (21) through the semiconductor layer (210). In this way, the semiconductor layer (210) can be used to adjust the breakdown voltage characteristics of the Zener diode (14).

[0043] FIG. 4 illustrates a cross-sectional view of a semiconductor device (40) configured as a bidirectional ESD device within a single semiconductor die according to the present description. The semiconductor device (40) is similar to the semiconductor device (10), and only the differences between the devices are described. In the semiconductor device (40), the doping region (22) includes multiple parts (e.g., parts (22A and 22B)) to form the doping region (22) on the back side of the semiconductor substrate (21). Part (22B) extends inward from the lower side of the semiconductor substrate (21) by a distance greater than the distance to which part (22A) extends inward. In some examples, part (22B) has a different peak dopant concentration than the peak dopant concentration of part (22A). In some examples, the peak dopant concentration of part (22B) is smaller than the peak dopant concentration of part (22A). The portion (22B) forms a PN junction with the semiconductor substrate (21) to provide a Zener diode (18). Multiple portions for the doping region (22) can be used to adjust the breakdown voltage characteristics of the Zener diode (18).

[0044] According to the description herein, FIG. 5 illustrates a cross-sectional view of a semiconductor device (50) configured as a bidirectional ESD device, and FIG. 6 illustrates a cross-sectional view of a semiconductor device (60) configured as a bidirectional ESD device within a single semiconductor die. The semiconductor device (50) and the semiconductor device (60) are similar to the semiconductor device (10), and only the differences between the devices will be described. The semiconductor device (50) includes an annular ring configuration in which a semiconductor region (24) and a doping region (33) are provided as a ring shape or structure surrounding a semiconductor region (32) and a doping region (34). That is, the semiconductor region (32) and the doping region (34) are provided in the central part of the semiconductor layer (27), and the semiconductor region (24) and the doping region (33) are provided as a ring surrounding the semiconductor region (32) and the doping region (34). In some examples, the semiconductor region (32) and the doping region (34) may have a circular shape. In this way, the semiconductor device (50) is configured to distribute the current more uniformly during an ESD event.

[0045] The semiconductor device (60) includes an annular ring configuration in which the semiconductor region (32) and the doping region (34) are provided as a ring shape or structure surrounding the semiconductor region (24) and the doping region (33). That is, the semiconductor region (24) and the doping region (33) are provided in the central part of the semiconductor layer (27), and the semiconductor region (32) and the doping region (34) are provided as a ring surrounding the semiconductor region (24) and the doping region (33). In some examples, the semiconductor region (24) and the doping region (33) may have a circular shape. In this way, the semiconductor device (60) is configured to distribute current more uniformly during an ESD event. In some examples of the semiconductor devices (50 and 60), the diode (18) may also have a circular shape. In other examples, the diode (18) has a rectangular shape with rounded corners to reduce electric field density and premature breakdown.

[0046] It is understood that different examples described herein may be combined with any of the other examples described herein to obtain different embodiments.

[0047] Additionally, it is understood that different semiconductor materials may be selected for the semiconductor substrate (21) and the semiconductor layer (27). In some examples, both the semiconductor substrate (21) and the semiconductor layer (27) may be silicon. However, this description relates to other materials including other heterojunction semiconductor materials such as SiGe, SiGeC, GaAs, InGaP, GaN, and AlN. Additionally, the semiconductor substrate and the semiconductor layer (27) (and the semiconductor layer (210)) may be the same or different materials.

[0048] From all of the foregoing, a person skilled in the art may determine, for example, that the semiconductor device may include an isolation structure that isolates a first semiconductor region, a second semiconductor region, and a first doping region from a third semiconductor region and a second doping region, wherein the first doping region is spaced apart from the first semiconductor region by a distance of at least 2 microns.

[0049] In another example, the isolation structure may include a first isolation trench extending into the semiconductor substrate through the first semiconductor region from the upper side of the second semiconductor region, and a second isolation trench extending into the semiconductor substrate through the third semiconductor region from the upper side of the fourth semiconductor region. In some examples, the first isolation trench surrounds the first doping region. In some examples, the second isolation trench surrounds the second doping region. In another example, the first semiconductor region has a first width, and the third doping region has a second width, and the second width is greater than the first width. In another example, the second terminal is coupled to the third doping region on the lower side of the semiconductor substrate, the third doping region has a first width, and the second terminal has a second width, and the second width is smaller than the first width. In yet another example, the first semiconductor region surrounds the second semiconductor region. In another example, the second semiconductor region surrounds the first semiconductor region.

[0050] From all of the foregoing, those skilled in the art would, for example, understand that the first peak dopant concentration is approximately 1.0 x 10 19 It can be determined that it is atomic / cm³ or more. In another example, the semiconductor device may include an isolation structure that isolates the first semiconductor region, the second semiconductor region, and the first doping region from the third semiconductor region and the second doping region.

[0051] While the subject matter of the present invention is described by specific preferred examples, the foregoing drawings and descriptions thereof illustrate only ordinary examples of the subject matter and are therefore not to be construed as limiting the scope thereof. It is evident that many alternatives and variations will be self-evident to those skilled in the art. For example, the type of conductivity in various regions may be reversed. Additionally, different edge termination structures may be included. Furthermore, other isolation techniques may be used to isolate diodes (13, 14, and 17) as well as diode (18). It is understood that the term semiconductor substrate may refer to individual semiconductor dies, multiple semiconductor dies, or semiconductor wafers.

[0052] As indicated by the claims below, the embodiments of the invention may be fewer than all the features of the single example disclosed above. Accordingly, the claims expressed below are explicitly incorporated into the detailed description of the drawings, together with each claim which is independent in itself as a separate example of the invention. Furthermore, while some examples described herein include some features but do not include other features included in other examples, a combination of features of different examples means that they are within the scope of the invention and form different examples as understood by those skilled in the art.

Claims

Claim 1 A semiconductor device comprises: a first terminal; a second terminal; a first PN diode having an anode and a cathode coupled to the first terminal; a first Zener diode in series combination with the first PN diode having a cathode and an anode coupled to the cathode of the first PN diode; a second PN diode coupled in parallel with the series combination of the first PN diode and the first Zener diode, having a cathode and an anode coupled to the first terminal; and a second Zener diode having a cathode and an anode coupled to the second terminal, wherein the anode of the second Zener diode is coupled to the anode of the second PN diode and coupled to the anode of the first Zener diode, and the semiconductor device comprises 1.0 x 10 19 A semiconductor substrate of a first conductive type having a first peak dopant concentration of atomic / cm³ or greater; a first semiconductor region of a second conductive type opposite to the first conductive type and having the first peak dopant concentration, wherein the first semiconductor region forms a first PN junction with the semiconductor substrate and the first PN junction forms a junction of the first Zener diode; a second semiconductor region of the second conductive type on the first semiconductor region, wherein the second semiconductor region has a second peak dopant concentration smaller than the first peak dopant concentration; a first doping region of the first conductive type positioned within the second semiconductor region and above the first semiconductor region; a third semiconductor region laterally adjacent to the first semiconductor region and having the first conductive type and a third peak dopant concentration; a fourth semiconductor region of the first conductive type on the third semiconductor region having a fourth peak dopant concentration smaller than the third peak dopant concentration; and a semiconductor located in the fourth semiconductor region and above the third semiconductor region A semiconductor device comprising: a second doping region of the second conductive type; and a third doping region of the second conductive type adjacent to the lower side of the semiconductor substrate and the second terminal, wherein the third doping region provides a second PN junction to the semiconductor substrate including a first peak dopant concentration, and the second PN junction forms a junction of the second Zener diode. Claim 2 In claim 1, the third doping region is a patterned region inserted from the edge of the semiconductor substrate; the first doping region and the second doping region have the first peak dopant concentration; the semiconductor substrate has the first conductive type semiconductor layer on the semiconductor substrate; the semiconductor layer has a peak dopant concentration smaller than the first peak dopant concentration; the first semiconductor region and the second semiconductor region are within the semiconductor layer; a part of the semiconductor layer is interposed between the first semiconductor region, the second semiconductor region, and the semiconductor substrate; the first semiconductor region forms the first PN junction with the semiconductor layer; the third doping region includes a first portion extending a first distance from the lower side of the semiconductor substrate and a second portion extending a second distance from the lower side of the semiconductor substrate; the first distance is greater than the second distance; the second portion has the first peak dopant concentration; the first portion has a peak dopant concentration smaller than the first peak dopant concentration; and A semiconductor device having a first part forming the semiconductor substrate and the second PN junction. Claim 3 As a semiconductor device, a semiconductor substrate of a first conductive type having a first peak dopant concentration, an upper side, and a lower side facing the upper side; a first semiconductor region of a second conductive type opposite to the first conductive type in a first portion of the upper side, wherein the first semiconductor region has the first peak dopant concentration, forms a first PN junction with the semiconductor substrate, and the first PN junction forms a junction of a first Zener diode; a second semiconductor region of a second conductive type lying on the first semiconductor region and having a second peak dopant concentration smaller than the first peak dopant concentration; a first doping region of the first conductive type lying within and on the first semiconductor region and forming a second PN junction with the second semiconductor region; a third semiconductor region in a second portion of the upper side laterally adjacent to the first semiconductor region and having the first conductive type and a third peak dopant concentration; a fourth peak lying on the third semiconductor region and having a third peak dopant concentration smaller than the third peak dopant concentration A semiconductor device comprising: a fourth semiconductor region of the first conductive type having a dopant concentration; a second doping region of the second conductive type positioned within the fourth semiconductor region and above the third semiconductor region, forming a third PN junction with the fourth semiconductor region; a third doping region of the second conductive type adjacent to the lower side and having the first peak dopant concentration, wherein the third doping region forms a fourth PN junction with the semiconductor substrate and the fourth PN junction forms a junction of a second Zener diode; a first conductor coupled to the first doping region and the second doping region on the upper side; and a second conductor adjacent to the third doping region and the lower side of the semiconductor substrate. Claim 4 A semiconductor device according to claim 3, wherein the first doping region has a first width; the second doping region has a second width; the first semiconductor region has a third width; the third doping region has a fourth width; the third width and the fourth width are greater than the first width and the second width; the fourth width is greater than the third width; the third doping region is a patterned region; and the third peak dopant concentration is smaller than the first peak dopant concentration. Claim 5 A method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate of a first conductive type having a first peak dopant concentration, an upper side, and a lower side opposite to the upper side; providing a first semiconductor region of a second conductive type opposite to the first conductive type in a first portion of the upper side, wherein the first semiconductor region has the first peak dopant concentration and forms a first PN junction with the semiconductor substrate, and the first PN junction forms a junction of a first Zener diode; providing a second semiconductor region of the first conductive type laterally adjacent to the first semiconductor region having a second peak dopant concentration in a second portion of the upper side; and providing a third semiconductor region of the second conductive type placed on the first semiconductor region and a fourth semiconductor region of the first conductive type placed on the second semiconductor region, wherein the third semiconductor region has a third peak dopant concentration smaller than the first peak dopant concentration, and the fourth semiconductor region has a fourth peak dopant smaller than the second peak dopant concentration A step of providing a fourth semiconductor region having a concentration; a step of providing a first doping region of the first conductive type that is positioned within the third semiconductor region and on the first semiconductor region and forms a second PN junction with the third semiconductor region; a step of providing a second doping region of the second conductive type that is positioned within the fourth semiconductor region and on the second semiconductor region and forms a third PN junction with the fourth semiconductor region; and a step of providing a first conductor coupled to the first doping region and the second doping region.A method for manufacturing a semiconductor device, comprising: providing a third doping region of the second conductive type adjacent to the lower side of the semiconductor substrate and having the first peak dopant concentration, so as to provide a fourth PN junction on the semiconductor substrate, wherein the fourth PN junction forms a junction of a second Zener diode; and providing a second conductor adjacent to the lower side of the semiconductor substrate and the third doping region. Claim 6 A method for manufacturing a semiconductor device according to claim 5, wherein the step of providing the third doping region comprises the step of forming a mask on the lower side of the semiconductor substrate, wherein the mask has an opening; and the step of ion implanting the second conductive type dopant into the lower side of the semiconductor substrate through the opening, and the step of ion implanting the dopant comprises the step of using more than one ion implantation dose.

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