Decoders for analog neural memory in deep learning artificial neural network

Abstract

A number of embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, high-voltage and low-voltage versions of the decoders are used.

Description

Technology Field

[0001] Claim of priority

[0002] This application claims priority to U.S. Provisional Application No. 62 / 642,884, filed March 14, 2018, with the title "Decoders for Analog Neuromorphic Memory in Artificial Neural Network," and U.S. Patent Application No. 15 / 991,890, filed May 29, 2018, with the title "Decoders For Analog Neural Memory In Deep Learning Artificial Neural Network."

[0003] Technology field

[0004] A number of embodiments of decoders for use with vector-by-matrix multiplication (VMM) arrays in artificial neural networks are disclosed. Background Technology

[0005] Artificial neural networks mimic biological neural networks (the central nervous system of animals, particularly the brain), and they can rely on multiple inputs and are used to estimate or approximate generally unknown functions. Artificial neural networks generally consist of layers of interconnected "neurons" that exchange messages with one another.

[0006] Figure 1 illustrates an artificial neural network, where circles represent layers of neurons or inputs. Connections (referred to as synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This enables the neural network to adapt to and learn from the inputs. Typically, a neural network includes multiple layers of inputs. Typically, there are one or more intermediate layers of neurons and an output layer of neurons that provides the output of the neural network. Neurons at each level make decisions individually or collectively based on data received from the synapses.

[0007] One of the major challenges in the development of artificial neural networks for high-performance information processing is the lack of suitable hardware technology. In fact, real neural networks rely on a very large number of synapses to enable high connectivity between neurons, that is, very high computational parallelism. In principle, such complexity can be achieved with digital supercomputers or clusters of specialized graphics processing units. However, in addition to high costs, these approaches also suffer from mediocre energy efficiency compared to biological networks, which consume much less energy, because they primarily perform low-precision analog calculations. Although CMOS analog circuits have been used in artificial neural networks, most CMOS-implemented synapses have become too bulky given a large number of neurons and synapses.

[0008] The applicant previously disclosed, in U.S. Patent Application No. 15 / 594,439 incorporated herein, an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses. The non-volatile memory arrays operate as analog neuromorphic memory. A neural network device comprises a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses comprise a plurality of memory cells, wherein each of the memory cells comprises a separated source region and a drain region formed within a semiconductor substrate and having a channel region extending between them, a floating gate disposed over a first portion of the channel region and isolated therefrom, and a non-floating gate disposed over a second portion of the channel region and isolated therefrom. Each of the plurality of memory cells is configured to store a weight value corresponding to the number of electrons on the floating gate. The plurality of memory cells are configured to generate a first plurality of outputs by multiplying the first plurality of inputs by the stored weight values.

[0009] Each non-volatile memory cell used in an analog neuromorphic memory system must be erased and programmed to hold a very specific and precise amount of charge at the floating gate. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, and 64.

[0010] Conventional decoding circuits used in conventional flash memory arrays (e.g., bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders) are not suitable for use with VMMs in analog neuromorphic memory systems. One reason for this is that in VMM systems, the verification part (which is the read operation) of the programming and verification operations operates on a single selected memory cell, whereas the read operation operates on all memory cells in the array.

[0011] Improved decoding circuits suitable for use with VMMs in analog neuromorphic memory systems are required.

[0012] A number of embodiments of decoders for use with a VMM array in an artificial neural network are disclosed. Brief explanation of the drawing

[0013] Figure 1 is a diagram illustrating an artificial neural network. Figure 2 is a side cross-sectional view of a conventional 2-gate non-volatile memory cell. Figure 3 is a side cross-sectional view of a conventional 4-gate non-volatile memory cell. Figure 4 is a side cross-sectional view of a conventional 3-gate non-volatile memory cell. FIG. 5 is a side cross-sectional view of another conventional 2-gate non-volatile memory cell. Figure 6 is a diagram illustrating different levels of an exemplary artificial neural network utilizing a non-volatile memory array. Figure 7 is a block diagram illustrating a vector multiplier matrix. Figure 8 is a block diagram illustrating a vector multiplier matrix of various levels. FIG. 9 illustrates an example of a vector multiplier matrix. Figure 10 illustrates another embodiment of a vector multiplier matrix. Figure 11 illustrates another embodiment of a vector multiplier matrix. Figure 12 illustrates another embodiment of a vector multiplier matrix. Figure 13 illustrates another embodiment of a vector multiplier matrix. FIG. 14 illustrates one embodiment of a bit line decoder for a vector multiplier matrix. FIG. 15 illustrates another embodiment of a bit line decoder for a vector multiplier matrix. FIG. 16 illustrates another embodiment of a bit line decoder for a vector multiplier matrix. FIG. 17 illustrates a system for operating a vector multiplier matrix. Figure 18 illustrates another system for operating a vector multiplier matrix. FIG. 19 illustrates another system for operating a vector multiplier matrix. FIG. 20 illustrates an embodiment of a word line driver for use with a vector multiplier matrix. FIG. 21 illustrates another embodiment of a word line driver for use with a vector multiplier matrix. FIG. 22 illustrates another embodiment of a word line driver for use with a vector multiplier matrix. FIG. 23 illustrates another embodiment of a word line driver for use with a vector multiplier matrix. FIG. 24 illustrates another embodiment of a word line driver for use with a vector multiplier matrix. FIG. 25 illustrates another embodiment of a word line driver for use with a vector multiplier matrix. FIG. 26 illustrates another embodiment of a word line driver for use with a vector multiplier matrix. Figure 27 illustrates a source line decoder circuit for use with a vector multiplier matrix. FIG. 28 illustrates a word line decoder circuit, a source line decoder circuit, and a high-voltage level shifter for use with a vector multiplier matrix. FIG. 29 illustrates an erase gate decoder circuit, a control gate decoder circuit, a source line decoder circuit, and a high voltage level shifter for use with a vector multiplier matrix. Figure 30 illustrates a word line decoder circuit for use with a vector multiplier matrix. Figure 31 illustrates a control gate decoder circuit for use with a vector multiplier matrix. Figure 32 illustrates another control gate decoder circuit for use with a vector multiplier matrix. Figure 33 illustrates another control gate decoder circuit for use with a vector multiplier matrix. FIG. 34 illustrates a current-to-voltage circuit for controlling word lines within a vector multiplier matrix. FIG. 35 illustrates another current-voltage circuit for controlling word lines within a vector multiplier matrix. FIG. 36 illustrates a current-voltage circuit for controlling control gate lines within a vector multiplier matrix. FIG. 37 illustrates another current-voltage circuit for controlling control gate lines within a vector multiplier matrix. FIG. 38 illustrates another current-voltage circuit for controlling control gate lines within a vector multiplier matrix. FIG. 39 illustrates another current-voltage circuit for controlling word lines within a vector multiplier matrix. FIG. 40 illustrates another current-voltage circuit for controlling word lines within a vector multiplier matrix. Figure 41 illustrates another current-voltage circuit for controlling word lines within a vector multiplier matrix. Figure 42 illustrates the operating voltages for the vector multiplier matrix of Figure 9. Figure 43 illustrates the operating voltages for the vector multiplier matrix of Figure 10. Figure 44 illustrates the operating voltages for the vector multiplier matrix of Figure 11. Figure 45 illustrates the operating voltages for the vector multiplier matrix of Figure 12. Specific details for implementing the invention

[0014] The artificial neural network of the present invention utilizes a combination of CMOS technology and non-volatile memory arrays.

[0015] non-volatile memory cells

[0016] Digital nonvolatile memories are well known. For example, U.S. Patent No. 5,029,130 ​​("130 patent") discloses an array of separated gate nonvolatile memory cells, which are incorporated herein by reference for all purposes. Such a memory cell is illustrated in FIG. 2. Each memory cell (210) comprises a source region (14) and a drain region (16) formed within a semiconductor substrate (12), with a channel region (18) between them. A floating gate (20) is formed over a portion of the source region (16) and over a first portion of the channel region (18) and is insulated from there (and controls its conductivity). A word line terminal (22) (typically coupled to a word line) has a first portion disposed over a second portion of the channel region (18) and is insulated from there (and controls its conductivity), and a second portion extending upward and over the floating gate (20). The floating gate (20) and word line terminal (22) are insulated from the substrate (12) by a gate oxide. A bit line (24) is coupled to a drain region (16).

[0017] The memory cell (210) is erased by applying a high positive voltage to the word line terminal (22) (where electrons are removed from the floating gate), which causes electrons on the floating gate (20) to tunnel from the floating gate (20) to the word line terminal (22) by passing through an intermediate insulator via Fowler-Nordheim tunneling.

[0018] The memory cell (210) is programmed by applying a positive voltage to the word line terminal (22) and a positive voltage to the source (16) (where electrons are placed on the floating gate). An electron current will flow from the source (16) toward the drain (14). The electrons will be accelerated and heated when they reach the gap between the word line terminal (22) and the floating gate (20). Some of the heated electrons will pass through the gate oxide (26) and be injected onto the floating gate (20) due to electrostatic attraction from the floating gate (20).

[0019] The memory cell (210) is read by placing positive read voltages on the drain (14) and the word line terminal (22) (which turns on the channel region below the word line terminal). When the floating gate (20) is positively charged (i.e., electrons are erased and positively coupled to the drain (16)), the portion of the channel region below the floating gate (20) is also turned on, and current will flow across the channel region (18), which is detected as erased or "1" state. When the floating gate (20) is negatively charged (i.e. programmed with electrons), the portion of the channel region below the floating gate (20) is mostly or completely turned off, and current will not flow across the channel region (18) (or there will be almost no flow), which is detected as programmed or "0" state.

[0020] Table 1 illustrates typical voltage ranges that can be applied to the terminals of a memory cell (210) to perform read, erase, and programming operations:

[0021] [Table 1]

[0022]

[0023] Other separate gate memory cell configurations are known. For example, FIG. 3 illustrates a 4-gate memory cell (310) comprising a source region (14), a drain region (16), a floating gate (20) over a first portion of a channel region (18), a select gate (28) (typically coupled to a word line) over a second portion of the channel region (18), a control gate (22) over the floating gate (20), and an erase gate (30) over the source region (14). Such a configuration is described in U.S. Patent No. 6,747,310, incorporated herein by reference for all purposes. Here, all gates are non-floating gates except for the floating gate (20), which means that they are electrically connected to or capable of being connected to a voltage source. Programming is manifested by heated electrons from the channel region (18) injecting themselves onto the floating gate (20). Erasing occurs as electrons tunnel from the floating gate (20) to the erasure gate (30).

[0024] Table 2 illustrates typical voltage ranges that can be applied to the terminals of the memory cell (310) to perform read, erase, and programming operations:

[0025] [Table 2]

[0026]

[0027] FIG. 4 illustrates a separated gate 3-gate memory cell (410). The memory cell (410) is identical to the memory cell (310) of FIG. 3, except that the memory cell (410) does not have a separate control gate. The erase operation (erasing through the erase gate) and the read operation are similar to those of FIG. 3, except that there is no control gate bias. The programming operation is also performed without control gate bias, and thus the programming voltage on the source line is higher to compensate for the lack of control gate bias.

[0028] Table 3 illustrates typical voltage ranges that can be applied to the terminals of a memory cell (410) to perform read, erase, and programming operations:

[0029] [Table 3]

[0030]

[0031] FIG. 5 illustrates a stacked gate memory cell (510). The memory cell (510) is similar to the memory cell (210) of FIG. 2, except that it is separated by an insulating layer, so that a floating gate (20) extends over the entire channel area (18) and a control gate (22) extends over the floating gate (20). Erasing, programming, and reading operations operate in a manner similar to that previously described for the memory cell (210).

[0032] Table 4 illustrates typical voltage ranges that can be applied to the terminals of a memory cell (510) to perform read, erase, and programming operations:

[0033] [Table 4]

[0034]

[0035] To utilize memory arrays containing one of the types of non-volatile memory cells described above in an artificial neural network, two modifications are made. First, the lines are configured so that each memory cell can be programmed, erased, and read individually without adversely affecting the memory state of other memory cells in the array, as further described below. Second, sequential (or similar) programming of the memory cells is provided.

[0036] Specifically, the memory state (i.e., charge on the floating gate) of each memory cell in the array can be changed continuously from a completely erased state to a completely programmed state independently and with minimal disturbance to other memory cells. In another embodiment, the memory state (i.e., charge on the floating gate) of each memory cell in the array can be changed continuously from a completely programmed state to a completely erased state independently and with minimal disturbance to other memory cells, and vice versa. This means that the cell storage can store one of similar or at least many individual values ​​(e.g., 16 or 64 different values), which allows for very precise and individual tuning of all cells in the memory array and makes the memory array ideal for storing and performing fine-tuning adjustments for the synaptic weights of a neural network.

[0037] Neural networks employing non-volatile memory cell arrays

[0038] FIG. 6 conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array. This example uses a non-volatile memory array neural network for a face recognition application, but any other suitable application can be implemented using a non-volatile memory array-based neural network.

[0039] S0 is an input, for this example, a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, each pixel having 5-bit precision). Synapses (CB1) from S0 to C1 have different sets of weights and shared weights, and scan the input image through 3x3 pixel overlapping filters (kernels) to shift the filters by 1 pixel (or more than 1 pixel as indicated by the model). Specifically, values ​​for nine pixels (i.e., referred to as filters or kernels) within a 3x3 portion of the image are provided to synapses (CB1), thereby multiplying these nine input values ​​with appropriate weights and summing the outputs of the multiplication, after which a single output value is determined and provided by the first neuron of CB1 to generate a pixel in one layer of the feature map (C1). Subsequently, the 3x3 filter is shifted one pixel to the right (i.e., adding a column of three pixels to the right and subtracting a column of three pixels from the left), thereby providing the nine pixel values ​​in this newly positioned filter to synapses (CB1), thereby multiplying them with the same weights, and a second single output value is determined by the associated neuron. This process continues for all three colors and for all bits (precision values) until a 3x3 filter scans across the entire 32x32 pixel image. Then, the process is repeated using different sets of weights to generate different feature maps of C1 until all feature maps of layer (C1) are calculated.

[0040] In C1, in this example, there are 16 feature maps, each having 30x30 pixels. Each pixel is a new feature pixel extracted from multiplying the inputs by a kernel, and thus each feature map is a 2D array, and thus, in this example, the synapses (CB1) constitute 16 layers of 2D arrays (note that the neuron layers and arrays mentioned herein are not necessarily physical but logical—that is, the arrays are not necessarily physically oriented into 2D arrays). Each of the 16 feature maps is generated by one of 16 different sets of synaptic weights applied to the filter scan. All of the C1 feature maps may relate to different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared for all scans used to generate the first map) can identify circular edges, and a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges, or aspect ratios of specific features, etc.

[0041] An activation function (P1) (pooling) is applied before going from C1 to S1, which pools values ​​from consecutive non-overlapping 2x2 regions within each feature map. The purpose of the pooling stage is, for example, to average neighboring locations to reduce dependency on edge locations and reduce data size before moving to the next stage (or a maximum function may also be used). S1 has 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). Synapses and associated neurons in CB2 going from S1 to C2 scan the maps in S1 with 4x4 filters having a filter shift of 1 pixel. C2 has 22 12x12 feature maps. An activation function (P2) (pooling) is applied before going from C2 to S2, which pools values ​​from consecutive non-overlapping 2x2 regions within each feature map. S2 contains 22 6x6 feature maps. An activation function is applied at the synapses (CB3) from S2 to C3, where every neuron in C3 is connected to every map in S2. C3 contains 64 neurons. The synapses (CB4) from C3 to the output (S3) completely connect S3 to C3. The output from S3 contains 10 neurons, where the highest output neuron determines the classification. This output can represent, for example, the identification or classification of the content of the original image.

[0042] Each level of the synapses is implemented using an array of non-volatile memory cells or a portion of their array. FIG. 7 is a block diagram of a VMM array comprising non-volatile memory cells and utilized as synapses between an input layer and a next layer. Specifically, the VMM (32) comprises an array of non-volatile memory cells (33), an erase gate and word line gate decoder (34), a control gate decoder (35), a bit line decoder (36), and a source line decoder (37), which decode inputs to the memory array (33). In this example, the source line decoder (37) also decodes the output of the memory cell array. Alternatively, the bit line decoder (36) may decode the output of the memory array. The memory array serves two purposes. First, it stores weights to be used by the VMM. Second, the memory array effectively multiplies the inputs with the weights stored in the memory array and sums them for each output line (source line or bit line) to generate an output, which will be an input to the next layer or an input to the final layer. By performing the multiplication and summing functions, the memory array eliminates the need for separate multiplication and summing logic circuits and is also power efficient due to in-situ memory computation.

[0043] The output of the memory array is fed to a differential summer (e.g., a summing operation amplifier) ​​(38), which sums the outputs of the memory cell array to generate a single value for the convolution. The differential summer is intended to realize, for example, the summing of positive weights and negative weights and positive inputs. The summed output values ​​are then fed to an activation function circuit (39) that rectifies the output. The activation function may include sigmoid, tanh, or ReLU functions. The rectified output values ​​become elements of a feature map as the next layer (e.g., C1 in the description above) and are then applied to the next synapse to create the next feature map layer or the final layer. Thus, in this example, the memory array constitutes multiple synapses (which receive their inputs from the previous neuron layer or from an input layer such as an image database), and the summing operation amplifier (38) and the activation function circuit (39) constitute multiple neurons.

[0044] FIG. 8 is a block diagram of VMMs of various levels. As illustrated in FIG. 14, the input is converted from digital to analog by a digital-to-analog converter (31) and provided to an input VMM (32a). The output generated by the input VMM (32a) is provided as an input to the next VMM (hidden level 1) (32b), and the input to the next VMM then generates an output provided as an input to the next VMM (hidden level 2) (32b), and so on. The various layers of the VMM (32) function as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM may be a standalone non-volatile memory array, or multiple VMMs may utilize different parts of the same non-volatile memory array, or multiple VMMs may utilize overlapping parts of the same non-volatile memory array. The example illustrated in FIG. 8 includes five layers (32a, 32b, 32c, 32d, 32e), namely one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will understand that this is merely exemplary and that the system may instead include more than two hidden layers and more than two fully connected layers.

[0045] VMM arrays

[0046] FIG. 9 illustrates a neuron VMM (900), which is particularly suitable for memory cells of the type illustrated in FIG. 2 and is utilized as a portion of synapses and neurons between the input layer and the next layer. The VMM (900) includes a memory array (903) of non-volatile memory cells, a reference array (901), and a reference array (902). The reference arrays (901, 902) serve to convert current inputs flowing into terminals BLR0 to BLR3 into voltage inputs WL0 to WL3. The reference arrays (901, 902) as illustrated are in a column direction. Generally, the direction of the reference arrays is orthogonal to the input lines. In effect, the reference memory cells are diode-connected through multiplexers (multiplexers (914) including a cascoding transistor (VBLR) for biasing the reference bit line) into which current inputs flow. The reference cells are tuned to target reference levels.

[0047] The memory array (903) serves two purposes. First, it stores weights to be used by the VMM (900). Second, the memory array (903) effectively multiplies inputs (current inputs provided to terminals BLR0 through BLR3; reference arrays (901, 902) convert these current inputs into input voltages to be supplied to word lines WL0 through WL3) with the weights stored in the memory array to produce an output, which will be an input to the next layer or an input to the final layer. By performing a multiplication function, the memory array eliminates the need for separate multiplication logic circuits and is also power efficient. Here, voltage inputs are provided on the word lines, and the output comes out on the bit line during the read (inference) operation. The current placed on the bit line performs a summation function of all currents from the memory cells connected to the bit line.

[0048] FIG. 42 illustrates the operating voltages for the VMM (900). The columns in the table represent the voltages placed on the word lines for selected cells, the word lines for unselected cells, the bit lines for selected cells, the bit lines for unselected cells, the source lines for selected cells, and the source lines for unselected cells. The rows represent read, erase, and programming operations.

[0049] FIG. 10 illustrates a neuron VMM (1000), which is particularly suitable for memory cells of the type illustrated in FIG. 2 and is utilized as a portion of synapses and neurons between an input layer and a next layer. The VMM (1000) includes a memory array (1003) of non-volatile memory cells, a reference array (1001), and a reference array (1002). The VMM (1000) is similar to the VMM (900), except that the word lines in the VMM (1000) are arranged vertically. There are two reference arrays (1001) (located at the top, which provides a reference for converting input current into voltage for even rows) and a reference array (1002) (located at the bottom, which provides a reference for converting input current into voltage for odd rows). Here, inputs are provided on the word lines, and outputs come out on the source lines during a read operation. The current placed on the source line performs the summation function of all currents from the memory cells connected to the source line.

[0050] FIG. 43 illustrates the operating voltages for the VMM (1000). The columns in the table represent the voltages placed on the word lines for selected cells, the word lines for unselected cells, the bit lines for selected cells, the bit lines for unselected cells, the source lines for selected cells, and the source lines for unselected cells. The rows represent read, erase, and programming operations.

[0051] FIG. 11 illustrates a neuron VMM (1100), which is particularly suitable for memory cells of the type illustrated in FIG. 3 and is utilized as a portion of synapses and neurons between an input layer and a next layer. The VMM (1100) comprises a memory array (1101) of non-volatile memory cells, a reference array (1102) (providing a reference for converting input current into input voltage for even rows), and a reference array (1103) (providing a reference for converting input current into input voltage for odd rows). The VMM (1100) is similar to the VMM (900) except that the VMM (1100) further comprises a control line (1106) coupled to the control gates of the rows of memory cells and a control line (1107) coupled to the erase gates of adjacent rows of memory cells. Here, the word lines, control gate lines, and erase gate lines have the same direction. The VMM further includes a reference bit line selection transistor (1104) (part of mux (1114)) that selectively couples a reference bit line to a bit line contact of a selected reference memory cell, and a switch (1105) (part of mux (1114)) that selectively couples a reference bit line to a control line (1106) for a specific selected reference memory cell. Here, inputs are provided on word lines (of the memory array (1101)), and outputs appear on a bit line such as a bit line (1109) during a read operation. The current placed on the bit line performs a summation function of all currents from the memory cells connected to the bit line.

[0052] FIG. 44 illustrates the operating voltages for the VMM (1100). The columns in the table represent the word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, control gates for selected cells, control gates for unselected cells within the same sector as the selected cells, control gates for unselected cells within a different sector from the selected cells, erase gates for selected cells, erase gates for unselected cells, source lines for selected cells, and voltages placed on the source lines for unselected cells. The rows represent read, erase, and programming operations.

[0053] FIG. 12 illustrates a neuron VMM (1200), which is particularly suitable for memory cells of the type illustrated in FIG. 3 and is utilized as a portion of synapses and neurons between the input layer and the next layer. The VMM (1200) is similar to the VMM (1100) except that erasure gate lines, such as the erasure gate line (1201) in the VMM (1200), are connected in a vertical direction. Here, inputs are provided on word lines, and outputs appear on source lines. The current placed on the bit line performs a summation function of all currents from the memory cells connected to the bit line.

[0054] FIG. 45 illustrates the operating voltages for the VMM (1200). The columns in the table represent the word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, control gates for selected cells, control gates for unselected cells within the same sector as the selected cells, control gates for unselected cells within a different sector from the selected cells, erase gates for selected cells, erase gates for unselected cells, source lines for selected cells, and voltages placed on the source lines for unselected cells. The rows represent read, erase, and programming operations.

[0055] FIG. 13 illustrates a neuron VMM (1300), which is particularly suitable for memory cells of the type illustrated in FIG. 3 and is utilized as a portion of synapses and neurons between an input layer and a next layer. The VMM (1300) includes a memory array (1301) of non-volatile memory cells and a reference array (1302) (located at the top of the array). Alternatively, another reference array may be placed at the bottom, similar to that of FIG. 10. In another respect, the VMM (1300) is similar to the VMM (1200) except that control gate lines, such as control gate lines (1303) in the VMM (1300), are arranged vertically (thus, a reference array (1302) in a row direction orthogonal to the input control gate lines), and erase gate lines, such as erase gate lines (1304), are arranged horizontally. Here, inputs are provided on the control gate lines, and outputs come out on the source lines. In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current placed on the source line performs a summation function of all currents from the memory cells connected to the source line.

[0056] As described in this specification regarding neural networks, flash cells are preferably configured to operate in a sub-critical region.

[0057] The memory cells described in this specification are biased with a weak inversion as follows:

[0058] Ids = Io * e (Vg- Vth) / ㎸t = w * Io * e (Vg) / ㎸t

[0059] w = e (- Vth) / ㎸t

[0060] To enable an IV (I-to-V) log converter using memory cells to convert input current into input voltage:

[0061] Vg = k * Vt * log [Ids / wp * Io]

[0062] For a memory array used as a vector-matrix multiplier (VMM), the output current is as follows:

[0063] Iout = wa * Io * e (Vg) / ㎸t , in other words

[0064] Iout = (wa / wp) * Iin = W * Iin

[0065] W = e (Vthp - Vtha) / ㎸t

[0066] A word line or control gate can be used as an input to the memory cell for the input voltage.

[0067] Alternatively, flash memory cells can be configured to operate in a linear region:

[0068] Ids = beta* (Vgs-Vth)*Vds; beta = u*Cox*W / L

[0069] W α (Vgs-Vth)

[0070] For an IV linear converter, a memory cell operating in the linear region can be used to linearly convert input / output current into input / output voltage.

[0071] Other embodiments of the ESF vector matrix multiplier are as described in U.S. Patent Application No. 15 / 826,345, incorporated herein by reference. A source line or a bit line may be used as a neuron output (current summing output).

[0072] FIG. 14 illustrates an embodiment of a bit line decoder circuit (1400). The bit line decoder circuit (1400) includes a column decoder (1402) and an analog neuromorphic neuron ("ANN") column decoder (1403), each of which is coupled to a VMM array (1401). The VMM array may be based on any of the previously discussed VMM designs (e.g., VMM (900, 1000, 1100, 1200, 1300)) or other VMM designs.

[0073] One challenge in analog neuromorphic systems is that the system must be able to program and verify individual selected cells (which entails a read operation), and it must also be able to perform an ANN read in which all cells within the array are selected and read. In other words, a bit line decoder sometimes needs to select only one bit line, and in other cases, all bit lines must be selected.

[0074] A bit line decoder circuit (1400) achieves this purpose. A column decoder (1402) is a conventional column decoder (programming and erasing, i.e., PE, decoding path) and can be used to select individual bit lines, for example, for programming and programming verification (sensing operation). The outputs of the column decoder (1402) are coupled to a PE column driver circuit (not shown in FIG. 14) to control programming, programming / erasing (PE) verification, and erasing. An ANN column decoder (1403) is a column decoder specifically designed to simultaneously enable read operations for each bit line. The ANN column decoder (1403) includes an exemplary select transistor (1405) coupled to a bit line (here, BL0) and an output circuit (e.g., a current summer and an activation function, e.g., tanh, sigmoid, ReLU) (1406). A set of identical devices is attached to each of the other bit lines. All of the select transistors, such as select transistors (1405), are coupled to the select line (1404). During the ANN read operation, the select line (1404) is enabled, which turns on each of the select transistors, such as select transistor (1405), and each of these select transistors subsequently causes current from each bit line to be received and output by an output circuit such as circuit (1406).

[0075] FIG. 15 illustrates an embodiment of a bit line decoder circuit (1500). The bit line decoder circuit (1500) is coupled to a VMM array (1501). The VMM array may be based on any of the previously discussed VMM designs (e.g., VMM (900, 1000, 1100, 1200, 1300)) or other VMM designs.

[0076] Select transistors (1502, 1503) are controlled by a pair of complementary control signals V0 and VB_0 and coupled to bit line BL0. Select transistors (1504, 1505) are controlled by another pair of complementary control signals V1 and VB_1 and coupled to another bit line BL1. Select transistors (1502, 1504) are coupled to the same output, for example, to enable programming, and select transistors (1503, 1505) are coupled to the same output, for example, to disable programming. The output lines (programming and erasing PE decoding paths) of transistors (1502 / 1503 / 1504 / 1505) are coupled to a PE column driver circuit (not shown) for controlling programming, PE verification, and erasure, for example.

[0077] The select transistor (1506) is coupled to the bit line BL0 and to the output and activation function circuit (1507) (e.g., current summer and activation function, e.g., tanh, S-phase, ReLU). The select transistor (1506) is controlled by the control line (1508).

[0078] When only BL0 is to be activated, the control line (1508) is de-asserted and the signal V0 is asserted, so that only BL0 is read accordingly. During the ANN read operation, the control line (1508) is asserted, the select transistor (1506) and similar transistors are turned on, and all bit lines are read, for example, for all neuron processing.

[0079] FIG. 16 illustrates an embodiment of a bit line decoder circuit (1600). The bit line decoder circuit (1600) is coupled to a VMM array (1601). The VMM array may be based on any of the previously discussed VMM designs (e.g., VMM (900, 1000, 1100, 1200, 1300)) or other VMM designs.

[0080] The select transistor (1601) is coupled to the bit line BL0 and the output and enable function circuit (1603). The select transistor (1602) is coupled to the bit line BL0 and the common output (PE decoding path).

[0081] When only BL0 needs to be activated, the select transistor (1602) is activated and BL0 is attached to the common output. During the ANN read operation, the select transistor (1601) and similar transistors are turned on and all bit lines are read.

[0082] For decoding in FIGS. 14, 15, and 16, a negative bias may be applied to unselected transistors to reduce the impact of transistor leakage on memory cell performance. Alternatively, a negative bias may be applied to the PE decoding path while the array is in ANN operation. The negative bias may be -0.1 V to -0.5 V or higher.

[0083] FIG. 17 illustrates a VMM system (1700). The VMM system (1700) comprises a VMM array (1701) and a reference array (1720) (which may be based on any of the previously discussed VMM designs, e.g., VMM (900, 1000, 1100, 1200, 1300) or other VMM designs), a low-voltage row decoder (1702), a high-voltage row decoder (1703), a reference cell low-voltage column decoder (1704) (illustrated for the reference array in the column direction, meaning it provides input-output conversion in the row direction), a bit line PE driver (1712), a bit line multiplexer (1706), an activation function circuit and summer (1707), control logic (1705), and an analog bias circuit (1708).

[0084] As described, the reference cell low voltage column decoder (1704) is for the reference array (1720) in the column direction, which means providing input-output conversion in the row direction. If the reference array is in the row direction, the reference decoder needs to be implemented at the top and / or bottom of the array to provide input-output conversion in the column direction.

[0085] The low-voltage row decoder (1702) provides a bias voltage for read and programming operations and provides a decoding signal for the high-voltage row decoder (1703). The high-voltage row decoder (1703) provides a high-voltage bias signal for programming and erase operations. The reference cell low-voltage column decoder (1704) provides a decoding function for reference cells. The bit line PE driver (1712) provides a control function for the bit line during programming, verification, and erase. The bias circuit (1705) is a shared bias block that provides multiple voltages required for various programming, erase, programming verification, and read operations.

[0086] FIG. 18 illustrates a VMM system (1800). The VMM system (1800) is similar to the VMM system (1700), except that the VMM system (1800) additionally includes a red array (1801), a bit line PE driver BLDRV (1802), a high-voltage column decoder (1803), NVR sectors (1804), and a reference array (1820). The high-voltage column decoder (1803) provides a high-voltage bias for vertical decoding lines. The red array (1802) provides array redundancy to replace defective array parts. The NVR (non-volatile register, also known as information sectors) sectors (1804) are sectors that are array sectors used to store user information, device ID, password, security key, trimming bits, configuration bits, manufacturing information, etc.

[0087] FIG. 19 illustrates a VMM system (1900). The VMM system (1900) is similar to the VMM system (1800) except that the VMM system (1900) additionally includes a reference system (1999). The reference system (1999) includes a reference array (1901), a reference array low-voltage row decoder (1902), a reference array high-voltage row decoder (1903), and a reference array low-voltage column decoder (1904). The reference system may be shared across multiple VMM systems. The VMM system additionally includes NVR sectors (1905).

[0088] The reference array low-voltage row decoder (1902) provides a bias voltage for read and programming operations involving the reference array (1901) and also provides a decoding signal for the reference array high-voltage row decoder (1903). The reference array high-voltage row decoder (1903) provides a high-voltage bias for programming and operations involving the reference array (1901). The reference array low-voltage column decoder (1904) provides a decoding function for the reference array (1901). The reference array (1901) is intended to provide a reference target for, for example, programming verification or cell margining (searching for margin cells).

[0089] FIG. 20 illustrates a word line driver (2000). The word line driver (2000) selects a word line (such as the exemplary word lines shown herein (WL0, WL1, WL2, WL3)) and provides a bias voltage to the word line. Each word line is attached to a select transistor, such as a select iso (isolation) transistor (2002), which is controlled by a control line (2001). The iso transistor (2002) is used to isolate high voltage (e.g., 8 to 12 V) from erasure, for example, from word line decoding transistors, which can be implemented as IO transistors (e.g., 1.8 V, 3.3 V). Here, during any operation, the control line (2001) is activated, and all select transistors similar to the select iso transistor (2002) are turned on. An exemplary bias transistor (2003) (part of the word line decoding circuit) selectively couples a word line to a first bias voltage (e.g., 3 V), and an exemplary bias transistor (2004) (part of the word line decoding circuit) selectively couples a word line to a second bias voltage (lower than the first bias voltage, which includes a bias between ground, a negative voltage bias to reduce leakage from unused memory rows). During an ANN read operation, all used word lines will be selected and associated with the first bias voltage. All unused word lines will be associated with the second bias voltage. For example, during other operations for a programming operation, only one word line will be selected, and other word lines will be associated with a second bias voltage, which may be a negative bias (e.g., -0.3 to -0.5 V or higher) to reduce array leakage.

[0090] FIG. 21 illustrates a word line driver (2100). The word line driver (2100) is similar to the word line driver (2000) except that upper transistors, such as the bias transistor (2103), can be individually coupled to the bias voltage, and not all such transistors are associated together as in the word line driver (2000). This allows all word lines to have different independent voltages simultaneously in parallel.

[0091] FIG. 22 illustrates a word line driver (2200). The word line driver (2200) is similar to the word line driver (2100) except that bias transistors (2103, 2104) are coupled to a decoder circuit (2201) and an inverter (2202). Accordingly, FIG. 22 illustrates a decoding subcircuit (2203) within the word line driver (2200).

[0092] FIG. 23 illustrates a word line driver (2300). The word line driver (2300) is similar to the word line driver (2100) except that bias transistors (2103, 2104) are coupled to the outputs of stage (2302) of the shift register (2301). The shift register (1301) serially shifts data (serially clocking the registers) to allow each row to be controlled independently, so that, for example, one or more rows can be enabled simultaneously according to the shifted data pattern.

[0093] FIG. 24 illustrates a word line driver (2400). The word line driver (2400) is similar to the word line driver (2000), except that each select transistor is additionally coupled to a capacitor such as capacitor (2403). The capacitor (2403) can provide pre-charge or bias to the word line at the start of operation, which is enabled by the transistor (2401) to a sample voltage on the line (2440). The capacitor (2403) acts to sample and hold (S / H) the input voltage for each word line. The transistors (2401) are turned off during the ANN operation (array current summer and enable function) of the VMM array, which means that the voltage on the S / H capacitor will act as a (floating) voltage source for the word line. Alternatively, the capacitor (2403) may be provided by the word line capacitance from the memory array.

[0094] FIG. 25 illustrates a word line driver (2500). The word line driver (2500) is similar to the word line drivers described above, except that bias transistors (2501, 2502) are respectively connected to switches (2503, 2504). Switch (2503) receives the output of opa (operational amplifier) ​​(2505), and switch (2504) provides a reference input to the negative input of opa (2505), which, essentially, provides a voltage stored by capacitor (2403) through the action of a closed loop provided by opa (2505), transistor (2501), and switches (2503, 2504). In this way, when switches (2503, 2504) are closed, the voltage on the input (2506) is superimposed on capacitor (2403) by transistor (2501). Alternatively, the capacitor (2403) may be provided by the word line capacitance from the memory array.

[0095] FIG. 26 illustrates a word line driver. The word line driver (2600) is similar to the word line drivers described above, except for the addition of an amplifier (2601) that acts as a voltage buffer for the voltage on the capacitor (2604) to drive the voltage into the word line WL0, which means that the voltage on the S / H capacitor will act as a (floating) voltage source for the word line. This is intended to avoid, for example, word line-word line coupling affecting the voltage on the capacitor.

[0096] FIG. 27 illustrates a high-voltage source line decoder circuit (2700). The high-voltage source line decoder circuit includes transistors (2701, 2702, 2703) configured as illustrated. Transistor (2703) is used to deselect the source line for low voltage. Transistor (2702) is used to drive high voltage into the source line of the array, and transistor (2701) is used to monitor the voltage on the source line. The transistors (2702, 2701) and the driver circuit (e.g., opa) are configured in a closed-loop manner (force / sensing) to maintain voltage across PVT (process, voltage, temperature) and fluctuating current load conditions. An SLE (driven source line node) and an SLB (monitored source line node) may be located at one end of the source line. Alternatively, the SLE may be at one end of the source line and the SLN may be at the other end of the source line.

[0097] FIG. 28 illustrates VMM high-voltage decode circuits including a word line decoder circuit (2801), a source line decoder circuit (2804), and a high-voltage level shifter (2808), suitable for use with memory cells of the type shown in FIG. 2.

[0098] The word line decoder circuit (2801) includes a PMOS select transistor (2802) (controlled by signal HVO_B) and an NMOS deselect transistor (2803) (controlled by signal HVO_B) configured as shown.

[0099] The source line decoder circuit (2804) includes NMOS monitor transistors (2805) (controlled by signal HVO), a driving transistor (2806) (controlled by signal HVO), and a deselection transistor (2807) (controlled by signal HVO_B) configured as shown.

[0100] The high voltage level shifter (2808) receives the enable signal EN and outputs the high voltage signal HV and its complement HVO_B.

[0101] FIG. 29 illustrates VMM high-voltage decode circuits including an erase gate decoder circuit (2901), a control gate decoder circuit (2904), a source line decoder circuit (2907), and a high-voltage level shifter (2911), suitable for use with memory cells of the type shown in FIG. 3.

[0102] The erase gate decoder circuit (2901) and the control gate decoder circuit (2904) use the same design as the word line decoder circuit (2801) in FIG. 28.

[0103] The source line decoder circuit (2907) uses the same design as the source line decoder circuit (2804) in FIG. 28.

[0104] The high-voltage level shifter (2911) uses the same design as the high-voltage level shifter (2808) in FIG. 28.

[0105] FIG. 30 illustrates a word line decoder (300) for exemplary word lines WL0, WL1, WL2, and WL3. The exemplary word line WL0 is coupled to a pull-up transistor (3001) and a pull-down transistor (3002). When the pull-up transistor (3001) is activated, WL0 is enabled. When the pull-down transistor (3002) is activated, WL0 is disabled. The function of FIG. 30 is similar to that of FIG. 21 without isolation transistors.

[0106] FIG. 31 illustrates a control gate decoder (3100) for exemplary control gate lines CG0, CG1, CG2, and CG3. An exemplary control gate line CG0 is coupled to pull-up transistors (3101) and a pull-down transistor (3102). When the pull-up transistor (3101) is activated, CG0 is enabled. When the pull-down transistor (3102) is activated, CG0 is disabled. The selection and deselection functions of FIG. 31 are similar to those of FIG. 30 for the control gates.

[0107] FIG. 32 illustrates a control gate decoder (3200) for exemplary control gate lines CG0, CG1, CG2, and CG3. The control gate decoder (3200) is similar to the control gate decoder (3100) except that the control gate decoder (3200) includes a capacitor such as a capacitor (3203) coupled to each control gate line. These sample-and-hold (S / H) capacitors can provide a pre-charge bias on each control gate line before operation, which means that the voltage on the S / H capacitor will act as a (floating) voltage source for the control gate lines. The S / H capacitor may be provided by the control gate capacitance from the memory cell.

[0108] FIG. 33 illustrates a control gate decoder (3300) for exemplary control gate lines CG0, CG1, CG2, and CG3. The control gate decoder (3300) is similar to the control gate decoder (3200) except that the control gate decoder (3300) additionally includes a buffer (3301) (e.g., opa).

[0109] FIG. 34 illustrates a current-voltage circuit (3400). The circuit includes a configured diode-connected reference cell circuit (3450) and a sample-and-hold circuit (3460). The circuit (3450) includes an input current source (3401), an NMOS transistor (3402), a cascoding bias transistor (3403), and a reference memory cell (3404). The sample-and-hold circuit consists of a switch (3405) and an S / H capacitor (3406). In a diode-connected configuration, the memory (3404) is biased with a bias on its bit line, for example, to supply a word line, in order to convert the input current into a voltage.

[0110] FIG. 35 illustrates a current-voltage circuit (3500) similar to the current-voltage circuit (3400) with an amplifier (3501) added after the S / H capacitor. The current-voltage circuit (3500) includes a configured diode-connected reference cell circuit (3550), a sample-and-hold circuit (3470), and an amplifier stage (3562).

[0111] FIG. 36 illustrates a current-voltage circuit (3600) that is of the same design as the current-voltage circuit (3400) for a control gate in a diode-connected configuration. The current-voltage circuit (3600) includes a configured diode-connected reference cell circuit (3650) and a sample-and-hold circuit (3660).

[0112] FIG. 37 illustrates a current-voltage circuit (3700) in which a buffer (3790) is placed between a reference circuit (3750) and an S / H circuit (3760).

[0113] FIG. 38 illustrates a current-voltage circuit (3800) similar to FIG. 35 having a control gate connected in a diode-connected configuration. The current-voltage circuit (3800) includes a configured diode-connected reference cell circuit (3550), a sample-and-hold circuit (3870), and an amplifier stage (3862).

[0114] FIG. 39 illustrates a current-voltage circuit (3900) similar to FIG. 34, as applied to the memory cell in FIG. 2. The current-voltage circuit (3900) includes a configured diode-connected reference cell circuit (3950) and a sample-and-hold circuit (3960).

[0115] FIG. 40 illustrates a current-voltage circuit (4000) similar to FIG. 37, which is applied to the memory cell in FIG. 2, wherein a buffer (4090) is placed between the reference circuit (4050) and the S / H circuit (4060).

[0116] FIG. 41 illustrates a current-voltage circuit (4100) similar to FIG. 38, as applied to the memory cell in FIG. 2. The current-voltage circuit (4100) includes a configured diode-connected reference cell circuit (4150), a sample-and-hold circuit (4170), and an amplifier stage (4162).

[0117] As used herein, it should be noted that both terms “on” and “on” comprehensively include “directly on” (without any intermediate materials, elements, or spaces placed between them) and “indirectly on” (with intermediate materials, elements, or spaces placed between them). Likewise, the term "adjacent" includes "directly adjacent" (with no intermediate materials, elements, or spaces placed between them) and "indirectly adjacent" (with intermediate materials, elements, or spaces placed between them), "mounted on" includes "directly mounted on" (with no intermediate materials, elements, or spaces placed between them) and "indirectly mounted on" (with intermediate materials, elements, or spaces placed between them), and "electrically coupled" includes "directly electrically coupled to" (with no intermediate materials or elements electrically connecting the elements together between them) and "indirectly electrically coupled to" (with intermediate materials or elements electrically connecting the elements together between them). For example, forming an element "on a substrate" may include not only forming the element directly on the substrate without any intermediate materials / elements between them, but also forming the element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

Claim 1 A word line driver coupled to a vector-by-matrix multiplication (VMM) array comprising an array of non-volatile memory cells organized into rows and columns, wherein each row is coupled to a word line, each word line is coupled to the word line driver, and the word line driver comprises a plurality of select transistors, each comprising a first terminal, a second terminal, and a gate, wherein the gate of each of the plurality of select transistors is coupled to a common control line, the first terminal of each of the plurality of select transistors is coupled to a different word line, and the second terminal of each of the plurality of select transistors is coupled to a bias circuit comprising one or more bias transistors, wherein each bias circuit is coupled to a separate bias voltage source or to a common bias voltage source coupled to all bias circuits. Claim 2 delete Claim 3 delete Claim 4 In claim 1, the gate of each bias transistor is coupled to a word line driver for decoding a word line address. Claim 5 A word line driver according to claim 1, wherein the gates of the bias transistors are coupled to a single shift register. Claim 6 A word line driver according to claim 1, wherein the second terminal of each selection transistor is coupled to a capacitor. Claim 7 A word line driver according to claim 1, wherein the gate of each bias transistor is coupled to a comparator.

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