Back-contact solar cell, and production thereof

Abstract

The invention relates to a method for producing a backcontact solar cell (10), and to a back-contact solar cell (10) comprising a semiconductor substrate (12), in particular a silicon wafer, comprising a front side (16) and a back side (14), the solar cell (10) comprising electrodes (36) of a first polarity and electrodes (38) of a second polarity on the back side, characterized in that that the electrodes (36) of the first polarity are located on a highly doped silicon layer (20) of the first polarity, the highly doped silicon layer (20) being located on a first passivation layer (18) located on the semiconductor substrate, and the electrodes (38) of the second polarity directly electrically and mechanically contacting the semiconductor substrate (12) via highly doped base regions (30) of the second polarity of the semiconductor substrate (12). (Fig. 1)

Description

[0001] Title : Back-contacted solar cell and

[0002] Production of such

[0003] Description

[0004] The invention relates to a solar cell and a method for producing a solar cell.

[0005] Solar cells are known to serve as photovoltaic elements for converting light into electrical energy. Charge carrier pairs generated by the absorption of light in a semiconductor substrate are separated at the junction between an emitter region, which has a first doping type, e.g. n-type or p-type, to generate a first polarity, and a base region, which has an opposite doping type to generate an opposite polarity. The charge carrier pairs generated and separated in this way can be fed to an external circuit via emitter contacts, which contact the emitter region, and base contacts, which contact the base region.

[0006] Solar cells are known in which contacts of one polarity are arranged on the front and contacts of the opposite polarity on the back. The front side is the side facing the sun, and the back side is the side facing away from the sun. In order to minimize losses resulting from shading by the contacts arranged on the front and thus increase efficiency, back-contact solar cells were developed in which both contact types, i.e. the emitter contacts and the base contacts, are arranged on the back of the semiconductor substrate.

[0007] Electrodes of both polarities are arranged next to each other on the back of the solar cell. The generated charge carriers must therefore also flow laterally within the solar cell. In order to minimize the resistance losses caused by this lateral current flow and to prevent the free charge carriers from recombinating before they reach the electrodes, the electrodes of both polarities should be as close to each other as possible. Since the electrodes are connected to either p- or n-type silicon, depending on the polarity, the pn junctions are also located as close together as possible. The pn junctions, fine, comb-like structures with a resolution of less than 500 pm, can be realized, for example, using laser irradiation. In this process, a pulsed laser beam drives two different dopants, e.g.Boron and phosphorus are melted locally into the silicon by melting the surface at different times and locations, creating either a high p-type or n-type doping depending on the dopant. This is disclosed, for example, in DE 10 2013 219 564 Al. Such fine structures enable low internal series resistances and efficiencies g up to q = 24%. Higher efficiencies are essentially limited by recombination mechanisms in the base as well as at the highly doped contacted and non-contacted surfaces. Recombination in the base depends on the wafer quality and can only be influenced to a small extent in the further manufacturing process of the solar cell. Recombination at the highly doped n- and p-type surfaces is limited in the non-contacted area with good surface passivation, such as with amorphous hydrogenated silicon, by Auger recombination, which increases with the dopant concentration in the silicon.In the contacted area, the silicon is in contact with a metal, which results in high interfacial recombination. In the solar cell process, Auger recombination at the non-contacted surfaces can be reduced if there is as little dopant as possible in the silicon, while interfacial recombination at the metal / silicon contacts can be reduced by keeping the contact area as small as possible. However, simply reducing the dopant and the contact areas results in an increase in series resistance, which then becomes the limiting factor for efficiency. For this reason, passivated or selective contacts are used, for example as known from DE 10 2013 219 564 Al or WO 2014 / 100004 Al.The electrodes are not directly electrically connected to the crystalline base, but are separated by a thin tunnel oxide which passivates the silicon surface but is at the same time so thin that the electrons can tunnel through the oxide from the semiconductor to the electrode or from the electrode to the semiconductor, depending on the polarity. To stimulate the electrons to tunnel, there must be an electric field at the tunnel oxide. The electric field can be generated by highly doped n- or p-type silicon on the tunnel oxide. Since doping this silicon above the tunnel oxide leads to band bending in the silicon base below the tunnel oxide, higher doping of the silicon base is no longer necessary.In highly doped n-type silicon, only electrons pass through the tunnel oxide, also known as electron flow, whereas in highly doped p-type silicon only a so-called hole flow occurs: electrons pass from the highly doped p-type silicon into the silicon base. The metal electrodes themselves are only in electrical and mechanical contact with the highly doped n- or p-type silicon above the tunnel oxide. The selectivity of the highly doped silicon regions in combination with the tunnel oxide ensures, depending on the doping, the transport of almost exclusively one type of charge carrier to the metal / silicon contact surfaces and minimizes interfacial recombination. The structure presented further reduces Auger recombination at the surface of the silicon base to the tunnel oxide, since no high doping is required at this interface for the pn junction or the ohmic contact to the base.Back-contact solar cells with passivated contacts have so far achieved a record efficiency of g = 26.7%. However, the production of such cells has been very complex, as the two differently doped selective contacts can only be applied using various complex masking and patterning steps. High precision and fine resolution of the masking / patterning are essential.

[0008] The distance between the selective contacts must not be too large and should not exceed the diffusion length of the free charge carriers and should not lead to an increase in the internal series resistance due to the lateral current flow in the base.

[0009] These disadvantages are overcome by a solar cell according to the invention and a method according to the invention for producing such a solar cell. At the same time, the method according to the invention enables industrial production with low process costs.

[0010] According to the invention, for a back-contacted solar cell comprising a semiconductor substrate, in particular a silicon wafer, comprising a front side and a back side, wherein the solar cell comprises electrodes of a first polarity on the back side and electrodes of a second polarity, it is proposed that the electrodes of the first polarity are arranged on a highly doped silicon layer of the first polarity, wherein the highly doped silicon layer is arranged on a first passivation layer arranged on the semiconductor substrate, and the electrodes of the second polarity directly electrically and mechanically contact the semiconductor substrate via highly doped base regions of the second polarity of the semiconductor substrate.

[0011] It is therefore proposed to use a different contacting concept for the electrodes of the first polarity and for the electrodes of the second polarity, so that both contacting concepts are combined in the back-contacted solar cell proposed according to the invention. For the electrodes of the first polarity, it is proposed that they contact the highly doped silicon layer deposited on a passivation layer, also referred to as a tunnel layer. For the electrodes of the second polarity, it is proposed that they contact the semiconductor substrate directly. This requires masking and unmasking during production.

[0012] According to one embodiment, it is provided that the highly doped base regions of the second polarity are formed within doped base regions of the second polarity on the back of the solar cell, wherein a dopant concentration in the highly doped base regions is higher than a dopant concentration in the doped base regions, and wherein the dopant concentration in the highly doped base regions is higher than a dopant concentration of a doped region on the front of the solar cell. The doped base regions on the back have a dopant concentration on the surface of Ixl O 17 cur 3 to Ixl O 19 cur 3 The doping on the entire front side can also cause a dopant concentration on the surface of Ixl O 17 cur 3 to Ixl O 19 cur 3The dopant concentration of the highly doped base regions for the base contact is preferably above a dopant concentration of 2xl 0 19 cnr 3 .

[0013] According to one embodiment, a second passivation layer is arranged on surface regions of the rear side that are not contacted by the electrodes of the first polarity and not by the electrodes of the second polarity. The second passivation layer is thicker than the first passivation layer. The region between two electrodes of different polarity comprises regions in which the second passivation layer and regions in which a layer stack comprising the first and second passivation layers is arranged.

[0014] The surface of the solar cell according to the invention therefore comprises the following differently doped areas:

[0015] - a highly doped polycrystalline silicon layer of the first polarity on the back side of the solar cell on the first passivation layer arranged on the semiconductor substrate, wherein the dopant concentration of the highly doped polycrystalline silicon layer is higher than the dopant concentration of the base;

[0016] - doped monocrystalline base regions of the second polarity on the back side, wherein the dopant concentration of the doped base regions is higher than the dopant concentration of the base;

[0017] - highly doped monocrystalline base regions of the second polarity within the doped base regions on the back side, the dopant concentration of these highly doped base regions being higher than the dopant concentration of the base and the dopant concentration of the doped base regions.

[0018] - a doped monocrystalline surface of a first or second polarity on the entire front side , the dopant concentration of the doped surface being higher than the dopant concentration of the base .

[0019] Further embodiments relate to a method for producing a back-contacted solar cell according to the embodiments described above.

[0020] A semiconductor substrate of the solar cell comprises a, in particular polished or textured, back side and a, in particular textured, front side. The texturing is carried out, for example, by a wet-chemical solution. A first passivation layer, in particular comprising silicon dioxide, is applied to a surface of the back side and / or to a surface of the front side. The first passivation layer has, for example, a thickness of preferably a maximum of 4 nm. The first passivation layer is produced, for example, in a thermal or wet-chemical process or by deposition. According to one embodiment, the method further comprises a step of depositing a, in particular full-area, highly doped silicon layer of a first polarity on the first passivation layer on the back side and / or on the front side.The highly doped silicon layer of the first polarity can be deposited, for example, using plasma-enhanced chemical vapor deposition (PECVD), atmospheric chemical vapor deposition (APCVD), low-pressure chemical vapor deposition (LPCVD), or cathodic sputtering. The highly doped silicon layer of the first polarity has a thickness of approximately 50 nm to 400 nm. The dopant concentration of the highly doped silicon layer is higher than the dopant concentration of the semiconductor substrate. The in-situ deposited dopant in the silicon layer is, for example, boron, aluminum, or gallium.

[0021] The deposition of the highly doped silicon layer of the first polarity can take place in two steps instead of one. In this case, undoped silicon is deposited first and then a dopant is introduced. The dopant is introduced, for example, by means of ion implantation or the application of a dopant source and subsequent diffusion using a thermal process or laser diffusion. The dopant is, for example, boron, aluminum or gallium. The diffusion can also take place at a later time. For example, the method can include a later step for introducing a further dopant. In this case, the dopants can be diffused simultaneously with the second dopant in a common thermal process.

[0022] According to one embodiment, a dielectric layer is applied to the rear side. The dielectric layer comprises, for example, silicon nitride, silicon oxide, silicon carbide, or aluminum oxide. The dielectric layer serves as a so-called diffusion barrier against a dopant to be applied later, for example, phosphorus, and has etch-resistant properties against a wet-chemical solution to be applied later. The dielectric layer has, for example, a greater thickness than the first passivation layer, preferably a thickness of more than 4 nm.

[0023] According to one embodiment, it is provided that by locally removing the dielectric layer, the highly doped silicon layer of the first polarity, and the first passivation layer on the rear side, base regions of the semiconductor substrate are exposed on the rear side. The removal of the individual layers is carried out, for example, at least partially by laser irradiation. According to one embodiment, it is provided that in the base regions of the semiconductor substrate on the rear side, a portion of the semiconductor substrate is locally removed. This can also be carried out by laser irradiation.

[0024] According to one embodiment, the exposure of the base regions of the semiconductor substrate on the rear side comprises etching the highly doped silicon layer of the first polarity and / or the first passivation layer and / or a portion of the semiconductor substrate locally in the base regions. For example, it can be provided that a wet-chemical solution etches the highly doped silicon layer, the first passivation layer, and a portion of the semiconductor substrate at the previously laser-irradiated base regions. Alternatively, it can be provided that the wet-chemical solution etches only the highly doped silicon layer or only a portion of the semiconductor substrate. In this case, the other layers, for example the first passivation layer or the highly doped silicon layer, are removed by laser irradiation.Advantageously, the wet-chemical solution can also etch a highly doped silicon layer deposited on the front side of the semiconductor substrate and / or a passivation layer deposited on the front side of the semiconductor substrate.

[0025] It can be provided that the etching comprises an isotropic etching for polishing regions and / or that the etching comprises an anisotropic etching for texturing regions. For example, the base regions can be polished by isotropic etching with a wet-chemical solution on the back side. Alternatively, the base regions can be textured by anisotropic etching with a wet-chemical solution on the back side. It can also be advantageous if the front side is textured by anisotropic etching with a wet-chemical solution. Different wet-chemical solutions can be used to remove the different layers and, if appropriate, to texturing and / or polish the surfaces. According to one embodiment, the method comprises a step for applying a precursor layer comprising a dopant, in particular phosphorus, to the back side or to the back side and to the front side.The precursor layer can be deposited on the front side and on the back side in one process step or in different process steps. The precursor layers on the front and back side can have the same or different properties. The precursor layer is a layer comprising a dopant of a second polarity, in particular a phosphosilicate glass layer, PSG. The precursor layer is applied in particular to the dielectric layer and to, in particular the wet-chemically etched, regions on the back side and on the front side. If the highly doped silicon layer of the first polarity is a p-type silicon layer, the dopant in the precursor layer for doping the silicon according to the second polarity is, for example, phosphorus.To apply the precursor layer, for example, a furnace diffusion process can be used, in which a phosphosilicate glass layer grows on the previously etched areas on the back and front sides. In special cases, the PSG layer can also grow on the dielectric layer on the back. The furnace diffusion process can be carried out in such a way that, after the furnace diffusion process, the phosphosilicate glass layer contains a high proportion of phosphorus. In a further embodiment, the precursor layer, for example PSG, can be deposited using PECVD, LPCVD, or APCVD.

[0026] According to one embodiment, it is provided that by a high-temperature step in which the dopant from the precursor layer diffuses into the base regions on the back side and / or into the surface of the front side, the doping in the base regions on the back side is increased and / or a doped region is created on the front side. The dopant dopes the base regions on the back side according to a second polarity, opposite to the first polarity of the highly doped silicon layer, so that doped base regions are created. The doped base regions on the back side comprise a higher dopant concentration than the dopant concentration of the semiconductor substrate. On the back side, the dopant from the precursor layer does not diffuse into the highly doped silicon layer because the dielectric layer serves as a diffusion barrier against the dopant from the precursor layer.On the front side, a doped region is created by doping the surface according to the second polarity. The dopant concentration of the doped region on the front side is higher than the dopant concentration of the semiconductor substrate. The high-temperature step is, for example, the furnace diffusion step for applying the precursor layer. Alternatively, it can also be an additional high-temperature step. The high-temperature step can, for example, be carried out in such a way that only a portion of the second dopant diffuses from the precursor layer into the base regions on the back side.

[0027] According to one embodiment, a highly doped base region is created within the base regions on the rear side by locally increasing the dopant concentration, in particular by laser irradiation. The laser irradiation locally heats and melts the surface on the rear side in the irradiated regions. Additional dopant from the precursor layer diffuses into the surface in the irradiated regions and, after cooling and recrystallization, further dopes the irradiated region according to the second polarity, so that highly doped base regions are created. The dopant concentration in the highly doped base regions is significantly higher than the dopant concentration of the semiconductor substrate, higher than that of the doped base regions on the rear side, and higher than that in the doped region on the front side.

[0028] By creating the highly doped base regions by laser irradiation, a doping optimized particularly for the front side of the solar cell can advantageously be created in the preceding furnace diffusion step. Ideally, the front side is more lightly doped than the base regions on the back side. If the front and back sides are doped in a single process step, a compromise in doping is necessary. This disadvantage is overcome by creating the highly doped base regions on the back side using laser irradiation.

[0029] According to one embodiment, the method comprises a step for removing the precursor layer, in particular phosphosilicate glass, from the front side and / or from the back side. The removal takes place, for example, in a wet-chemical cleaning step. Advantageously, the wet-chemical cleaning step or a further post-chemical cleaning step also removes any remaining residues of the dielectric layer from the highly doped silicon layer. According to one embodiment, the method comprises a step for applying a second passivation layer to the back side and / or a third passivation layer to the front side. A passivation layer comprises, for example, silicon dioxide, silicon nitride, aluminum oxide, or a layer stack comprising two or more dielectric layers.The thickness, refractive index and composition of the passivation layer on the back side can differ from the thickness, refractive index and composition of the passivation layer on the front side. The thicknesses of the passivation layers are advantageously optimized such that the reflection is reduced on the front side and increased on the back side. The second and / or third passivation layer advantageously has a greater thickness than the first passivation layer. The thickness of the second and / or third passivation layer is advantageously greater than 4 nm. According to one embodiment, the method comprises a step for selectively removing the second passivation layer on the back side. The passivation layer can be removed locally, for example by laser irradiation.

[0030] According to one embodiment, the method comprises a step for applying electrodes of a first polarity and electrodes of a second polarity to the back of the solar cell. The electrodes can be applied, for example, by means of screen printing, vapor deposition, sputtering or electrodeposition of one or more metals or other conductive layers. The electrodes can, for example, comprise silver paste, silver / aluminum paste, aluminum paste or pure aluminum, copper, tin, palladium, silver, titanium, nickel or layer stacks or alloys of the aforementioned metals or other conductive layers, in particular conductive polymers or oxides, or a combination of such layers with metals. The composition and the deposition process of the electrodes can differ for the electrodes of the two polarities.

[0031] Preferably, the electrodes of the second polarity contact only the highly doped base regions and not the doped base regions.

[0032] This invention also relates to a solar cell and a method for producing a solar cell, in which the described polarities each comprise a polarity opposite to the described polarities. The solar cell then comprises, for example, a p-type doped base, a correspondingly n-type doped emitter and, in turn, a p-type base doping of the surfaces. Further features, possible applications and advantages of the invention emerge from the following description of exemplary embodiments of the invention, which are illustrated in the figures of the drawing. All of the described or illustrated features, individually or in any combination, form the subject matter of the invention, regardless of their summary in the patent claims or their reference back to them, and regardless of their wording or illustration in the description or in the drawing.

[0033] The drawing shows:

[0034] Fig. 1 is a schematic view of a section of a solar cell according to the invention, and

[0035] Fig. 2a to 2h show a solar cell according to Figure 1 in different steps of a method for producing the solar cell.

[0036] Figure 1 shows a section of a solar cell 10 with a semiconductor substrate 12, in particular a silicon wafer, a rear side 14, and a front side 16 facing the sun during operation of the solar cell. The silicon wafer 12 can be doped either n-type or p-type. The solar cell 10 is explained using an example of n-type doping of the silicon wafer 12, the "base." The front side 16 of the solar cell 10 is preferably textured. The back side 14 of the solar cell 10 can be polished or textured, in particular differently in different areas.

[0037] A polycrystalline, highly doped p-type silicon layer 20 is provided on the rear side 14. This layer forms a first polarity with a first dopant concentration on the rear side 14. In the region of the highly doped p-type silicon layer 20, a first passivation layer 18, in particular comprising silicon dioxide, passivates the surface of the silicon wafer 12. Furthermore, doped base regions 24 of a second polarity, opposite to the first polarity, are provided. The doped base regions 24 on the rear side 14 have the same polarity but a higher dopant concentration than the semiconductor substrate 12.

[0038] On the front side 16 is a doped region 28. The doped region 28 also has the same polarity but a higher dopant concentration than the semiconductor substrate 12. Highly doped base regions 30 are formed within the doped base regions 24 on the back side. The highly doped base regions also have the second polarity but a significantly higher dopant concentration than the semiconductor substrate 12, the doped base regions 24, and the doped region 28.

[0039] The solar cell 10 further comprises a second passivation layer 32 on the rear side 14 and a third passivation layer 34 on the front side 16. The passivation layer 32 at least partially covers the highly doped silicon layer 20, the doped base regions 24 and the highly doped base regions 30 in the regions not contacted by electrodes 36, 38. The second passivation layer 32, formed for example by a dielectric layer or layer stack, preferably has a greater thickness than the first passivation layer 18, preferably a thickness of more than 4 nm. The second passivation layer 32 can consist, for example, of silicon dioxide, silicon nitride or aluminum oxide, or of a layer stack of these layers.The thicknesses and refractive indices of the passivation layer 32 can be optimized such that as much electromagnetic radiation as possible that was not absorbed by the solar cell is reflected back into the solar cell at the rear. The third passivation layer 34 on the front side 16 preferably also has a greater thickness than the first passivation layer 18, preferably a thickness of more than 4 nm. The third passivation layer 34 can consist, for example, of silicon dioxide, silicon nitride or aluminum oxide, or of a layer stack of these layers. The thicknesses and refractive indices of the third passivation layer 34 can be optimized such that as much electromagnetic radiation incident on the front side 16 as possible is not reflected and is absorbed.

[0040] The solar cell 10 comprises on the back 14 electrodes 36 of a first polarity and electrodes 38 of a second polarity. The electrodes 36 of the first polarity contact the highly doped silicon layer 20 of the first

[0041] Polarity deposited on the first passivation layer 18. Advantageously, the electrodes 36 do not penetrate the first passivation layer 18. However, it may happen that the electrodes 36 partially penetrate the first passivation layer 18 and contact the semiconductor substrate 12. The electrodes 38 of the second polarity contact the semiconductor substrate 12 directly electrically and mechanically in the doped base regions 24, preferably only in the highly doped regions 30 of the doped base regions 24.

[0042] Regions not contacted by the electrodes 36, 38 can be covered and passivated either by the layer stack comprising the first passivation layer 18 and the highly doped silicon layer 20 of the first polarity, or by the second passivation layer 32 in the doped base regions 24 and the highly doped base regions 30. The second passivation layer 32 can also cover the highly doped silicon layer 20 in the non-contacted regions.

[0043] Preferably, the area electrically contacted by the electrodes 36 of the second polarity corresponds to the areas of the highly doped base regions 30 of the second polarity.

[0044] The manufacturing process of the solar cell 10 is explained below with reference to Figures 2a to 2h. Figures 2a to 2h illustrate the process flow for the production of a back-contacted solar cell 10 with a passivated contact in the region of the highly doped silicon layer 20 and a dif-founded contact in the region of the highly doped base regions 30. As a starting material, the semiconductor substrate 12 can be n- or p-type doped. The process flow is explained using an n-type doping of the wafer, the "base."

[0045] Figure 2a shows the initial shape of the silicon wafer 12 with a polished rear side 14 and a textured front side 16. According to a further initial shape (not shown), the front and rear sides can either both be polished or both textured. According to the illustrated embodiment, a first passivation layer 18, e.g. a silicon dioxide, with a thickness of preferably a maximum of approximately 4 nm is produced on the front side 16 and on the rear side 14, for example in a thermal or wet-chemical process or by deposition. Alternatively, according to a further embodiment (not shown), the deposition of the first passivation layer can only take place on the rear side 14.

[0046] In a next step (cf. Figure 2b), a highly doped silicon layer 20 of a first polarity, in particular a full-surface layer, is deposited on the tunnel layer 18 on the rear side 14. Furthermore, a p-type doping is assumed as the first polarity of the highly doped silicon layer. The highly doped p-type silicon layer 20 can be deposited, for example, by means of plasma-enhanced chemical vapor deposition (PECVD), atmospheric chemical vapor deposition (APCVD), low-pressure chemical vapor deposition (LPCVD), or cathode sputtering. The highly doped p-type silicon layer 20 has a thickness of approximately 50 nm to 400 nm. According to a further embodiment not shown, the highly doped silicon layer can also be deposited on both sides, on the front and rear sides.

[0047] The deposition of the highly doped p-type silicon layer 20 can be carried out in two steps instead of one. In this case, the deposition of the p-type silicon layer 20 comprises the deposition of undoped silicon and the subsequent introduction of a dopant. The dopant is introduced, for example, by means of furnace diffusion or laser diffusion from a doping source applied to the silicon layer or by means of ion implantation. The dopant is, for example, boron, aluminum, or gallium.

[0048] In a next step of the method (see Figure 2c), a dielectric layer 22 is deposited on the back side 14 of the highly doped silicon layer 20. The layer is deposited only on the back side 14. Parasitic deposition on the front side 16 cannot be completely ruled out. The dielectric layer 22 is deposited, for example, using PECVD, APCVD, LPCVD, or PVD. The dielectric layer 22 has a greater thickness than the first passivation layer 18 and is thus thicker than 4 nm.

[0049] Figure 2d shows a further method step, the exposure of base regions 24 of the semiconductor substrate 12 on the rear side 14 by locally removing the dielectric layer 22, the highly doped silicon layer 20 of the first polarity and the first passivation layer 18. The removal of the passivation layer 18 on the front side 16 is also shown. In a further embodiment not shown, removal of a silicon layer on the front side 16 may also be necessary. The exposure of the base regions 24 takes place, for example, by locally removing the dielectric layer 22 by laser irradiation. It is also conceivable that the second dielectric layer 22 is not completely removed. The highly doped silicon layer 20, the first passivation layer 18 and optionally a part of the semiconductor substrate 12 can also be at least partially removed locally by laser irradiation.

[0050] Alternatively, the highly doped silicon layer 20 and / or the first passivation layer 18 can be partially etched locally using a wet-chemical solution. The dielectric layer 22 has advantageously been selected such that the wet-chemical solution does not etch the dielectric layer 22, or does so much more slowly than the highly doped silicon layer 20 and the first passivation layer 18. Depending on which layers have already been removed previously by laser irradiation, the wet-chemical solution may also etch any remaining remnants of the dielectric layer 22, the first passivation layer 18 on the front side 16, and possibly a portion of the semiconductor substrate on the front side 16 and back side 14. Alternatively, the first passivation layer 18 can also serve as an etch barrier, so that the first passivation layer and the semiconductor substrate 12 are not etched.If the highly doped silicon layer is also located on the front side 16, this is also etched in a further embodiment not shown. It can be provided that the etching comprises an isotropic etching for polishing regions and / or that the etching comprises an anisotropic etching for texturing regions. For example, the base regions 24 can be polished on the back side 14 by isotropic etching with a wet-chemical solution. Alternatively, the base regions 24 can be textured on the back side 14 by anisotropic etching with a wet-chemical solution. It can also be advantageous if the front side 16 is textured by anisotropic etching with a wet-chemical solution. Different wet-chemical solutions can be used for removing and, if necessary, texturing and / or polishing the different layers and surfaces.

[0051] Figure 2e shows the deposition of a precursor layer 26 on the entire rear side 14 and the entire front side 16 of the solar cell 10. The deposition on the front side 16 and back side 14 takes place, for example, simultaneously. The precursor layers 26 on the front side 16 and back side 14 can have different properties, for example with regard to the thickness or an amount of dopant contained in the precursor layer 26. On the rear side, the precursor layer 26 can be deposited differently on the different surfaces, the dielectric layer 22 or the exposed base region 24, and thus have different properties. The precursor layer 26 is a layer comprising a dopant of a second polarity, in particular a phosphosilicate glass layer, PSG.To apply the precursor layer 26, for example, a furnace diffusion process can be used, in which a phosphosilicate glass layer grows on the highly doped silicon layer 20 on the back side 14 and on the front side 16. The furnace diffusion process can be carried out in such a way that, after the furnace diffusion process, the phosphosilicate glass layer contains a high proportion of phosphorus. Alternatively, the precursor layer 26, for example, PSG, can be deposited using PECVD, LPCVD, or APCVD.

[0052] In a high-temperature step in which the dopant from the precursor layer 26 is dipped into the base regions 24 on the back side 14 and / or into the surface of the front side 16, the doping in the base regions 24 on the back side 14 is increased and a doped region 28 is created on the front side 16. The dopant dopes the base regions 24 on the back side 14 according to a second polarity, opposite to the first polarity of the highly doped silicon layer 20, so that doped base regions 24 are created. The doped base regions 24 on the back side 14 comprise a higher dopant concentration than the dopant concentration of the semiconductor substrate 12. On the back side 14, the dopant from the precursor layer 26 does not penetrate, or only in small quantities, into the highly doped silicon layer 20, since the dielectric layer 22 serves as a diffusion barrier against the dopant from the precursor layer 26.On the front side 16, the doped region 28 is created on the front side 16 by doping the surface according to the second polarity. The dopant concentration of the doped region 28 on the front side 16 is higher than the dopant concentration of the semiconductor substrate 12. The high-temperature step is, for example, the furnace diffusion step for applying the precursor layer 26. Alternatively, it can also be an additional high-temperature step.

[0053] The high-temperature step can, for example, be carried out in such a way that only a portion of the second dopant from the precursor layer diffuses into the base regions on the back side, so that a significant amount of dopant is preferably still present in the precursor layer 26. The high-temperature step can also serve to activate the dopant in the highly doped layer 20.

[0054] Figure 2f shows the creation of highly doped base regions 30 in the doped base regions 24 by locally increasing the dopant concentration, in particular by laser irradiation. The laser irradiation melts or evaporates the previously deposited precursor layer 26 and the surface on the back side is locally heated and melted in the irradiated regions. Further dopant from the precursor layer diffuses into the surface at the irradiated regions and, after cooling and recrystallization, further dopes the irradiated region according to the second polarity, so that the highly doped base regions 30 are created. The dopant concentration in the highly doped base regions 30 is significantly higher than the dopant concentration of the semiconductor substrate 12, the doped base regions 24 and the doped region 28 on the front side 16.By appropriately selecting the laser parameters, differently highly doped sections can also be locally selectively created in the highly doped base regions 30. Furthermore, it is provided that, in particular, remaining residues of the precursor layer 26 are removed from the front side 16 and the back side 14. Removal takes place after laser irradiation, for example, in a wet-chemical cleaning step. Advantageously, the wet-chemical cleaning step or a further post-chemical cleaning step also removes remaining residues of the dielectric layer 22 from the highly doped silicon layer 20.

[0055] The method further comprises a step of applying a second passivation layer 32 on the rear side 14 and a third passivation layer 34 on the front side 16, see Figure 2g. The passivation layers 32, 34 comprise, for example, silicon dioxide, silicon nitride, aluminum oxide or a layer stack of two or more dielectric layers. The thickness, refractive index and composition of the second passivation layer 32 on the rear side 14 can differ from the thickness, refractive index and composition of the third passivation layer 34 on the front side 16. The thicknesses of the passivation layers 32, 34 are advantageously optimized such that the reflection is reduced on the front side 16 and increased on the rear side 14. The passivation layers 32, 34 advantageously have a greater thickness than the first passivation layer 18. The thickness of the second passivation layer 32 is advantageously greater than 4 nm.The high temperature step for growing the thermal silicon dioxide, the passivation layers 32, 34 can also serve to activate the dopant in the highly doped layer 20.

[0056] The method further comprises a step of applying electrodes 36 of a first polarity and electrodes 38 of a second polarity to the back side 14 of the solar cell 10, see Figure 2h. The application of the electrodes 36, 38 can be carried out, for example, by means of screen printing, vapor deposition, sputtering or electrodeposition of one or more metals or other conductive layers. The electrodes 36, 38 can, for example, comprise silver paste, silver / aluminum paste, aluminum paste or pure aluminum, copper, tin, palladium, silver, titanium, nickel or layer stacks or alloys of the aforementioned metals or other conductive layers, in particular conductive polymers or oxides, or a combination of such layers with metals. The composition and the deposition process of the electrodes 36, 38 can differ for the electrodes 36, 38 of the two polarities.The electrodes 36, 38 can, particularly in a high-temperature step after screen printing, locally penetrate the passivation layer 32 and, depending on the polarity of the electrodes 36, 38, contact either a doped base region 24, the highly doped silicon layer 20, or a highly doped base region 30. Preferably, the electrodes 38 of the second polarity contact only the highly doped base regions 30 and not the doped base regions 24. Optionally, before the electrodes 36, 38 are applied, the passivation layer 32 can be selectively removed, for example by laser irradiation, so that the electrodes directly contact the highly doped silicon layer 20 or the locally highly doped base regions 30 exclusively in the selectively removed regions.

Claims

Claims: Back-contacted solar cell (10) comprising a semiconductor substrate (12), in particular a silicon wafer, comprising a front (16) and a back (14), wherein the solar cell (10) comprises electrodes (36) of a first polarity and electrodes (38) of a second polarity on the back, characterized in that the electrodes (36) of the first polarity are arranged on a highly doped silicon layer (20) of the first polarity, wherein the highly doped silicon layer (20) is arranged on a first passivation layer (18) arranged on the semiconductor substrate, and the electrodes (38) of the second polarity directly electrically and mechanically contact the semiconductor substrate (12) via highly doped base regions (30) of the second polarity of the semiconductor substrate (12).Back-contacted solar cell (10) according to claim 1, characterized in that the highly doped base regions (30) of the second polarity are formed within the doped base regions (24) of the second polarity on the back (14) of the solar cell (10), wherein a dopant concentration in the highly doped base regions (30) is higher than a dopant concentration in the doped base regions (24), and wherein the dopant concentration in the highly doped. Base areas (30) is higher than a dopant concentration of a doped area (28) on the front (16) of the solar cell (10). Back-contacted solar cell (10) according to one of claims 1 or 2, characterized in that a second passivation layer (32) is arranged on surface areas of the back (14) that are not contacted by the electrodes (36) of the first polarity and not by the electrodes (38) of the second polarity, wherein the second passivation layer is thicker than the first passivation layer. Method for producing a back-contacted solar cell according to at least one of claims 1 to 2. 3, wherein a semiconductor substrate (12) of the solar cell (10) comprises a, in particular polished or textured, back surface (14) and a, in particular textured, front surface (16), characterized in that a first passivation layer (18), in particular comprising silicon dioxide, is applied to a surface of the front surface (16) and / or to a surface of the back surface (14). The method according to claim 3, characterized in that the method comprises a step for depositing a, in particular full-surface, highly doped silicon layer (20) of a first polarity on the first passivation layer (18) on the back surface (14). A method according to claim 4 or 5, characterized in that a dielectric layer (22) is applied to the back side (14). A method according to any one of claims 4 to 6, characterized in that base regions (24) of the semiconductor substrate on the back side (14) are exposed by locally removing the dielectric layer (22), the highly doped silicon layer (20) of the first polarity, and the first passivation layer (18) on the back side (14). A method according to claim 7, characterized in that a portion of the semiconductor substrate (12) is locally removed in the base regions (24). A method according to claim 7 or 8, characterized in that exposing the base regions (24) of the semiconductor substrate on the back side comprises locally etching the highly doped silicon layer (20) of the first polarity and / or the first passivation layer (18) and / or a portion of the semiconductor substrate in the base regions (24).A method according to claim 9, characterized in that the etching comprises isotropic etching for polishing areas and / or anisotropic etching for texturing areas. A method according to any one of claims 4 to 10, characterized in that the method comprises a step for applying a precursor layer (26) comprising a. A dopant, in particular phosphorus, on the back (14), or on the back (14) and on the front (16). A method according to claim 11, characterized in that, by a high-temperature step in which the dopant diffuses from the precursor layer (26) into the base regions (24) on the back (14) and / or into the surface of the front (16), the doping in the base regions (24) on the back is increased and / or a doped region (28) on the front (16) is generated. A method according to any one of claims 4 to 12, characterized in that a highly doped base region (30) is generated within the doped base regions (24) on the back (14) by locally increasing the dopant concentration, in particular by laser irradiation. A method according to at least one of claims 11 to 12. 13, characterized in that the method comprises a step for removing the precursor layer (26), in particular phosphosilicate glass, from the front (16) and / or from the back (14). Method according to at least one of claims 4 to 14, characterized in that the method includes a step for applying a second passivation layer (32) to the back side (14) and / or a third The passivation layer (34) on the front side (16) comprises a method according to claim 15, characterized in that the method includes a step for selectively removing the second passivation layer (32) on the Rear side (14) comprises. Method according to at least one of claims 4 to 16, characterized in that the method comprises a step for applying electrodes (36) of a first polarity and electrodes (38) of a second polarity. Polarity on the back (14) of the solar cell (10) includes .