An electrowetting optical tile, device and method of manufacturing such

Abstract

An electrowetting optical tile, comprising: a plurality of pixels, each pixel comprising a thin-film transistor (TFT) having a gate, source, and drain, the gate being connected to a gate line and the source being connected to a source line, wherein the drain serves as a pixel electrode (Vpixel), the pixel being configured to charge to a desired voltage level between the drain and a common line when the gate is driven and the voltage on the source line is transferred to the drain; a driving unit configured to: drive the pixels in an alternating current (AC) mode, by alternating the common line voltage between a positive and negative voltage, defining a common line voltage swing; drive the gate line for charging the pixels; wherein the driving unit is further configured to: set all pixel voltages to the common line voltage just before the common line voltage reverses, thereby preventing the voltage potential over the pixel from exceeding the voltage of the common line voltage swing, restore the pixel voltages to the original values immediately after the common line voltage reversal. (fig. 11)

Description

Title: An electrowetting optical tile, device and method of manufacturing such Description: TECHNICAL FIELD The present invention relates to electrowetting displays, specifically to a method for driving thin-film transistors (TFTs) in such displays. BACKGROUND Electrowetting technology operates by modulating the effective wetting behavior of a hydrophobic surface of an insulating layer for a non-polar liquid in relation to a polar liquid. This modulation is achieved through the alteration of the applied electric field strength across the insulating layer. The insulating layer, polar liquid, and non-polar liquid form part of a capacitor assembly that also includes electrodes across which a voltage is applied to generate an electric field. An electrowetting tile, which may also be referred to as an electrowetting optical tile, typically consists of multiple layers. From bottom to top (in reverse viewing direction), these layers include a first electrode layer stack comprising a substrate, a first electrode, and an electrically insulating layer on top of the first electrode. Above this is a second electrode layer stack, which includes a superstrate and a second electrode. Between these two stacks, a containment space is formed, housing a polar liquid and a non-polar liquid, both immiscible with each other and contained within individual cells defined by cell walls. Each cell, or group of cells, forms a pixel in the optical display, where a pixel is the smallest addressable element. Pixels may consist of one or multiple electrowetting cells and borders of pixels may also cross electrowetting cells. The containment space is functionally defined and not restricted to specific physical configurations. The polar and non-polar liquids may either be fully encapsulated or allowed to migrate between cells, depending on the configuration of the cell walls. This flexibility in liquid containment enables greater versatility in electrowetting display applications. Electrowetting displays are composed of numerous pixels, with each pixel comprising either a single cell, part of a cell, or, more commonly, a group of cells. For example, a pixel might be formed from around 400 cells, yielding a pixel size of approximately 1 cm by 1 cm. These tiles, when combined in an array, form a display capable of rendering arbitrary images by independently controlling the electrowetting pixels. The fundamental principle of operation involves the manipulation of liquids within the electrowetting cells via an applied voltage. In the unpowered state, the non-polar liquid (typically an oily liquid) forms a boundary between the polar liquid (e.g., water-based) and the hydrophobic surface of the insulating layer, obstructing light transmission. Upon the application of a sufficient voltage across the electrodes, electrostatic forces cause the polar liquid to displace the non-polar liquid, allowing the polar liquid to contact the hydrophobic layer. This transition from opaque to transmissive states forms the basis for pixel control in electrowetting displays. Electrowetting displays offer significant advantages in applications such as outdoor digital signage, including traffic signs, message centres, and billboards. Conventional electrowetting displays require each pixel to be addressed individually through separate electrical contact tracks, a design which introduces complexity and limits scalability. In the current state of the art, electrowetting displays utilize thin-film transistors (TFTs) to drive pixels or cells, with each pixel connected to a driving chip and driven by a block-shaped alternating current (AC) signal of +15V and -15V. The voltage alternates for example every 10 milliseconds, and all pixels switch in sync with the superstrate of the EWD, resulting in the ON pixel being at -15V when the superstrate is at +15V, and vice versa, due to the AC operation mode of the EWD, which AC operation mode is preferred in order to avoid undesirable charging effects that arise from single-polarity driving. Moreover, EWDs are constrained to the voltage range typical for electrophoretic displays, limited to i30V, as exceeding this range raises concerns of damage of transistors from excessive voltage, which has been a point of concern for TFT manufacturers. Traditional gate line activation methods involve sequentially activating each row's gate line during for example a 10ms frame, with 144 lines activated in 69us intervals. This setup introduces the risk of short-duration voltage spikes of up to +60V when the pixel voltage of 30V coincides with the common voltage switch to 30V, potentially damaging the display. The object of the present invention is to provide for an improved electrowetting display with TFT technology whereinAC driving is maintained, while the driving is kept within the acceptable i30V range and voltage surges that can damage the EWD are prevented. SUMMARY One aspect of the present invention relates to an electrowetting optical tile. The electrowetting optical tile, comprising: a plurality of pixels, each pixel comprising a thin-film transistor (TFT) having a gate, source, and drain, the gate being connected to a gate line and the source being connected to a source line, wherein the drain serves as a pixel electrode (Vpixel), the pixel being configured to charge to a desired voltage level between the drain and a common line when the gate is driven and the voltage on the source line is transferred to the drain; a driving unit configured to: drive the pixels in an alternating current (AC) mode, by alternating the common line voltage between a positive and negative voltage, defining a common line voltage swing; drive the gate line for charging the pixels; wherein the driving unit is further configured to: set all pixel voltages to the common line voltage just before the common line voltage reverses, thereby preventing the voltage potential over the pixel from exceeding the voltage of the common line voltage swing, restore the pixel voltages to the original values immediately after the common line voltage reversal. Another aspect of the present invention relates to a method of manufacturing an electrowetting optical tile. The method comprising the steps of: forming a plurality of pixels, each pixel comprising a thin-film transistor (TFT) having a gate, a source, and a drain, wherein the gate is connected to a gate line and the source is connected to a source line, and the drain serves as a pixel electrode (Vpixel), the pixel being configured to charge to a desired voltage level between the drain and a common line when the gate is driven and the voltage on the source line is transferred to the drain; controlling a driving unit to drive the plurality of pixels in an alternating current (AC) mode, wherein the common line voltage alternates between a positive and negative voltage, defining a common line voltage swing; controlling the driving unit to drive the gate line for charging the pixels; further configuring the driving unit to controlling a driving unit to set all pixel voltages to the common line voltage just before the common line voltage reverses, thereby preventing the voltage potential across the pixels from exceeding the common line voltage swing; and controlling a driving unit to restore the pixel voltages to their original values immediately after the common line voltage reversal. Another aspect of the present invention relates to a method of driving a thin-film transistor (TFT) in an electrowetting optical tile. The method comprising the steps of: applying a voltage to a gate line connected to the gate of the TFT, wherein the source of the TFT is connected to a source line and the drain serves as a pixel electrode (Vpixel); driving the pixel in an alternating current (AC) mode, wherein a driving unit alternates the common line voltage between a positive and negative voltage, defining a common line voltage swing; charging the pixel to a desired voltage level between the drain and the common line when the gate is driven and the voltage on the source line is transferred to the drain; detecting an impending reversal of the common line voltage from negative to positive, and setting the pixel voltages to the common line voltage just before the common line voltage reverses; restoring the pixel voltages to their original values immediately after the common line voltage reversal. An electrowetting optical tile may be understood as a display component that utilizes the electrowetting effect to control the behavior of liquids for optical purposes, typically forming part of a larger display system. The electrowetting optical tile comprises a plurality of pixels, each pixel including a thin-film transistor (TFT) with a gate, source, and drain. A thin-film transistor is a special kind of field-effect transistor made by depositing thin films of an active semiconductor layer as well as the dielectric layer and metallic contacts over a supporting substrate. In this arrangement, the gate is connected to a gate line, which controls the on / off state of the transistor, while the source is connected to a source line, which provides the input signal. The drain serves as the pixel electrode (Vpixel), effectively controlling the state of the pixel. This configuration allows the pixel to charge to a desired voltage level between the drain and a common line when the gate is driven and the voltage on the source line is transferred to the drain. An effect of this arrangement is precise control over individual pixels, enabling high-resolution display capabilities while minimizing crosstalk between adjacent pixels. The electrowetting optical tile further includes a driving unit configured to drive the pixels in an alternating current (AC) mode. This is achieved by alternating the common line voltage between a positive and negative voltage, defining a common line voltage swing. AC driving in electrowetting displays helps prevent charge accumulation and improves the long-term stability of the display. The driving unit is also configured to drive the gate line for charging the pixels. This arrangement allows for dynamic control of the display, enabling rapid updates and smooth transitions between different display states. The driving unit is further configured to set all pixel voltages to the common line voltage just before the common line voltage reverses. This action prevents the voltage potential over the pixel from exceeding the voltage of the common line voltage swing. An effect of this arrangement is the prevention of voltage spikes that could potentially damage the display components or lead to undesired visual artifacts. By proactively adjusting the pixel voltages in anticipation of the common line voltage reversal, the system maintains stable operation within safe voltage limits. lmmediately after the common line voltage reversal, the driving unit restores the pixel voltages to their original values. This rapid restoration ensures that the display maintains its intended visual state without interruption. An effect of this arrangement is the preservation of image quality and continuity, even during the voltage reversal process. By controlling the pixel voltages during common line voltage transitions and introducing a blanking pulse, stable AC operation is maintained while staying within safe voltage limits, thereby extending the lifespan of the display components and improving overall display performance. ln an example, the electrowetting optical tile is configured such that the driving unit generates a blanking pulse by briefly setting the pixel voltage to the common line voltage just before the reversal of the common line voltage. lt may be provided that the blanking pulse temporarily aligns the pixel voltage with the common line voltage, ensuring that no excessive potential difference exists across the pixel during the voltage transition. Herewith voltage spikes are prevented that could damage the transistors of the TFT. By introducing a brief blanking pulse, the system ensures a smoother transition, preventing damage of transistors from excessive voltage and thereby minimizing wear of the display. ln an example, the timing of the blanking pulse is synchronized with the reversal of the common line voltage, such that the blanking pulse occurs immediately prior to the voltage reversal. ltmay be provided that the synchronization ofthe blanking pulse with the common line voltage reversal ensures that the pulse is applied at the exact moment needed to prevent any overvoltage across the pixels. ln an example, the duration of the blanking pulse is defined as a ratio of the common line AC frequency, wherein the duration of the blanking pulse is proportional to the half-period oftheAC signal. lt may be provided that this proportional relationship between the blanking pulse duration and theAC signals half-period allows the system to adapt to different operating frequencies. An effect of this feature is improved flexibility in display operation, as the timing of the blanking pulse can be adjusted and tuned to maintain optimal performance across varying AC frequencies. This ensures minimal impact of the blank pulse while preventing damage to the transistors. ln an example, the duration of the blanking pulse is defined based on the ink response time in the electrowetting display. lt may be provided that the response time of the ink, which refers to the time it takes for the ink to react to electrical stimuli, is used to optimize the blanking pulse. When the cell is electrically turned on or off, it will take some time for the ink to actually respond, which time window can be used for the blanking pulse, e.g. the timing of the blanking pulse may be synchronized the ink response time, ensuring smooth transitions between opaque and transparent states without visual artifacts caused by the blanking pulse. This precise adjustment leads to better display quality, especially in fast-changing image environments. ln an example, the duration of the blanking pulse is defined based on the transmission signal half-life of the ink, such that the duration of the blanking pulse is optimized to correspond with the transmission signal half-life. lt may be provided that the half-life of the transmission signal, which indicates the time for the signal to decay to half of its initial value, determines or defines the pulse duration. An effect thereof is an enhanced synchronization between the electrical driving and the optical behavior of the display, reducing any visible lag or distortion or visual artefacts from the blanking pulse. ln an example, the pixel voltages are set to the common line voltage during the blanking pulse by fast scanning all rows of the pixels, ensuring that the pixel voltages are synchronized with the common line voltage reversal. lt may be provided that a rapid scanning of all pixel rows ensures uniform voltage adjustments across the entire display. An effect of this feature is the prevention of inconsistencies or image artifacts caused by unsynchronized voltage changes in different parts of the display. This scanning process enables faster and more efficient operation, particularly in large, high-resolution displays. ln an example, each pixel comprises a common gate structure including a transistor configured to set the pixel voltage to the common voltage just before the reversal of the common line voltage. lt may be provided that the common gate structure allows multiple pixels to be controlled simultaneously, simplifying the circuit design and ensuring that all pixel voltages are correctly set before the voltage reversal. An effect of this feature is the improved synchronization of pixel control across the display, reducing complexity while maintaining precise voltage management. This arrangement also supports higher scalability and more efficient power usage. ln an example, the thin-film transistors (TFTs) driving the pixels are fast- switching transistors, preferably indium gallium zinc oxide (IGZO) transistors, configured to support rapid voltage adjustments during the blanking pulse. lt may be provided that IGZO transistors, known for their high mobility and fast switching characteristics, enable the display to handle rapid voltage changes effectively. An effect of this feature is improved response times and higher display refresh rates, contributing to smoother and more responsive visual outputs, particularly in applications requiring fast image transitions. Such fast switching TFTs, allows of short blanking pulses. ln an example, the thin-film transistors (TFTs) driving the pixels are fast- switching transistors selected from materials such as zinc oxide (ZnO), Nano- crystalline ZnO, lndium Tin Zinc Oxide (lTZO), lndium Oxide (ln203), Amorphous IGZO, or organic thin-film transistors (OTFTs), configured to minimize delay in voltage switching. lt may be provided that these materials are selected for their favorable electronic properties, of high conductivity and fast switching capabilities. An effect of this feature is reduced latency in pixel control, ensuring that the display operates with minimal delay, allowing short blanking pulses. ln an example, the driving unit is configured to dynamically adjust the duration and timing of the blanking pulse based on real-time monitoring of the transmission signal half-life. lt may be provided that real-time monitoring allows the system to adjust the blanking pulse to match the changing characteristics ofthe display environment, such as temperature or voltage fluctuations. An effect of this feature is that the system continuously optimizes its performance, maintaining high image quality and operational stability under varying conditions. This dynamic adjustment capability enhances the robustness and adaptability of the display system. Each of the examples and aspects described in relation to any aspect of the invention is also applicable in relation to other aspects of the invention. Correspondingly, all advantages of any aspect and further examples thereof also apply to other aspects and its examples. The invention will further be described with reference to the enclosed drawings wherein embodiments of the invention are illustrated, and wherein: Fig. 1 shows in an illustrative manner, an electrowetting optical element; Fig. 2 shows an electrowetting optical display comprising an array of electrowetting optical tiles; Fig. 3, 4 and 5 show timing diagrams of the Vcommon and Vpixel; Fig. 6 shows the TFT and gate, source and common lines of electrowetting optical tile; Fig. 7 and 8 show the voltage to exceed the 30V limit upon reversal of the Vcommon; Fig. 9 shows an electrical circuit layout of a pixel of an electrowetting optical tile; Fig. 10 shows the blanking time pulse of the Vpixel, in accordance with an aspect of the present disclosure; Fig. 11a shows the ink response by oil transmission in relation to the voltage reversal in the situation wherein there is no blanking, and; Fig. 11b shows the ink response by the oil transmission in relation the voltage reversal upon implementation of the blanking pulse in accordance with an aspect of the present disclosure; Fig. 12 shows an electrical circuit layout of a pixel of an electrowetting optical tile with a common gate structure in accordance with an aspect of the present disclosure. Fig. 1 shows an electrowetting optical element or further also referred to as electrowetting element, according to the state of the art. The element consists of two electrode layer stacks 110, 120, one at the bottom 120 and one at the top 110. The stack at the bottom 120 is referred to as the first electrode layer stack 120, and consists of respectively a substrate 121, a first electrode layer 122, an electrically insulating hydrophobic layer 123 or an insulating layer 123 having a hydrophobic surface 124. The hydrophobic surface 124 interfaces with at least a non-polar liquid 141 capable of displacing a polar liquid 142 from the hydrophobic surface 124 through its preferential wetting of the hydrophobic surface 124. These liquids 141, 142 are immiscible with each other and contained in a containment space 140. The containment space 140 defines one cell and is formed by the first stack at the bottom 120, the second stack at the top 110, and a set of cell walls 130 which are disposed in parallel at a certain distance from each other. The first electrode layer 122 and the second electrode layer 112 are arranged to apply a voltage across one single cell 140 or across multiple cells at the same time. As shown in Fig. 1, the configuration is arranged, e.g., the first and second electrode layers 122, 112 are continues across multiple cells or containment spaces 140, to thereby set a voltage across multiple cells at the same time. In this way, multiple cells together may form one single pixel element which is independently addressable. In order to define the cells and to keep the liquids inside their cells in the containment space, the element contains cell walls 130. The cell walls may be fixedly mounted At one end, e.g. at the second electrode layer stack 111, or to the first electrode layer stack 121. lf attached to the second electrode layer stack 111, the opposite end of the cell walls may or may not be fixedly mounted at that end to the other, e.g. first interface surface 124 of the first electrode layer stack 120, or may have a free and thus non-fixed end. This free end may comprise a hydrophobic top. The non-polar liquid 141 is attracted to both the hydrophobic end face surface of the cell wall and to the hydrophobic first interface surface in both the non-powered and the powered-up state of the electrowetting cell. As indicated, the cell walls may however also be configured in an alternative, opposite manner, wherein the cells walls 130 are fixedly attached to the first electrode layer stack 120. It is expressed that the definition of containment space 140 is to be interpreted in a functional and non-limiting manner. This means that the polar 142 or non-polar liquid 141 may flow freely or partly from one part of the containment space to another part of the containment space, depending on the type of configuration of the electrowetting optical element 100. To allow or promote such migration, the cell walls 130 disposed between the first 120 and second 110 electrode layer stack do not fully encapsulate the polar 142 and non-polar141 liquid within the containment space 140 but allow a full or a restricted migration of liquids from one cell 140 to neighbouring cells 140 and thus from one part of the containment space to neighbouring parts of the containment space. The definition of containment space is thus used as a known definition but not limited to examples which prevent any migration of liquid between adjacent containment spaces. In the example shown in Fig. 1, the top of the cell walls 130 demonstrate a small slit with the first electrode layer stack 120. Since the top of the cell wall are preferably hydrophobic, it enables the non-polar liquid 141 to be entrained more easily into the slit between the end face of the cell wall 130 and the first stack 120. As such, the polar liquid 141 is trapped inside the containment space and is prevented from spreading from one cell 140 to another 141. ln Fig. 2 an array of electrowetting tiles is shown, in this example, an array of 2x2 tiles. Each tile is comprised of the components of the electrowetting element as shown in Fig. 1. Moreover, each tile also comprises additional elements such as one or several drivers for switching the pixels. An electrowetting optical display is thus typically comprised of a plurality of electrowetting optical tiles 210, 220, 230, 240, which are arranged in either a one dimensional array, but preferably in a two dimensional array as shown in Fig. 2. For a monochrome type of display a single electrowetting optical element configuration would be sufficient, but typically, electrowetting displays comprise a stack of three, such tiles 210 above each other. Each tile or layer comprises a different dye colouring, e.g. respectively a cyan, magenta and yellow dye, as in conventional printing technology. Each layer can be controlled individually, such that for a particular pixel the cyan, magenta and yellow non-polar liquids may be controlled individually to switch between absorbing and non-absorbing state and to thus generate the desired colour. Each electrowetting display thus comprises several electrowetting tiles 210-240, each comprising the element 100 and additional components such as one or several drivers 215 to drive the individual pixels. Each element consists of many cells, which may have a square shape, but may also have other shapes such as hexagons. Preferably, a certain number of adjacent cells are controlled simultaneously to operate as one single pixel of the tile. The pixel pitch may be small for example less than 20 mm, or preferably less than 10 mm, or even more preferably less than 5 mm or even 2.5 mm or less. The pixels and thereby single or preferably multiple cells are be controlled through a Thin Film Transistor layer. The TFT layer may be comprised in the first electrode layer 122 and is preferably provided as a TFT array having a single transistor for each pixel. The transistor is arranged to apply a voltage over or across the electrode layers of the first and second electrode layer stack 120, 110, thereby rearranging the polar liquid relative to the non-polar liquid. ln Fig. 3 a shows the timing of the Vcommon signal 310 of the superstrate of the electrowetting optical tile in a so called direct drive configuration. The superstrate may be driven by a driver chip or the like, which supplies a block- shaped alternating current (AC) signal 310 of +15V and -15V, as shown in Fig. 3. The voltage may alternate, as shown, for example shown in Fig. 3, every 10 milliseconds, and all pixels switch in sync with the superstrate of the EWD, resulting in the ON pixel being at +15V and OFF at -15V. As can be seen, the voltage is provided in AC, or bi- polarity, which is preferred in order to avoid undesirable charging effects that arise from single-polarity. ln Fig. 4, is shown in more detail that the voltage of the Vcommon has a range of approximately 30V. TheVcommon 410 and the Vpixel 420 may be kept within range of this 30V when both are synchronized accurately, i.e. when they are complete complementary signals or inverted signals, which are in antiphase, as demonstrated in Fig. 4. In such way, the voltage range between the Vcommon 410 and Vpixel 420 are kept within the desirable range of 30V. Fig. 5 shows the state of the pixel when it is in OFF mode, with the Vcommon 410 and Vpixel 520 in sync. Fig. 6 shows a TFT layout of an electrowetting optical tile 600, wherein for each pixel the TFT occupies a certain transistor area 660. The horizontal lines are the gate lines 651, and these meet at the side of the tile 600 and are fed downwards from there to the driver chip (not shown, but shown in Fig. 2, with reference 215). These vertical line sections between the horizontal gate lines and the connection at the edge of the tile to the driver chip are disposed in an inactive part of the tile. The vertical lines connecting with each pixel, are the source lines 652. To prevent these lines from shorting out to the gate lines, each pixel transistor area 660 is provided with a gate insulator 670. Fig. 7 shows that without the driving unit to set the pixel voltages to the common line voltage, a voltage differential of +45V may be achieved at the time of the common line voltage reversal. This high voltage is undesirable for reasons given above. With the system and method according to the present disclosure, this is however prevented as will be described in more detail in respect of the further figures. ln Fig. 8 it is shown that the Vpixel changes to -15V when the row is selected. And from that time on, the voltage differential between the Vcommon 810 and the Vpixel 820, remains below or at the desirable range of 30V. This however demonstrates that during the Vcommon reversal and the row selection, the voltage level over the transistors of the TFT exceed the 30V range, which should be prevented and is prevented by the system and method of the present disclosure. ln Fig. 9 a circuit layout 900 is shown of a TFT pixel with the transistor having the gate connected to a gate line, the source connected to the source line, which is set at -15V at this example, and the drain connected to the capacitance of the electrowetting cell and the storage capacitor Cst. As can be seen, the voltage over the electrowetting cell may be 30V but as a result thereof, the voltage potential over the transistor is approximately 60V, i.e. since the source line is at -15 and the drain of the transistor has a voltage potential over 45V (being the total of the 30V over the capacitance of the cell added to the +15V at the common). ln Fig. 10 the timing diagram of the electrowetting optical tile according to an aspect of the present disclosure is shown, wherein just before the common line voltage reversal, all pixels voltages, i.e. Vpixel 420, 520, 720, 820, 1020, are set to the common line voltage just before the common line voltage reverses, thereby preventing the voltage potential over the pixel from exceeding the voltage of the common line voltage swing. Just after this common line voltage reversal, the pixel voltages Vpixel 420, 520, 720, 820, 1020, are restored to their original values. Hence, just before and just after this common line voltage reversal the driver unit is configured to effect a change of the Vpixel by generating a blanking pulse which is illustrated in Fig. 11 with the dashed line 1280. The blanking pulse thus briefly or for a short period of time sets the pixel voltage to the common line voltage just before the reversal of the common line voltage. ln other words, the directly before the reversal, the Vpixel is set equal to the common line voltage, and directly after the reversal, the Vpixel is restored to its original state. It is noted that the transmission signal curve shown in Fig. 11a represents the scenario where no blanking pulse is applied (i.e., blanking time dt = 0). The dips in the transmission signal are a result of the voltage reversal. Fig. 11b represents a scenario wherein the blanking pulse is applied (i.e. dt > 0, and in this particular scenario a blanking pulse of 0.5ms 1285). The dip in the transmission signal 1285 shown in Fig. 11b thus is slightly deeper due to the temporary alignment of the pixel voltage with the common line voltage. This brief synchronization, facilitated by the blanking pulse, minimizes the voltage differential during the reversal and thereby protects the transistors, but it may also cause a marginal increase in the depth of the transmission signal dips as illustrated in Fig. 11b. This implementation of the blanking pulse in the electrowetting optical tile prevents the voltage potential over the pixel from exceeding the voltage of the common line voltage swing. An effect of this arrangement is the prevention of voltage spikes that could potentially damage the display components or lead to undesired visual artifacts. By proactively adjusting the pixel voltages in anticipation of the common line voltage reversal, the system maintains stable operation within safe voltage limits. With the blanking pulse, each EW capacitance is mostly or completely discharged with a small fraction of time, so for example within 1ms all 144 gate lines are activated.. The use of this blanking pulse is facilitated by the relatively slow response time of the oil within the electrowetting cells. Since the oil's reaction time defines the transmission time of the display, which is not instantaneous, the brief blanking pulse can be applied with minimal impact on the display's optical performance. This delay in the oil's movement means that the display does not immediately register changes in voltage states, allowing the system to momentarily set all pixel voltages to the common line voltage without disrupting the overall visual output. Thus, the blanking pulse serves as a protective measure, reducing potential damage to the TFTs while maintaining the integrity of the display's operational principles. lts timing and duration may be chosen based on the known transmission characteristics of the oil, ensuring a seamless transition between voltage states with limited impact on the display's functioning. The blanking time, being the time duration of the blanking pulse may be very short, for example as small as 0.1ms, 0.3ms, 0.5ms, 1ms or 2ms. ln particular, the blanking pulse preferably has a duration of approximately 0.5ms, which might be considered an optimum between sufficient time for performing the pulse, being able to implement such pulse with available components capable of providing such fast switching, and having minimum impact on the transmission characteristics of the oil and thus the overall optical performance of the display. In blanking pulse may be implemented in several manners, for example by setting the pixel voltage to zero very fast by scanning all rows, e.g. by use of fast switching transistors, such as IGZO transistors or the like. Another way of implementing the blanking pulse is by adding another transistor 1290 to the pixel circuit layout, as illustrated in Figure 12. This transistor is driven by a common gate line 1295, which, by switching transistor 1290, allows the drain or electrowetting capacitance EW to be discharged with a small fraction of time, as described above. As will be appreciated by the person skilled in the art, the present invention may be practised otherwise than as specifically described herein. Obvious modifications to the embodiments disclosed, and specific design choices, will be apparent to the skilled reader. The scope of the invention is only defined by the 5 appended claims.

Claims

1. An electrowetting optical tile, comprising: a multiple of pixels, where each pixel is a thin-film transistor (TFT) comprises with a gate, source, and drain, where the gate is connected to a gate line and the source are connected directly to the source line, and the drain serves as a pixel- electrode (Vpixel), where the pixel is configured to charge as desired voltage value between the drain and a common line when the gate is controlled and the voltage on the source line is transferred to the drain; a control unit configured to: to drive the pixels in an alternating current (AC) mode, by the to make the voltage on the common line alternately positive and negative, whereby a voltage oscillation of the common line is defined; to control the gate line for charging the pixels; where the control unit is further configured to: to set all pixel voltages to the voltage of the common line just before the voltage of the common line reverses, thereby preventing the voltage difference across the pixel from increasing then becomes the voltage oscillation of the common line; the pixel stresses immediately after the reversal of the to bring the common line back to their original values.

2. The electrowetting optical tile according to claim 1, where the The control unit is configured to generate a blanking pulse by the to momentarily set pixel voltage to the common line voltage just before the voltage of the common line reverses.

3. The electrowetting optical tile according to claim 2, where the timing (T) of the blanking pulse is synchronized with the reversal of the voltage of the common line, so that the blanking pulse immediately precedes the reversal of the common line voltage.

4. The electrowetting optical tile according to claim 2, where the duration (dt) of the blanking pulse is defined as a ratio to the AC frequency of the common line, where the duration of the the blanking pulse is proportional to half the period of the AC signal.

5. The electrowetting optical tile according to claim 2, where the The optimal duration of the blanking pulse is determined based on the ink response time of the ink in the electrowetting display, where the ink response time is the time-dependent displays change in the ink transmission signal.

6. The electrowetting optical tile according to claim 2, where the duration of the blanking pulse is defined based on the transmission signal- ink half-life, so that the duration of the blanking pulse is optimized to match the transmission signal half-life of the ink in the electrowetting display.

7. The electrowetting optical tile according to claim 2, where the Pixel voltages are set to the common line voltage. during the blanking pulse by rapidly scanning all rows of the pixels, so that the Pixel voltages are synchronized with the voltage reversal of the common line 8. The electrowetting optical tile according to one of the preceding conclusions, where each pixel comprises a common gate structure including a transistor that is configured to set the pixel voltage (Vpixel) to the common voltage just before the voltage of the common reverses line.

9. The electrowetting optical tile according to one of the preceding conclusions, where the thin-film transistors (TFTs) that drive the pixels fast Switching transistors are, preferably, indium gallium zinc oxide (IGZO)- transistors, configured to enable fast voltage adjustments during the blanking pulse.

10. The electrowetting optical tile according to one of the preceding conclusions, where the thin-film transistors (TFTs) that drive the pixels fast switching transistors are, selected from materials from the group consisting of zinc oxide (ZnO), nanocrystalline ZnO, indium-tin-zinc oxide (ITZO), indium oxide (ln203), amorphous IGZO or organic thin-film transistors (OTFTs), configured to minimize delay during voltage switching.

11. The electrowetting optical tile according to one of the preceding conclusions, whereby the control unit is further configured for the duration and timing to dynamically adjust the blanking pulse based on real-time monitoring of the transmission signal half-life.

12. A method for producing an electrowetting optical tile, comprising the steps of: forms of a multiple of pixels, where each pixel is a thin- A film transistor (TFT) comprises a gate, a source, and a drain, where the gate is connected to a gate line and the source is connected to a source line, and the drain serves as a pixel electrode (Vpixel), where the pixel is configured to charge to a desired voltage value between the drain and a common line when the gate is driven and the voltage on the source line is transferred to the drain; control a control unit to the multitude of pixels in a to control alternating current (AC) mode, where the voltage of the common line alternates between a positive and a negative voltage, whereby a voltage oscillation of the common line is defined; operate a control unit to control the gate line for the charging the pixels; configure the control unit to set all pixel voltages to the voltage of the common line just before the voltage of the reverses common line, thereby preventing the voltage difference across the pixels becomes greater than the voltage oscillation of the common line; and configure the control unit to the pixel voltages immediately after to reduce the voltage reversal of the common line to their original values.

13. A method for controlling a thin-film transistor (TFT) in an electrowetting optical tile, comprising the steps of: applying a voltage to a gate line connected to the gate of the TFT, where the source of the TFT is connected to a source line and the drain serves as a pixel electrode (Vpixel); drive the pixel in alternating current (AC) mode, where a control unit the voltage of the common line alternately positive and makes negative, thereby causing a voltage oscillation of the common line is defined; charge the pixel to a desired voltage value between the drain and the common line when the gate is actuated and the voltage on the source line is transferred to the drain; detecting an impending reversal of the voltage of the common line from negative to positive, and set the pixel voltages to the voltage of the common line just before the voltage of the reverses common line; the pixel voltages immediately after the voltage reversal of bringing the common thread back to their original values.

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