Method of manufacturing a shadow mask for stencil lithography

Abstract

The disclosure relates to a method of manufacturing a shadow mask (1) for stencil lithography. The method comprises providing (SO) a blank multi-layer stack (1000); creating (Sl) a first recess (22) that protrudes in a first direction (Z-) through a first thin-film layer (110) and into at least part of a support layer (120); depositing (S2) a metal layer (140) on a second thin-film layer (130) and depositing a resist layer (150) on the metal layer (140); creating (S3) a second recess (24a) that protrudes through the resist layer (150) in a second direction (Z+) opposite to the first direction (Z-); extending (S4) the second recess (24a) to an extended second recess (24b) that protrudes further through the metal layer (140) and through the second thin-film layer (130) in the second direction (Z+); creating (SS) a pattern of apertures (26) through the second- film layer (130). [Fig. 2]

Description

Field ofthe invention The invention relates to a , in particular for resist-free fabrication ofJosephson junctions. Background art A Josephsonjunction refers to two superconductors that are in close proximity to each other and that are separated by a thin barrier that joints the two superconductors to form the junction. Josephson junctions exhibit intriguing electrical phenomena known as Josephson effects and are a useful component in superconducting electronics. A Josephson junction can, for example, be used as a building block for dening a standard for the unit volt, for highly- sensitive magnetometers known as superconducting quantum interference devices, SQUIDS, and for realizing superconducting qubits in quantum computing, such as the transmon qubit. However, fabricating a Josephsonjunction with control over thejunctions dimensions still poses a challenge. For instance, in the context of realizing superconducting qubits, the quality ofthe Josephsonjunction can affect qubit decoherence times and noise. The quality of the Josephson junction can in turn be negatively affected by contamination of surfaces occurring during fabrication. For fabricating a desired Josephsonjunction feature, stencil lithography can be used to deposit materials in a certain target pattern on a substrate, the target pattern relating to the desired Josephsonjunction feature. For example, for creating a target pattern ofAluminium for a superconducting element / feature on a Silicon, Si, substrate, one may align a shadow mask with the substrate and create aow ofAluminium atoms passing through the shadow mask for depositing and creating the Aluminium superconducting element / feature on the substrate. A nal target pattern may be created by one or more such depositing steps. The quality of the target pattern on the substrate depends on the quality ofpatterns ofthe shadow mask. So, there is an interest in improving manufacturing ofshadow masks for fabrication of Josephson junctions. Summary ofthe invention A task set forth by the inventors is to improve manufacturing of shadow masks for fabrication ofJosephsonjunction. The inventors solved the task by providing a method of manufacturing shadow masks for Josephson junction fabrication according to the appended independent claim. The method l enables efcient manufacturing of shadow masks for improved fabrication of Josephson junctions. Advantageous aspects are provided by the appended dependent claims. Further advantages are discussed further below in the detailed description. Embodiments ofthe present disclosure will be described herein below with reference to the accompanying drawings. However, the embodiments of the present disclosure are not limited to the specic embodiments and should be construed as including all modications, changes, equivalent devices and methods, and / or alternative embodiments of the present disclosure. The terms have, may have, include, and may include as used herein indicate the presence of corresponding features (for example, elements such as numerical values, functions, operations, or parts), and do not preclude the presence of additional features. The terms A or B, at least one ofA or / and B, or one or more ofA or / and B as used herein include all possible combinations ofitems enumerated with them. For example, A or B, at least one ofA and B, or at least one ofA orB means (1) including at least one A, (2) including at least one B, or (3) including both at least oneA and at least one B. The terms such as rst and second as used herein may modify various elements regardless of an order and / or importance of the corresponding elements, and do not limit the corresponding elements. These termsmay be used for the purpose ofdistinguishing one element from another element. For example, a rst element may be referred to as a second element without departing from the scope the present invention, and similarly, a second element may be referred to as a rst element. It will be understood that, when an element (for example, a rst element) is (operatively or communicatively) coupled with / to or connected to another element (for example, a second element), the elementmay be directly coupled with / to another element, and there may be an intervening element (for example, a third element) between the element and another element. To the contrary, it will be understood that, when an element (for example, a rst element) is directly coupled with / to or directly connected to another element (for example, a second element), there is no intervening element (for example, a third element) between the element and another element. The expression congured to (or set to) as used herein may be used interchangeably with suitable for having the capacity to designed to adapted to made to, or capable of according to a context. The term congured to (set to) does not necessarily mean specically designed to in a hardware level. Instead, the expression apparatus congured 2 to... may mean that the apparatus is capable of... along with other devices or parts in a certain context. The terms used in describing the various embodiments ofthe present disclosure are for the purpose of describing particular embodiments and are not intended to limit the present disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. All ofthe terms used herein including technical or scientic terms have the same meanings as those generally understood by an ordinary skilled person in the related art unless they are dened otherwise. The terms dened in a generally used dictionary should be interpreted as having the same or similar meanings as the contextual meanings of the relevant technology and should not be interpreted as having ideal or exaggerated meanings unless they are clearly dened herein. According to circumstances, even the terms dened in this disclosure should not be interpreted as excluding the embodiments of the present disclosure. The person skilled in the art will understand that the features described above and / or below may be combined in any way deemed useful. The drawings of the present disclosure show examples / embodiments ofthe invention, which will be described in detail hereinafter. It is to be understood that one or more ofelements / components shown and / or described in one or more of these examples / embodiments and not in others may be used in those others too unless mechanical or other limitations prevent such an implementation. Moreover, describing features of different examples / embodiments in a single passage does not automatically mean that those features are inextricably linked. They may be applied separately from one another. Brief description ofthe drawings The present invention is discussed in more detail below, with reference to the attached drawings, in which: Fig. 1 illustrates fabricating a Josephsonjunction feature by a shadow mask. Fig. 2 shows a method of manufacturing a shadow mask according to the present invention. Fig. 3 shows a preferred manner of creating a rst recess. Fig. 4 shows a preferred manner of creating a pattern of apertures. Detailed description Stencil lithography is used to deposit materials in a certain target pattern on a substrate. To that end, a shadowmask for stencil lithography canbe manufactured as outlined for example in Chapter 5 of the Ph.D. thesis of Michaela Eichinger, [Eichinger]. The target pattern can 3 relate to a desired feature that one wishes to create on the substrate such as a Josephsonjunction feature. A stencil used in stencil lithography is a hard mask / shadow mask made of inorganic materials. The quality of the target pattern on the substrate depends on the quality of patterns created in the shadow mask. For example, for creating a target pattern of Aluminium for a superconducting element / feature on a Silicon, Si, substrate, one may align the shadow mask with the substrate and create a ow of Aluminium atoms for depositing and creating the Aluminium superconducting element / feature on the substrate. The target patternmay be created by one or more such depositing steps. Fig. 1 illustrates a stencil / shadow mask (1) that may be used to deposit and create a Josephson junction feature on a substrate via a pattern of apertures (26) of the stencil. As illustrated, the creating of the Josephson junction feature may involve one or more deposition steps, for example one or more deposition steps ofthe superconducting material Al. When manufacturing the shadow mask, an initial membrane is typically provided in the form of a blank multi-layer stack (1000) as shown in Fig. 2, top left part relating to step S0. Fig. 2 shows a cross-section side-view. The multi-layer stack (1000) has a support layer (120) that is surrounded by thin-lm layers (110, 130). For manufacturing a shadow mask, a task is to create a pattern of apertures (26) through which a ux of atoms can be sent for depositing and creating target features on a substrate. The thin-lm layers are typically based on a semiconductor material. One of the two thin-lm layers (e.g., 110) relates to an outer layer that, after manufacturing, is congured to receive a ux ofatoms when using the shadowmask in stencil lithography. Such thin-lm layer may also be referred to as a window layer. In other words, when using the shadow mask, a ux of atoms such as Aluminium atoms is targeted at the window layerwhich receives the ux ofatoms and guides the ux ofatoms towards the other thin-lm layer. The other thin-lm layer (e.g. 130) relates to the other outer layer opposite to thewindow layer and is, after manufacturing, congured to comprise a pattern ofapertures (26) protruding therethrough. The other thin-lm layermay also be referred to as a feature-pattern layer as it exhibits the pattern of apertures (26) by which a target pattern on a substrate can be created via stencil lithography. For example, when placing the shadow mask (1) on a desired position for creating a target pattern such as a Josephson junction feature on a substrate, the ux of atoms created by an e-beam evaporator is received through the window layer and can pass through the pattern of apertures (26) ofthe feature-pattern layer, so that the target pattern is created on the substrate. 4 A goal of the present invention is to manufacture a shadow mask (1) with a pattern of apertures (26) for stencil lithography with high precision while maintaining a high quality of the shadow mask (1). To that end, a method of manufacturing a shadow mask (1) for stencil lithography is provided. The method comprises: providing (S0) a blank multi-layer stack (1000) comprising a rst thin-lm layer (110), a support layer (120) of monocrystalline Silicon, Si, and a second thin-lm layer (130), the support layer (120) being surrounded by the rst and second thin-lm layers (110, 130), creating (Sl) a rst recess (22) that protrudes in a rst direction (Z.) through the rst thin-lm layer (110) and into at least part ofthe support layer (120); depositing (S2) a metal layer (140) on the second thin-lm layer (130) and depositing a resist layer (150) on the metal layer (140); creating (S3), by photolithography and subsequent development, a second recess (24a) that protrudes through the resist layer (150) in a second direction (Z+) opposite to the rst direction (Z-), the second recess (24a) being opposite to the rst recess (22); extending (S4), by reactive ion etching, the second recess (24a) to an extended second recess (24b) that protrudes further through the metal layer (140) and through the second thin- lm layer (130) in the second direction (Z+), creating (S5) a pattern of apertures (26) through the second-lm layer (130), by removing (S5-l) the resist layer (150) and the metal layer (140) and subsequently extending (S5-3) the rst recess (22) further in the rst direction (Z-) until the rst recess (22) meets the extended second recess (24b) so as to together form the pattern of apertures (26). The inclusion ofthe metal layer (140) overcomes a cracking problem that occurs when directly depositing the resist layer (150), as this resist layer (150) can exhibit cracks after the development process. Such cracks are however detrimental to the quality of the nal shadow mask by obtaining a lower resolution of created patterns. The metal layer (140) acts as an adhesion layer for the resist layer (150) and moreover acts as a discharging layer. By including the metal layer (140), the number ofcracks can be reduced. The providing (S0) of the blank multi-layer stack (1000) may involve creating membranes from an initial silicon wafer serving as basis for the support layer (120). The thin- 5 lm layers (110, 130) may be deposited on both sides ofthe silicon wafer. The thin-lm layers are preferably deposited using a low-pressure chemical vapour deposition (LPCVD) process. The rst recess (22) may be understood as an opening through which aluminium can pass through the shadowmask (1). The rst recess (22) may also be called awindow which is created on awindow side ofthe shadowmask (1). The window is suitable for receiving a ux ofatoms for depositing and creating a target feature on a substratewhen using the shadowmask. Preferred steps S1-1, S1-2, S1-3, S1-4, S1-5 are illustrated in Fig. 3. Preferably, the creating of the rst recess (22) is combined with creating (S1-2, S1-3, S1-5) markers (21, 23) that are suitable for aligning the shadow mask (1) on a substrate when using the shadow mask (1) for stencil lithography. Preferably, the creating (S1) of the rst recess (22) comprises etching (S1-5) by Potassium Hydroxide, KOH, through the Si ofthe support layer (120). Preferably, the creating (S1) of the rst recess (22) comprises spinning (S1-1) a polymethylmethacrylate, PMIVIA, layer (109) on the rst thin-lm layer (110) and using the KOH to etch through the Si ofthe support layer (120). ThePMMA is an electronbeam resist that can thus be initially spun on thewindow side ofthe blank multi-layer stack (1000). In general, an ElectronBeam Pattern Generator (EBPG) can be used to expose resist to write desired patterns on a resist. The markers (21, 23) can thus be created by exposing a part ofthe resist to an electron beam from the EBPG, developing the exposed part of the resist by using a developer solution and etching through the developed resist. After the remaining resist is stripped, KOH can be used to etch the silicon symmetrically and in the rst direction, i.e. in a direction vertically down (Z.) as also illustrated in Figs. 2-3. TheKOH etch of silicon through the marker areas can be stopped mid-way before the etching reaches second thin-lm layer (130). Thereby, the marker areas for the markers (21, 23) can be fully etched while the rst recess (22) protrudes only through a part ofthe support layer (120). Preferably, the monocrystalline Si of the support layer (120) is a <100> Si. Thereby, when etching with for exampleKOH, a truncated-cone shape can be obtained as the etching is then inherently symmetric, as also illustrated in Figs. 24. The wafer can be cleaned, for example with anMF-21A developer, to remove any residues that were formed due precipitation after etching withKOH. Preferably, the metal ofthe metal layer (140) is Chromium, Cr. 6 Chromium can act as an adhesion promoter and can effectively reduce a number of cracks. However, the inventors also found out that Cr can be more difcult to get fully etched and can lead to non-optimal patterns of apertures, so that for example Josephson junction features can not be fully etched at parts where Cr is still present. More preferably, the metal of the metal layer (140) is Niobium Titanium Nitride, NbTiN. As compared to Cr, usingNbTiN has the additional advantage that the etching does not leave any residues behind. Moreover, NbTiN can be dry etched for example by uorine radicals, Which ensures etching below developed resist with efcient removal ofresidues. Preferably, the resist is Polymethylmethacrylate, PMMA, or a Chemical Semi Amplied Resist, CSAR, preferably the CSAR. In particular, the combination ofNbTiN and CSAR is preferred. For example, a same etching recipe can be used for bothNbTiN and CSAR. Moreover, the inventors have found that NbTiN has a particularly good compatibility as an adhesion and discharging layer forCSAR to support etching for longer time scales. Preferably, the thin-lm layers are based on Silicon Nitride, Si3N4, or Silicon Carbide, SiC. Preferably, the reactive ion etching is based on Triuoromethane, CHF3. Preferably, the method comprises creating markers (21, 23), the markers being suitable for aligning the shadow mask (1) on a substrate when using the shadow mask (1) for stencil lithography. The second recess (24a) is opposite to the rst recess (22) so that in the nal step (S5) ofthe manufacturing, the patterns of apertures (26) is obtained. Preferably, the creating (S3) ofthe second recess (24a) by photolithography comprises using an electron beam to write, on the resist layer (150), a pattern for the second recess (24a) and using the pattern as mask for developing the second recess (24a) by a developer solution. Preferably, the extending (S4) of the second recess (24a) by reactive ion etching comprises using one or more reactive ion etchers, RIEs, to etch away material from the metal layer (140) and the second thin-lm layer (130) based on using the second recess (24a) as mask to obtain the extended second recess (24b). Preferably, the metal layer (140) is based on Chromium, Cr, or Niobium Titanium Nitride, NbTiN. 7 Preferably, the rst and second thin-lm layers (110, 130) are based on Silicon Nitride, Si3N4, or Silicon Carbide, SiC. Preferably, the reactive ion etching is based on a Triuoromethane, CHF3, plasma. Preferably, the resist is Polymethylmethacrylate, PMMA, or a Chemical Semi Amplied Resist, CSAR. For example, the gases SF6 and CHF3 can be used to etch Si3N4. The gas SF6 etches Si3N4 isotropically while the gas CHF3 etches Si3N4 anisotropically. When the second thin-lm layer (130) is based on Si3N4, then preferably the gas CHF3 is used for etching. Various developer solutions can be used depending on the resist. For example, exposed CSAR can be developed by rinsing in pentyl acetate (PA) followed by isopropanol (IPA) and deionized water (DI). As another example, exposedPMMA can be developed using various developers such as MIBK:IPA 1:3, IPA:H20 3:1, IPA: H20 7:3 and IPA: H20 10:1. Furthermore, the temperature during the development process may be controlled to affect contrast and width ofthe developed resist. For example, forPMMA, preferably relatively-cold IPA: H20 3:1 is used to attain vertical walls. Sonication may be performed for effective development of small features. Preferably, the metal layer (140) has a thickness in between 10nm and 700nm, more preferably in between 50nm and 500nm, yet more preferably in between 50nm and 400nm, even more preferably in between 50nm and 200nm, yet even more preferably in between 50nm and 150nm, most preferably in between 80nm and 120nm. Preferably, the resist layer (150) has a thickness in between 500nm and 1.5um; more preferably in between 500nm and 1.2um; yet more preferably in between 550nm and 800nm, most preferably in between 550nm and 600nm. A resist-layer thickness of above 600nm may also result in formation of cracks in the resist layer (150), which can be healed and are preferably healed by performing a post-development bake before the etching process. Preferably, the creating (S5) ofthe pattern of apertures (26) further comprises: spinning (S5-2) a spin-protective layer (160) on the second thin-lm layer (130) before the extending (S5-3) ofthe rst recess (22), and removing (S5-4) the spin-protective layer (160) after the extending (S5-3) of the rst recess (22). The spin-protective layer (160) can stop a RIE; used during the extending (S5-3) ofthe rst recess (22), from entering through the second thin-lm layer (130). For example, when KOH is used and the thin-lm layers are based on Si3N4, then Si could be etched which can 8 lead to creation ofsuspended Si3N4 and unwanted corners in the Si3N4 layer that can cause high stress and undesired cracks. By inclusion ofthe spin-protective layer (160), such disadvantages can be reduced. Preferably, the spin-protective layer (160) isPMMA. Preferably, the rst and second thin-lm layers (110, 130) are based on Silicon Nitride, Si3N4, the metal of the metal layer (140) is based on Niobium Titanium Nitride, NbTiN, and the resist layer (150) is based on a Chemical Semi Amplied Resist, CSAR. Preferably, the extending (S4) ofthe second recess (24a)by reactive ion etching isbased on a Triuoromethane, CHF3, plasma. Preferably, the pattern of apertures (26) relates to a Josephsonjunction feature. Preferably, the thin-lm layers (110, 130) ofthe blank multi-layer stack (1000) have a thickness in between 200nm and 600nm and the support layer (120) of the blank multi-layer stack (1000) has a thickness in between 200um and 400um. More preferably; the thin-lm layers (110, 130) of the blank multi-layer stack (1000) have a thickness in between 300nm and 500nm and the support layer (120) ofthe blank multi- layer stack (1000) has a thickness in between 220um and 300um. In an example, the thin-lm layers (110, 130) had a thickness of480nm and the support layer (120) a thickness of260nm. Preferably, a width of the apertures (26) in a direction perpendicular to the rst and second directions (Z+, Z-) is in between 50nm and 300nm. The following list of references is referred to in the present document and is incorporated herein by way ofreference. List of references [Eichinger] Michaela Eichinger. Novel Methods andMaterialsfor Superconducting Qubits and Circuits. Ph.D. Thesis, The Faculty of Science, Niels Bohr Institute, The University of Copenhagen. April 2023. 9

Claims

1. Method for making a shadow mask (1) for stencil lithographs, the working method comprising: the provision (SO) of a blank multilayer stack (1000) comprising a first thin-film layer (110), a support layer (120) of monocrystalline silicon, Si, and a second thin-lm layer (130), where the support layer (120) is surrounded by the first and second thin-film layers (110, 130), creating (Sl) of a first recess (22) that protrudes in a first direction (Z-) through the first thin-lm layer (110) and in at least part of the support layer (120); the deposition (S2) of a metallic layer (140) on the second thin-film layer (130) and the deposition of a resist layer (150) on the metallic layer (140), the creation (S3), by photolithography and subsequent development, of a second recess (24a) through the resist layer (150) in a second direction (Z+) projects out opposite to the first direction (Z-), with the second recess (24a) is opposite to the first recess (22), extending (S4), by reactive ion etching, of the second recess (24a) to an extended second recess (24b) that continues through the metallic layer (140) and through the second thin-film layer (130) protrudes in the second direction (Z+), creating (S5) a pattern of openings (26) by the second thin-film layer (130), by removing (S5-1) the resist layer (150) and the metallic layer (140) and then extending (S5-3) the first recess (22) further in the first direction (Z-) until the first recess (22) meets the extended second recess (24b) to the to form a pattern of openings (26).

2. The method according to conclusion 1, whereby the creation (S3) of the second recess (24a) by photolithographs the use of an electron beam to, on the resist layer (150), to write a pattern for the second recess (24a) and the use of the pattern as mask includes for developing the second recess (24a) by a developer solution. 10 3. The method according to one of the preceding conclusions, whereby the extension (S4) of the second recess (24a) by reactive ion etching the use of one or more reactive ion etchers, RIEs, to remove material from the metallic layer (140) and the second thin- film layer (130) to etch away based on the use of the second recess (24a) as mask to obtain the extended second recess (24b).

4. The method according to one of the preceding claims, whereby the metallic layer (140) is based on chromium, Cr, or niobium titanium nitride, NbTiN.

5. The method in accordance with one of the preceding conclusions, whereby the first and second thin-lm coatings (110, 130) are based on silicon nitride, Si3N4, or silicon carbide, SiC.

6. The method according to one of the preceding conclusions, whereby the reactive ion etching is based on a triuormethane, CHF3, plasma.

7. The method according to one of the preceding conclusions, whereby the resist polymethyl methacrylate, PMMA, or a chemical semi-reinforced resist, CSAR, is.

8. The method pursuant to one of the preceding claims, involving the provision of the membrane (10) creating (Sl-2, Sl-3, Sl-5) markings (21, 23) on the membrane (10) includes, where the markings (21, 23) are suitable for aligning the shadow mask (1) on a substrate when using the shadow mask (10) for stencil lithography.

9. The method according to one of the preceding conclusions, whereby the creation (Sl) of the first recess (22) etching (Sl-5) by means of potassium hydroxide, KOH, by the Si of the support layer (120) includes.

10. The method according to the preceding conclusion, whereby the creation (Sl) of the first recess (22) spinning (S1-1) of a polymethylmethacrylate,PMMA, layer (109) on the first thin-film layer (110) and the use of the KOH to the Si of the includes support layer (120) to be etched. 1 1 11. The method according to one of the preceding conclusions, whereby the creation (S5) of the pattern of openings (26) further includes: the spinning (S5-2) of a spider protection layer (160) on the second thin-film layer (130) for extending (S5-3) the first recess (22), and removing (S5-4) the spider protection layer (160) after extending (S5-3) of the first recess (22).

12. The method in accordance with one of the preceding conclusions, whereby the first and second thin-film layers (110, 130) are based on silicon nitride, Si3N4, the metallic layer (140) is based on niobium titanium nitride, NbTiN, and the resist layer (150) is based on a chemical semi-reinforced resist, CSAR.

13. The method according to the preceding conclusion, whereby extending (S4) the second recess (24a) by reactive ion etching is based on a triuormethane, CHF3, plasma.

14. The method according to one of the preceding conclusions, whereby the pattern of openings (26) relate to a Josephson junction feature. 12

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