PSEUDO-DOHERTY LOAD-MODULATED BALANCED AMPLIFIER MODULE

Abstract

PSEUDO-DOHERTY LOAD-MODULATED BALANCED AMPLIFIER MODULE Abstract According to an aspect of the present disclosure, the balanced amplifier of the PD-LMBA module comprises one or more first semiconductor dies mounted on the substrate and on which a first power transistor and a second power transistor are integrated. The balanced amplifier further comprises a first matching network, a second matching network, and a transmission line-based directional coupler. The first and second matching network each comprise a shunt capacitive element of which a non-grounded terminal is connected to the relevant port of the directional coupler and a connection connecting the output of the relevant power transistor to this port. [FIG. 1]

Description

PSEUDO-DOHERTYLOADMODULATED BALANCED AMPLIFIERMODULE M Aspects ofthe present disclosure relate to a pseudo-Doherty load-modulated balanced amplifier, PD-LMBA, module, configured for amplifying an inputRF signal and for providing the amplified RF signal to an external load. Further aspects of the present disclosure relate to a base station for mobile telecommunications comprising such a module. Background Several different amplifier topologies have been developed to improve efficiency ofpower amplifiers. For example, Doherty amplifiers are currently widely used in base stations for mobile telecommunications, such as 4G and5G base stations. As the maximum data rate or speed oftelecommunications standards keeps increasing, it becomes more and more important to use amplifier topologies that provide excellent efficiencies over relatively large bandwidths. Furthermore, efficiencies should not only be acceptable at saturated output powers but also in a power back-offregime as modern telecommunications standards rely on signals having a relatively high peak-to-average ratio. In a Doherty amplifier, a main amplifier and one or more peak amplifiers are used. The main amplifier is biased in class B, whereas the one or more peak amplifiers are biased in class C. During operation and at relatively low input powers, only the main amplifier is amplifying signals. At higher input powers, also the one or more peak amplifiers will amplify signals. In addition, the load seen by the main amplifier is modulated using the current output by the peak amplifier(s). For example, the load seen by the main amplifier is higher at lower input powers, thereby offering improved efficiencies under power back-off. A more recently proposed topology is referred to as a pseudo-Doherty load-modulated balanced amplifier, PD-LMBA.APD-LMBA comprises a control amplifier, sometimes also referred to as main amplifier, and a balanced amplifier. The balanced amplifier comprises a first amplifier, a second amplifier, and a directional coupler for combining a signal amplified by the first amplifier and a signal amplified by the second amplifier. The directional coupler has a through port connected to an output of the first amplifier, a forward coupled port connected to an output of the second amplifier, an input port configured to be connected to an external load, and a reverse coupled port connected to an output of the control amplifier. Furthermore, the first, second, and third amplifier may each comprise a power transistor, such as a Gallium Nitride-based field-effect transistor. In the known PD-LMBA, the impedance seen at the reverse coupled port looking towards the directional coupler is substantially constant with input power. Consequently, contrary to a Doherty amplifier, the control / main amplifier is not modulated by the current of the other amplifiers. On the other hand, the impedance seen by the first and second amplifiers is modulated by the current output by the control amplifier. The knownPD-LMBA displays two efficiency peaks as a function ofinput power.A first efficiency peak is obtained at relatively low input powers, when only the control amplifier is switched on. Typically, the impedance seen by the control amplifier at its output corresponds to a predefined impedance for outputting power at given efficiency.A second peak is obtained at relatively high input powers, when the balanced amplifier and control amplifier are both switched on. The impedance presented at the outputs of the first and second amplifiers corresponds to a predefined impedance for outputting saturated output power. Recently, PDLMBAs have demonstrated superior bandwidth capabilities compared to conventional Doherty amplifiers. Furthermore, PD-LMBAs exhibit inherent linearity and can be effectively linearized compared toLMBA. Nevertheless, PD-LMBAs encounter several significant challenges during their industrialization phase. Firstly, the physical size of thePD-LMBA can be substantial, making it less suitable for compact, small form factor designs. Secondly, PDLMBAs may fall short of realizing their full theoretical bandwidth potential, primarily due to device parasitics and the presence of output matching components. my According to an aspect ofthe present disclosure, aPD-LMBA module is provided in which the ahovementioned problems do not occur or at least to a lesser extent. To this end, the present disclosure provides aPD-LMBA that comprises a substrate, and a balanced amplifier comprising one or more first semiconductor dies mounted on the substrate and on which a firstpower transistor and a second power transistor are integrated. The balanced amplifier further comprises a first matching network, a second matching network, and a transmission line-based directional coupler for combining a signal amplified by the first power transistor and a signal amplified by the second power transistor, wherein the directional coupler comprises a plurality of transmission lines integrated on the substrate or integrated on a ceramic die or semiconductor die that is mounted on the substrate. In an embodiment, the first and second power transistor are integrated on a same single first semiconductor die. In another embodiment, the first and second power transistors are each integrated on a respective first semiconductor die. ThePD-LMBA module according to an aspect of the present disclosure further comprises a second semiconductor die on which a third power transistor is integrated, wherein the second semiconductor die is mounted on the substrate. Furthermore, a third shunt capacitive network is present at an output of the third power transistor that includes an output capacitance of the third power transistor. The one or more first semiconductor dies and the second semiconductor die may be based on the same of different semiconductor technology. The directional coupler has an input port configured to be connected to the external load, a reverse coupled port connected to an output of the third power transistor using a third connection, a through port, and a forward coupled port. The first matching network comprises a first shunt capacitive element ofwhich a non- grounded terminal is connected to the through port and a first connection connecting an output of the firstpower transistor to the through port. Similarly, the second matching network comprises a second shunt capacitive element ofwhich a non-grounded terminal is connected to the forward coupled port and a second connection connecting an output of the second power transistor to the forward coupled port. The first connection, second connection, and third connection each comprise one or more bond-wires or a ip-chip connection in combination with a transmission line arranged on the substrate. Within the context ofthe present invention, the substrate may comprise one or more dielectric layers, and one or more electrically conductive layers, such as metal layers, arranged on or in between the dielectric layers. The substrate may have been formed using lamination. Furthermore, the substratemay be provided with vias to make an electrical connection between structures formed in different conductive layers. The first matching network can be configured to form, together with a first shunt capacitive network present at the output of the first power transistor, an electrical equivalent of a quarter-wavelength transmission line, wherein the first shunt capacitive network comprises an output capacitance of the firstpower transistor. Similarly, the second matching network can be configured to form, together with a second shunt capacitive network present at the output of the second power transistor, an electrical equivalent of a quarter-wavelength transmission line, wherein the second shunt capacitive network comprises an output capacitance of the second power transistor. Alternatively, instead offorming equivalents for quarter wavelength transmission lines, different impedance matching networks could be formed. ThePDLMBA module of the present disclosure can be configured to operate within a given frequency band arranged around a given center frequency. This latter center frequency may lie in a frequency range between 500MHZ and 50 GHz, whereas typical bandwidths range from 10% to 80% ofthe center frequency. Within the context of the present application, when a component or network is said to operate as a quarter-wavelength transmission line, this component or network displays, at or close to a given operational frequency in the frequency band of the PD- LMBA module, the same or similar electrical behavior as a transmission line that would impart a phase offset of90 degrees at that frequency. By using the output capacitances of the first and second power transistor in combination with shunt capacitive elements connected to the through port and the forward coupled port and the first and second connection, a broadband impedance matching can be obtained between the port impedances of the directional coupler and the impedances that are to be presented at the outputs of the first and second power transistors for reaching saturated output power. Accordingly, instead of degrading performance, the output capacitances are used in impedance matching networks for mimicking a quarter wavelength transmission line. Furthermore, this broadband behavior can be obtained with a relatively small footprint. Within the context ofthe present disclosure, the port impedance of a port of a directional coupler is the impedance that needs to be connected to that port to prevent reection of signals at the interface between the port and that impedance. Typically, with known PDLMBAs, a hybrid coupler is used for combining signals amplified by the first amplifier and second amplifier.A hybrid coupler is a particular example of a directional coupler in which power provided at its input port is evenly (-3dB) distributed over its two output ports, i.e. the through port and the forward coupled port. When used in reverse, it can be used to combine signals. More in particular, signals provided to the through port and the forward coupled port are combined at the input port. It is noted that the present disclosure is not limited to using hybrid couplers for combing the signals amplified by the first and second amplifiers. lnstead, non-3dB directional couplers can equally be used in which the coupling factor preferably lies in between -4 and -3 dB. ThePDLMBA may further comprise a body of solidified molding compound that encapsulates the one or more first semiconductor dies and the second semiconductor die. This body also contacts the substrate. In other embodiments, a lid or cover is attached to the substrate thereby creating an air cavity inside the module in which the one or more first semiconductor dies and the second semiconductor die are arranged. ThePD-LMBAmay further comprise a first splitter and a second splitter. The first splitter may be configured for splitting the inputRF signal into a first part to be supplied to the third power transistor and a second part to be supplied to the second splitter. In turn, the second splitter can be configured for splitting the second part into a primary second part to be supplied to the firstpower transistor and a secondary second part to be supplied to the second power transistor. The first and second splitter may each comprise a directional coupler, such as a hybrid coupler. The third power transistor can be configured to output saturated power when presented with a first impedance at its output at a predefined power back-off level of thePD-LMBA module. Typically, thePDLMBA module is characterized by a maximum power that can be output. The power back-off level is related to this maximum power. For example, a power back-off level of -9 dB corresponds to thePD-LMBA module outputting a power that is 9dB less than its maximum power. Furthermore, at the abovementioned predefined power back-off level, the balanced amplifier is typically switched off. A port impedance ofthe reverse coupled portmay correspond to the first impedance. In such a case, an impedance matching need not be arranged in between the output of the third power transistor and the reverse coupled port of the directional coupler. However, in other embodiments, such impedance matching network can be used. This may for example apply when realizing the directional coupler with the first impedance is disadvantageous in terms of losses or bandwidth. In these cases, thePD-LMBA may include a third matching network comprising the third connection and a third shunt capacitive element ofwhich a non-grounded terminal is connected to the reverse coupled port, wherein the third matching network is preferably configured to form, together with the third shunt capacitive network, an electrical equivalent of a quarter-wavelength transmission line. Alternatively, instead offorming an equivalent for a quarter wavelength transmission line, a different impedance matching network could be formed. The third matching network and the third shunt capacitive network can be configured to transform a port impedance of the reverse coupled port to the first impedance. The firstpower transistor and second power transistor can be each configured to output saturated power when they are each presented with a second impedance at their outputs at a maximum power level of thePDLMBA module, wherein the first matching network and the first shunt capacitive network are configured to transform a port impedance of the through port to the second impedance, and wherein the second matching network and the second shunt capacitive network are configured to transform a port impedance of the forward coupled port to the second impedance. Typically, the first and second power transistors are identical and have amaximum saturated power that is higher than that of the third power transistor. Moreover, a ratio between the maximum saturated power of the first or second power transistor and the maximum saturated power of the third power transistor can be at least substantially identical to the ratio between the first impedance and second impedance. Although not limited thereto, each port of the directional couplermay have a same port impedance. The first shunt capacitive networkmay further comprise a first auxiliary shunt capacitive element arranged in parallel to the output capacitance of the first power transistor. Additionally, or alternatively, the second shunt capacitive network may further comprise a second auxiliary shunt capacitive element arranged in parallel to the output capacitance of the second power transistor. Additionally, or alternatively, the third shunt capacitive networkmay further comprise a third auxiliary shunt capacitive element arranged in parallel to the output capacitance of the third power transistor. These auxiliary shunt capacitive elements may be required when a value of the output capacitance ofthe first, second, or third power transistor is insufficient for realizing the intended matching. At least one of the first shunt capacitive element, the first auxiliary shunt capacitive element, the second shunt capacitive element, the second auxiliary shunt capacitive element, the third shunt capacitive element, and the third auxiliary shunt capacitive element, may comprise a surface-mounted device capacitor mounted on the substrate, or a capacitor integrated on a ceramic die or semiconductor die that is mounted on the substrate. The directional coupler may be a branch line coupler. In this case, the directional coupler may comprise a first transmission line having a first characteristic impedance, and a second transmission line and third transmission line, each having a second characteristic impedance.A length of the first, second, and third transmission lines may correspond to a quarter wavelength, and the second characteristic impedance may correspond to& times the first characteristic impedance. For example, the second characteristic impedance may fall in a range between 0.9 x@ times the first characteristic impedance and 1.1 x@ times the first characteristic impedance. A second end of the first transmission line can be connected to a first end of the second transmission line in a first connecting region, wherein the first connecting region is connected to and / or forms the input port. The first connecting regionmay be part of the first and / or second transmission line. A first end of the first transmission line can be connected to a first end of the third transmission line in a second connecting region, wherein the second connecting region is connected to and / or forms the through port. The second connecting regionmay be part of the first and / or third transmission line. The directional coupler may further comprise a branch network between the forward coupled port and the reverse coupled port, wherein the branch network comprises a fourth shunt capacitive element arranged in parallel to the second shunt capacitive element and a series inductive element between a non-grounded terminal of the fourth shunt capacitive element and the output of the third power transistor. A non-grounded terminal of the fourth shunt capacitive element can be connected to and / or form the forward coupled port. The output of the third power transistor can be connected to and / or form the reverse coupled port. In this case, the branch network and the third shunt capacitive networkmay jointly form an equivalent of a quarter-wavelength transmission line ofwhich a characteristic impedance corresponds to the first characteristic impedance. Alternatively, in the case wherein an impedance matching network is arranged between the reverse coupled port and the output of the third power transistor, the non-grounded terminal of the third shunt capacitive element can be connected to and / or form the reverse coupled port. The directional coupler may then further comprise a fifth shunt capacitive element ofwhich a non- grounded terminal is connected to the reverse coupled port. In addition, the branch network and the fifth shunt capacitive element may jointly form an equivalent of a quarter-wavelength transmission line ofwhich a characteristic impedance corresponds to the first characteristic impedance. The third shunt capacitive element and fifth shunt capacitive element can be combined into a single combined third shunt capacitor. The second and fourth shunt capacitive elements can be combined into a single combined second shunt capacitor. The series inductive elementmay comprise a surface-mounted device, SMD, inductor arranged on the substrate. The branch networkmay further comprise one more bond-wires through which the output of the third power transistor is electrically connected to the series inductive element. In addition, the output ofthe third power transistor can be connected using one or more bond-wires to a second end of the second transmission line. The abovementioned second shunt capacitive element, the fourth shunt capacitive element, said single combined second shunt capacitive element, the third shunt capacitive element, the fifth shunt capacitive element, and / or said single combined third shunt capacitive element, may comprise a surface-mounted device capacitor or a capacitor integrated on a ceramic die or semiconductor die that is arranged on the substrate. The first transmission line, second transmission line, and third transmission line can be integrated on a ceramic die or semiconductor die that is mounted on the substrate. lnstead ofbeing a branch line coupler, the plurality of transmission lines may comprise a first transmission line having a first end and an opposing second end and a second transmission line having a first end and an opposing second end, wherein the first transmission line is capacitively and / or inductively coupled to the second transmission line. In this case, the first transmission line may have a first characteristic impedance and the second transmission line a second characteristic impedance. Furthermore, the first end of the first transmission line may be connected to and / or form the forward coupled port, and the second end of the second transmission line may be connected to and / or form the through port. In addition, the second end of the first transmission line can be connected to and / or form the reverse coupled port, and the first end of the second transmission line can be connected to and / or form the input port. Accordingly, in this case, the directional coupler is based on a pair ofcoupled lines, said pair comprising the abovementioned first and second transmission line. The first ends of the first and second transmission lines may lie adjacent to each other, and the second ends of the first and second transmission lines may lie adjacent to each other. ThePD-LMBAmay comprise a further shunt network connected to the output of the third power transistor and comprising a series connection of an inductor and capacitor, wherein, at or close to an operational frequency of the PD-LMBA, the further shunt network resonates with the output capacitance of the third power transistor. In this case, the output of the third power transistor can be connected using one or more bond-wires to the second end of the second transmission line. An inductance associated with the connection between the output of the third power transistor and the second end of the second transmission line is preferably kept small. The inductor of the further shunt networkmay comprise a first inductive element from the group consisting of a transmission line integrated on the substrate, a surface-mounted device inductor, and a transmission line integrated on a ceramic or semiconductor die that is mounted on the substrate. The inductor of the further shunt networkmay further comprise one or more bond- wires by which the output of the third power transistor is connected to the first inductive element. The abovementioned first and second transmission lines can be realized in or on the substrate. The firstpower transistor and second power transistor can at least substantially be identical. Additionally, or alternatively, amaximum saturated power that can be output by the first, second, and third power transistor is in accordance with a ratio n:n: 1, wherein n lies in a range between 1 and 5. At least one of the first, second, and third power transistormay comprise a Gallium Nitride-based transistor such as a field-effect transistor, or a Silicon-based laterally diffused metal oxide semiconductor transistor. In some embodiments, the one or more first semiconductor dies are based on a different semiconductor technology and / or material system than the second semiconductor die. The substrate may comprise one or more dielectric layers ofwhich at least one is provided on both sides thereof with one or more conductive layers. Preferably, the substrate comprises a printed circuit board or other laminate substrate. According to a further aspect, the present disclosure provides a base station for mobile telecommunications comprising thePD-LMBA as defined above. So that the manner in which the features of the present disclosure can be understood in detail, a more particular description is made with reference to embodiments, some ofwhich are illustrated in the appended figures. It is to be noted, however, that the appended figures illustrate only typical embodiments and are therefore not to be considered limiting of its scope. The figures are for facilitating an understanding ofthe disclosure and thus are not necessarily drawn to scale. Advantages of the subject matter claimed will become apparent to those skilled in the art upon reading this description in conjunction with the accompanying figures, in which like reference numerals have been used to designate like elements, and in which: Figure 1 illustrates a general embodiment of aPD-LMBA module in accordance with the present disclosure; Figure 2 illustrates a first detailed embodiment of aPD-LMBA module in accordance with the present disclosure based on coupled lines; Figure 3 illustrates an equivalent circuit of thePDLMBA module of figure 2; Figure 4 illustrates a second detailed embodiment of aPD-LMBA module in accordance with the present disclosure based on coupled lines; Figure 5 illustrates an equivalent circuit of thePDLMBA module of figure 4; Figure 6 illustrates a first detailed embodiment of aPD-LMBA module in accordance with the present disclosure based on a branch line coupler; Figure 7 illustrates an equivalent circuit of thePDLMBA module of figure 6; Figure 8 illustrates a second detailed embodiment of aPD-LMBA module in accordance with the present disclosure based on a branch line coupler; and Figure 9 illustrates an equivalent circuit of thePD-LMBA module of figure 8. Figure 1 illustrates aPD-LMBA module 100 in accordance with the present disclosure. lt comprises a substrate 110, such as a printed circuit board, comprising one or more dielectric layers, a top metal layer arranged on one side of substrate 110, a bottom metal layer arranged on an opposite side of substrate 110, and optionally one or more inner metal layers arranged in between adjacent dielectric layers, if any. AnRF input signal, RFin, is input into a first splitter 121 that splits signal RFin into a first part and a second part. The first part is provided to a GalliumNitride-based field-effect power transistorQ3 that is integrated on a second semiconductor die 132. The second part is provided to second splitter 122 that splits the second part into a primary second part and a secondary second part. The primary second part is provided to a GalliumNitride-based field-effect power transistor Q1 that is integrated on a first semiconductor die 131A, whereas the secondary second part is provided to a Gallium Nitride-based field-effect power transistorQ2 that is integrated on a first semiconductor die 131B. Typically, transistors Q1 andQ2 are identical in terms ofmaximum saturated output power. In some embodiments, first semiconductor dies 131A, 131B are identical. In other embodiments, power transistors Q1 and Q2 are integrated on the same first semiconductor die. The present disclosure does neither exclude thatpower transistors Q1, Q2, Q3 are all integrated on the same semiconductor die nor that at least one power transistor has a different size and / ormaximum outputpower compared to the otherpower transistor(s). The output of the first, second, and third power transistor Q1, Q2, Q3, is connected to a respective shunt capacitive networkN1, N2, N3. In figure 1, each of these networks comprises an output capacitance of the respective power transistor Q1, Q2, Q3. These output capacitances are modelled as qu1, qu2, qu3, respectively. PD-LMBA module 100 further comprises a directional coupler 140 that has an input port P1, a through port P2, a forward coupled port P4, and a reverse coupled port P3. The output ofpower transistor Q1 is connected to through port P2 via a first matching networkM1. This latter network comprises a first shunt capacitive element C1 and a first connection 141 that connects the output ofpower transistor Q1 to through port P2. Similarly, the output ofpower transistorQ2 is connected to forward coupled port P4 via a second matching networkM2. This latter network comprises a second shunt capacitive element C2 and a second connection 142 that connects the output ofpower transistorQ2 to forward coupled port P2. In addition, the output ofpower transistorQ3 is connected to reverse coupled port P3 via a third connection 143. Input port P1 is configured to be connected to an external load (not shown). Splitters 121, 122, and directional coupler 140 may each comprise a 3dB hybrid coupler. However, in some embodiments, the coupling factor for directional coupler 140may deviate slightly from -3dB to improve reliability ofPD-LMBA module 100. First connection 141 forms, together withqu1 and C1, an equivalent for a quarter wavelength transmission line. For example, C1 may equal qu1, and first connection 141 may be inductive such that a C-L-C equivalent of a quarter wavelength transmission line is constructed. Similarly, second connection 142 forms, together withqu2 and C2, an equivalent for a quarter wavelength transmission line. For example, C2may equal qu2, and second connection 142 may be inductive such that a C-L-C equivalent of a quarter wavelength transmission line is constructed. First connection 141, second connection 142, and / or third connection 143, depend on the manner by which semiconductor dies 131A, 131B, 132 are mounted on substrate 110. In some embodiments, semiconductor dies 131A, 131B, 132 are mounted with the substrates of these dies facing substrate 110. In these embodiments, bond-wires are used for connecting power transistors Q1, Q2, Q3 to substrate 110. These bond-wires form part of connections 141, 142, 143, respectively. In other embodiments, semiconductor dies 131A, 131B, 132 are ip-chipped onto substrate 110. In these embodiments, the balls or pillars by which semiconductor dies 131A, 131B, 132 are mounted substrate 110 form part of connections 141, 142, 143, respectively. Next, several different embodiments of aPD-LMBA module in accordance with the present disclosure will be described. The description of these embodiments is limited to transistors Q1, Q2, Q3, and the circuitry that is connected to their outputs. The description ofother components, such as splitters 121, 122 is omitted. Figure 2 illustrates aPD-LMBA module 200 in accordance with the present disclosure. In this embodiment, directional coupler 140 comprises a pair ofcoupled lines. More specifically, directional coupler 140 comprises a first line 1401 and a second line 1402. First line 1401 has a first end 1401A and an opposing second end 1401B and is realized in a top metal layer of substrate 110. Second line 1402 has a first end 1402A and an opposing second end 1402B and is mostly realized in an inner metal layer of substrate 110. More specifically, the part of second line 1402 in between first end 1402A and second end 1402B is arranged directly below the corresponding part of first line 1401 and is therefore not visible in figure 2. The small, dashed part to which reference sign 1402 points, shows a segment of second line 1402 in this inner metal layer. A ground plane, not shown, is arranged on the bottom metal layer underneath lines 1401, 1402. Furthermore, a via 111 is used to make the connection between the top metal layer and the inner metal layer in which the largest part of second line 1402 is implemented. First end 1401A forms forward coupled port P4, first end 1402A input port P1, second end 1401B reverse coupled port P3, and second end 1402B through P2. The output ofpower transistor Q1, shown in figure 2 as a bond-bar B1 on semiconductor die 131A, is connected to second end 1402B using bond-wires BW1. The output is also connected, using one or more bond-wires BW4, to a bond-pad arranged on substrate 110. This bond-pad is connected to a terminal ofSMD capacitor Caux1 ofwhich the other terminal is connected to ground using a ground via 112 that connects to the ground plane or contact arranged on the backside of substrate 110. Second end 1402B is connected using bond-wiresBW7 to a bond-pad arranged substrate 110. This bond-pad is connected to a terminal ofSMD capacitor C1 ofwhich the other terminal is connected to ground using a ground via 112. Similarly, the output ofpower transistor Q2, shown in figure 2 as a bond-barB2 on semiconductor die 131B, is connected to first end 1401A using bond-wires BW2. The output is also connected, using one or more bond-wiresBW5 to a bond-pad arranged on substrate 110. This bond-pad is connected to a terminal ofSMD capacitor Caux2 ofwhich the other terminal is connected to ground using a ground via 112. First end 1401A is connected using bond-wiresBW8 to a bond-pad arranged on substrate 110. This bond-pad is connected to a terminal ofSMD capacitor C2 ofwhich the other terminal is connected to ground using a ground via 112. The output ofpower transistor Q3, shown in figure 2 as a bond-bar B3 on semiconductor die 132, is connected to second end 1401B using bond-wires BW3. The output is also connected, using one or more bond-wires BW6, to a bond-pad arranged on substrate 110. This bond-pad is connected to a series connection of anSMD inductorL4 and anSMD capacitor Cblock. Using ground via 112, this series connection is connected to ground. In figure 2, substrate 110 comprises, on its backside, pads realized in the bottom metal layer, which together with the ground plane (not shown), form a land-grid array. Figure 2 illustrates one ofthose pads, i.e. pad 113, which is connected to first end 1402A using via 112, and which forms an output ofPD-LMBA 200. More in particular, using pad 113, substrate 110 can be connected to an external load. Figure 3 illustrates an equivalent circuit ofPD-LMBA module 200. Here, inductance L1 represents bond-wires BW1, inductance L2 bond-wires BW2, and inductance L3 bond-wires BW3. Furthermore, qu1+Caux1 = C1 andqu2+Caux2 = C2. Together, qu1, Caux1, C1 and L1 form a C-L-C equivalent of a quarter wavelength transmission line that transforms a port impedance of through port P2 to an impedance Roptq1 that is to be presented at the output ofQ1 for obtaining maximum saturated output power. Similarly, together, qu2, Caux2, C2 andL2 form a C-L-C equivalent of a quarter wavelength transmission line that transforms a port impedance offorward coupled port P4 to an impedance Roptq2 that is to be presented at the output ofQ2 for obtaining maximum saturated output power. Typically, Roptq1=Roptq2. As mentioned in conjunction with figure 2, directional coupler 140 comprises a pair of coupled lines. These lines are designed such that the port impedance at each port is preferably identical and such that a coupling factor at least substantially amounts to 3dB. In figure 3, inductance L3 is ideally zero or negligible. Any non-zero contribution ofL3 could be accounted for when designing directional coupler 140. In addition, the series combination ofL4 and Cblock is inductive at the operational frequency. More specifically, the net inductance of the series combination ofL4 and Cblock resonates together withqu3 at or close to the operational frequency, thereby mitigating any adverse impact ofqu3 on performance. In the embodiment of figures 2 and 3, the output capacitances are either used, e.g. for transistors Q1 and Q2 where these capacitances are part of a matching network, or they are cancelled as with transistor Q3. Next, a possible methodology for designingPD-LMBA 200 will be described. Here, it is assumed that transistors Q1 andQ2 are identical. Furthermore, PD-LMBA 200 is capable of outputting amaximum power ofPtot and it displays an efficiency peak underX dB power back- off. For aPDLMBA, the impedance seen by transistorQ3 is substantially independent of the level of the input signal. Assuming thatL3 is negligible, the impedance seen at the output of transistorQ3 equals the port impedance, which impedance is determined by the geometry of the coupled lines. Assuming that the maximum current that can be output by a transistor scales with its size, and assuming that themaximum drain voltage swing for transistors Q1-Q3 is identical, one finds that Roptq3 = n x Roptq1, wherein Roptq3 is the impedance to be presented at the output of transistorQ3 for it to output its maximum saturated power, and wherein n is the ratio between the size of transistor Q1 and the size of transistor Q3. Furthermore, Psatq1 = n x Psatq3, wherein Psatq1 and Psatq3 are themaximum saturated outputpower of transistor Q1 and Q3, respectively. Hence, 2 x (n x Psatq3) + Psatq3 = Ptot and 10log(Psatq3 / Ptot) =-X. Accordingly, when choosing a particular value for Ptot and back-offefficiency peak X, Psatq1, Psatq2, and Psatq3 can be determined. Having determined Psatq3, impedance Roptq3 can be calculated. Furthermore, Psatq3 is related to the size of transistorQ3 which in turn is related to a capacitance qu3. This latter value determines a value for inductance L4, wherein C3 is sufficiently large to act as anRF short at the operational frequency. Directional coupler 140 can now be designed to have a port impedance equal to Roptq3 and a coupling factor of -3dB. These requirements determine the width and spacing of the coupled lines, where it is assumed that both lines are identical. Next, the matching network formed byqu1, Caux1, L1, and C1 needs to be determined. This matching network should mimic a quarter wavelength transmission line transforming Roptq3 to Roptq1. Put differently, the matching network should mimic a quarter wavelength transmission line having a characteristic impedance ZO given by ZO=(Roptq1 x Roptq3)"0.5. As Roptq1 and Roptq3 are both known, ZO can be determined. This in turn determines values for L1 and C1 using Z0 / (27tf) and 1 / (ZO27tf), respectively, wherein f is the frequency at which the matching network should mimic the quarter wavelength transformer. Once C1 is determined, Caux1 can be determined using Caux1 = C1 qu1. The value for L1 determines the number, shape, and length ofbond-wires BW1. As transistorQ2 is identical to transistor Q1, L2, C2, and Caux2 can be determined in correspondence with L1, C1, and Caux1, respectively. In some embodiments, it is possible to determine combinations ofX and Pout such that Caux1 and Caux2 can be omitted. In some embodiments, bond-wiresBW3 are part of a matching network that mimics a quarter wavelength transformer similar to the matching networks connected to the outputs of transistor Q1 and Q2. An example of such aPD-LMBA 300 is shown in figures 4 and 5, wherein figure 5 illustrates the equivalent circuit of the layout of figure 4. In figures 4 and 5, a C-L-C equivalent of a transmission line is formed by inductance L5, which is related to bond-wires BW3, in combination with qu3, Caux3, and C3. Using this matching network allows a port impedance different from Roptq3 to be used for directional coupler 140. This in turn allows a different impedance matching to be used in the matching networks connected to the outputs of transistors Q1, Q2. In some embodiments, the matching network connected to the output of transistorQ3 is chosen such that Caux1=Caux2=0. Figure 5 further illustrates how an external load with impedanceZL is connected to input port P1 through an impedance inverter TL4. This latter impedance inverter matches the port impedance ofport P1, e.g. Roptq3, to impedance ZL. Impedance inverter TL4, which may incorporate one or more quarter wavelength transmission line segments, may be part ofPD-LMBA 300 and can for example be implemented substrate 110. Figure 6 illustrates aPD-LMBA module 400 and figure 7 illustrates the corresponding equivalent circuit. InPD-LMBA module 400, directional coupler 140 is formed as a branch line coupler. This coupler comprises a first transmission line TL1, a second transmission line TL2, and a third transmission line TL3 all having a length corresponding to a quarter wavelength.A second end of first transmission line TL1 is connected to a first end of second transmission line TL2 in a connecting region C01. This connecting region forms input port P1. Similarly, a first end of first transmission line TL1 is connected to a first end of third transmission line TL3 in a connecting regionCO3 that forms through port P2. The characteristic impedance oftransmission lines TL2 and TL3 is a square root oftwo times that of first transmission line TL1. Furthermore, the port impedance at each port ofthe branch line coupler equals the characteristic impedance of transmission lines TL2, TL3, which impedance is equal to Roptq3. Similar toPD-LMBA module 200, transistor Q1 is connected to through port P2 through a matching network formed by bond-wires BW1, C1, Caux1, and qu1. Similarly, transistorQ2 is connected to forward coupled port P4 through a matching network formed by bond-wires BW2, C2, Caux2, andqu2. The fourth transmission line ofthe branch line coupler is formed using qu3. More in particular, the output of transistorQ3 is connected using bond-wiresBW9 to a bond-pad that in turn is connected to anSMD inductor L6. The output of transistorQ3 is further connected using bond-wiresBW6 to a bond-pad that is connected to a shuntSMD capacitor Caux3. Together, SMD inductor L6, capacitance qu3, Caux3, and part ofcapacitance C2* form an equivalent of a quarter wavelength transmission line having a characteristic impedance equal to that of first transmission line TL1. The remaining part of capacitance C2* forms, together with qu2, Caux2, and inductance L2 associated with bond-wires BW2, an equivalent of a quarter wavelength transmission line that transforms the port impedance of the branch line coupler, which equals Roptq3, to Roptq1. The inductance associated with bond-wires BW3, modelled as inductor L7 in figure 5, can be accounted for when designing transmission line TL2. In the embodiment shown in figure 6, transmission lines TL1, TL2, TL3, are realized on a ceramic die 450. Such die allows for lower losses in transmission lines TL1, TL2, TL2, compared to embodiments in which these transmission lines are realized on substrate 110. Next, a possible methodology for designingPD-LMBA 400 will be described referring to figure 7, wherein capacitorC2* is split into its constituents C2 and C4. Furthermore, it is assumed that transistors Q1 and Q2 are identical and thatPD-LMBA400 is capable of outputting a maximum power of Ptot while displaying an efficiency peak underX dB power back-off. Roptq3, Ropt1, and Ropt2 can be determined as described in relation toPD-LMBA 200. Roptq3 should correspond to the port impedance of the reverse coupled port, which in turn equals the characteristic impedance oftransmission lines TL2, TL3. The characteristic impedance of transmission line TL1 can then be found by using Roptq3 / sqrt(2). Roptq3 is also the characteristic impedance of the transmission line that is mimicked by Caux3, qu3, C4, and L6. More specifically, Roptq3 determines the values for Caux3, L6, and C4. As described before, Roptq3 determines qu1, Caux1, L1, and C1, and determines qu2, Caux2, L2, and C2 as described before. Hence, in figures 6 and 7, capacitor C2* is a combined capacitor in the sense that it contributes to the equivalent of the transmission line in between ports P4 and P3 of the branch line coupler and to the equivalent of the transmission line in between the output of transistorQ2 and forward coupled port P4. In some embodiments, bond-wiresBW3 are part of a matching network that mimics a quarter wavelength transmission line similar to the matching networks connected to the outputs of transistor Q1 and Q2. An example of such aPD-LMBA 800 is shown in figures 8 and 9, wherein figure 9 illustrates the equivalent circuit of the layout of figure 8. In figures 8 and 9, a C-L-C equivalent of a transmission line is formed by inductance L5, which is related to bond-wires BW3, in combination with qu3, Caux3, and C3. Using this matching network allows a port impedance different from Roptq3 to be used for directional coupler 140. This in turn allows a different impedance matching to be used in the matching networks connected to the outputs of transistors Q1, Q2. In some embodiments, the matching network connected to the output of transistorQ3 is chosen such that Caux1=Caux2=0. C5 forms together withL6 and C4 a C-L-C equivalent of a quarter wavelength transmission line with a characteristic impedance equal to that of transmission line TL1. Similar to capacitors C2 and C4, capacitors C3 and C5 can form constituents of a single capacitor C3*. In the embodiments above, PD-LMBAs 200, 300, 400, 500 were described in which a given total power and back-off efficiency peak position were taken as design goals. In other embodiments, the total power is taken as a design goal and the size ratio between transistors Q1, Q2 and transistorQ3 is chosen such that Caux1=Caux2=0, such that Caux3=0, or such that Caux1=Caux2=Caux3=0. The scope of the present disclosure includes any novel feature or combination of features disclosed therein either explicitly or implicitly or any generalization thereof irrespective ofwhether or not it relates to the claimed invention or mitigate against any or all of the problems addressed by the present invention. The applicant hereby gives notice thatnew claims may be formulated to such features during prosecution of this application or of any such further application derived therefrom. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in specific combinations enumerated in the claims. Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub combination. The term comprising does not exclude other elements or steps, the term a or an does not exclude a plurality.

Claims

1. Pseudo-Doherty load-modulated balanced amplifier (EN: Pseudo Doherty load-modulated balanced amplier, PDLMBA ) -m0dule (100; 200; 300; 400; 500) configured for amplifying an input RF signal (RFin) and for providing the amplified input RF signal to an external load (ZL), thePD-LMBA (100; 200; 300; 400; 500) comprising: a substrate (110); a balanced amplifier comprising one or more first semiconductor dies (131A, 131B) mounted on the substrate (110) and on which a first power transistor (Q1) and a the second power transistor (Q2) is integrated, further comprising the balanced amplifier a first matching network (M1) (EN: matching network), a second matching network (M2), and a transmission line-based directional coupler (140) for combining a signal amplified by the first power transistor (Q1) and a signal amplified by the second power transistor (Q2), where the directional coupler (140) a multiple of includes transmission lines which are integrated on the substrate (110) or on a ceramic that (450) or semiconductor - that which is mounted on the substrate (110); a second semiconductor (132) on which a third power transistor (Q3) is integrated is, where the second semiconductor (132) is mounted on the substrate (110), and where a third shunt-capacitive network (N3) is present at an output of the third power transistor (Q3) which includes an output capacity (qu3) of the third power transistor (Q3); where the directional coupler (140) has an input port (P1) which is configured to to be connected to the external load (ZL), a backward coupled port (P3) connected to an output of the third transistor (Q3) by means of a third connection (143), a throughport (P2) (EN: a throughport ), and a forward-coupled port (P4); and where the first matching network (M1) is a first shunt capacitive element (C1) comprises of which an ungrounded terminal is connected to the pass-through port (P2) and a first connection (141) which is an output of the first power transistor (Q1) with pass-through gate (P2) connects; where the second matching network (M2) a second shunt-capacitive element (C2) includes one of which is an ungrounded terminal connected to the forward-linked port (P4) and a second connection (142) which connects an output of the second power transistor (Q2) to the forward coupled port (P4) connects; and where the first connection (141), second connection (142), and third connection (143) each one or more bond wires (BW1, BW2, BW3) comprise or an IP chip connection in combination with a transmission line arranged on the substrate (110).

2. PD-LMBA module (100; 200; 300; 400; 500) according to claim 1, where the first adaptation network (M1) is configured for forming, together with a first shunt- capacitive network (N1) present at the output of the first power transistor (Q1), of a electrical equivalent of a quarter-go length transmission line, where the first shunt-capacitive network (N1) includes an output capacitor (qu1) of the first power transistor (Q1); and where the second adaptation network (M2) is configured to form, together with a second shunt-capacitive network (N2) present at the output of the second power transistor (Q2), of an electrical equivalent of a quarter-go length transmission line, where the second shunt-capacitive network (N2) an output capacitance (qu2) of the second power transistor (Q2) includes.

3. PD-LMBA module (100; 200; 300; 400; 500) according to claim 1, further comprising a first splitter (121) and a second splitter (122); where the first splitter (121) is configured to split the input RF signal into a first part which must be fed to the third power transistor (Q3) and a second part which must be supplied to the second splitter (122); where the second splitter (122) is configured to split the second part into a primary second part which must be fed to the first power transistor (Q1) and a secondary second part which must be supplied to the second power transistor (Q2); where the first splitter (121) and the second splitter (122) each preferably a directional include coupler, such as a hybrid coupler.

4. PD-LMBA module (100; 200; 300; 400; 500) according to one of the preceding conclusions, where the third power transistor (Q3) is configured to perform saturated power when presented with a first impedance at its output at a predefined power back-off level of the PD-LMBA module (100; 200; 300; 400; 500).

5. PD-LMBA module (100; 200; 300; 400; 500) according to claim 4, where a port impedance of the backward coupled port (P3) corresponds to the first impedance.

6. PD-LMBA module (300; 500) pursuant to claim 4, further comprising a third matching network arranged between the backward-coupled port (P3) and the output of the third power transistor (Q3), the third matching network comprising the third connection (143) and a third shunt capacitive element (C3) to which an ungrounded terminal is connected with the backward-linked port (P3), where the third adaptation network is configured for forming, together with the third shunt-capacitive network (N3), an electrical equivalent of a quarter-go length transmission line.

7. PD-LMBA module (300; 500) according to claim 6, where the third the matching network and the third shunt-capacitive network (N3) are configured to a to convert the port impedance of the backward-coupled port (P3) to the first impedance.

8. PD-LMBA module (100; 200; 300; 400; 500) according to one of the preceding conclusions, where the first power transistor (Q1) and second power transistor (Q2) each be configured to output saturated power when each is presented with a second impedance during their execution at a maximum power level of the PD- LMBA module (100; 200; 300; 400; 500), where the first matching network (M1) and the first shunt-capacitive network (N1) configured for converting a gate impedance from the pass-through gate (P2) to the second impedance, and where the second matching network (M2) and the second shunt-capacitive network (N2) are each configured to convert a gate impedance from the forward-coupled gate (P4) to the second impedance.

9. PD-LMBA module (100; 200; 300; 400; 500) according to one of the preceding conclusions, where each port (P1, P2, P3, P4) of the directional coupler (140) has the same has port impedance.

10. PD-LMBA module (200; 300; 400; 500) according to one of the preceding conclusions, whereby the first shunt-capacitive network (N1) further a first aid shunt capacitive element (Cauxl) comprises which is parallel to the output capacity (qu1) of the first power transistor (Q1) is arranged; and / or where the second shunt-capacitive network (N2) further a second auxiliary shunt capacitive element (Caux2) comprises which is parallel to the output capacity (qu2) of the second power transistor (Q2) is arranged; and / or where the third shunt-capacitive network (N3) further a third auxiliary shunt-capacitive element (Caux3) comprises which parallel to the output capacity (qu3) of the third power transistor (Q3) is arranged.

11. PD-LMBA module (100; 200; 300; 400; 500) according to one of the preceding conclusions, where at least one of the first shunt-capacitive element (C1), first aid- shunt-capacitive element (Caux1), the second shunt-capacitive element (C2), the second auxiliary shunt-capacitive element (Caux2), the third shunt-capacitive element (C3), and the third auxiliary shunt-capacitive element (Caux3), a surface-mounted device (EN: surface-mounted device) -capacitor comprises which is mounted on the substrate, or a capacitor which is integrated on a ceramic die or semiconductor die which is mounted on the substrate (1 10).

12. PD-LMBA module (400; 500) according to one of the preceding claims, where the directional coupler (140) is a branch line coupler includes 13. PD-LMBA module (400; 500) according to claim 12, where the directional coupler (140) includes: a first transmission line (TL1) with a first characteristic impedance; a second transmission line (TL2) and a third transmission line (TL3), each with a second characteristic impedance, where a length of the first, second, and third transmission lines (TL1, TL2, TL3) correspond to a quarter-go length, and where the second characteristic impedance corresponds to 1 / 2 times the first characteristic impedance; where a second end of the first transmission line (TL1) is connected to a first end of the second transmission line (TL2) in a first connection area (C01), where the first connection area (C01) forms the entry port (P1) and / or is connected to it; where a first end of the first transmission line (TL1) is connected to a first end of the third transmission line (TL3) in a second link area (CO2), where the second connection area (CO2) forms the gateway (P2) and / or is connected to it; where the directional coupler further comprises a branch network between the forward coupled port (P4) and the backward coupled port (P3), where the branch network includes a fourth shunt-capacitive element (C4) which is arranged in parallel to the second shunt capacitive element (C2) and a series inductive element (L6); where an ungrounded terminal of the fourth shunt-capacitive element (C4) the forms and / or is connected to a forward coupled port (P4).

14. PD-LMBA module (400) under claim 13, insofar as dependent on conclusion 5, where the output of the third power transistor (Q3) is the backward-coupled forms port (P3) and / or is connected to it; where the branch network and the third shunt-capacitive network (N3) jointly form an equivalent of a quarter-go length transmission line of which a characteristic impedance corresponds to the first characteristic impedance.

15. PD-LMBA module (500) under claim 13, insofar as dependent on conclusion 6, where the ungrounded terminal of the third shunt-capacitive element (C3) the forms and / or is connected to the backward coupled port (P4), the directional coupler (140) further comprising a fifth shunt capacitive element (C5) of which an ungrounded terminal is connected to the backward-linked port (P3); where the branch network and the fifth shunt-capacitive element (C5) together form an equivalent of a quarter-go length transmission line of which a characteristic impedance corresponds to the first characteristic impedance.

16. PD-LMBA module (500) according to claim 15, where the third shunt- capacitive element (C3) and fifth shunt-capacitive element (C5) are combined in a single Combined third shunt capacitor (C3*).

17. PD-LMBA module (400; 500) according to one of the claims 13-16, where the second shunt-capacitive element (C2) and fourth shunt-capacitive element (C4) combined are in a single combined second shunt capacitor (C2*).

18. PD-LMBA module (400; 500) according to one of the claims 13-17, where the series inductive element (L6) a surface-mounted device, SMD, -inductor which comprises arranged on the substrate (110).

19. PD-LMBA module (400; 500) according to one of the claims 13-18, where the second shunt-capacitive element (C2), the fourth shunt-capacitive element (C4), the aforementioned single second shunt-capacitive element (C2*), the third shunt-capacitive element (C3), the fifth shunt-capacitive element (C5), and / or the said single third shunt-capacitive element (C3*), a surface-mounted device capacitor arranged on the substrate (110) or a capacitor which is integrated on a ceramic die or semiconductor die which arranged on the substrate (110).

20. PD-LMBA module (400; 500) according to one of the claims 13-19, where the first transmission line (TL1), second transmission line (TL2), and third transmission line (TL3) be integrated on a ceramic die (450) or a semiconductor die which is mounted on the substrate (110).

21. PD-LMBA module (200; 300) according to one of claims 1-11, where the multiple transmission lines of the directional coupler (140) a first transmission line (1401) comprises with a first end (1401A) and an opposite second end (1401B), and a second transmission line (1402) with a first end (1402A) and an opposite second end (1402B), where the first transmission line (1401) is capacitively and / or inductively coupled to the second transmission line (1402); where the first end (1401A) of the first transmission line (1401) is the forward forms and / or is connected to coupled port (P4); where the second end (1402B) of the second transmission line (1402) is the pass-through port (P2) forms and / or is connected with; where the second end (1401B) of the first transmission line (1401) is the reverse forms and / or is connected to coupled port (P3); and where the first end (1402A) of the second transmission line (1402) is the input port (P1) forms and / or is connected with it.

22. PD-LMBA module (200; 300) according to claim 21, where the first ends (1401A, 1402A) of the first and second transmission lines (1401, 1402) lie next to each other, and where the second ends (1401B, 1402B) of the first and second transmission lines (1401, 1402) lie side by side.

23. PD-LMBA module (200) under claim 20 or 21, insofar as dependent on conclusion 5, further comprising a further shunt network connected to the output of the third power transistor (Q3) and comprising a series connection of an inductor (L4) and capacitor (Cblock), where, at or near an operating frequency, the further shunt network resonates with the output capacity (qu3) of the third power transistor (Q3).

24. PD-LMBA module (200) according to claim 23, where the inductor of the further shunt network comprises a first inductive element from the group consisting of a transmission line integrated on the substrate (110), a surface-mounted device-inductor mounted on the substrate (110), and a transmission line integrated on a ceramic or semiconductor that which is mounted on the substrate (110).

25. PD-LMBA module (100; 200; 300; 400; 500) according to one of the preceding conclusions, where the directional coupler (140) is a hybrid coupler.

26. PD-LMBA module pursuant to one of the preceding claims, where the first power transistor (Q1) and second power transistor (Q2) at least substantially identical be and / or are integrated on the same first semiconductor die.

27. PD-LMBA module (100; 200; 300; 400; 500) according to one of the preceding conclusions, where a maximum saturated power that can be performed by the first, second, and third power transistors (Q1, Q2, Q3) correspond to a ratio n:n: 1, where n lies in a range between 1 and 5.

28. PD-LMBA module (100; 200; 300; 400; 500) according to one of the preceding conclusions, where at least one of the first, second, and third power transistors (Q1, Q2, Q3) includes a Gallium Nitride-based transistor such as a field-effect transistor, or one based on Silicon-based laterally diffused metal-oxide semiconductor transistor.

29. PD-LMBA module (100; 200; 300; 400; 500) according to one of the preceding conclusions, where the substrate comprises one or more dielectric layers of which at least one both sides thereof are provided with one or more conductive layers; where the substrate preferably comprises a printed circuit board or other laminated substrate.

30. Mobile telecommunications base station comprising the PD-LMBA (100; 200; 300; 400; 500) according to one of the preceding conclusions.

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