High-speed buffer amplifier
Patent Information
- Authority / Receiving Office
- RU · RU
- Patent Type
- Patents
- Current Assignee / Owner
- FEDERALNOE GOSUDARSTVENNOE BYUDZHETNOE OBRAZOVATELNOE UCHREZHDENIE VYSSHEGO OBRAZOVANIYA DONSKOJ GOSUDARSTVENNYJ TEKHNICHESKIJ UNIV DGTU
- Filing Date
- 2025-10-24
- Publication Date
- 2026-06-30
AI Technical Summary
Existing push-pull buffer amplifier circuits fail to provide high-speed response when handling large negative pulse input signals due to parasitic capacitance issues.
Incorporating an additional transistor with a correction capacitor into the circuit design to accelerate the recharging of parasitic capacitance, specifically targeting the base circuit of a bipolar transistor.
The design significantly enhances the maximum rate of output voltage fall by over 300 times for negative pulse signals while maintaining high-speed response for positive pulses.
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Abstract
Description
[0001] The proposed invention relates to the microelectronic element base of communication systems, computing technology, instrument making and automation, including those operating at high temperatures due to the use of wide-bandgap semiconductors.
[0002] A significant number of push-pull buffer amplifier (BU) circuits with input field-effect transistors are known [1-6], the implementation of which is possible on silicon or gallium arsenide pn-p bipolar transistors and n-channel field-effect JFet transistors [7-10].
[0003] The closest prototype of the claimed device is a buffer amplifier (Fig. 1), presented in patent RU 2784046, 2022. It contains an input 1 and an output 2 of the device, an input field-effect transistor 3, the gate of which is connected to the input 1 of the device, the drain is matched with the first 4 bus of the power source, and the source is connected to the emitters of the first 5 and second 6 bipolar transistors, the bases of which are combined and connected to the collector of the first 5 bipolar transistor and the output 2 of the device, wherein the collector of the second 6 bipolar transistor is connected to the base of the third 7 bipolar transistor and is connected to the second 8 bus of the power source through the reference current source 9, the emitter of the third 7 bipolar transistor is connected to the output 2 of the device, and its collector is connected to the second 8 bus of the power source.
[0004] A significant drawback of the prototype BU is that it does not provide high speed response when working with large pulse input signals of negative polarity.
[0005] The main objective of the proposed invention is to increase the maximum rate of rise of the output voltage (SR (-) ) when working with large negative pulse input signals. At the same time, a high SR level is maintained (+) when working with positive pulse input signals.
[0006] The stated task is achieved in that in the buffer amplifier of Fig. 1, containing an input 1 and an output 2 of the device, an input field-effect transistor 3, the gate of which is connected to input 1 of the device, the drain is matched with the first 4 bus of the power supply, and the source is connected to the emitters of the first 5 and second 6 bipolar transistors, the bases of which are combined and connected to the collector of the first 5 bipolar transistor and the output 2 of the device, wherein the collector of the second 6 bipolar transistor is connected to the base of the third 7 bipolar transistor and is connected to the second 8 bus of the power supply through a reference current source 9, the emitter of the third 7 bipolar transistor is connected to the output 2 of the device, and its collector is connected to the second 8 bus of the power supply, new elements and connections are provided - an additional transistor 10 is introduced into the circuit, the base of which is connected to input 1 of the device,the emitter is connected to the first 4 bus of the power supply through an additional reference current source 11 and is connected to the base of the third 7 bipolar transistor through an additional correction capacitor 12, wherein the collector of the additional transistor 10 is matched with the second 8 bus of the power supply.,
[0007] The drawing in Fig. 1 shows a diagram of a gallium arsenide buffer amplifier - a prototype according to patent RU 2784046, 2022.
[0008] The drawing Fig. 2 shows a circuit diagram of the claimed buffer amplifier in accordance with paragraph 1 of the claims.
[0009] The drawing in Fig. 3 shows an example of constructing the claimed buffer amplifier on complementary transistors for the case when the input JFET transistor is replaced by an equivalent bipolar n-p-n transistor
[11] .
[0010] The drawing in Fig. 4 shows the static mode of the control unit in Fig. 2 in the LTSpice environment on the CJFET3+ABMK-2.2-1 transistor models at t=27°C and parasitic capacitance C p1 =l pF.
[0011] The drawing in Fig. 5 shows the trailing edge of the transient process of the control unit in Fig. 4 at t=27°C and different values of the capacitance of the correction capacitor C к1 =0 pF / 0 pF.
[0012] The high-speed buffer amplifier of Fig. 2 comprises an input 1 and an output 2 of the device, an input field-effect transistor 3, the gate of which is connected to the input 1 of the device, the drain is matched with the first 4 bus of the power supply, and the source is connected to the emitters of the first 5 and second 6 bipolar transistors, the bases of which are combined and connected to the collector of the first 5 bipolar transistor and the output 2 of the device, wherein the collector of the second 6 bipolar transistor is connected to the base of the third 7 bipolar transistor and is connected to the second 8 bus of the power supply through a reference current source 9, the emitter of the third 7 bipolar transistor is connected to the output 2 of the device, and its collector is connected to the second 8 bus of the power supply.An additional transistor 10 is introduced into the circuit, the base of which is connected to input 1 of the device, the emitter is connected to the first 4 bus of the power supply through an additional reference current source 11 and is connected to the base of the third 7 bipolar transistor through an additional correction capacitor 12, and the collector of the additional transistor 10 is matched to the second 8 bus of the power supply. Two-terminal R. H in the diagram of Fig. 2 models the properties of the load.
[0013] Let's consider the operation of the proposed control unit, Fig. 2.
[0014] If a high-amplitude pulsed positive signal is supplied to input 1, it is transmitted with a minimum delay to the source of the input field-effect transistor 3 and then through the emitter p-n junction of the first 5 bipolar transistor to the load circuit R H In this mode, the control unit under consideration has a high response speed. The maximum positive output current in the load is I (+) н.max will be equal to:
[0015] I (+)н.max =I c2.max ,
[0016] I c2.max - maximum drain current of the input field-effect transistor 3.
[0017] With negative input pulse signals, the transient processes in the BU prototype (Fig. 1) are influenced by the parasitic capacitance C р in the base circuit of the third 7 bipolar transistor. In this case, the maximum possible recharging current of the capacitor C р cannot be greater than:
[0018] I (-) cp ,
[0019] I9- static current of reference current source 9.
[0020] In the claimed control unit (Fig. 2), a large negative pulse signal is transmitted to the emitter of the additional transistor 10 and then to the base of the third bipolar transistor 7. If the capacitance of the additional correction capacitor 12 is selected to be significantly greater than the capacitance of the parasitic capacitor C р, then the additional correction capacitor 12 significantly accelerates the process of recharging this parasitic capacitance. Thus, the maximum rate of "fall" of the output voltage (SR (-) ) the trailing edge of the transient process in the control unit of Fig. 2 with an input voltage amplitude of 3 V at zero capacitance of the correction capacitor 12 (C к1 =0 pF):
[0021]
[0022] where U вых.max - maximum signal amplitude at the BU output.
[0023] If the correction capacitor C к1 =10 pF, then the trailing edge of the transient process of the control unit in Fig. 4 with an input voltage amplitude of 3 V is equal to
[0024] Therefore, the proposed design of the control unit ensures that the maximum output voltage fall rate for the trailing edge increases by more than 300 times.
[0025] The drawing in Fig. 3 shows an example of the construction of the claimed control unit on complementary transistors for the case when the input field-effect transistor 3 is replaced by a bipolar npn transistor in accordance with the recommendations
[11] . This makes it possible to implement the circuit of the proposed control unit within the framework of the technological processes mastered in Russia, containing only bipolar pn-p and npn transistors.
[0026] Thus, the claimed high-speed control unit has significant advantages in comparison with the prototype control unit.
[0027] BIBLIOGRAPHICAL LIST
[0028] 1. Dvornikov O.V., Pavlyuchik A.A., Prokopenko N.N., Chekhovsky V.A., et al. Unified circuit design solutions for analog gallium arsenide microcircuits / / News of universities. Electronics. - 2022. - Vol. 27. - No. 4. - P. 475-488. - DOI: https: / / doi.org / 10.24151 / 1561-5405-2022-27-4-475-488, Fig. 7.
[0029] 2 Chumakov V., Pakhomov I., Klejmenkin DV, Kunts A. Gallium arsenide buffer amplifier: preprint / / TechRxiv [PubMed] https: / / doi.org / 10.36227 / techrxiv.17194979.v1
[0030] 3 Price RU 2767976, 2022 Pl.
[0031] 4 Price RU 2766868, 2022 Pl.
[0032] 5 Price RU 2784046, 2022 Pl.
[0033] 6 Price RU 2796638, 2023 г.
[0034] 7 Zampardi PJ, Sun M., Cismaru C, Li J. Prospects for a BiCFET III-V HBT Process / / Compound Semiconductor Integrated Circuit Symposium (CSICS). - 2012. - Pp. 1-3
[0035] 8 Sun, M., Li, J., Zampardi, PJ, Ramanathan, R., Metzger, AG, Cismaru, С, Но, V., Rushing, L., Stevens, KS, Chaplin, M., & Welser, RE 24-27, 2006, Vancouver, British Columbia, Canada, pp. 24-27. 149-152.
[0036] 9. SC Cheng, JT Chung, SH Tsai, FH Huang, S.K. Lin, D. Williams, and Y. C. Wang, “Advanced BiHEMT Technology with 0.25um Enhancement Mode pHEMT for 5G Sub-6GHz Power Amplifier Applications,” IEEE Journal of the Electron Devices Society, vol. 9, pp. 734-740, 2021, DOI: 10.1109 / JEDS.2021.3097193.
[0037] 10. Dvornikov O.V., Pavlyuchik A.A., Prokopenko N.N., Chekhovsky V.A., Kunz A.V., Chumakov V.E. Gallium arsenide analog base crystal / / Problems of developing promising micro- and nanoelectronic systems - 2021. Collection of works / edited by Academician of the Russian Academy of Sciences A.L. Stempkovsky. Moscow: IPPM RAS. - 2021. - P. 47-54.
[0038] 11. Horowitz P., Hill W. The Art of Circuit Design: Trans. from English. - 2nd ed. - Moscow: BINOM Publishing House. - 2014. - 704 p.
Claims
A high-speed buffer amplifier comprising an input (1) and an output (2) of a device, an input field-effect transistor (3) whose gate is connected to the input (1) of the device, the drain is matched with the first (4) bus of the power supply, and the source is connected to the emitters of the first (5) and second (6) bipolar transistors, the bases of which are combined and connected to the collector of the first (5) bipolar transistor and the output (2) of the device, wherein the collector of the second (6) bipolar transistor is connected to the base of the third (7) bipolar transistor and is connected to the second (8) bus of the power supply through a reference current source (9), the emitter of the third (7) bipolar transistor is connected to the output (2) of the device, and its collector is connected to the second (8) bus of the power supply, characterized in that an additional transistor (10) is introduced into the circuit, the base of which is connected to the input (1) of the device,the emitter is connected to the first (4) power supply bus via an additional reference current source (11) and is connected to the base of the third (7) bipolar transistor via an additional correction capacitor (12), wherein the collector of the additional transistor (10) is matched with the second (8) power supply bus.,