Multibit multi-height cell to improve pin accessibility

Abstract

A MOS IC includes a MOS logic cell that includes first and second sets of transistor logic in first and second subcells, respectively. The first and second sets of transistor logic are functionally isolated from each other. The MOS logic cell includes a first set of M xlayer interconnects on an M xlayer extending in a first direction over the first and second subcells. A first subset of the first set of M xlayer interconnects is coupled to inputs / outputs of the first set of transistor logic in the first subcell and is unconnected to the second set of transistor logic. Each of the first subset of the first set of M xlayer interconnects extends from the corresponding input / output of the first set of transistor logic of the first subcell to the second subcell, and is the corresponding input / output of the first set of transistor logic.

Description

[Technical Field]

[0001] This application claims the benefit of U.S. Patent Application No. 17 / 030,087, filed on September 23, 2020, entitled “MULTIBIT MULTI-HEIGHT CELL TO IMPROVE PIN ACCESSIBILITY”, which is expressly incorporated herein by reference in its entirety.

[0002] This disclosure generally relates to standard / logic cell architectures, and more specifically, to multi-bit, multi-height cells for improving pin accessibility. [Previous Technology]

[0003] Standard cell devices are integrated circuits (ICs) that implement digital logic. Such standard cell devices can be reused multiple times within application-specific integrated circuits (ASICs). ASICs such as system-on-a-chip (SoC) devices can contain thousands to millions of standard cell devices. Typical ICs consist of a stack of layers formed sequentially. Each layer can be stacked or overlaid on the previous layer and patterned to define the shape of transistors (e.g., field-effect transistors (FETs) and / or finned FETs (FinFETs)) and to connect the transistors to the circuitry.

[0004] When cell pins are close together (such as in high pin density cells), cell routing can become congested. To reduce congestion, some cells may need to be placed further apart from each other. As a result, cell placement density may decrease, and larger IC area / footprint may be required. Therefore, there is a need for a cell architecture that improves pin accessibility without requiring ICs with larger area / footprints. [Summary of the Invention]

[0005] In one aspect of this disclosure, a metal-oxide-semiconductor (MOS) IC includes a MOS logic cell. The MOS logic cell includes a first transistor logic set in a first sub-cell of the logic cell and a second transistor logic set in a second sub-cell of the logic cell. The first and second transistor logic sets are functionally isolated from each other within the MOS logic cell. The MOS logic cell also includes a first Mx layer interconnect set on an Mx layer, the first Mx layer interconnect set extending over the first and second sub-cells in a first direction. A first subset of the first Mx layer interconnect set is coupled to an input or output of the first transistor logic set in the first sub-cell, and the first subset of the first Mx layer interconnect set is not connected to the second transistor logic set. Each Mx layer interconnect in the first subset of the first Mx layer interconnect set extends from an input or output of the first transistor logic set in the first sub-cell to the second sub-cell. Each Mx layer interconnect in the first subset of the first Mx layer interconnect set is an input / output of the first transistor logic set.

Implementation Method

[0013] The specific embodiments described below with reference to the drawings are intended as descriptions of various configurations and are not intended to represent the only configuration in which the concepts described herein can be practiced. The specific embodiments include particular details for providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, known structures and components are shown in block diagram form to avoid obscuring these concepts. Apparatus and methods will be described in the following specific embodiments and can be illustrated in the drawings through various blocks, modules, components, circuits, steps, processes, algorithms, elements, etc.

[0014] FIG1 is a first figure 100, which is a side view illustrating a standard cell and various layers within an IC. The various layers change in the y-direction. As shown in FIG1, the transistor has a gate 102 (which may be referred to as POLY, even if the gate may be formed of metal, polysilicon, or a combination of polysilicon and metal), a source 104, and a drain 106. The source 104 and drain 106 may be formed by fins. The gate 102 may extend in a first direction (e.g., a direction perpendicular to the z-axis away from the page), and the fins may extend in a second direction orthogonal to the first direction (e.g., a horizontal direction along the x-axis). A contact layer interconnect 108 (also referred to as a metal POLY (MP) layer interconnect) may contact the gate 102. A contact layer interconnect 110 (also referred to as a metal diffused (MD) layer interconnect) may contact the source 104 and / or the drain 106. A via 112 may contact the layer interconnect 110. A metal I (M1) layer interconnect 114 may contact the via 112. M1 layer interconnect 114 may extend only in the first direction or only in the second direction (i.e., unidirectional in either the first or second direction). M1 layer interconnect 114 is illustrated as extending unidirectionally in the second direction. Via V1 116 may contact M1 layer interconnect 114. Metal 2 (M2) layer interconnect 118 may contact via V1 116. M2 layer interconnect 118 may extend only in the first direction (i.e., unidirectional in the first direction). Specifically, the M2 layer may be unidirectional in the vertical direction. The higher layers include a via layer containing via V2 and a metal 3 (M3) layer containing M3 layer interconnects. The M3 layer interconnects may extend in the second direction.

[0015] FIG2 is a second figure 200, which is a side view illustrating a standard cell and various layers within an IC. The various layers change in the y-direction. As shown in FIG2, the transistor has a gate 202, a source 204, and a drain 206. The source 204 and drain 206 may be formed by fins. The gate 202 may extend in a first direction (e.g., a direction perpendicular to the z-axis away from the page), and the fins may extend in a second direction orthogonal to the first direction (e.g., a horizontal direction along the x-axis). Layer interconnect 208 may contact the gate 202. Layer interconnect 210 may contact the source 204 and / or the drain 206. Via 212 may contact the layer interconnect 208. M1 layer interconnect 214 may contact the via 212. M1 layer interconnect 214 may extend only in the first direction or only in the second direction (i.e., unidirectional in the first or second direction). M1 layer interconnect 214 is illustrated as extending unidirectionally in the second direction. Via V1 216 can contact M1 layer interconnect 214. M2 layer interconnect 218 can contact via V1 216. M2 layer interconnect 218 can extend only in a first direction (i.e., unidirectionally in the first direction). Specifically, the M2 layer can be unidirectional in the vertical direction. Higher layers include a via layer containing via V2 and an M3 layer containing M3 layer interconnect. The M3 layer interconnect can extend in a second direction.

[0016] A standard cell is a cell standardized in a design. The same standard cell can be used thousands of times throughout an IC. In this document, a standard cell may be referred to as a logic cell. A logic cell has a set of inputs and a set of outputs, wherein the transistor logic between the inputs and outputs is interconnected through inter-cell wiring within the logic cell (rather than intra-cell wiring across different logic cells). Using the same inter-cell wiring configuration, such a logic cell can be used hundreds to thousands of times in an IC.

[0017] As mentioned above, when cell pins are close together (e.g., in high pin density cells), cell routing can become congested. To reduce congestion, some cells can be placed further apart from each other. Therefore, cell placement density may be reduced, and larger IC area / pin pads may be required. The following provides a cell architecture that improves pin accessibility without requiring ICs with larger area / pin pads.

[0018] Figure 3 is a conceptual illustration of a first figure 300 of a multi-bit, multi-height unit for improving pin routing accessibility and pin routing congestion. Four individual units 310 include unit 1, unit 2, unit 3, and unit 4. Unit 1 has inputs a1, b1, and output z1. Unit 2 has inputs a2, b2, and output z2. Unit 3 has inputs a3, b3, and output z3. Unit 4 has inputs a4, b4, and output z4. Input / output pins are illustrated using small circles. After units 1 to 4 are placed, the pins of units 1 to 4 are routed through in-unit wiring to other pins of other units (units other than units 1 to 4). To illustrate possible routing collisions 312 to 328 during the intra-cell routing phase, intra-cell M2 layer interconnects (extending in the first direction) and intra-cell M3 layer interconnects (extending in the second direction) for each pin can be illustrated, even though it is possible to actually use only one of the intra-cell M2 layer interconnects or intra-cell M3 layer interconnects. As shown in Figure 3, the M3 layer interconnect for the in-cell routing of inputs a1 and a3 may have routing conflicts 312, the M3 layer interconnect for the in-cell routing of inputs b1 and b3 may have routing conflicts 314, the M3 layer interconnect for the in-cell routing of outputs z1 and z3 may have routing conflicts 316, the M2 layer interconnect for the in-cell routing of outputs z3 and b4 may have routing conflicts 318, the M3 layer interconnect for the in-cell routing of inputs b2 and a4 may have routing conflicts 320, the M3 layer interconnect for the in-cell routing of outputs z2 and b4 may have routing conflicts 322, the M2 layer interconnect for the in-cell routing of outputs z1 and z2 may have routing conflicts 324, the M2 layer interconnect for the in-cell routing of inputs a1 and a2 may have routing conflicts 326, and / or the M2 layer interconnect for the in-cell routing of inputs b1 and b2 may have routing conflicts 328.

[0019] To improve pin accessibility of wiring within a cell, four cells 1 to 4 can be combined into a multi-row (multi-bit) cell 330 of the MOS IC 398, wherein each cell 1 to 4 corresponds to a sub-cell 1 to 4 within cell 330. The first sub-cell 352 includes a first transistor logic set, the second sub-cell 354 includes a second transistor logic set, the third sub-cell 356 includes a third transistor logic set, and the fourth sub-cell 358 includes a fourth transistor logic set, wherein the first, second, third, and fourth transistor logic sets are functionally isolated from each other (not interconnected) within a multi-row cell 330. The first, second, third, and fourth transistor logic sets can be AND-OR-Invert (AOI) logic or OR-AND-Invert (OAI) logic. Sub-units 352, 354, 356, and 358 each include gate interconnects extending in a first direction (e.g., see Figures 1 and 2), wherein the gate interconnects form transistor gates for different transistor logic sets. The multi-bit unit 330 may include a set of inter-unit M2 layer interconnects 390, which span at least a portion of the first sub-unit 352 and the second sub-unit 354 (inter-unit M2 layer interconnects 386 include inter-unit M2 layer interconnects 362, 364, 366, 368, 370, and 372) and at least a portion of the third sub-unit 356 and the fourth sub-unit 358 (inter-unit M2 layer interconnects 388 include inter-unit M2 layer interconnects 374, 376, 378, 380, 382, ​​and 384) in the first direction, extending from a first edge of unit 330 to a second edge of unit 330. The M2 layer interconnect 390 is illustrated as extending fully across the first / second sub-units 352, 354 and the third / fourth sub-units 356, 358, but one or more of the M2 layer interconnects 390 may extend over only a portion of the first / second sub-units 352, 354 and only a portion of the third / fourth sub-units 356, 358. The M2 layer interconnect 390 may extend input / output pins into different sub-units in a first direction. Input / output pins are illustrated with small circles. The actual location of the input / output within each sub-unit is illustrated with an X.

[0020] For example, for subcells 352 and 354, M2 layer interconnect 362 extends input a1 from the first subcell 352 into the second subcell 354, wherein the intra-cell M3 layer interconnect 332 (located above cell 330 within the MOS IC 398) can be coupled at the second subcell 354 to the a1 input pin of the first subcell 352. As another example, M2 layer interconnect 364 extends input a2 from the second subcell 354 into the first subcell 352, wherein the intra-cell M3 layer interconnect 334 (located above cell 330 within the MOS IC 398) can be coupled at the first subcell 352 to the a2 input pin of the second subcell 354. The pin connections for the remaining inputs / outputs b1, z1, b2, z2 for subcells 352 and 354 are illustrated as being connected within the same subcell via intra-cell M3 layer interconnects 331, 333, 335, and 337. All the illustrated intra-cell M3 layer interconnects 331, 332, 333, 334, 335, and 337 forming the pin connections are within the MOS IC 398 and are not part of cell 330. The intra-cell M3 layer interconnects 331, 332, 333, 334, 335, and 337 extend over and across at least a portion of cell 330, and can extend to connect the input of cell 330 to the output of other cells within the MOS IC 398, and to connect the output of cell 330 to the input of other cells within the MOS IC 398.

[0021] For example, for sub-units 356 and 358, M2 layer interconnects 374, 378, and 382 extend inputs / outputs a3, b3, and z3 from the third sub-unit 356 to the fourth sub-unit 358, respectively. Within the unit, M3 layer interconnects 336, 338, and 340 can be coupled to the input / output pins a3, b3, and z3 of the third sub-unit 356 at the fourth sub-unit 358, respectively. As another example, M2 layer interconnects 376, 380, and 384 extend inputs / outputs a4, b4, and z4 from the fourth sub-unit 358 to the third sub-unit 356, respectively. Within the unit, M3 layer interconnects 342, 344, and 346 can be coupled to the input / output pins a4, b4, and z4 of the fourth sub-unit 358 at the third sub-unit 356, respectively.

[0022] A multi-bit multi-height cell is a multi-row cell because a multi-height cell has at least two columns. A multi-bit multi-height cell may include one or more columns. Figure 3 illustrates a multi-bit multi-height cell with 2×2 sub-cells. Generally, a multi-bit multi-height cell may have R×C sub-cells, where R (columns) ≥ 2 and C (rows) ≥ 1. Each sub-cell may include at least one input and one output. In a configuration, each sub-cell may include at least three inputs / outputs (e.g., two inputs and one output). When a sub-cell includes a larger number of inputs / outputs (such as in sub-cells with higher pin density), greater reductions in pin routing congestion can be achieved through the cell architecture that provides improved pin routing accessibility.

[0023] As described above, in a multi-bit, multi-height cell, the inter-cell M2 layer interconnect extends across multiple sub-cells, providing improved pin routing accessibility for the intra-cell router, thereby reducing intra-cell routing congestion. Therefore, the intra-cell router can have greater freedom in selecting pin locations for the intra-cell M3 layer interconnect connections. This greater freedom in selecting pin locations allows the intra-cell router to select pin locations that reduce pin routing congestion. The inter-cell layer interconnect extending across multiple sub-cells is illustrated as an M2 layer interconnect, but can typically be an Mx layer interconnect on an Mx layer, where the Mx layer is the lowest metal layer or the second lowest metal layer extending in a first direction. If the Mx-1 layer is unidirectional in the second direction, then the Mx layer is the lowest metal layer extending unidirectionally in the first direction. If the Mx-1 layer is unidirectional in the first direction, then the Mx layer is the second lowest metal layer extending unidirectionally in the first direction. In one configuration, the Mx layer can be an M2 layer.

[0024] Figure 4 is a conceptual illustration of pin routing congestion and a multi-bit, multi-height cell for improving pin routing accessibility. As shown in Figure 4, one or more sub-cells may be located between a first sub-cell 352 and a second sub-cell 354. For example, a third sub-cell 450 may be located between the first sub-cell 352 and the second sub-cell 354. Thus, the MOS logic cell 430 may also include a third transistor logic set in the third sub-cell 450 of the logic cell 430. The first, second, and third transistor logic sets are functionally isolated from each other within the MOS logic cell 430. The third sub-cell 450 is located between the first sub-cell 352 and the second sub-cell 354. Mx layer interconnects 362, 366, and 368 are not connected to the third transistor logic set. Each Mx layer interconnect in Mx layer interconnects 362, 366, and 368 extends entirely over the third sub-cell 450 from the input or output of the first transistor logic set of the first sub-cell 352 to the second sub-cell 354. Mx layer interconnects 364, 368, and 370 are not connected to the third transistor logic set. Each Mx layer interconnect in Mx layer interconnects 364, 368, and 370 extends entirely above the third sub-cell 450 from the input or output of the second transistor logic set in the second sub-cell 354 to the first sub-cell 352. Additional Mx layer interconnects may be included within cell 430 to extend the input / output pin accessibility of the third sub-cell 450 to the first sub-cell 352 and / or the second sub-cell 354. Pin connections may be made via Mx+1 layer interconnects within the cell.

[0025] The MOS logic cell 430 has a first edge at the first sub-cell 352 and a second edge at the second sub-cell 354. The first sub-cell 352 and the third sub-cell 450 are adjacent to each other in a first direction. The third sub-cell 450 and the second sub-cell 354 are adjacent to each other in the first direction. Each Mx layer interconnect in the Mx layer interconnect 386 extends from the first edge to the second edge across the first sub-cell 352, the second sub-cell 354 and the third sub-cell 450.

[0026] Figure 5 is a diagram of Figure 500 illustrating four individual units 502, 504, 506, and 508 that are adjacent to each other. Through in-cell wiring, eight of the 16 pins can be interconnected across units 502, 504, and 506, 508 via in-cell M2 layer interconnects (at arrow 510) to expand the possible pin locations of those eight pins. Figure 6 is a diagram of Figure 600 illustrating a multi-bit multi-height unit including sub-units 602, 604, 606, and 608. Units 502, 504, 506, and 508 correspond to sub-units 602, 604, 606, and 608, respectively. The four individual units 502, 504, 506, and 508 are combined into a multi-bit multi-height unit with corresponding sub-units 602, 604, 606, and 608. The multi-bit multi-height cell design features inter-cell M2 layer interconnects (at arrow 610) that extend across sub-cells 602, 604 and sub-cells 606, 608. These inter-cell M2 layer interconnects expand the possible pin locations for 14 of the 16 pins. As can be seen from the comparison between the multi-bit multi-height cell in Figure 6 and the four individual cells in Figure 5, the multi-bit multi-height cell improves pin accessibility due to greater flexibility in pin location for a larger number of inputs / outputs. Specifically, when a cell is designed as a multi-bit multi-height cell, as shown in Figure 6, the cell can be designed with inter-cell M2 layer interconnects (610), which allows for improved pin accessibility for a larger number of inputs / outputs compared to using intra-cell M2 layer interconnects (510) with separate cells (as shown in Figure 5).

[0027] Figure 7 is a conceptual illustration of a plurality of multi-bit multi-height units on an IC. As shown in Figure 7, multi-bit multi-height units 702, 704, and 706 are multi-column units, wherein each column includes at least one separate sub-unit, and each sub-unit is functionally isolated from other sub-units. Multi-bit multi-height unit 702 is a 2×C unit, where C (rows) ≥ 1 and the number of sub-units is equal to 2*C. Multi-bit multi-height units 704 and 706 are 3×C units, where C (rows) ≥ 1 and the number of sub-units is equal to 3*C. For example, if multi-bit multi-height unit 704 is a 3×1 unit, then multi-bit multi-height unit 704 will include sub-units 720, 722, and 724. Inter-cell M2 layer interconnects 710 can extend completely across the height of multi-bit multi-height cells, as shown by multi-bit multi-height cells 702 and 704, or a subset of inter-cell M2 layer interconnects 710 can extend only partially across the height of multi-bit multi-height cells, as shown by multi-bit multi-height cells 706.

[0028] Referring again to Figures 3, 4, 6, and 7, the MOS IC 398 includes a MOS logic cell 330. The MOS logic cell 330 includes a first transistor logic set in a first sub-cell 352 and a second transistor logic set in a second sub-cell 354. The first and second transistor logic sets are functionally isolated from each other within the MOS logic cell 330. The MOS logic cell 330 also includes a first set of Mx layer interconnects 386 on the Mx layer, the Mx layer interconnects 386 extending in a first direction over the first sub-cell 352 and the second sub-cell 354. A first subset of the first set of Mx layer interconnects 362, 366, and 370 is coupled to an input or output of the first transistor logic set in the first sub-cell 352, and the first subset is not connected to the second transistor logic set. Each Mx-layer interconnect in the first subset of the first set of Mx-layer interconnects 362, 366, and 370 extends from an input or output of the first transistor logic set of the first subunit 352 to the second subunit 354. Each Mx-layer interconnect in the first subset of the first set of Mx-layer interconnects 362, 366, and 370 is an input / output of the first transistor logic set.

[0029] In one configuration, the MOS logic cell 330 has a first edge (top edge) at a first sub-cell 352 and a second edge (bottom edge) at a second sub-cell 354. The first sub-cell 352 and the second sub-cell 354 are adjacent to each other in a first direction. Each Mx layer interconnect in a first set of Mx layer interconnects 386 extends from the first edge across the first and second sub-cells from the second edge. In one configuration, the first transistor logic set and the second transistor logic set include a plurality of gate interconnects extending in the first direction (see Figures 1 and 2), wherein the gate interconnects form transistor gates for the first and second transistor logic sets. In one configuration, the Mx layer is a lowest metal layer or a second low metal layer extending unidirectionally in the first direction. In one configuration, the Mx layer is an M2 layer.

[0030] In one configuration, the MOS IC 398 further includes a set of Mx+1 layer interconnects 331, 332, 333 extending in a second direction. Each Mx+1 layer interconnect in the set of Mx+1 layer interconnects 331, 332, 333 is coupled to an Mx layer interconnect of a first subset of a first set of Mx layer interconnects 362, 366, 370. For example, Mx+1 layer interconnect 331 is coupled to Mx layer interconnect 366, Mx+1 layer interconnect 332 is coupled to Mx layer interconnect 362, and Mx+1 layer interconnect 333 is coupled to Mx layer interconnect 370. At least one Mx+1 layer interconnect 332 in the set of Mx+1 layer interconnects 331, 332, 333 is coupled to a corresponding Mx layer interconnect 362 above the second subcell 354 of the first subset of the first set of Mx layer interconnects 362, 366, 370. Note that in the example described, although the Mx layer interconnects 362, 366, and 370 extend the pin accessibility of inputs / outputs a1, b1, and z1 from the first sub-cell 352 to both the first sub-cell 352 and the second sub-cell 354, only one pin connection for input a1 is routed through the cell above the second sub-cell 354. In the example described, the remaining pin connections for b1 and z1 are routed through the cell above the first sub-cell 352.

[0031] In one configuration, a second subset 364, 368, 372 of the first set of Mx layer interconnects 386 is coupled to the input or output of the second transistor logic set in the second subunit 354 and is not connected to the first transistor logic set. Each Mx layer interconnect in the second subset of the first set of Mx layer interconnects 364, 368, 372 extends from the input or output of the second transistor logic set of the second subunit 354 to the first subunit 352. Each Mx layer interconnect in the second subset of the first set of Mx layer interconnects 364, 368, 372 is an input / output of the second transistor logic set.

[0032] In one configuration, the MOS IC 398 further includes a set of Mx+1 layer interconnects 334, 337, and 335 extending in a second direction. Each Mx+1 layer interconnect in the set of Mx+1 layer interconnects 334, 337, and 335 is coupled to an Mx layer interconnect of a second subset of the first set of Mx layer interconnects 364, 368, and 372. For example, Mx+1 layer interconnect 334 is coupled to Mx layer interconnect 364, Mx+1 layer interconnect 337 is coupled to Mx layer interconnect 368, and Mx+1 layer interconnect 335 is coupled to Mx layer interconnect 372. At least one Mx+1 layer interconnect 334 in the set of Mx+1 layer interconnects 334, 337, and 335 is coupled to a corresponding Mx layer interconnect 364 above the first subcell 352 of the second subset of the first set of Mx layer interconnects 364, 368, and 372. Note that in the example described, although the Mx layer interconnects 364, 368, and 372 extend the pin accessibility of inputs / outputs a2, b2, and z2 from the second sub-unit 354 to both the first sub-unit 352 and the second sub-unit 354, only one pin connection for input a2 is routed through the in-cell wiring above the first sub-unit 352. In the example described, the remaining pin connections for b2 and z2 are routed through the in-cell wiring above the second sub-unit 354.

[0033] Assuming a third subunit 450 exists between the first subunit 352 and the second subunit 354, referring to Figures 4 and 7, in one configuration, the MOS logic units 430 and 704 further include a third transistor logic set in the third subunits 450 and 722 of the logic units 430 and 704. The first (in 352 and 720), second (in 354 and 724), and third (in 450 and 722) transistor logic sets are functionally isolated from each other within the MOS logic units 430 and 704. The third subunits 450 and 722 are located between the first subunits 352 and 720 and the second subunits 354 and 724. A first subset of the first set of Mx layer interconnects 362, 366, and 370 is not connected to the third transistor logic set. Each Mx-layer interconnect in a first subset of the first set of Mx-layer interconnects 362, 366, 370 extends entirely over the third sub-cells 450, 722 from the input or output of the first transistor logic set of the first sub-cells 352, 720 to the second sub-cells 354, 724. MOS logic cells 430, 704 have a first edge at the first sub-cells 352, 720 and a second edge at the second sub-cells 354, 724. The first sub-cells 352, 720 and the third sub-cells 450, 722 are adjacent to each other in a first direction. The third sub-cells 450, 722 and the second sub-cells 354, 724 are adjacent to each other in a first direction. Each Mx-layer interconnect in the first set of Mx-layer interconnects 386 extends from the first edge to the second edge across the first sub-cells 352, 720, the second sub-cells 354, 724 and the third sub-cells 450, 722.

[0034] Referring again to FIG. 3, the MOS logic cell 330 further includes a third transistor logic set in the third sub-cell 356 of the logic cell 330, and a fourth transistor logic set in the fourth sub-cell 358 of the logic cell 330. The first, second, third, and fourth transistor logic sets are functionally isolated from each other in the MOS logic cell 330. The MOS logic cell 330 also includes a second set of Mx layer interconnects 388 on the Mx layer, the Mx layer interconnects 388 extending in a first direction above the third sub-cell 356 and the fourth sub-cell 358. A first subset of the second set of Mx layer interconnects 374, 378, 382 is coupled to an input or output of the third transistor logic set in the third sub-cell 356, and the first subset of the second set is not connected to the fourth transistor logic set. Each Mx layer interconnect in the first subset of the second set of Mx layer interconnects 374, 378, 382 extends from an input or output of the third transistor logic set of the third sub-cell 356 to the fourth sub-cell 358. Each Mx layer interconnect in the first subset of the second set of Mx layer interconnects 374, 378, and 382 is an input / output of the third transistor logic set.

[0035] In one configuration, the MOS logic cell 330 has a first edge at a third sub-cell 356 and a second edge at a fourth sub-cell 358. The third sub-cell 356 and the fourth sub-cell 358 are adjacent to each other in a first direction. Each Mx layer interconnect in the second set of Mx layer interconnects 388 extends from the first edge to the second edge across the third sub-cell 356 and the fourth sub-cell 358.

[0036] In one configuration, the MOS IC 398 further includes a set of Mx+1 layer interconnects 336, 338, 340 extending in a second direction. Each Mx+1 layer interconnect in the set of Mx+1 layer interconnects 336, 338, 340 is coupled to an Mx layer interconnect of a first subset of a second set of Mx layer interconnects 374, 378, 382. For example, Mx+1 layer interconnect 336 is coupled to Mx layer interconnect 374, Mx+1 layer interconnect 338 is coupled to Mx layer interconnect 378, and Mx+1 layer interconnect 340 is coupled to Mx layer interconnect 382. At least one Mx+1 layer interconnect 336, 338, 340 in the set of Mx+1 layer interconnects 336, 338, 340 is coupled to a corresponding Mx layer interconnect 374, 378, 382 above the fourth sub-cell 358 of the first subset of the second set of Mx layer interconnects 374, 378, 382. Note that in this example, Mx layer interconnects 374, 378, and 382 extend the pin accessibility of inputs / outputs a3, b3, and z3 from the third subunit 356 to both the third and fourth subunits 356 and 358, respectively. In this example, each pin connection for inputs / outputs a3, b3, and z3 is routed through the in-cell wiring above the fourth subunit 358.

[0037] In one configuration, a second subset of the second set of Mx layer interconnects 376, 380, 384 is coupled to an input or output of a fourth transistor logic set in a fourth subunit 358, and the second subset of the second set is not connected to a third transistor logic set. Each Mx layer interconnect in the second subset of the second set of Mx layer interconnects 376, 380, 384 extends from an input or output of the fourth transistor logic set in the fourth subunit 358 to the third subunit 356. Each Mx layer interconnect in the second subset of the second set of Mx layer interconnects 376, 380, 384 is an input / output of the fourth transistor logic set.

[0038] In one configuration, the MOS IC 398 further includes a set of Mx+1 layer interconnects 342, 344, 346 extending in a second direction. Each Mx+1 layer interconnect in the set of Mx+1 layer interconnects 342, 344, 346 is coupled to an Mx layer interconnect of a second subset of the second set of Mx layer interconnects 376, 380, 384. For example, Mx+1 layer interconnect 342 is coupled to Mx layer interconnect 376, Mx+1 layer interconnect 344 is coupled to Mx layer interconnect 380, and Mx+1 layer interconnect 346 is coupled to Mx layer interconnect 384. At least one Mx+1 layer interconnect 342, 344, 346 in the set of Mx+1 layer interconnects 342, 344, 346 is coupled to a corresponding Mx layer interconnect 376, 380, 384 above the third sub-cell 356 of the second subset of the second set of Mx layer interconnects 376, 380, 384. It should be noted that, in the example described, Mx layer interconnects 376, 380, and 384 extend the pin accessibility of inputs / outputs a4, b4, and z4 from the fourth subunit 358 to both the third and fourth subunits 356 and 358, respectively. In this example, each pin connection for inputs / outputs a4, b4, and z4 is routed through the in-cell wiring above the third subunit 356.

[0039] In one configuration, in a second direction orthogonal to the first direction, the third subunit 356 is adjacent to one of the first subunit 352 or the second subunit 354, and the fourth subunit 358 is adjacent to the other of the first subunit 352 or the second subunit 354 in the second direction. As shown in FIG3, the third subunit 356 is adjacent to the first subunit 352 in the second direction, and the fourth subunit 358 is adjacent to the second subunit 354 in the second direction.

[0040] In one configuration, the first transistor logic set and the second transistor logic set are at least one logic set of AOI logic or OAI logic. In one configuration, the first transistor logic set and the second transistor logic set each have at least three inputs / outputs.

[0041] As described above, when cell pins are close together (such as in high pin density cells), cell pin routing can become congested. Figures 3, 4, 6, and 7 provide cell architectures that improve pin routing accessibility. A MOS IC including a MOS logic cell is provided, wherein the MOS logic cell includes a plurality of sub-cells, wherein an inter-cell Mx layer interconnect within the cell extends across at least two sub-cells in a first direction. At least a subset of the Mx layer interconnect is connected to the inputs / outputs of the transistor logic of each sub-cell within the sub-cell. The Mx layer interconnect extends pin routing accessibility for pin connections made via in-cell routing after cell placement. Thus, at least some pin connections via an in-cell Mx+1 layer interconnect (extending in a second direction) can be made on sub-cells different from those associated with the corresponding inputs / outputs. The provided cell architecture reduces pin congestion and improves pin routing accessibility.

[0042] It should be understood that the specific order or hierarchy of the steps in the disclosed process is an illustration of an exemplary method. It should be understood that the specific order or hierarchy of the steps in these processes can be rearranged based on design preferences. Furthermore, some steps can be combined or omitted. The appended method claims present the elements of various steps in an exemplary order and are not intended to be limited to the specific order or hierarchy presented.

[0043] The preceding description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the universal principles defined herein may be applied to other aspects. Therefore, the scope of the claim is not intended to be limited to the aspects shown herein, but should be granted the full scope consistent with the linguistic scope of the claim, wherein, unless specifically stated otherwise, references to the singular form of an element are not intended to mean “one and only one,” but rather “one or more.” The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects. Unless specifically stated otherwise, the term “some” refers to one or more. Combinations such as “at least one of A, B, or C,” “at least one of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and / or C, and may include multiple A, multiple B, or multiple C. Specifically, combinations such as "at least one of A, B, or C," "at least one of A, B, and C," and "A, B, C, or any combination thereof" can be A only, B only, C only, A and B, A and C, B and C, or A and B and C, wherein any such combination may include one or more members of A, B, or C. All structural and functional equivalents of the elements throughout the various aspects described in this disclosure, now or hereafter known to a person skilled in the art, are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be offered to the public, whether or not such disclosure is explicitly stated in the claims. No claim element should be construed as a component plus function unless the element is explicitly described using the phrase "component for...".

[0044] The following examples are merely illustrative and may be combined with other embodiments or teachings described herein, without limitation.

[0045] Example 1 is a MOS IC including a MOS logic cell, the MOS logic cell comprising: a first transistor logic set in a first sub-cell of the logic cell and a second transistor logic set in a second sub-cell of the logic cell. The first transistor logic set and the second transistor logic set are functionally isolated from each other in the MOS logic cell. The MOS logic cell further comprises: a first Mx layer interconnect set on an Mx layer, the first Mx layer interconnect set extending over the first sub-cell and the second sub-cell in a first direction. A first subset of the first Mx layer interconnect set is coupled to an input or output of the first transistor logic set in the first sub-cell, and the first subset of the first Mx layer interconnect set is not connected to the second transistor logic set. Each Mx layer interconnect in the first subset of the first Mx layer interconnect set extends from the input or output of the first transistor logic set in the first sub-cell to the second sub-cell. Each Mx layer interconnect in the first subset of the first Mx layer interconnect set is an input / output of the first transistor logic set.

[0046] Example 2 is a MOS IC according to Example 1, wherein the MOS logic cell has a first edge at the first sub-cell and a second edge at the second sub-cell. The first sub-cell and the second sub-cell are adjacent to each other in the first direction. Each Mx layer interconnect in the first Mx layer interconnect set extends from the first edge to the second edge across the first sub-cell and the second sub-cell.

[0047] Example 3 is a MOS IC according to any one of Examples 1 and 2, wherein the first transistor logic set and the second transistor logic set include a plurality of gate interconnects extending in the first direction.

[0048] Example 4 is a MOS IC according to any one of Examples 1 to 3, wherein the Mx layer is a lowest metal layer or a second low metal layer extending in the first direction.

[0049] Example 5 is a MOS IC according to Example 4, wherein the Mx layer is the M2 layer.

[0050] Example 6 is a MOS IC according to any one of Examples 1 to 5, wherein the MOS IC further includes an Mx+1 layer interconnect set extending in a second direction. Each Mx+1 layer interconnect in the Mx+1 layer interconnect set is coupled to an Mx layer interconnect of a first subset of the first Mx layer interconnect set. At least one Mx+1 layer interconnect in the Mx+1 layer interconnect set is coupled to a corresponding Mx layer interconnect of the first subset of the first Mx layer interconnect set above the second sub-cell.

[0051] Example 7 is a MOS IC according to any one of Examples 1 to 6, wherein a second subset of the first Mx-layer interconnect set is coupled to an input or output of the second transistor logic set in the second sub-cell, and the second subset of the first Mx-layer interconnect set is not connected to the first transistor logic set. Each Mx-layer interconnect in the second subset of the first Mx-layer interconnect set extends from the input or output of the second transistor logic set of the second sub-cell to the first sub-cell. Each Mx-layer interconnect in the second subset of the first Mx-layer interconnect set is an input / output of the second transistor logic set.

[0052] Example 8 is a MOS IC according to Example 7, wherein the MOS IC further includes an Mx+1 layer interconnect set extending in a second direction. Each Mx+1 layer interconnect in the Mx+1 layer interconnect set is coupled to an Mx layer interconnect of a second subset of the first Mx layer interconnect set. At least one Mx+1 layer interconnect of the Mx+1 layer interconnect set is coupled to a corresponding Mx layer interconnect of the second subset of the first Mx layer interconnect set above the first sub-cell.

[0053] Example 9 is a MOS IC according to any one of Examples 1 to 8, wherein the MOS logic cell further includes a third transistor logic set in a third sub-cell of the logic cell. The first transistor logic set, the second transistor logic set, and the third transistor logic set are functionally isolated from each other in the MOS logic cell. The third sub-cell is located between the first sub-cell and the second sub-cell. The first subset of the first Mx layer interconnect set is not connected to the third transistor logic set. Each Mx layer interconnect in the first subset of the first Mx layer interconnect set extends entirely over the third sub-cell from the input or the output of the first transistor logic set of the first sub-cell to the second sub-cell.

[0054] Example 10 is a MOS IC according to Example 9, wherein the MOS logic cell has a first edge at the first sub-cell and a second edge at the second sub-cell. The first sub-cell and the third sub-cell are adjacent to each other in the first direction. The third sub-cell and the second sub-cell are adjacent to each other in the first direction. Each Mx layer interconnect in the first Mx layer interconnect set extends from the first edge to the second edge across the first sub-cell, the second sub-cell, and the third sub-cell.

[0055] Example 11 is a MOS IC according to any one of Examples 1 to 10, wherein the MOS logic cell further includes: a third transistor logic set in a third sub-cell of the logic cell, and a fourth transistor logic set in a fourth sub-cell of the logic cell. The first, second, third, and fourth transistor logic sets are functionally isolated from each other in the MOS logic cell. The MOS logic cell further includes: a second Mx layer interconnect set on an Mx layer, the second Mx layer interconnect set extending over the third and fourth sub-cells in the first direction. A first subset of the second Mx layer interconnect set is coupled to an input or output of the third transistor logic set in the third sub-cell, and the first subset of the second Mx layer interconnect set is not connected to the fourth transistor logic set. Each Mx layer interconnect in the first subset of the second Mx layer interconnect set extends from the input or output of the third transistor logic set in the third sub-cell to the fourth layer sub-cell. Each Mx-layer interconnect in the first subset of the second Mx-layer interconnect set is an input / output of the third transistor logic set.

[0056] Example 12 is a MOS IC according to Example 11, wherein the MOS logic cell has a first edge at the third sub-cell and a second edge at the fourth sub-cell. The third sub-cell and the fourth sub-cell are adjacent to each other in the first direction. Each Mx layer interconnect in the second Mx layer interconnect set extends from the first edge to the second edge across the third sub-cell and the fourth sub-cell.

[0057] Example 13 is a MOS IC according to Example 12, wherein the MOS IC further includes an Mx+1 layer interconnect set extending in a second direction. Each Mx+1 layer interconnect in the Mx+1 layer interconnect set is coupled to an Mx layer interconnect of a first subset of the second Mx layer interconnect set. At least one Mx+1 layer interconnect of the Mx+1 layer interconnect set is coupled to a corresponding Mx layer interconnect of the first subset of the second Mx layer interconnect set above the fourth sub-cell.

[0058] Example 14 is a MOS IC according to any one of Examples 11 to 13, wherein a second subset of the second Mx-layer interconnect set is coupled to an input or output of the fourth transistor logic set in the fourth sub-cell, and the second subset of the second Mx-layer interconnect set is not connected to the third transistor logic set. Each Mx-layer interconnect in the second subset of the second Mx-layer interconnect set extends from the input or output of the fourth transistor logic set of the fourth sub-cell to the third sub-cell. Each Mx-layer interconnect in the second subset of the second Mx-layer interconnect set is an input / output of the fourth transistor logic set.

[0059] Example 15 is a MOS IC according to Example 14, wherein the MOS IC further includes an Mx+1 layer interconnect set extending in a second direction. Each Mx+1 layer interconnect in the Mx+1 layer interconnect set is coupled to an Mx layer interconnect of a second subset of the second Mx layer interconnect set. At least one Mx+1 layer interconnect in the Mx+1 layer interconnect set is coupled to a corresponding Mx layer interconnect of the second subset of the second Mx layer interconnect set above the third sub-cell.

[0060] Example 16 is a MOS IC according to any one of Examples 11 to 15, wherein in a second direction orthogonal to the first direction, the third sub-unit is adjacent to one of the first sub-units or the second sub-units, and the fourth sub-unit is adjacent to the other of the first sub-units or the second sub-units in the second direction.

[0061] Example 17 is a MOS IC according to any one of Examples 1 to 16, wherein the first transistor logic set and the second transistor logic set are at least one of AOI logic or OAI logic.

[0062] Example 18 is a MOS IC according to any one of Examples 1 to 17, wherein the first transistor logic set and the second transistor logic set each have at least three inputs / outputs. [Simplified Explanation of the Diagram]

[0006] Figure 1 is the first side view of the standard cell and various layers within the IC.

[0007] Figure 2 is a second side view illustrating the standard cell and various layers within the IC.

[0008] Figure 3 is a conceptual illustration of the first diagram of pin wiring congestion and multi-bit multi-height cells for improving pin wiring accessibility.

[0009] Figure 4 is a conceptual illustration of pin routing congestion and a second diagram of multi-bit, multi-height cells for improving pin routing accessibility.

[0010] Figure 5 is a diagram showing four individual units that are adjacent to each other.

[0011] Figure 6 is a diagram illustrating a multi-bit, multi-height unit.

[0012] Figure 7 is a conceptual diagram illustrating multiple multi-bit, multi-height cells on an IC.

Claims

1. A metal-oxide-semiconductor (MOS) integrated circuit (IC), comprising: A MOS logic cell includes: a first transistor logic set in a first sub-cell of the logic cell and a second transistor logic set in a second sub-cell of the logic cell, the first transistor logic set and the second transistor logic set being functionally isolated from each other in the MOS logic cell; and a first metal x (Mx) layer interconnect set on an Mx layer, the first metal x (Mx) layer interconnect set extending over the first sub-cell and the second sub-cell in a first direction, a first subset of the first Mx layer interconnect set being coupled to an input or output of the first transistor logic set in the first sub-cell and not being connected to the second transistor logic set, each Mx layer interconnect in the first subset of the first Mx layer interconnect set extending from the input or output of the first transistor logic set in the first sub-cell to the second sub-cell, each Mx layer interconnect in the first subset of the first Mx layer interconnect set being an input / output of the first transistor logic set.

2. The MOS IC according to claim 1, wherein the MOS logic cell has a first edge at the first sub-cell and a second edge at the second sub-cell, the first sub-cell and the second sub-cell are adjacent to each other in the first direction, and each Mx layer interconnect in the first Mx layer interconnect set extends from the first edge to the second edge across the first sub-cell and the second sub-cell.

3. The MOS IC according to claim 1, wherein the first transistor logic set and the second transistor logic set include a plurality of gate interconnects extending in the first direction.

4. The MOS IC according to claim 1, wherein the Mx layer is a lowest metal layer or a second low metal layer extending in the first direction.

5. The MOS IC according to claim 4, wherein the Mx layer is a metal 2 (M2) layer.

6. The MOS IC according to claim 1, wherein the MOS IC further comprises an Mx+1 layer interconnect set extending in a second direction, each Mx+1 layer interconnect in the Mx+1 layer interconnect set being coupled to an Mx layer interconnect of a first subset of the first Mx layer interconnect set, and at least one Mx+1 layer interconnect in the Mx+1 layer interconnect set being coupled to a corresponding Mx layer interconnect of the first subset of the first Mx layer interconnect set above the second sub-cell.

7. The MOS IC according to claim 1, wherein a second subset of the first Mx layer interconnect set is coupled to an input or output of the second transistor logic set in the second sub-cell, and the second subset of the first Mx layer interconnect set is not connected to the first transistor logic set, each Mx layer interconnect in the second subset of the first Mx layer interconnect set extends from the input or output of the second transistor logic set of the second sub-cell to the first sub-cell, and each Mx layer interconnect in the second subset of the first Mx layer interconnect set is an input / output of the second transistor logic set.

8. The MOS IC according to claim 7, wherein the MOS IC further comprises an Mx+1 layer interconnect set extending in a second direction, each Mx+1 layer interconnect in the Mx+1 layer interconnect set being coupled to an Mx layer interconnect of a second subset of the first Mx layer interconnect set, and at least one Mx+1 layer interconnect of the Mx+1 layer interconnect set being coupled to a corresponding Mx layer interconnect of the second subset of the first Mx layer interconnect set above the first subcell.

9. The MOS IC according to claim 1, wherein the MOS logic unit further includes a third transistor logic set in a third sub-unit of the logic unit, the first transistor logic set, the second transistor logic set, and the third transistor logic set being functionally isolated from each other in the MOS logic unit, the third sub-unit being between the first sub-unit and the second sub-unit, a first subset of the first Mx layer interconnect set not being connected to the third transistor logic set, and each Mx layer interconnect in the first subset of the first Mx layer interconnect set extending entirely over the third sub-unit from the input or the output of the first transistor logic set of the first sub-unit to the second sub-unit.

10. The MOS IC according to claim 9, wherein the MOS logic cell has a first edge at the first sub-cell and a second edge at the second sub-cell, the first sub-cell and the third sub-cell are adjacent to each other in the first direction, the third sub-cell and the second sub-cell are adjacent to each other in the first direction, and each Mx layer interconnect in the first Mx layer interconnect set extends from the first edge to the second edge across the first sub-cell, the second sub-cell and the third sub-cell.

11. The MOS IC according to claim 1, wherein the MOS logic unit further comprises: A third transistor logic set in the third sub-unit of the logic unit, and a fourth transistor logic set in the fourth sub-unit of the logic unit, wherein the first transistor logic set, the second transistor logic set, the third transistor logic set, and the fourth transistor logic set are functionally isolated from each other in the MOS logic unit; and a second Mx layer interconnect set on the Mx layer, the second Mx layer interconnect set extending in the first direction above the third sub-unit and the fourth sub-unit, a first subset of the second Mx layer interconnect set being coupled to an input or output of the third transistor logic set in the third sub-unit, and the first subset of the second Mx layer interconnect set not being connected to the fourth transistor logic set, each Mx layer interconnect in the first subset of the second Mx layer interconnect set extending from the input or output of the third transistor logic set in the third sub-unit to the fourth layer sub-unit, each Mx layer interconnect in the first subset of the second Mx layer interconnect set being an input / output of the third transistor logic set.

12. The MOS IC according to claim 11, wherein the MOS logic cell has a first edge at the third sub-cell and a second edge at the fourth sub-cell, the third sub-cell and the fourth sub-cell being adjacent to each other in the first direction, and each Mx layer interconnect in the second Mx layer interconnect set extending from the first edge across the third sub-cell and the fourth sub-cell to the second edge.

13. The MOS IC of claim 12, wherein the MOS IC further comprises an Mx+1 layer interconnect set extending in a second direction, each Mx+1 layer interconnect in the Mx+1 layer interconnect set being coupled to an Mx layer interconnect of a first subset of the second Mx layer interconnect set, and at least one Mx+1 layer interconnect of the Mx+1 layer interconnect set being coupled to a corresponding Mx layer interconnect of the first subset of the second Mx layer interconnect set above the fourth sub-cell.

14. The MOS IC of claim 11, wherein a second subset of the second Mx layer interconnect set is coupled to an input or output of the fourth transistor logic set in the fourth sub-unit, and the second subset of the second Mx layer interconnect set is not connected to the third transistor logic set, each Mx layer interconnect in the second subset of the second Mx layer interconnect set extends from the input or output of the fourth transistor logic set of the fourth sub-unit to the third sub-unit, and each Mx layer interconnect in the second subset of the second Mx layer interconnect set is an input / output of the fourth transistor logic set.

15. The MOS IC of claim 14, wherein the MOS IC further comprises an Mx+1 layer interconnect set extending in a second direction, each Mx+1 layer interconnect set being coupled to an Mx layer interconnect of a second subset of the second Mx layer interconnect set, and at least one Mx+1 layer interconnect set being coupled to a corresponding Mx layer interconnect of the second subset of the second Mx layer interconnect set above the third sub-cell.

16. The MOS IC according to claim 11, wherein in a second direction orthogonal to the first direction, the third sub-unit is adjacent to one of the first sub-units or the second sub-unit, and the fourth sub-unit is adjacent to the other of the first sub-units or the second sub-units in the second direction.

17. The MOS IC according to claim 1, wherein the first transistor logic set and the second transistor logic set are at least one of AND-OR-NOT (AOI) logic or OR-AND-NOT (OAI) logic.

18. The MOS IC according to claim 1, wherein the first transistor logic set and the second transistor logic set each have at least three inputs / outputs.

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