Efuse inside and gate structure on triple-well region

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to an eFuse and gate structure on a triple-well and methods of manufacture. The structure includes: a substrate comprising a bounded region; a gate structure formed within the bounded region; and an eFuse formed within the bounded region and electrically connected to the gate structure.

Description

[Technical Field]

[0001] This invention relates to semiconductor structures, and more specifically, to electronic fuse and gate structures and manufacturing methods in the Mitsui region. [Previous Technology]

[0002] An electronic fuse (eFuse) is a miniature fuse used in computer chips. Electronic fuses allow for dynamic, real-time reprogramming of the chip. For example, a chip manufacturer can use a set of electronic fuses to make the circuitry on the chip change as it operates.

[0003] Electronic fuses can be made of silicon or metal traces. These traces are weaker than other traces on the wafer, thus failing earlier than the others. For example, the electronic fuse can be burned out by electromigration, and the wafer can be programmed during operation. However, electronic fuses require a larger wafer area, especially in technologies where the field-effect transistor (FET) is only provided in the Mitsui region. For example, in this layout, the electronic fuse uses up to 12% of the wafer area. [Summary of the Invention]

[0004] In one embodiment of the present invention, a structure includes: a substrate having a bounded region; a gate structure formed in the bounded region; and an electronic fuse formed in the bounded region and electrically connected to the gate structure.

[0005] In one embodiment of the present invention, a structure includes: a substrate containing a well-formed bounded region; at least one shallow trench isolation structure in the well-formed bounded region; and an electronic fuse electrically connected to the gate structure and above at least one shallow trench isolation structure in the well-formed bounded region.

[0006] In one embodiment of the present invention, a method includes: forming a bounded region in a bounded substrate formed by a well; forming at least one shallow trench isolation structure in the bounded region; forming a gate structure above the bounded region; and forming an electronic fuse electrically connected to the gate structure, the electronic fuse being formed above the at least one shallow trench isolation structure in the bounded region.

Implementation Method

[0014] This invention relates to semiconductor structures, and more particularly to an electron fuse and gate structure draped over a tri-well region, and a method of manufacturing thereof. More specifically, the electron fuse structure comprises a silicon polysilicon electron fuse combined with a programmable field-effect transistor (FET) within a tri-well region (e.g., a ring). Advantageously, the silicon polysilicon electron fuse within the tri-well region can significantly reduce the area of ​​the electron fuse array cell. For example, compared to known electron fuse layouts, the silicon polysilicon electron fuse within the tri-well region can save 58% of the area in an 8-bit electron fuse array cell.

[0015] In more specific embodiments, the siliconized polycrystalline silicon electronic fuse may be disposed on top of the tri-well region with the programmable field-effect transistor; that is, the siliconized polycrystalline silicon electronic fuse may share the same tri-well region with the programmable field-effect transistor. In a further embodiment, the electronic fuse, the programmable field-effect transistor, and the bottom-mounted diode share the same tri-well region. The bottom-mounted diode avoids plasma charging during the process that could cause damage to the wells and / or gates. It is further envisioned that an array of electronic fuses with all parallel bit cells may be disposed in the same tri-well region. In a further embodiment, the tri-well region may be replaced by an embedded polycrystalline silicon layer. By grouping the electronic fuses and field-effect transistors within the same tri-well (or above the embedded polycrystalline silicon material), a miniaturized design layout can be achieved.

[0016] The electronic fuse of the present invention can be manufactured in a variety of ways using a variety of tools. However, in general, these methods and tools are used to form structures at the micrometer and nanometer scale. Methods (i.e., techniques) for manufacturing the electronic fuse of the present invention have been adopted from integrated circuit (IC) technology. For example, these structures are built on a wafer and realized in a thin film of material patterned by lithography on top of the wafer. In particular, the manufacture of the electronic fuse uses three basic building blocks: (i) depositing a thin film of material on a substrate, (ii) applying a patterned photomask on top of the film by lithography, and (iii) selectively etching the film onto the photomask.

[0017] Figure 1 illustrates the Mitsui region and other features and relative processes of various embodiments according to the present invention. More specifically, structure 10 of Figure 1 includes a substrate 12. In various embodiments, substrate 12 comprises a bulk substrate having any suitable crystal orientation (e.g., (100), (110), (111), or (001) crystal orientation). Substrate 12 may be composed of any suitable material, including but not limited to silicon, silicon germanium, silicon germanium silicon carbide, gallium arsenide, indium arsenide, indium phosphide, and other III / V or II / VI compound semiconductors.

[0018] Figure 1 further shows a three-well region 15 in the substrate 12. The three-well region 15 includes wells 14, 16, and 18. In several embodiments, well 14 is a deep N-type well, well 16 is a P-type well, and well 18 is an N-type well (isolation well) surrounding the P-type well 16. In several embodiments, the N-type wells 14 and 18 are doped with n-type dopants, such as arsenic (As), phosphorus (P), and antimony, and other suitable examples; however, the P-type wells are doped with p-type dopants, such as boron (B).

[0019] Wells 14, 16, and 18 can be formed by introducing dopants into the substrate 12, for example, using an ion implantation process. In several embodiments, a patterned implantation photomask can be used to define selected areas exposed for the implantation process. The implantation photomask may include a layer of photosensitive material, such as an organic photoresist, which can be applied by a spin-coating process, pre-baking, exposure to light projected through the photomask, post-exposure baking, and development with a chemical developer. The thickness and blocking power of the implantation photomask are sufficient to block the masked area to prevent the reception of a dose of implanted ions.

[0020] Referring again to FIG. 1, shallow trench isolation structures 20, 20a are formed in the substrate 12, and more preferably in wells 16, 18 and their junctions. In several embodiments, the shallow trench isolation structure 20a may be entirely within well 16. The shallow trench isolation structures 20, 20a can be formed using conventional lithography, etching, and deposition processes. For example, a resist formed on the substrate 12 is exposed to energy (light) to form a pattern (opening). An etching process with selective chemistry (e.g., reactive ion etching (RIE)) is used to transfer the pattern from the resist to the substrate 12 to form one or more trenches in the substrate 12 through the openings in the resist. After the resist is removed by a conventional oxygen ashing process or other known stripping agent, an insulating material can be deposited by any conventional deposition process (e.g., chemical vapor deposition (CVD) process). Any residual material on the surface of the substrate 12 can be removed by a conventional chemical mechanical polishing (CMP) process.

[0021] Figure 2 illustrates the electron fuse 24 and gate structure 22 draped over the three-well region 15, as well as other features and relative processes. For example, the electron fuse 24 and gate structure 22 are completely defined within well 18, above well 14, and in and / or above well 16. In several embodiments, both the gate structure 22 and the electron fuse 24 may comprise polycrystalline silicon material and be deposited and patterned using known deposition and patterning processes (e.g., lithography and etching processes).

[0022] In several embodiments, the gate structure 22 may be formed by a pre-gate process. In the pre-gate process, for example, gate material 22a (e.g., gate dielectric material and polysilicon material) is deposited on a substrate 12 covered over well 16, followed by a patterning process, such as lithography and etching. The deposition of polysilicon material for the gate structure 22 may also be used for the electron fuse 24. For example, a chemical vapor deposition (CVD) process may be used to deposit the polysilicon material. In several embodiments, the gate dielectric material may be a low-dielectric gate constant material, such as an oxide. After the electron fuse 24 is formed on the shallow trench isolation structure 20a and the gate structure 22 is formed and covered over well 16 in the patterning process, sidewall spacers 22b may be formed on the sidewalls of the patterned gate structure 22 and may be selectively formed on the sidewalls of the electron fuse 24. The sidewall spacing 22b can be a nitride or oxide material (or a combination thereof) formed by any known deposition process, followed by an anisotropic etching process.

[0023] Figure 3 shows the silicate junction 28 on the electron fuse 24 and the diffusion regions 26, 26a above the three-well region 15, and other features. The diffusion regions 26, 26a can be formed in the well 16 using a conventional ion implantation process known to those skilled in the art prior to the formation of the silicate junction 28, therefore no further explanation is required to fully understand the invention. In several embodiments, the diffusion region 26a may be a bottom-mounted diode to prevent plasma charging during subsequent processing steps. Furthermore, the diffusion region 26 may be a source / drain region formed by a conventional implantation process, including sequentially formed halo implants and extended implants after the deposition of sidewall spacer material.

[0024] The silicate contact 28 can be formed using conventional silicate processes. For example, the silicate process begins by depositing a thin layer of transition metal, such as nickel, cobalt, or titanium, over a fully formed and patterned semiconductor device (e.g., diffusion regions 26, 26a, electron fuse 24, and gate structure 22 (not shown in this cross-sectional view)). After material deposition, the structure is heated, causing the transition metal to react with the semiconductor material (silicon or other semiconductor materials described herein) exposed from the active region of the device, forming a low-resistance transition metal silicate. After the reaction, any remaining transition metal is removed by chemical etching, leaving the silicate contact 28 on the active region of the device 22 and the electron fuse 24.

[0025] Figure 4 shows the contacts and other features of the electron fuse 24 and other components covering the Mitsui region 15. More specifically, contacts 30a-30e (e.g., metallized features) are formed on the diffusion regions 26, 26a and the electron fuse 24 (and the gate material 22a of the gate structure 22 (not shown in this cross-sectional view)). In several embodiments, contacts 30a-30e can be formed using conventional techniques. For example, a stack of interlayer dielectric material 34 can be deposited using a conventional deposition process (e.g., chemical vapor deposition), followed by lithography and etching processes to form trenches, thereby exposing silicate contacts 28 (or metallic features on silicate contacts 28). After trenches are formed in the interlayer dielectric material 34, conductive material can be deposited using any conventional deposition process (e.g., chemical vapor deposition) to form contacts 30a-30e. Any residual material on the surface of the interlayer dielectric material 34 can be removed by a conventional chemical mechanical polishing (CMP) process.

[0026] Figure 4 further illustrates another metallization feature, such as the wiring structure 32 connecting the electronic fuse 24 to the gate structure 22. In various embodiments, the wiring structure 32 can be formed by a conventional complementary metal-oxide-semiconductor process similar to that used to form contacts 30a-30c, and therefore requires no further explanation to fully understand the invention. In various embodiments, the wiring structure 32 contacts the contacts 30a of the diffusion region 26 of the gate structure 22 and the contacts 30b of the electronic fuse 24. Thus, the electronic fuse 24 is electrically connected to the gate structure 22, such as a programmable field-effect transistor.

[0027] Figure 5 shows a top view of the electronic fuse 24 covering the isolation well (e.g., P-type well 16) over the three-well region 15 (defined by the N-type well 18), and other features. More specifically, Figure 5 shows the electronic fuse 24, the gate structure 22, and the diffusion region 26a (e.g., a bottom-mounted diode) located in and sharing a single three-well region 15 defined by the N-type well 18 (e.g., an N-type well ring). As further shown in Figure 5, the gate structure 22 may be a multi-finger field-effect transistor (or parallel bit cell) over the three-well region 15, connected to the electronic fuse 24 via a wiring structure 32. Furthermore, the electronic fuse 24 may be disposed and covered over the shallow trench isolation structure 24 within the three-well region 15.

[0028] Figure 6 shows an electron fuse 24 over an embedded amorphous semiconductor layer 36 in a substrate 12 and defined by P-type well regions 38, 38a. In this embodiment, wells 14, 16 may be excluded. In several embodiments, the embedded amorphous semiconductor layer 36 may be fabricated by amorphizing the substrate 12 using an implantation process, wherein an implantation photomask protects, for example, the substrate regions used to form the P-type well regions 38, 38a. The implantation process may be performed at a critical dose to prevent recrystallization of the substrate 12 (e.g., a single-crystal material). In several embodiments, the implantation process may be an argon implantation process at a dose level of about 1E14 to 1.5E15, followed by an annealing process (e.g., 950°C to 1100°C) to form a polycrystalline silicon material layer. The implantation process may also utilize other implantation elements (e.g., other inert gases, such as other rare gases (e.g., xenon, germanium, nitrogen, or oxygen)) provided prior to the formation of the electron fuse 24 and gate structure 22. A buried amorphous semiconductor layer 36 is attached to the bottom of the N-type well 18 to define the electron fuse 24 and gate structure 22.

[0029] Furthermore, P-type well regions 38, 38a and P-type well 38b can be formed in the substrate 12 using, for example, an ion implantation process. As disclosed, an implantation mask used in the ion implantation process of the buried amorphous semiconductor layer 36 will prevent the formation of the amorphous semiconductor layer 36 at the locations of the P-type well regions 38, 38a. The P-type well region 38a can be used for the diffusion region 26a (e.g., a diode), and the P-type well 38b can be used for the gate structure 22. In an embodiment, the P-type well regions 38, 38a are connected to (contact with) the substrate 12 beneath the buried amorphous semiconductor layer 36. Thus, the P-type well regions 38, 38a can form a ring extending beneath the amorphous semiconductor layer 36 and connected to the substrate 12, while also defining the electron fuse 24 and the gate structure 22. Those skilled in the art will also understand that the ion implantation process of the P-type well 38b can cause the substrate to recrystallize, for example, between the well 38b and the embedded amorphous semiconductor layer 36, as shown by the single crystal material 12a. Furthermore, in this embodiment, the gate structure 22 can be a floating body field-effect transistor.

[0030] Electronic fuses can be used in System-on-a-Chip (SoC) technology. A SoC is an integrated circuit (also called a "chip") that integrates all components of an electronic system onto a single chip or substrate. Because the components are integrated onto a single substrate, SoCs consume significantly less power and occupy a much smaller area compared to multi-chip designs with equivalent functionality. For this reason, SoCs are becoming a dominant force in the mobile computing (such as smartphones) and edge computing markets. SoCs can also be used in embedded systems and the Internet of Things (IoT).

[0031] The above-described methods are used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier, with leads fixed to a motherboard or other higher-order carrier) or a multi-chip package (such as a ceramic carrier with either or both surface-mount or buried interconnects). In any case, the chip is subsequently integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product containing integrated circuit chips, ranging from toys and other low-end applications to high-end computer products with displays, keyboards or other input devices, and central processing units.

[0032] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen for the purpose of best explaining the principles of the embodiments, their practical application, or improvements to techniques found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein. [Simplified Explanation of the Diagram]

[0007] In the following embodiments, the invention is described with reference to a plurality of drawings while using non-limiting examples of exemplary embodiments of the invention.

[0008] Figure 1 shows the Mitsui region and other features and the relative process of various forms according to the present invention.

[0009] Figure 2 shows the electronic fuse, other features, and relative processes of various forms of the present invention covering the Mitsui region.

[0010] Figure 3 shows the silicate, other features and relative processes of various forms of the present invention coated on the electron fuse above the Mitsui region.

[0011] Figure 4 shows the contacts of the electronic fuse covering the Mitsui region according to various forms of the present invention, as well as other features and the corresponding process.

[0012] Figure 5 shows a top view of the electronic fuse and gate structure covering the Mitsui area, as well as other features.

[0013] Figure 6 shows the electronic fuses and other features and the corresponding process of a plurality of additional states of the present invention draped over an embedded amorphous semiconductor layer.

Claims

1. A structure comprising: A substrate, the substrate comprising a bounded region; A gate structure is formed within the bounded region; And an electronic fuse, which is formed in the bounded region and electrically connected to the gate structure.

2. The structure as described in claim 2, wherein the bounded region comprises a three-well region, the three-well region comprising an embedded N-type well, a P-type well above the embedded N-type well, and an N-type well ring defining the gate structure and the electronic fuse.

3. The structure as described in claim 1, wherein the N-type well ring contacts the embedded N-type well.

4. The structure as described in claim 2, wherein the electronic fuse is disposed above a shallow trench isolation structure within the P-type well and is electrically connected to the gate structure by means of at least one metallization feature.

5. The structure as described in claim 4, wherein the electronic fuse comprises a siliconized polycrystalline silicon material.

6. The structure as described in claim 5, wherein the gate structure comprises a field-effect transistor and the gate structure comprises a polysilicon gate structure.

7. The structure as described in claim 5, further comprising a down-connected diode in the Mitsui region.

8. The structure as described in claim 1, wherein the bounded region includes an amorphous semiconductor layer embedded in the substrate and a P-type well extending through the amorphous semiconductor layer.

9. The structure as described in claim 8, wherein the gate structure and the electron fuse are located above the amorphous semiconductor layer.

10. The structure as described in claim 9, wherein the amorphous semiconductor layer comprises a polycrystalline silicon material.

11. The structure as described in claim 10, wherein the gate structure includes a floating body field-effect transistor.

12. A structure comprising: a substrate including a bounded region formed by a well; at least one shallow trench isolation structure located within the bounded region formed by the well; a gate structure covering the bounded region formed by the well; and an electronic fuse electrically connected to the gate structure and covering the at least one shallow trench isolation structure within the bounded region formed by the well.

13. The structure as described in claim 12 further includes a diffusion region located in the bounded region formed by the well.

14. The structure as described in claim 13, wherein the diffusion region comprises a down-connected diode.

15. The structure as described in claim 12, wherein the well includes an N-type well ring, and the region includes a three-well region comprising an embedded N-type well and a P-type well overlying the embedded N-type well and surrounded by the N-type well ring.

16. The structure as described in claim 15, wherein the gate structure includes parallel bit cells located in the three-well region.

17. The structure as described in claim 15, further comprising a shallow trench isolation structure located at the interface of the Mitsui area.

18. The structure as described in claim 12, wherein the well includes a P-type well ring extending through an embedded polycrystalline silicon material.

19. The structure as described in claim 18, wherein the gate structure is a floating gate structure.

20. A method comprising: forming a bounded region in a substrate surrounded by a well; forming at least one shallow trench isolation structure in the bounded region; forming a gate structure above the bounded region; and forming an electronic fuse electrically connected to the gate structure, the electronic fuse being draped over the at least one shallow trench isolation structure in the bounded region.

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