Phase detection auto focus and correlated multiple sampling

Abstract

An arithmetic logic unit includes a GC to binary stage, an adder stage, an adder output stage, an adder input latch stage coupled to latch outputs of the GC to binary stage, a feedback multiplexer stage coupled to receive the outputs of the GC to binary stage, a latch output multiplexer coupled to receive outputs of the first adder input latches, where the latch output multiplexer is configured to multiply the outputs of the first adder input latches by either -1 or -2, and an adder input multiplexer stage, where first inputs of the adder input multiplexer stage are coupled to receive outputs of the latch output multiplexer and second inputs of the adder input multiplexer stage are coupled to receive outputs of the second adder input latches. The arithmetic logic performs adaptive correlated multiple sampling for image sensing pixels and phase detection auto focus for other pixels.