Memory system

Abstract

This invention provides a memory system capable of suppressing degradation in the access performance of non-volatile memory. According to one embodiment, the memory system includes multiple memory chips, each containing multiple first blocks, and a controller. The controller controls the parallel access of the multiple memory chips using multiple parallel access units. Each parallel access unit contains one of multiple second blocks, which are allocated sequentially from each memory chip. The controller manages transition information for each memory chip, specifying that the number of initial defective blocks in each parallel access unit is below a permissible number. The controller generates, corresponding to each parallel access unit, an indication of whether the number of defective blocks in each reconstructed parallel access unit is below a permissible number.