Artificial intelligence accelerator having computing units heterogeneously integrated with memory dies

Abstract

Disclosed are architectures of semiconductor integrated circuit (IC) device, more specifically an artificial intelligence (AI) accelerator. The AI accelerator comprises a processing block, a memory block disposed laterally side-by-side to each other and over a common substrate, and a logic base die vertically interposed between the common substrate and the memory block. The processing block comprises a computing die that comprises a plurality of parallel processing cores for processing artificial intelligence algorithms. The memory block heterogeneously integrated with the processing block through electrical connections formed in the common substrate. The memory block comprises a memory stack that comprises one or more vertically stacked memory die layers. The logic base die comprises one or more data communication interfaces between the memory block and the processing block. The data communication interfaces include at least a network on chip configured to electrically connect the memory block with each processing core.