Semiconductor device including memory cell array regions and interface region

Abstract

A semiconductor device is provided. The semiconductor device comprises: first and second memory cell array regions spaced apart from each other; a first interface region between the first and second memory cell array regions; first and second word lines crossing the first memory cell array region, the first interface region, and the second memory cell array region; a first back gate electrode between the first and second word lines in the first memory cell array region, and extending into the first interface region; and a first back gate dielectric layer. The first back gate dielectric layer comprises a first portion between the first word line and the first back gate electrode in the first memory cell array region, and a second portion between the second word line and the first back gate electrode.