Semiconductor memory devices

Abstract

This invention provides a semiconductor memory device that can suppress the degradation of memory cell reliability. One embodiment of the semiconductor memory device includes: a first word line; a second word line; a first memory cell connected to the first word line; a second memory cell connected to the second word line; and a control circuit that performs data writing operations to the first and second memory cells. During the writing operation, a plurality of programming cycles, each including a programming operation and a verification operation, are executed sequentially. During the verification operation for the first memory cell, when a first voltage is applied to the second word line and a second voltage is applied to the first word line, the control circuit applies a third voltage corresponding to the writing state to the first word line, and changes the voltage level of the second voltage as the plurality of programming cycles progress.