Vertical junction field effect transistor and manufacturing method thereof

Abstract

The present invention provides a vertical junction field-effect transistor (JFET) and a manufacturing method thereof. The vertical JFET comprises an N+ type substrate, an N type bulk region, an N type drift region, two P type buried regions, two P type base regions, two P+ type gate regions, and an N+ type source region. When the vertical JFET is in a conduction mode, a channel is formed in a vertical direction between the N+ type source region and the N+ type substrate through the N type drift region and the N type bulk region, allowing conduction of current. The structure of the vertical JFET ensures that the channel is formed exclusively in the vertical direction, with the conduction current flowing vertically from the N+ type source region to the N+ type substrate. Furthermore, each of the P type buried region and the corresponding P type base region form a continuous P type region, which improves the vertical JFET's conductive resistance, breakdown voltage, and leakage current characteristics.

Description

Technical Field

[0001] This invention relates to a vertical junction field-effect transistor and its manufacturing method, particularly to a vertical junction field-effect transistor and its manufacturing method that can improve the on-resistance, breakdown voltage and leakage current characteristics of the vertical junction field-effect transistor. Prior Technology

[0002] As shown in Figure 1, a vertical junction field-effect transistor (vertical JFET) is a semiconductor device that uses an electric field to control the conductivity of a channel. Its characteristic is that the current transmission direction of the channel is vertical (perpendicular to the substrate).

[0003] The vertical JFET 10 includes a drain 18 located at the bottom of the device, typically made of highly doped N+ type semiconductor material, used to carry current. Above the drain 18 is an N-type region 12, a layer of N-type semiconductor responsible for supporting high voltage and assisting in vertical current transport. Above and adjacent to the N-type region 12 is a P+ type gate 16 region, composed of P-type regions, located on both sides of the channel. Applying voltage controls the opening and closing of the channel, thus affecting current transport. The channel is the current transport path between the N+ type source 17 and the drain 18, and can be divided into vertical channels and horizontal channels. The N+ type source 17 of the vertical JFET 10 is located at the top of the device, serving as the starting point for providing current.

[0004] The vertical JFET 10 operates based on the depletion effect. When a reverse bias is applied between the P+ gate 16 and the N-type region 12, the depletion region expands and blocks current flow; however, when an appropriate voltage is applied to the P+ gate 16, the channel is opened, allowing current to flow through the channel between the N+ source 17 and drain 18. The conductivity of the channel is determined by the gate voltage, thus enabling precise current control.

[0005] The vertical junction field-effect transistor (VJFET)10 in the prior art still has significant shortcomings in terms of performance optimization in terms of structural design. Its main problem is that it has failed to effectively balance the doping concentration in different regions to simultaneously optimize the electric field distribution and on-resistance.

[0006] First, from a reliability standpoint, the relatively high doping concentration in the N-type region 12 in prior art leads to a smaller depletion region. This structure restricts the uniform distribution of the electric field in the N-type region 12, causing the electric field to become overly concentrated in specific areas, thereby reducing the device's breakdown voltage. This design not only affects the device's breakdown voltage characteristics but also limits its reliability in high-voltage environments.

[0007] Secondly, from the perspective of on-resistance, the doping concentration of the N-type region 12 in the prior art is relatively low, which cannot provide a sufficiently low resistance to improve the conduction path of the P+ gate region 16. When the vertical junction field-effect transistor 10 operates in the on-state, the higher base region resistance increases the resistive loss between the N+ source region 17 and the drain region 18, further affecting the device's conduction efficiency. At the same time, an excessively low doping concentration of the N-type region 12 may lead to insufficient electrical connection between the source region 17 and the drain region 18, weakening the effective control of the current path.

[0008] In view of the shortcomings of prior art, the present invention provides a design for a vertical junction field-effect transistor that can significantly improve on-resistance, breakdown voltage and leakage current characteristics through a simple manufacturing process. Summary of the Invention

[0009] From one perspective, the present invention provides a vertical junction field-effect transistor, comprising: an N+ type substrate, which is a semiconductor material; an N-type substrate region formed and connected to the N+ type substrate; an N-type drift region formed and connected to the N-type substrate region; two P-type buried regions formed below the N-type drift region, horizontally separated and not connected to each other, and located to the left and right of the N-type drift region, respectively, with a portion of the N-type substrate region separating the two P-type buried regions; two P-type base regions formed and connected to the corresponding two P-type buried regions; and two P+ type gate regions connected to the corresponding two P-type base regions, and electrically connected to the P-type buried regions via the corresponding two P-type base regions. An N+ type source region is formed within the N-type drift region. When the vertical junction field-effect transistor is turned on, a channel is formed only in the vertical direction between the N+ type source region and the N+ type substrate, through the N-type drift region and the N-type substrate region, to conduct a conduction current. The structure of the vertical junction field-effect transistor ensures that the channel is formed only in the vertical direction, and the conduction current flows vertically from the N+ type source region to the N+ type substrate. The two P-type buried regions are respectively connected to the corresponding two P-type base regions to form two independent and continuous P-type regions. The two P-type regions are used to improve the on-resistance, breakdown voltage, and leakage current characteristics of the vertical junction field-effect transistor.

[0010] In one embodiment, the semiconductor material is silicon (Si), silicon carbide (SiC), or gallium nitride (GaN).

[0011] In one embodiment, the N-type drift region is formed by an epitaxial growth process or an ion implantation process.

[0012] In one embodiment, the two P-type buried areas extend in the horizontal direction relative to the corresponding two P-type base areas in the following ways: extending beyond the sides of the corresponding two P-type base areas to cover and connect part of the lower surface of the N-type drift area; or not extending beyond the sides of the corresponding two P-type base areas and not covering the lower surface of the N-type drift area.

[0013] In one embodiment, the structure of the vertical junction field-effect transistor includes the following: the two P-type buried regions extend in the horizontal direction relative to the corresponding two P-type base regions in such a way as: extending beyond the sides of the corresponding two P-type base regions to cover and connect a portion of the lower surface of the N-type drift region; or not extending beyond the sides of the corresponding two P-type base regions and not covering the lower surface of the N-type drift region.

[0014] In one embodiment, when the vertical junction field-effect transistor is turned on, the structure of the vertical junction field-effect transistor includes: a planar structure, wherein the upper surface of the N-type drift region and the upper surfaces of the two P-type base regions are completely located on a horizontal plane at the same vertical height, and the two gates that are electrically connected to the two P+ type gate regions by ohmic contacts are completely located on the horizontal plane; or a trench structure, wherein the upper surface of the N-type drift region and the upper surfaces of the two P-type base regions are located on a horizontal plane at the same vertical height, and at least part of the two P+ type gate regions are located below the bottom surface of the two trenches corresponding to the horizontal plane and inside the sidewalls, wherein the two trenches extend downward from the horizontal plane into the interior of the two P-type buried regions.

[0015] In one embodiment, the two P-type regions and the N-type drift interval form a super junction.

[0016] In one embodiment, the doping concentration of the two P-type base regions is higher than that of the two P-type buried regions to reduce the resistance between the two P+ type gate regions and the corresponding two P-type buried regions, and the doping concentration of the two P-type buried regions is relatively lower to improve the breakdown voltage.

[0017] In one embodiment, the vertical junction field-effect transistor further includes two gates respectively connected to the two P+ type gate regions, and the two gates and the corresponding two P+ type gate regions respectively form ohmic contacts, wherein the material of the two gates is titanium nitride (TiN), tantalum nitride (TaN) or aluminum (Al).

[0018] In one embodiment, the N-type drift region is formed by an ion implantation process step, and the implantation element used is nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb) or bismuth (Bi).

[0019] In one embodiment, the two P-type buried regions and the two P-type base regions are formed by corresponding two-ion implantation process steps, and the implantation elements used are boron (B), aluminum (Al), gallium (Ga) or indium (In).

[0020] From another perspective, the present invention provides a method for manufacturing a vertical junction field-effect transistor, comprising: providing an N+ type substrate, which is a semiconductor material; forming an N-type substrate region on the N+ type substrate, the N-type substrate region being connected to the N+ type substrate; forming an N-type drift region on the N-type substrate region; forming two P-type buried regions and two P-type base regions; forming two P+ type gate regions by an ion implantation process step, which are respectively connected to the corresponding two P-type base regions; and forming an N+ type source region in the N-type drift region by an ion implantation process step; wherein the two P-type buried regions are located below the N-type drift region, are horizontally separated, are not connected to each other, and are respectively located on the left and right sides of the N-type drift region, and are separated by a portion of the N-type substrate region; wherein the two P-type base regions are respectively located on and connected to the corresponding two P-type buried regions; wherein the two P+ The gate regions are electrically connected to the corresponding P-type buried regions via the corresponding P-type base regions. When the vertical junction field-effect transistor is turned on, the N+ type source region and the N+ type substrate are connected only through the N-type drift region and the N-type substrate region, forming a channel in the vertical direction to conduct a conduction current. The structure of the vertical junction field-effect transistor allows the channel to be formed only in the vertical direction, and the conduction current flows vertically from the N+ type source region to the N+ type substrate. The two P-type buried regions are connected to the corresponding P-type base regions to form two independent and continuous P-type regions. The two P-type regions are used to improve the on-resistance, breakdown voltage, and leakage current characteristics of the vertical junction field-effect transistor.

[0021] In one embodiment, the structure of the vertical junction field-effect transistor includes a planar structure; wherein the step of forming the two P-type buried regions and the two P-type base regions includes: forming the two P-type buried regions below the N-type drift region by an ion implantation process step; and forming the two P-type base regions above the corresponding two P-type buried regions by an ion implantation process step; wherein the N-type substrate region is formed by an epitaxial process step; wherein the upper surface of the N-type drift region and the upper surface of the two P-type base regions are completely located on a horizontal plane at the same vertical height, and the two gates that are electrically connected to the two P+ type gate regions by ohmic contacts are completely located on the horizontal plane.

[0022] In one embodiment, the structure of the vertical junction field-effect transistor includes a trench structure; wherein the step of forming the two P-type buried regions and the two P-type base regions includes: forming the two P-type implanted regions below the N-type drift region using an ion implantation process; etching downwards from an upper surface into the interior of the two P-type implanted regions using an etching process to form two trenches and the two P-type buried regions; and forming the two P-type base regions above the corresponding two P-type buried regions using an ion implantation process; wherein the ion implantation process forms the trenches and the two P-type buried regions. The steps of connecting the two P+ type gate regions to the corresponding two P type base regions include: implanting P-type impurities into the bottom surface and sidewall of each of the two trenches in an ion implantation process to form the two P+ type gate regions; wherein the N-type substrate region is formed by an epitaxial process; wherein the upper surface of the N-type drift region and the upper surface of the two P-type base regions are located at the same vertical height on a horizontal plane, and at least part of the two P+ type gate regions are located below the bottom surface and sidewall of the corresponding two trenches below the horizontal plane.

[0023] In one embodiment, the structure of the vertical junction field-effect transistor includes a superjunction structure; wherein the step of forming the two P-type buried regions and the two P-type base regions includes: forming two P-type implanted regions below the N-type drift region using an ion implantation process; etching from an upper surface downwards into the two P-type implanted regions to form two trenches and the two P-type buried regions using an etching process; implanting P-type impurities below the bottom surface and inside the sidewalls of each of the two trenches using an ion implantation process to form the two P-type base regions; and filling the two trenches with two P-type pillars respectively; wherein the two P-type regions and the N-type drift region form a superjunction.

[0024] Compared to prior art, this invention has significant advantages. The vertical junction field-effect transistor of this invention significantly improves device performance through the doping concentration of the P-type buried region and the P-type base region, offering several advantages. First, this invention employs a lower concentration of P-type buried region, formed beneath the N-type drift region. This design facilitates the formation of a uniform electric field distribution and depletion region in the N-type drift region during conduction mode, improving the control accuracy of the current path and reducing the risk of excessively high local electric fields, thus avoiding the adverse effects of electric field concentration on the device's breakdown voltage. This structural design not only enhances the device's withstand voltage performance but also enables it to exhibit higher stability and reliability in high-voltage applications.

[0025] On the other hand, this invention employs a high doping concentration in the P-type base region, successfully reducing the resistance within the base region. Since the P-type base region is located above the P-type buried region and electrically connects the P+ gate region and the P-type buried region in the vertical direction, the low resistance design of the base region effectively reduces current loss during conduction. This characteristic significantly improves the device's conduction efficiency, reduces power loss, and enhances the device's performance under high-power operating conditions. Furthermore, the high doping concentration in the P-type base region also enhances the stability of the electrical connection with the P-type buried region, thereby providing more precise channel control capabilities and improving the device's response characteristics during dynamic operation.

[0026] In summary, this invention achieves comprehensive performance optimization through the rational allocation of doping concentrations in the P-type buried region and the P-type base region. The low-concentration design of the P-type buried region ensures a uniform electric field distribution within the N-type drift region, improving conduction mode control capability, breakdown voltage, and reliability; while the high-concentration design of the P-type base region significantly reduces on-resistance, improves conduction efficiency, and enhances the overall performance of the device. This technological improvement enables the vertical-junction MOSFET of this invention to exhibit superior performance in high-voltage, high-power applications, overcoming the shortcomings of previous technologies and representing a significant innovation in high-efficiency electronic components.

[0027] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, features and effects achieved by this invention. Simple Explanation of the Diagram

[0028] Figure 1 shows a cross-sectional schematic diagram of a prior art vertical junction field-effect transistor structure.

[0029] Figure 2A shows a cross-sectional schematic diagram of a vertical junction field-effect transistor according to an embodiment of the present invention.

[0030] Figure 2B shows a cross-sectional schematic diagram of a vertical junction field-effect transistor according to an embodiment of the present invention.

[0031] Figure 3 shows a cross-sectional schematic diagram of another vertical junction field-effect transistor according to an embodiment of the present invention.

[0032] Figure 4 shows a cross-sectional schematic diagram of another vertical junction field-effect transistor according to an embodiment of the present invention.

[0033] Figures 5A-5F show cross-sectional schematic diagrams of a method for manufacturing a vertical junction field-effect transistor 20 according to an embodiment of the present invention.

[0034] Figures 6A-6F show cross-sectional schematic diagrams of a method for manufacturing a vertical junction field-effect transistor 30 according to another embodiment of the present invention.

[0035] Figures 7A-7F show cross-sectional schematic diagrams of a method for manufacturing a vertical junction field-effect transistor 40 according to another embodiment of the present invention. Implementation

[0036] The drawings in this invention are all schematic and are mainly intended to show the interrelationships between the components of the electronic components. The shapes and sizes are not drawn to scale.

[0037] Figure 2A shows a cross-sectional schematic of a vertical junction field-effect transistor 20, which has multiple semiconductor regions and is designed for efficient vertical current conduction. The vertical junction field-effect transistor 20 includes an N+ type substrate 21, an N-type base region 22, an N-type drift region 23, two P-type buried regions 24, two P-type base regions 25, two P+ type gate regions 26, two gates 26a, an N+ type source region 27, and an N+ type drain region 28.

[0038] The N+ type substrate 21 is a highly doped N-type semiconductor layer, a portion of which forms the drain region 28. The N-type substrate region 22 is located on and connected to the N+ type substrate 21. As a lightly doped N-type semiconductor layer, its main function is to improve the uniformity of the electric field distribution of the overall structure, thereby enhancing its breakdown voltage capability. The N-type drift region 23 is further formed and connected to the N-type substrate region 22. This layer is also a lightly doped N-type material and serves as the core region of the device, used to conduct current in the vertical direction and support high-voltage operation.

[0039] In one embodiment, the N+ type substrate 21 is a semiconductor material, specifically silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). In a preferred embodiment, the semiconductor material is silicon carbide.

[0040] In one embodiment, the N-type drift region 23 is formed by an epitaxial growth process or an ion implantation process.

[0041] In one embodiment, the P-type base region 25 has a higher doping concentration than the P-type buried region 24 to reduce the resistance between the P+ type gate region 26 and the P-type buried region 24, and the P-type buried region 24 has a relatively lower doping concentration to improve the breakdown voltage.

[0042] In one embodiment, the N-type drift region 23 is formed by an ion implantation process step, and the implantation element used is nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb) or bismuth (Bi).

[0043] In one embodiment, the P-type buried region 24 and the P-type base region 25 are formed by a corresponding ion implantation process step, and the implantation element used is boron (B), aluminum (Al), gallium (Ga) or indium (In).

[0044] Two P-type buried regions 24 are formed below the N-type drift region 23, horizontally separated and not connected to each other, and located to the left and right of the N-type drift region 23, respectively. A portion of the N-type substrate region 22 separates the two P-type buried regions 24. The two P-type buried regions 24 have a lower P-type doping concentration than the two P-type base regions 25, used to regulate the electric field distribution, making the electric field within the N-type drift region 23 more uniform, thereby improving the breakdown voltage of the vertical junction field-effect transistor 20. Connected to the two P-type buried regions 24 are the corresponding two P-type base regions 25, whose doping concentration is higher than that of the two P-type buried regions 24, thus significantly reducing the resistance within the two P-type base regions 25 and improving current conduction efficiency. Each P-type buried region 24 and its corresponding P-type base region 25 together form a continuous P-type region, which not only stabilizes the overall structure but also further improves the on-resistance, breakdown voltage, and leakage current characteristics of the vertical junction field-effect transistor 20.

[0045] Two P+ type gate regions 26 are located within corresponding two P-type base regions 25 and are electrically connected to corresponding two P-type buried regions 24 via the corresponding P-type base regions 25. The two P+ type gate regions 26 achieve the opening and closing of the vertical channel by applying a control voltage. The two P+ type gate regions 26 form ohmic contacts with the corresponding two gates 26a, providing stable electric field control capability. The material of the two gates 26a is, for example, titanium nitride (TiN), tantalum nitride (TaN), or aluminum (Al). The N+ type source region 27 is located on top of the N-type drift region 23 and serves as the main current input terminal. It forms a vertical channel with the N+ type substrate 21 below, achieving efficient current conduction.

[0046] In the on-state, a vertical channel is formed between the N+ source region 27 and the N+ substrate 21 via the N-type drift region 23 and the N-type base region 22, and the vertical junction field-effect transistor 20 exhibits only this vertical channel during conduction. The conduction current flows vertically from the N+ source region 27 to the N+ substrate 21. This vertical structure design ensures the directionality of the channel, preventing the formation of lateral channels, thereby significantly improving conduction efficiency and reducing power loss. Simultaneously, the structural optimization of the two P-type buried regions 24 and the two P-type base regions 25 further enhances the uniformity of the electric field distribution and low-resistance characteristics, which is particularly important for high-voltage applications.

[0047] The structure of the vertical junction field-effect transistor according to the present invention allows for various design variations, such as planar and trench structures. In the planar structure, the upper surface of the N-type drift region 23 and the upper surfaces of the two P-type base regions 25 are completely located on a horizontal plane at the same vertical height, and the two gates 26a, which are electrically connected to the two P+ type gate regions 26 by ohmic contacts, are also completely located on this horizontal plane. In the trench structure, the upper surface of the N-type drift region 23 and the upper surfaces of the two P-type base regions 25 are located on a horizontal plane at the same vertical height, and at least a portion of the two P+ type gate regions 26 are located in two corresponding trenches below this horizontal plane, wherein the two trenches extend downward from this horizontal plane into the interior of the two P-type buried regions 24, as will be described in detail later. These design variations provide flexibility for different applications and further expand the applicability of the device.

[0048] Overall, the vertical junction field-effect transistor 20 effectively improves the electrical performance of the device through its carefully designed multilayer structure and doping concentration distribution. It has advantages in on-resistance, withstand voltage and leakage current control, providing an efficient and reliable solution for high-voltage and high-power electronic applications.

[0049] Figure 2B shows a cross-sectional schematic diagram of another embodiment of the vertical junction field-effect transistor 20. The embodiment shown in Figure 2B differs from the embodiment shown in Figure 2A in that the extension of the two P-type buried regions 24 relative to the two P-type base regions 25 in the embodiment of Figure 2B is different from the design in the embodiment shown in Figure 2A. In Figure 2A, each P-type buried region 24 extends horizontally beyond the side of the corresponding P-type base region 25, covering and connecting a portion of the lower surface of the N-type drift region 23. The main purpose of this structural design is to enhance the electric field control capability between the two P-type buried regions 24 and the N-type drift region 23, thereby further improving the breakdown voltage and current control characteristics of the device.

[0050] However, the design in the embodiment shown in Figure 2B employs a different extension method. In Figure 2B, the two P-type buried regions 24 do not extend beyond the sides of the corresponding two P-type base regions 25 in the horizontal direction, and do not cover the lower surface of the N-type drift region 23. This design reduces the impact of the two P-type buried regions 24 on the lower surface of the N-type drift region 23, has lower on-resistance, is more suitable for certain applications requiring a simpler electric field distribution, and may reduce the complexity of the manufacturing process.

[0051] Figure 3 shows a cross-sectional schematic diagram of another vertical junction field-effect transistor according to an embodiment of the present invention. Figure 3 shows a trench-structured vertical junction field-effect transistor 30, characterized by the design of two vertical trenches to further improve device performance and control capability. The vertical junction field-effect transistor 30 includes an N+ type substrate 31, an N-type base region 32, an N-type drift region 33, two P-type buried regions 34, two P-type base regions 35, two P+ type gate regions 36, an N+ type source region 37, a drain 38, and a gate 36a.

[0052] In the structure shown in Figure 3, the N+ type substrate 31 serves as the main current outlet and also constitutes the drain region 38. The N-type substrate region 32 is immediately above the N+ type substrate 31, and its main function is to improve the uniformity of the electric field distribution and enhance the withstand voltage capability. The N-type drift region 33 is located above the N-type substrate region 32, providing the main vertical current conduction path.

[0053] Two P-type buried regions 34 are formed below the N-type drift region 33, horizontally separated and not connected to each other, and located to the left and right of the N-type drift region 33, respectively. A partial N-type substrate region 32 separates the two P-type buried regions 34. The two P-type buried regions 34 are designed below the N-type drift region 33 to adjust the electric field distribution and improve the breakdown voltage. Two P-type base regions 35 are located above the corresponding two P-type buried regions 34, and their higher doping concentration reduces resistance, further improving the efficiency of current conduction. P+ type gate regions 36 are embedded in the corresponding two trenches, extending into the device through the trench sidewalls, and are connected to the corresponding two P-type base regions 35, forming an electrical connection either through the corresponding two P-type base regions 35 or directly to the P-type buried regions 34.

[0054] Figure 3 shows a trench-structured vertical junction field-effect transistor 30, the core feature of which is the arrangement of two trenches, such that the two P+ type gate regions 36 are at least partially located in the corresponding two trenches. The main purpose of this trench design is to shorten the distance of the electric field control channel, enhance the control capability of the gate 36a, and further reduce the formation of transverse current. Simultaneously, the P+ type gate regions 36 inside the trenches form ohmic contacts with the gate 36a, allowing the vertical channel to be opened or closed by applying a control voltage.

[0055] The N+ source region 37 is located at the top of the N-type drift region 33 and serves as the main current input terminal. When the vertical junction field-effect transistor 30 is in the on state, a vertical channel is formed between the N+ source region 37 and the N+ substrate 31 through the N-type drift region 33 and the N-type substrate region 32, allowing the conduction current to flow vertically from the N+ source region 37 to the N+ substrate 31. This structural design ensures channel directionality, avoids the formation of lateral current, thereby improving conduction efficiency and reducing power loss.

[0056] Furthermore, this trench structure offers design flexibility. For example, the position of the P-type base region 35 in the trench and the depth of the P+ type gate region 36 can be adjusted according to application requirements to optimize the on-resistance, breakdown voltage, and leakage current control performance of the component. By adopting this design, the vertical-junction MOSFET 30 exhibits excellent performance in high-voltage, high-power applications, and is particularly advantageous in scenarios requiring strong electric field control.

[0057] The other parts of the vertical junction field-effect transistor 30, including the N+ type substrate 31, N type substrate region 32, N type drift region 33, two P type buried regions 34, two P type base regions 35, drain 38, and gate 36a, are similar in structure, function, and relative connection relationship to the N+ type substrate 21, N type substrate region 22, N type drift region 23, two P type buried regions 24, two P type base regions 25, drain 28, and gate 29 of the vertical junction field-effect transistor 20. Please refer to the description of the vertical junction field-effect transistor 20, which will not be repeated here.

[0058] Figure 4 shows a cross-sectional view of the vertical junction field-effect transistor 40 of the present invention, which has a superjunction structure. The vertical junction field-effect transistor 40 includes an N+ type substrate 41 as the base semiconductor material, on which an N-type substrate region 42 is formed to support its upper structure. Located above the N-type substrate region 42 is an N-type drift region 43, which provides the main current conduction path. Below the N-type drift region 43 are two P-type buried regions 44, which are located on both sides of the N-type drift region 43 and are separated in the horizontal direction without contacting each other.

[0059] Above the P-type buried region 44, each is connected to a P-type base region 45, forming a corresponding P-type region. A P+ type gate region 46 is further formed via an ion implantation process. This P+ type gate region 46 is embedded in a corresponding P-type pillar 49, and is electrically connected to the corresponding P-type base region 45 and P-type buried region 44 via the P-type pillar 49, providing good gate control capability. An N+ type source region 47 is embedded within the N-type drift region 43, serving as the source terminal for current transmission. Current is conducted downwards to the N+ type substrate 41 via the N-type drift region 43 and the N-type substrate region 42. A drain 48 is connected below the N+ type substrate 41.

[0060] Figure 4 shows that the P-type buried region 44 extends upward to form two trench structures, which are filled with P-type pillars 49. These P-type pillars 49 connect to the P-type base region 45, further enhancing the superjunction structure performance of the vertical junction field-effect transistor 40. The core of the superjunction structure lies in the doping concentration design between the P-type buried region 44, the P-type pillars 49, and the N-type drift region 43, achieving a uniform electric field distribution through alternating P-type and N-type regions. This uniform distribution significantly improves the breakdown voltage of the vertical junction field-effect transistor 40 while reducing the on-resistance, thereby improving the overall device performance.

[0061] Furthermore, the superjunction structure shown in Figure 4 helps reduce leakage current because the arrangement of the P-type regions in the vertical direction optimizes the formation of the depletion region, further suppressing lateral leakage current. This structure is particularly suitable for high-voltage applications, such as power conversion and power management circuits, providing excellent performance and reliability.

[0062] In a preferred embodiment, the doping concentration design between the two P-type regions and the complex N-type drift regions 43 ensures that the electric field distribution within the superjunction region is uniform when the vertical junction field-effect transistor 40 is on, thereby improving the breakdown voltage. The doping concentration of the P-type buried region 44 is designed to be lower than that of the P-type base region 45 to reduce parasitic current within the superjunction. The doping concentration of the N-type drift regions 43 is designed to match the doping concentration of the P-type regions, ensuring that the depletion region within the superjunction is fully filled when the vertical junction field-effect transistor 40 is not on, thus reducing leakage current. By optimizing the doping concentration gradient design, the superjunction structure effectively reduces the on-resistance, thereby improving the efficiency and stability of the vertical junction field-effect transistor 40.

[0063] Figures 5A to 5F show cross-sectional schematic diagrams of a method for manufacturing a vertical junction field-effect transistor 20 according to an embodiment of the present invention. The method includes several steps, as described below.

[0064] First, as shown in FIG5A, an N+ type substrate 21 is provided as a substrate for the manufacturing process. This substrate is made of a semiconductor material, such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). In a preferred embodiment, the N+ type substrate 21 is silicon carbide. An N-type substrate region 22 is formed on the N+ type substrate 21 using an epitaxial growth process. The N-type substrate region 22 is connected to the N+ type substrate 21.

[0065] Next, as shown in Figure 5B, a drift extension region 23' is formed on the N-type substrate region 22 to form the N-type drift region 23. The drift extension region 23' can be formed using epitaxial growth or ion implantation. The N-type drift region 23 provides the main current conduction path for the vertical junction field-effect transistor 20, and its doping concentration and thickness design determine the on-resistance and breakdown voltage characteristics of the vertical junction field-effect transistor 20. When the drift extension region 23' is formed using an ion implantation process, for example, an ion implantation step can be used to dope N-type impurities in the upper portion of the N-type substrate region 22. As shown in Figure 5B, an N+ type drain region 28 is formed in a portion below the N+ type substrate 21. The N+ type drain region 28 can be formed, for example, using an ion implantation step to dope N-type impurities in the lower portion of the N+ type substrate 21.

[0066] Subsequently, as shown in Figure 5C, two P-type buried regions 24 are formed using an ion implantation process. These two P-type buried regions 24 are located on the left and right sides below the N-type drift region 23, respectively, and are horizontally separated and unconnected. A portion of the N-type substrate region 22 separates the two P-type buried regions 24 to ensure uniform electric field distribution and further improve the device's breakdown voltage performance.

[0067] Next, as shown in Figure 5D, two P-type base regions 25 are formed above the P-type buried region 24 using another ion implantation process step. These P-type base regions 25 are connected to the corresponding P-type buried regions 24, and their doping concentration is high to reduce the resistance between the P+ type gate region 26 and the P-type buried region 24.

[0068] As shown in Figure 5E, two P+ type gate regions 26 are further formed inside the P-type base region 25. This step is also completed using an ion implantation process. The P+ type gate region 26 is connected to the corresponding P-type base region 25 and electrically connected to the P-type buried region 24 through the P-type base region 25, forming a complete P-type region structure.

[0069] Finally, as shown in Figure 5F, an N+ type source region 27 is embedded within the N-type drift region 23. This region is also formed by the ion implantation process. The N+ type source region 27 serves as the current input terminal and is connected to the N-type drift region 23 and the N-type substrate region 22, ensuring that the current can be vertically conducted to the N+ type substrate 21, forming a complete vertical current channel.

[0070] In the overall structural design, the P-type buried region 24 and the P-type base region 25 form two independent and continuous P-type regions. These regions, together with the N-type drift region 23, can form a superjunction structure. This superjunction structure uniformly distributes the electric field, reduces the on-resistance, improves the breakdown voltage performance, and effectively reduces leakage current, thereby significantly improving the overall performance of the vertical junction field-effect transistor 20.

[0071] In one embodiment, the upper surface of the N-type drift region 23 and the upper surfaces of the two P-type base regions 25 are located at the same horizontal plane at the same vertical height, and the two gates 26a (see FIG. 2A), which are electrically connected to the two P+ type gate regions by ohmic contacts, are located entirely on this horizontal plane. The material of the two gates 26a is, for example, titanium nitride (TiN), tantalum nitride (TaN), or aluminum (Al).

[0072] In one embodiment, the N-type drift region 23 is formed by an ion implantation process step, and the implantation element used is nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb) or bismuth (Bi).

[0073] In one embodiment, the P-type buried region 24 and the P-type base region 25 are formed by a corresponding ion implantation process step, and the implantation element used is boron (B), aluminum (Al), gallium (Ga) or indium (In).

[0074] Figures 6A to 6F show cross-sectional schematic diagrams of a method for manufacturing a vertical junction field-effect transistor 30 according to an embodiment of the present invention.

[0075] First, referring to FIG6A, the manufacturing method begins by providing an N+ type substrate 31, which is a semiconductor material, such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). An N-type substrate region 32 is formed on the N+ type substrate 31 via an epitaxial process, and a drift extension region 33' is formed on the N-type substrate region 32 to further form an N-type drift region 33.

[0076] Next, two P-type implantation regions 34' are formed below the drift extension region 33' (the subsequently formed N-type drift region 33) using the ion implantation process. These P-type implantation regions 34' are the preliminary structure and will form the P-type buried region 34.

[0077] Next, referring to Figure 6B, an etching process is performed, etching downwards from the upper surface of the drift extension region 33' (the N-type drift region 33 subsequently formed) to the interior of the two P-type implantation regions 34', forming two trenches TRH. The inner wall of the trenches TRH contacts the P-type implantation region, further establishing the shape and position of the P-type buried region 34.

[0078] Then, as shown in Figure 6C, a counter doping process is performed on the left and right sides of the drift extension region 33' using an ion implantation step to further form two P-type base regions 35 and define an N-type drift region 33. The two P-type base regions 35 are located on the corresponding two P-type buried regions 34 and are electrically connected to them.

[0079] Referring to Figure 6D, in the two P-type base regions 35, P-type impurities are implanted below the bottom surface and inside the sidewalls of the two trenches Trh using an ion implantation process to form P+ type gate regions 36. The P+ type gate region 36 is structurally connected to the P-type base region 35 and is electrically connected to the corresponding P-type buried region 34 via the P-type base region 35 or directly.

[0080] Figure 6E further shows that an N+ type source region 37 is formed in the N-type drift region 33 using an ion implantation process. Simultaneously, a drain 38 is provided below the N+ type substrate 31, the structure of which may include a metallic material to improve conductivity.

[0081] Finally, as shown in Figure 6F, conductive material is further deposited on the surface of the structure to form a gate 36a that is electrically connected to the P+ type gate region 36, and the gate 36a forms an ohmic contact with the P+ type gate region 36.

[0082] The upper surface of the N-type drift region 33 and the upper surface of the two P-type base regions 35 are located on one of the same vertical heights on a horizontal plane, and at least part of the two P+ type gate regions 36 are located below the bottom surface of the two corresponding trenches Trh and inside the sidewalls below the horizontal plane.

[0083] Figures 7A to 7F show cross-sectional schematic diagrams of a method for manufacturing a vertical junction field-effect transistor 40 according to an embodiment of the present invention. The steps of the manufacturing method are described in detail below with reference to the figures.

[0084] In Figure 7A, an N+ type substrate 41, which is a semiconductor material, is first provided as the substrate for the vertical junction field-effect transistor 40. Subsequently, an N-type substrate region 42 is formed on the N+ type substrate 41. The N-type substrate region 42 can be grown using an epitaxial process to provide a layer connected to the N+ type substrate 41.

[0085] Continuing with Figure 7B, a drift extension region 43' is formed on the N-type substrate region 42 to further form the N-type drift region 43. This drift extension region 43' (which subsequently forms the N-type drift region 43) can be formed through epitaxial growth or ion implantation processes, and two P-type implantation regions 44' are formed below it, serving as the basis for the two corresponding P-type buried regions 44. This step ensures the vertical conductivity of the N-type drift region 43, laying the foundation for the subsequent channel formation.

[0086] As shown in Figure 7C, an etching process is performed, etching downwards from the upper surface of the drift extension region 43' (which will subsequently form the N-type drift region 43) into the interior of the two previously formed P-type implantation regions 44', forming two trenches 49'. These trenches 49' define the structure of the subsequently formed P-type buried region 44 and P-type base region 45.

[0087] In Figure 7D, a P-type impurity is implanted into the bottom surface and sidewalls of two trenches 49' using an ion implantation process, thereby forming two P-type base regions 45. Simultaneously, structures are formed that are connected to the corresponding two P-type buried regions 44. An N-type drift region 43 is also defined. The formation of the P-type base regions 45 can provide good electric field control and improve device performance.

[0088] As shown in Figure 7E, P-type pillars 49 are filled into the two trenches 49' to ensure structural integrity. In this step, the two P-type pillars 49 can be connected to the corresponding two P-type base regions 45 and the corresponding two P-type buried regions 44 respectively to further form a superjunction structure to improve the breakdown voltage and reduce the leakage current.

[0089] Finally, in Figure 7F, an N+ type source region 47 is formed in the N-type drift region 43, and a P+ type gate region 46 is formed in the P-type base region 45. The N+ type source region 47 and the P+ type gate region 46 can be formed by ion implantation processes, and the source and gate are formed using metal ohmic contact technology, respectively. At this point, the structure of the vertical junction field-effect transistor 40 is complete, and the continuous P-type region formed by the two P-type buried regions 44 and the P-type base region 45 above them provides an important mechanism for improving on-resistance and enhancing the device's breakdown voltage characteristics.

[0090] The present invention has been described above with reference to preferred embodiments. However, the above description is merely to facilitate understanding of the invention by those skilled in the art and is not intended to limit the scope of the invention. Within the same spirit of the invention, those skilled in the art can conceive of various equivalent variations. For example, other process steps or structures, such as deep well zones, can be added without affecting the main characteristics of the components. All such variations can be derived by analogy from the teachings of the present invention. Therefore, the scope of the present invention should cover the above and all other equivalent variations. Furthermore, no embodiment of the present invention is necessarily required to achieve all objectives or advantages; therefore, no claim should be limited thereto.

[0091] 10, 20, 30, 40: Vertical junction field-effect transistors 12: N-type area 16, 26, 36, 46: P+ type gate region 17,27,37,47: N+ type source pole regions 18,28,38,48: Jiji 21,31,41:N+ type substrate 22, 32, 42: N-type matrix region 23, 33, 43: N-type drift zone 23', 33', 43': Drift extension area 24, 34, 44: P-type buried area 25, 35, 45: P-type base region 26a, 36a: Gate 34', 44': P-type implantation area 49: P-type column 49',Trh: trench

Claims

1. A vertical-junction field-effect transistor, comprising: an N+ type substrate, which is a semiconductor material; an N-type substrate region formed and connected to the N+ type substrate; an N-type drift region formed and connected to the N-type substrate region; two P-type buried regions formed below the N-type drift region, horizontally separated and not connected to each other, and located to the left and right of the N-type drift region, respectively, and separated by a portion of the N-type substrate region; two P-type base regions formed and connected to the corresponding two P-type buried regions; two P+ type gate regions connected to the corresponding two P-type base regions and electrically connected to the P-type buried regions via the corresponding two P-type base regions; and an N+ type source region formed in the N-type drift region; wherein... When the vertical junction field-effect transistor is turned on, a channel is formed only in the vertical direction between the N+ type source region and the N+ type substrate, through the N-type drift region and the N-type base region, to conduct a conduction current. The structure of the vertical junction field-effect transistor ensures that the channel is formed only in the vertical direction, and the conduction current flows vertically from the N+ type source region to the N+ type substrate. The two P-type buried regions are respectively connected to the corresponding two P-type base regions, forming two independent and continuous P-type regions. These two P-type regions are used to improve the on-resistance, breakdown voltage, and leakage current characteristics of the vertical junction field-effect transistor.

2. The vertical junction field-effect transistor as described in claim 1, wherein the semiconductor material is silicon (Si), silicon carbide (SiC), or gallium nitride (GaN).

3. The vertical junction field-effect transistor as described in claim 1, wherein the N-type drift region is formed by an epitaxial growth process or an ion implantation process.

4. The vertical junction field-effect transistor as described in claim 1, wherein the two P-type buried regions extend in the horizontal direction relative to the corresponding two P-type base regions in such a manner as: extending beyond the sides of the corresponding two P-type base regions to cover and connect a portion of the lower surface of the N-type drift region; or not extending beyond the sides of the corresponding two P-type base regions and not covering the lower surface of the N-type drift region.

5. The vertical junction field-effect transistor as described in claim 1, wherein the structure of the vertical junction field-effect transistor includes: A planar structure, wherein the upper surface of the N-type drift region and the upper surfaces of the two P-type base regions are completely located on a horizontal plane at the same vertical height, and the two gates that are electrically connected to the two P+ type gate regions by ohmic contact are completely located on the horizontal plane; or a trench structure, wherein the upper surface of the N-type drift region and the upper surfaces of the two P-type base regions are located on a horizontal plane at the same vertical height, and at least part of the two P+ type gate regions are located below the bottom surface and inside the sidewall of the two trenches corresponding to the horizontal plane, wherein the two trenches extend downward from the horizontal plane into the interior of the two P-type buried regions.

6. The vertical junction field-effect transistor as described in claim 1, wherein the two P-type regions and the N-type drift region form a super junction.

7. The vertical junction field-effect transistor as claimed in claim 1, wherein the doping concentration of the two P-type base regions is higher than that of the two P-type buried regions to reduce the resistance between the two P+ type gate regions and the corresponding two P-type buried regions, and the doping concentration of the two P-type buried regions is relatively lower to improve the breakdown voltage.

8. The vertical junction field-effect transistor as described in claim 1 further comprises two gates respectively connected to the two P+ gate regions, and the two gates and the corresponding two P+ gate regions respectively form ohmic contacts, wherein the material of the two gates is titanium nitride (TiN), tantalum nitride (TaN) or aluminum (Al).

9. The vertical junction field-effect transistor as claimed in claim 1, wherein the N-type drift region is formed by an ion implantation process step, and the implantation element used is nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb) or bismuth (Bi).

10. The vertical junction field-effect transistor as claimed in claim 1, wherein the two P-type buried regions and the two P-type base regions are formed by corresponding two-ion implantation process steps, and the implantation element used is boron (B), aluminum (Al), gallium (Ga) or indium (In).

11. A method for manufacturing a vertical junction field-effect transistor, comprising: providing an N+ type substrate, which is a semiconductor material; forming an N-type substrate region on the N+ type substrate, the N-type substrate region being connected to the N+ type substrate; forming an N-type drift region on the N-type substrate region; forming two P-type buried regions and two P-type base regions; forming two P+ type gate regions by an ion implantation process step, which are respectively connected to the corresponding two P-type base regions; and forming an N+ type source region in the N-type drift region by an ion implantation process step; wherein the two P-type buried regions are located below the N-type drift region, are horizontally separated, are not connected to each other, and are respectively located on the left and right sides of the N-type drift region, and are separated by a portion of the N-type substrate region; wherein the two P-type base regions are respectively located on and connected to the corresponding two P-type buried regions; wherein the two P+ The gate regions are electrically connected to the corresponding P-type buried regions via the corresponding P-type base regions; wherein... When the vertical junction field-effect transistor is turned on, a channel is formed only in the vertical direction between the N+ type source region and the N+ type substrate, through the N-type drift region and the N-type base region, to conduct a conduction current. The structure of the vertical junction field-effect transistor ensures that the channel is formed only in the vertical direction, and the conduction current flows vertically from the N+ type source region to the N+ type substrate. The two P-type buried regions are respectively connected to the corresponding two P-type base regions, forming two independent and continuous P-type regions. These two P-type regions are used to improve the on-resistance, breakdown voltage, and leakage current characteristics of the vertical junction field-effect transistor.

12. A method for manufacturing a vertical junction field-effect transistor as claimed in claim 11, wherein the structure of the vertical junction field-effect transistor includes a planar structure; wherein the step of forming the two P-type buried regions and the two P-type base regions includes: The two P-type buried regions are formed below the N-type drift region by an ion implantation process step; and the two P-type base regions are formed above the corresponding two P-type buried regions by an ion implantation process step; wherein the N-type base region is formed by an epitaxial process step; wherein the upper surface of the N-type drift region and the upper surface of the two P-type base regions are completely located at the same vertical height on a horizontal plane, and the two gates that are electrically connected to the two P+ type gate regions by ohmic contacts are completely located on the horizontal plane.

13. A method for manufacturing a vertical junction field-effect transistor as described in claim 11, wherein the structure of the vertical junction field-effect transistor includes a trench structure; wherein the step of forming the two P-type buried regions and the two P-type base regions includes: Two P-type implantation regions are formed under the N-type drift region using a single ion implantation process step; The process involves an etching process step, in which two P-type implanted regions are etched downwards from an upper surface to form two trenches and two P-type buried regions; and an ion implantation process step, in which two P-type base regions are formed on the corresponding two P-type buried regions; wherein the step of forming two P+ type gate regions and connecting them to the corresponding two P-type base regions by an ion implantation process step includes: implanting P-type impurities into the bottom surface and sidewall of each of the two trenches by an ion implantation process step to form the two P+ type gate regions; wherein the N-type substrate region is formed by an epitaxial process step; wherein the upper surface of the N-type drift region and the upper surface of the two P-type base regions are located at the same vertical height on a horizontal plane, and at least a portion of the two P+ type gate regions are located below the bottom surface and sidewall of the corresponding two trenches below the horizontal plane.

14. A method for manufacturing a vertical junction field-effect transistor as described in claim 11, wherein the structure of the vertical junction field-effect transistor includes a superjunction structure; wherein the step of forming the two P-type buried regions and the two P-type base regions includes: Two P-type implantation regions are formed below the N-type drift region using a single ion implantation process step; An etching process is used to etch downwards from an upper surface into the interior of the two P-type implantation regions to form two trenches and the two P-type buried regions; an ion implantation process is used to implant P-type impurities into the interior of the bottom surface and sidewalls of each of the two trenches to form the two P-type base regions; and two P-type pillars are filled into the two trenches respectively; wherein the two P-type regions and the N-type drift region form a super junction.

15. A method for manufacturing a vertical junction field-effect transistor as described in claim 11, wherein the semiconductor material is silicon (Si), silicon carbide (SiC), or gallium nitride (GaN).

16. A method for manufacturing a vertical junction field-effect transistor as claimed in claim 11, wherein the N-type drift region is formed by an epitaxial growth process step or an ion implantation process step.

17. A method for manufacturing a vertical junction field-effect transistor as claimed in claim 11, wherein the two P-type buried regions extend in the horizontal direction relative to the corresponding two P-type base regions in such a manner as: extending beyond the sides of the corresponding two P-type base regions to cover and connect a portion of the lower surface of the N-type drift region; or not extending beyond the sides of the corresponding two P-type base regions and not covering the lower surface of the N-type drift region.

18. A method for manufacturing a vertical junction field-effect transistor as claimed in claim 11, wherein the doping concentration of the two P-type base regions is higher than that of the two P-type buried regions to reduce the resistance between the two P+ type gate regions and the corresponding two P-type buried regions, and the doping concentration of the two P-type buried regions is relatively lower to increase the breakdown voltage.

19. A method for manufacturing a vertical junction field-effect transistor as claimed in claim 11, wherein the vertical junction field-effect transistor further comprises two gates respectively connected to the two P+ type gate regions, and the two gates and the corresponding two P+ type gate regions respectively form ohmic contacts, wherein the material of the two gates is titanium nitride (TiN), tantalum nitride (TaN) or aluminum (Al).

20. A method for manufacturing a vertical junction field-effect transistor as claimed in claim 11, wherein the N-type drift region is formed by an ion implantation process step, and the implantation element used is nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb) or bismuth (Bi).

21. A method for manufacturing a vertical junction field-effect transistor as described in claim 11, wherein the P-type buried region and the P-type base region are formed by a corresponding ion implantation process step, and the implantation element used is boron (B), aluminum (Al), gallium (Ga) or indium (In).