Integrated circuit, single photon avalanche diode and method for forming integrated circuit device
Patent Information
- Application Number
- TW114105798
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-12-27
- Filing Date
- 2025-02-17
- Publication Date
- 2026-07-01
- Estimated Expiration
- 2045-02-16
Abstract
Claims
1. An integrated circuit comprising an array of avalanche photodiode elements, wherein: The first avalanche photodiode element of the avalanche photodiode element array includes: an absorption region including an absorbing semiconductor, the absorption region being configured to generate charge carriers in response to incident photons; a multiplication region, a diode including a multiplication semiconductor, the multiplication region being configured to generate an avalanche current including charge carriers in response to the generated charge carriers drifting into the multiplication region; a first-type doped region for collecting the charge carriers of the avalanche current, wherein the first-type doped region is part of the multiplication region; a mesh structure surrounding the absorption region; and an abutment contact including a deep contact portion contacting the first-type doped region and a mesh portion connected to a corresponding portion of the mesh structure.
2. The integrated circuit as claimed in claim 1, wherein the avalanche photodiode is a single-photon avalanche diode configured to operate in Geiger mode.
3. The integrated circuit as claimed in claim 1, wherein: The absorbing semiconductor is germanium; and the multiplying semiconductor is silicon.
4. The integrated circuit as claimed in claim 1, wherein: The diode in the multiplication region includes a P-type region covering and adjacent to the N-type region, the two regions forming a PN junction; the N-type region is electrically connected to a deep contact portion of the abutment contact; the absorption region is electrically connected to a bias contact; and the integrated circuit is configured to bias the abutment contact and the bias contact respectively to generate a reverse bias at the PN junction and to generate an electric field sufficient to accelerate the generated charge carriers to produce the avalanche current.
5. The integrated circuit as claimed in claim 1, wherein the abutting contact comprises tungsten.
6. The integrated circuit as claimed in claim 1, wherein the first avalanche photodiode element further includes a deep P-well surrounding the multiplication region, the deep P-well including a planar portion below the multiplication region and a sidewall portion surrounding the multiplication region.
7. The integrated circuit as claimed in claim 1, wherein: The array further includes a second avalanche photodiode element adjacent to the first avalanche photodiode element; The second avalanche photodiode element includes: an absorption region comprising the absorbing semiconductor, the absorption region being configured to generate charge carriers in response to incident photons; The device comprises: a multiplication region of the diode of the multiplication semiconductor, the multiplication region being configured to generate an avalanche current including charge carriers in response to charge carriers drifting into the multiplication region; a first-type doped region for collecting the charge carriers of the avalanche current, wherein the first-type doped region is part of the multiplication region of the second avalanche photodiode element; a grid structure surrounding the absorption region; and an abutment contact including a deep contact portion contacting the first-type doped region and a grid portion connected to a corresponding portion of the grid structure; and the first avalanche photodiode element and the second avalanche photodiode element sharing some features therebetween, such that a portion of the grid structure of the first avalanche photodiode is also a portion of the grid structure of the second avalanche photodiode.
8. A single-photon avalanche diode, comprising: The device comprises: an absorption region of an absorbing semiconductor configured to generate charge carriers in response to incident photons; a multiplication region of a diode comprising a multiplication semiconductor configured to generate an avalanche current comprising charge carriers by the drift of generated charge carriers into the multiplication region; a first-type doped region for collecting the charge carriers of the avalanche current, wherein the first-type doped region is part of the multiplication region; a conductive mesh structure surrounding the absorption region; and an abutment contact comprising a via portion extending to a contact portion of the first-type doped region and a raised body portion extending laterally from the via portion to the conductive mesh structure.
9. A method of forming an integrated circuit device, the method comprising: A first-type doped region and a second-type doped region covering it are formed to form a multiplication region, the multiplication region being configured to generate an avalanche current including charge carriers in response to the drift of generated charge carriers into the multiplication region; an absorption region covering the multiplication region is formed, the absorption region being configured to generate the charge carriers in response to incident photons; a mesh structure surrounding the absorption region is formed; And forming abutting contacts, including a deep contact portion that contacts the first type of doped region and a mesh portion that connects to a corresponding portion of the mesh structure.
10. The method as described in claim 9, wherein: The multiplication region includes silicon; and the absorption region includes germanium.