Capacitor structure and manufacturing method thereof

Abstract

A capacitor structure including a substrate, a first support layer, and a capacitor is provided. The first support layer is located on the substrate. The capacitor is located on the substrate. The capacitor includes a bottom electrode, a top electrode, and a dielectric layer. The bottom electrode includes a first portion and a second portion. The first portion is located on capacitor holes passing through the first support layer. The second portion is electrically connected to the first portion and covers a bottom surface of the first support layer. The top electrode is located on the bottom electrode. The dielectric layer is located between the bottom electrode and the top electrode.

Description

Capacitor Structure and Manufacturing Method This invention relates to a semiconductor structure and a method for manufacturing the same, and more particularly to a capacitor structure having a columnar capacitor and a method for manufacturing the same. Cylindrical capacitors are semiconductor components widely used in electronic products. However, as the size of cylindrical capacitors shrinks, further improving their capacitance and yield remains a continuous goal. For example, in conventional cylindrical capacitors, the bottom electrodes of multiple cylindrical capacitors are separated, which easily leads to defects such as bottom electrode peeling, thereby reducing yield and creating a bottleneck in increasing capacitance. This invention provides a capacitor structure and its manufacturing method, which can improve the defects of the bottom electrode and break through the bottleneck of capacitance improvement. This invention proposes a capacitor structure, including a substrate, a first support layer, and a capacitor. The first support layer is located on the substrate. The capacitor is located on the substrate. The capacitor includes a bottom electrode, a top electrode, and a dielectric layer. The bottom electrode includes a first portion and a second portion. The first portion is located on a plurality of capacitor holes penetrating the first support layer. The second portion is electrically connected to the first portion and covers the bottom surface of the first support layer. The top electrode is located on the bottom electrode. The dielectric layer is located between the bottom electrode and the top electrode. This invention proposes a method for manufacturing a capacitor structure, comprising the following steps: forming a first support layer on a substrate; forming a bottom electrode of the capacitor; the bottom electrode comprising a first portion and a second portion; the first portion being formed on a plurality of capacitor vias penetrating the first support layer; the second portion being electrically connected to the first portion and covering the bottom surface of the first support layer; forming a dielectric layer of the capacitor on the bottom electrode; and forming a top electrode of the capacitor on the dielectric layer. Based on the above, in the capacitor structure proposed in this invention, the bottom electrode includes a first portion and a second portion, with the second portion covering the bottom surface of the first support layer and even formed within a cavity. In this way, the second portion of the bottom electrode can provide additional coupling area, thereby effectively increasing the capacitance of the capacitor structure and providing a greater yield margin. Furthermore, the second portion of the bottom electrode can effectively improve the structural strength of the capacitor structure, thereby enhancing its overall quality. The following description provides detailed examples of embodiments. For ease of understanding, the same components will be designated with the same symbols in the description. Figures 1A to 1M are top views showing the manufacturing process of a capacitor structure according to some embodiments of the present invention. Figures 2A to 2M are cross-sectional views along section line I-I' in Figures 1A to 1M. Referring to Figures 1A and 2A, a dielectric layer 104 can be formed on a substrate 100, and a conductive plate 102 can be formed within the dielectric layer 104. Then, a stop layer 106, a sacrificial layer 108, a support layer 110, a sacrificial layer 112, and a support layer 114 can be formed sequentially on the conductive plate 102 and the dielectric layer 104. The substrate 100 can be a semiconductor substrate, such as a silicon substrate. In some embodiments, the substrate 100 can be silicon on insulation (SOI). The material of the conductive plate 102 can be a metal, such as tungsten or copper. In another embodiment, the conductive plate 102 can be a doped region (not shown) formed in the active region of the substrate 100. The material of the stop layer 106 can be a suitable etch-stop dielectric material. The materials of the support layers 110 and 114 can be suitable support dielectric materials. In this embodiment, the materials of the termination layer 106, the support layer 110, and the support layer 114 are, for example, nitrides (such as silicon nitride). In addition, the materials of the sacrificial layer 108 and the sacrificial layer 112 may be dielectric materials with an etch selectivity ratio to the support layers 110 and 114, such as oxides (such as silicon oxide). Referring to Figures 1B and 2B, a patterned photoresist layer 116 can be formed on the support layer 114. Referring to Figures 1C and 2C, the patterned photoresist layer 116 can be used as a mask to pattern the support layer 114, sacrificial layer 112, support layer 110, sacrificial layer 108, and termination layer 106, forming a plurality of capacitor holes OP1 in the support layer 114, sacrificial layer 112, support layer 110, sacrificial layer 108, and termination layer 106. In other words, the capacitor holes OP1 can penetrate the support layer 114, support layer 110, and termination layer 106, exposing the conductive plate 102. Then, the patterned photoresist layer 116 can be removed. Please refer to Figures 1D and 2D. An electrode material layer 118 is formed conformally on the support layer 114 and in the capacitor hole OP1. Referring to Figures 1E and 2E, a filling layer 120 can be formed on the electrode material layer 118 and in the capacitor via OP1. The material of the filling layer 120 is, for example, an oxide (e.g., silicon oxide). Next, a hard mask layer 122 can be formed on the filling layer 120. The hard mask layer 122 can be a single-layer structure or a multi-layer structure. The material of the hard mask layer 122 is, for example, carbon, silicon oxynitride, or a combination thereof. Then, a patterned photoresist layer 124 can be formed on the hard mask layer 122. Referring to Figures 1F and 2F, the patterned photoresist layer 124 can be used as a mask to pattern the hard mask layer 122, thus forming the patterned hard mask layer 122. Next, the patterned photoresist layer 124 can be removed. Then, the patterned hard mask layer 122 can be used as a mask to pattern the fill layer 120, the electrode material layer 118, and the support layer 114, and the patterned electrode material layer 118 forms the electrode layer 118a. This forms multiple openings OP2 that penetrate the support layer 114 and expose portions of the sacrificial layer 112, the electrode layer 118a, and the fill layer 120. Each opening OP2 connects to multiple capacitor holes OP1 on which the electrode layer 118a has been formed. The patterned hard mask layer 122 can be consumed during the above process or removed later. Referring to Figures 1G and 2G, a wet etching method can be used, for example, to remove the filler layer 120 and the sacrificial layer 112. Referring to Figures 1H and 2H, a dry etching method can be used, for example, to remove part of the support layer 110, thereby exposing part of the sacrificial layer 108. Next, referring to Figures 1I and 2I, a wet etching method can be used, for example, to remove the sacrificial layer 108, thereby forming an opening OP2 located between the plurality of electrode layers 118a and exposing the termination layer 106. As shown in Figure 2I, the electrode layer 118a can connect the support layer 114, the support layer 110, and the termination layer 106, and is supported by the support layer 114 and the support layer 110 without collapsing. Referring to Figures 1J and 2J, an electrode material layer 126 can be formed covering the electrode layer 118a, the support layer 114, the support layer 110, and the termination layer 106. Referring to Figures 1K and 2K, a dielectric material layer 128 and an electrode material layer 130 can be formed sequentially on the electrode material layer 126. The material of the dielectric material layer 128 is, for example, a high dielectric constant material. Referring to Figures 1L and 2L, electrode material layer 132 and electrode material layer 134 can be formed sequentially on electrode material layer 130. The material of electrode material layer 132 is, for example, doped silicon germanium, such as boron-doped silicon germanium (B-doped SiGe). The material of electrode material layer 134 is, for example, a conductive material such as tungsten. In this embodiment, the termination layer 106, sacrificial layer 108, support layer 110, sacrificial layer 112, support layer 114, electrode material layers 118, 126, 130, 134, and dielectric material layer 128 can be formed by chemical vapor deposition, but the present invention is not limited thereto. The materials of the electrode material layers 118, 126, and 130 are, for example, conductive materials such as titanium nitride (TiN), but the present invention is not limited thereto. Referring to Figures 1M and 2M, electrode material layers 134, 132, 130, 128, and 126 can be patterned to form electrode layers 134a, 132a, 130a, 128a, and 126a, and expose the termination layer 106 located in the peripheral region. The capacitor structure 10 of this embodiment will be described below with reference to Figures 1M and 2M. Furthermore, although the method for forming the capacitor structure 10 is described using the above method as an example, the present invention is not limited thereto. For clarity, the components related to the bottom electrode E1 are indicated in Figure 2J. Referring to Figures 1M, 2J, and 2M, the capacitor structure 10 includes a substrate 100, a support layer 114, and a capacitor C1. The support layer 114 is located on the substrate 100. The capacitor C1 is located on the substrate 100. The capacitor C1 includes a bottom electrode E1, a top electrode E2, and a dielectric layer 128a. The bottom electrode E1 includes a first portion E11 and a second portion E12. The first portion E11 of the bottom electrode E1 is located on a plurality of capacitor holes OP1 penetrating the support layer 114. The first portion E11 of the bottom electrode E1 connects these capacitor holes OP1. Furthermore, in this embodiment, the first portion E11 of the bottom electrode E1 may also cover the top surface S1 and the first sidewall S3 of the support layer 114. In this embodiment, the first portion E11 of the bottom electrode E1 includes an electrode layer 118a and an electrode layer 126a, and has a first thickness T1. The second portion E12 of the bottom electrode E1 is electrically connected to the first portion E11 of the bottom electrode E1 and covers the bottom surface 114b of the support layer 114. In this embodiment, the second portion E12 of the bottom electrode E1 includes an electrode layer 126a and may have a second thickness T2 (shown in FIG. 2J) that is less than the first thickness T1. Furthermore, in this embodiment, the second portion E12 of the bottom electrode E1 further covers the second sidewall S4 of the support layer 114, and the first sidewall S3 is opposite to the second sidewall S4. The second portion E12 of the bottom electrode E1 connects these capacitor holes OP1. A portion of the second portion E12 of the bottom electrode E1 may be located in the cavity 112H defined by the first portion E11 of the bottom electrode E1, the support layer 114, and the support layer 110. This improves the capacitance and structural strength of the capacitor structure 10. Furthermore, in this embodiment, as shown in Figures 1G and 2G, the electrode layer 118a may include a plurality of U-shaped cross-sectional structures 118U formed in these capacitor holes OP1 and a planar structure EC1 connecting these U-shaped cross-sectional structures 118U, but the present invention is not limited thereto. The planar structure EC1 of the electrode layer 118a may be located on the top surface S1 of the support layer 114. Through the above-described step of forming the opening OP2, the electrode layer 118a may have a plurality of top surfaces S2 (labeled in Figure 2M) at different heights, thereby facilitating the removal of the sacrificial layers 108 and 112 and the formation of the electrode material layer 126 and the dielectric material layer 128. As shown in Figures 1J, 2J, and 2M, the electrode layer 126a includes a plurality of U-shaped cross-sectional structures 126U formed in these capacitor holes OP1 and the opening OP2 and a planar structure EC2 connecting these U-shaped cross-sectional structures. Electrode layer 126a covers support layer 114 and electrode layer 118a, and electrode layer 126a is electrically connected to electrode layer 118a. This effectively improves the capacitance and structural strength of capacitor structure 10. Referring to FIG2M, top electrode E2 is located on bottom electrode E1, and dielectric layer 128a is located between bottom electrode E1 and top electrode E2. In this embodiment, the top electrode E2 located on dielectric layer 128a may sequentially include electrode layers 130a, 132a, and 134a. The capacitor structure 10 may further include a conductive plate 102 and a dielectric layer 104. The conductive plate 102 is located below the first portion E11 of the bottom electrode E1 and is electrically connected to the bottom electrode E1. In this embodiment, the conductive plate 102 may be directly connected to the electrode layer 118a. The capacitor structure 10 may further include a support layer 110 located between the support layer 114 and the substrate 100. A capacitor hole OP1 and an opening OP2 penetrate the support layer 110. A second portion E12 of the bottom electrode E1 may cover the top surface 110a and the bottom surface 110b of the support layer 110. In this embodiment, the second portion E12 of the bottom electrode E1 is located in the cavity 108H defined by the first portion E11, the support layer 110, and the termination layer 106. The capacitor structure 10 may further include a termination layer 106. A capacitor hole OP1 penetrates the termination layer 106, while an opening OP2 does not penetrate the termination layer 106. A second portion E12 of the bottom electrode E1 further covers the top surface 106a of the termination layer 106. The termination layer 106 is located between the conductive plate 102 and the second portion E12 of the bottom electrode E1. An electrode layer 118a may be connected to the termination layer 106. An electrode layer 126a may partially cover the termination layer 106. Furthermore, the details of each component in the capacitor structure 10 (e.g., materials and forming methods) have been described in detail in the above embodiments and will not be described again here. Based on the above embodiments, the bottom electrode E1 of the capacitor structure 10 includes a first portion E11 and a second portion E12, and the second portion E12 covers the bottom surface 114b of the support layer 114, and is even formed in the cavities 112H and 108H. Compared with conventional capacitor structures where the bottom electrode does not cover the bottom surface of the support layer and is not formed in the cavity, the capacitor structure 10 of this embodiment can provide additional coupling area, thus effectively increasing the capacitance of the capacitor structure 10 and providing a greater yield margin. In addition, the capacitor structure 10 of this embodiment can effectively improve the structural strength of the bottom electrode E1 by using the planar structure EC2 connecting these U-shaped cross-section structures 126U and / or the planar structure EC1 connecting these U-shaped cross-section structures 118U, thereby improving the quality of the capacitor structure 10. The following describes other variations of the invention, wherein the same or similar components are represented by the same symbols and the same descriptions are omitted, and only the differences may be stated. Figures 3A and 3B are top views showing the manufacturing process of a capacitor structure according to other embodiments of the present invention. Figures 4A and 4B are cross-sectional views along section line I-I' in Figures 3A and 3B. Please refer to Figures 3A and 4A. Similar steps to those in Figures 1E and 2E can be performed to obtain the structures in Figures 3A and 4A. The difference is that the pattern of the patterned photoresist layer 124 in Figures 3A and 4A is different from that in Figures 1E and 2E. Next, the steps described in Figures 1F to 1M and 2F to 2M can be performed to obtain the capacitor structure 20 shown in Figures 3B and 4B. The difference between capacitor structure 20 and capacitor structure 10 is as follows: In capacitor structure 20, the entire top surface S2 of electrode layer 118a can have the same height. In other words, capacitor structure 20 does not have the step of forming opening OP2. Figure 5 is a cross-sectional view of a capacitor structure according to some other embodiments of the present invention. Figure 6 is a top view of the electrode layer 118a and the support layer 114 in Figure 5. Referring to Figures 2M and 5, the differences in manufacturing method and structure between capacitor structure 30 and capacitor structure 10 are as follows. In the manufacturing method of capacitor structure 30, after forming electrode layer 118a, a portion of electrode layer 118a located on the top surface S1 of support layer 114 can be removed. Therefore, in capacitor structure 30, electrode layer 118a is not located on the top surface S1 of support layer 114, and electrode layer 118a does not include the planar structure EC1 shown in Figure 2M. As shown in Figure 6, in capacitor structure 30, electrode layer 118a can form multiple phase-separated circular structures 118O with a U-shaped cross-section. Figure 7 is a cross-sectional view of a capacitor structure according to some other embodiments of the present invention. Figure 8 is a top view of the electrode layer 118a and the support layer 114 in Figure 7. Referring to Figures 4B and 7, the differences in manufacturing method and structure between capacitor structure 40 and capacitor structure 20 are as follows. In the manufacturing method of capacitor structure 40, after forming electrode layer 118a, a portion of electrode layer 118a located on the top surface S1 of support layer 114 can be removed. Therefore, in capacitor structure 40, electrode layer 118a is not located on the top surface S1 of support layer 114, and electrode layer 118a does not include the planar structure EC1 shown in Figure 4B. As shown in Figure 8, in capacitor structure 40, electrode layer 118a can form multiple phase-separated circular structures 118O with a U-shaped cross-section. According to embodiments of the present invention, the structural strength and capacitance of capacitor structures are improved, and yield is increased. Furthermore, the present invention is applicable to the fabrication of miniaturized capacitor structures to increase the total number of dies on a wafer. Therefore, the present invention can reduce the production cost and energy consumption of manufacturing individual ICs, as well as the energy consumption of subsequent packaging, thereby reducing carbon emissions during semiconductor structure manufacturing. Thus, the present invention provides a green semiconductor technology. Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. 10: Capacitor Structure; 100: Substrate; 102: Conductive Plate; 104, 128a: Dielectric Layer; 106: Termination Layer; 106a, 110a, S1, S2: Top Surface; 108, 112: Sacrificial Layer; 110, 114: Support Layer; 110b, 114b: Bottom Surface; 108H, 112H: Cavity; 116, 124: Patterned Photoresist Layer; 118: Electrode Material Layer; 118a, 126a, 130a, 132a, 134a: Electrode Layer 118O: Circular structure; 118U, 126U: U-shaped cross-sectional structure; 120: Filler layer; 122: Rigid mask layer; 126, 130, 132, 134: Electrode material layers; 128: Dielectric material layer; C1: Capacitor; E1: Bottom electrode; E2: Top electrode; E11: First part; E12: Second part; EC1, EC2: Planar structure; OP1: Capacitor hole; OP2: Opening; S3: First sidewall; S4: Second sidewall; T1: First thickness; T2: Second thickness. Figures 1A to 1M are top views showing the manufacturing process of a capacitor structure according to some embodiments of the present invention. Figures 2A to 2M are cross-sectional views along section line I-I' in Figures 1A to 1M. Figures 3A to 3B are top views showing the manufacturing process of a capacitor structure according to other embodiments of the present invention. Figures 4A to 4B are cross-sectional views along section line I-I' in Figures 3A to 3B. Figure 5 is a cross-sectional view of a capacitor structure according to other embodiments of the present invention. Figure 6 is a top view of the electrode layer 118a and the support layer 114 in Figure 5. Figure 7 is a cross-sectional view of a capacitor structure according to other embodiments of the present invention. Figure 8 is a top view of the electrode layer 118a and the support layer 114 in Figure 7. 10: Capacitor Structure 100: Base 102: Conductive plate 104,128a: Dielectric layer 106: Termination Layer 110, 114: Support layer 118a, 126a, 130a, 132a, 134a: Electrode layers C1: Capacitor E1: Bottom electrode E2: Top electrode EC1: Planar Structure OP1: Capacitor port OP2: Opening S1, S2: Top surface

Claims

1. A capacitor structure, comprising: Base; A first support layer is located on the substrate; And a capacitor, located on the substrate, and comprising: a bottom electrode, comprising: a first portion located on a plurality of capacitor holes penetrating the first support layer; and a second portion electrically connected to the first portion and covering the bottom surface of the first support layer; a top electrode located on the bottom electrode; and a dielectric layer located between the bottom electrode and the top electrode. The capacitor structure as claimed in claim 1, wherein the first portion of the bottom electrode has a first thickness, and the second portion has a second thickness less than the first thickness. The capacitor structure as claimed in claim 1, wherein a portion of the second portion of the bottom electrode is located in a cavity defined by the first portion and the first support layer. The capacitor structure as claimed in claim 1, wherein the first portion of the bottom electrode covers the top surface and the first sidewall of the first support layer, and the second portion of the bottom electrode further covers the second sidewall of the first support layer, with the first sidewall and the second sidewall opposite to each other. The capacitor structure as claimed in claim 1, wherein the first portion of the bottom electrode covers the top surface, the first sidewall, and the second sidewall of the first support layer, and the first sidewall is opposite to the second sidewall. The capacitor structure as described in claim 1 further includes: A second support layer is located between the first support layer and the substrate, wherein a plurality of the capacitor holes penetrate the second support layer, and the second portion of the bottom electrode covers the top and bottom surfaces of the second support layer. The capacitor structure as claimed in claim 6, wherein the second portion of the bottom electrode is located in a cavity defined by the first portion, the first support layer and the second support layer. The capacitor structure as described in claim 1, wherein the first portion of the bottom electrode connects a plurality of the capacitor holes. The capacitor structure as described in claim 1, wherein the second portion of the bottom electrode connects a plurality of the capacitor holes. The capacitor structure as described in claim 6 further includes: A conductive plate is electrically connected to the bottom electrode and is located below the first portion of the bottom electrode; and a termination layer, wherein a plurality of said capacitor holes penetrate the termination layer, the second portion of the bottom electrode further covers the top surface of the termination layer, and the termination layer is located between the conductive plate and the second portion of the bottom electrode. The capacitor structure as described in claim 10, wherein a portion of the second portion of the bottom electrode is located in a cavity defined by the first portion, the second support layer and the termination layer. The capacitor structure as claimed in claim 2, wherein the first portion of the bottom electrode covers the first sidewall of the first support layer, and the second portion of the bottom electrode further covers the top surface and the second sidewall of the first support layer, with the first sidewall and the second sidewall facing each other. A method for manufacturing a capacitor structure, comprising: A first support layer is formed on the substrate; The bottom electrode of the capacitor is formed, and the bottom electrode includes: a first portion formed on a plurality of capacitor holes penetrating the first support layer; The second part is electrically connected to the first part and covers the bottom surface of the first support layer; a dielectric layer forming a capacitor is formed on the bottom electrode; and a top electrode forming a capacitor is formed on the dielectric layer. The method of manufacturing a capacitor structure as described in claim 13, wherein forming the bottom electrode of the capacitor includes: A first electrode layer is formed in the plurality of capacitor holes; A second electrode layer is formed on the first electrode layer and the first support layer, wherein the first portion of the bottom electrode has a first thickness, and the second portion has a second thickness less than the first thickness. The method of manufacturing the capacitor structure as described in claim 13 further includes: A second support layer is formed between the first support layer and the substrate, wherein a plurality of the capacitor holes penetrate the second support layer, and the second portion of the bottom electrode covers the top and bottom surfaces of the second support layer. The method of manufacturing a capacitor structure as claimed in claim 15, wherein a portion of the second portion of the bottom electrode is located in a cavity defined by the first portion, the first support layer, and the second support layer. The method of manufacturing a capacitor structure as described in claim 13, wherein the first portion of the bottom electrode connects a plurality of said capacitor holes. The method of manufacturing a capacitor structure as described in claim 13, wherein the second portion of the bottom electrode connects a plurality of said capacitor holes. The method of manufacturing the capacitor structure as described in claim 15 further includes: A conductive plate is formed prior to the formation of the first support layer, wherein the conductive plate is electrically connected to the bottom electrode and is located below the first portion of the bottom electrode; A termination layer is formed on the conductive plate, wherein a plurality of the capacitor holes penetrate the termination layer, and the second portion of the bottom electrode further covers the top surface of the termination layer. The method of manufacturing a capacitor structure as described in claim 19, wherein a portion of the second portion of the bottom electrode is located in a cavity defined by the first portion, the second support layer and the termination layer.