Integrated device and method of forming the same

Abstract

Some embodiments relate to an integrated device, including: an interconnect structure over a substrate; and a capacitor in the interconnect structure, the capacitor including: a bottom electrode having an upper portion, a first bottom surface, a second bottom surface, and a third bottom surface, an insulative layer, and a top electrode; where the first bottom surface, the second bottom surface, and the third bottom surface are coupled to the upper portion by a first sleeve portion, a second sleeve portion, and a third sleeve portion respectively; where the first sleeve portion is spaced from the second sleeve portion and the third sleeve portion by a first distance measured in a first direction; and where the second sleeve portion is spaced from the third sleeve portion by a second distance measured in a second direction perpendicular to the first direction, the second distance being greater than the first distance.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to integrated devices, and more particularly to integrated devices and methods of forming thereof. [Previous Technology]

[0002] Integrated circuits (ICs) are widely used in various modern electronic devices, such as cameras and mobile phones. Circuit elements, such as capacitors, resistors, diodes, and transistors, are formed in integrated circuits, creating circuits that are much smaller than those formed by discrete components. With the advancement of semiconductor manufacturing technology, even smaller features and components can be manufactured, bringing new challenges to the manufacturing process. [Summary of the Invention]

[0003] Embodiments of this disclosure provide an integrated device, including: an interconnect structure above a substrate; and a capacitor in the interconnect structure, the capacitor including: a bottom electrode having an upper portion, a first bottom surface, a second bottom surface, and a third bottom surface, a top electrode covering the bottom electrode, and an insulating layer separating the bottom electrode from the top electrode; wherein the first bottom surface, the second bottom surface, and the third bottom surface are respectively coupled to the upper portion via a first sleeve portion, a second sleeve portion, and a third sleeve portion; wherein the first sleeve portion and the second sleeve portion and the third sleeve portion are measured to be spaced apart by a first distance in a first direction; and wherein the second sleeve portion and the third sleeve portion are measured to be spaced apart by a second distance in a second direction perpendicular to the first direction, the second distance being greater than the first distance.

[0004] Embodiments of this disclosure provide an integrated device including: an interconnect structure covering a substrate; and a capacitor located within the interconnect structure, the capacitor including: a first upper portion; a first plurality of protrusions extending from the first upper portion, spaced apart from each other in a first direction, and extending a first distance in a second direction between a first outer sidewall and a second outer sidewall of the first plurality of protrusions; a second plurality of protrusions extending from the first upper portion, having a first outermost outer wall substantially aligned with the first outer sidewall of the first plurality of protrusions, and extending a second distance in the second direction, the second distance being less than the first distance; and a third plurality of protrusions extending from the first upper portion, having a first outermost outer wall substantially aligned with the second outer sidewall of the first plurality of protrusions, and extending a third distance in the second direction toward the second plurality of protrusions, the third distance being substantially equal to the second distance.

[0005] Embodiments of this disclosure provide a method of forming an integrated device, comprising: forming a first portion of an interconnect structure over a substrate, the first portion of the interconnect structure including an interlayer dielectric layer and a first line layer; patterning the interlayer dielectric layer to form a first plurality of openings extending from a first vertical plane to a second vertical plane, a second plurality of openings extending from the first vertical plane to a plurality of dielectric pillars remaining within the interlayer dielectric layer, and a third plurality of openings extending from the second vertical plane to the plurality of dielectric pillars, the first plurality of openings, the second plurality of openings and the third plurality of openings exposing the first line layer; and forming a bottom electrode, an insulating layer and a top electrode on the interlayer dielectric layer, such that the bottom electrode conforms to the sidewalls of the interlayer dielectric layer within the first plurality of openings, the second plurality of openings and the third plurality of openings.

Implementation Method

[0006] This disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar expressions may be used herein to describe the relationship between one device or feature shown in the figures and another device or feature. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein may be interpreted accordingly.

[0008] It should be understood that in this written description and in the following claims, the terms "first," "second," "third," etc., are merely general identifiers used for ease of explanation to distinguish different elements in a figure or series of figures. In themselves, these terms do not imply any temporal order or structural proximity of the elements, and are not intended to describe corresponding elements in different illustrated examples and / or examples not shown. For example, "first dielectric layer" illustrated in conjunction with the first figure may not necessarily correspond to "first dielectric layer" illustrated in conjunction with another figure, and may not necessarily correspond to "first dielectric layer" in examples not shown.

[0009] Integrated circuits (ICs) comprise multiple circuit elements, such as capacitors, resistors, transistors, and diodes. These circuit elements are formed on, within, or above a substrate within an interconnect structure. The location of the circuit elements in different parts of the integrated circuit depends on the vertical and lateral space used by the circuit elements to achieve the required functional parameters of the circuit.

[0010] In some embodiments, the capacitor is formed within the interconnect structure. The capacitor is formed within the interconnect structure (rather than directly on the substrate) to utilize the larger available vertical dimensions. In some embodiments, the capacitor includes multiple protrusions extending through multiple line layers, increasing the capacitor's area and capacitance value. Further embodiments also couple the bottom electrode of the capacitor to the lower line layer, reducing the area required to couple the bottom electrode to the upper portion of the capacitor within the interconnect structure.

[0011] With the advancement of semiconductor technology, the demand for smaller circuit elements is increasing. To meet this demand, capacitors with reduced spacing (e.g., the spacing between parallel protrusions is less than 300 nanometers) are desirable, where the protrusions extend from the upper portion. However, due to the lack of support for the interlayer dielectric layer during the etching process, the interlayer dielectric layer surrounding the protrusion openings is prone to collapse during the etching process. Therefore, there is a need for a capacitor with reduced spacing between protrusions and a more stable interlayer dielectric layer separating the protrusions.

[0012] This disclosure provides a capacitor having a plurality of protrusions separated by a plurality of dielectric pillars. The plurality of protrusions includes a first plurality of protrusions spaced apart from each other in a first direction. A second plurality of protrusions are staggered with the first plurality of protrusions in an alternating pattern in the first direction. A third plurality of protrusions are staggered with the first plurality of protrusions in an alternating pattern in the first direction and are separated from the second plurality of protrusions by the plurality of dielectric pillars in a second direction. A dielectric barrier spacees the first plurality of protrusions from the second and third plurality of protrusions and extends from the outermost wall of the first plurality of protrusions (e.g., a sidewall aligned with the first direction) to the dielectric pillars. The dielectric pillars are spaced apart from the outermost wall of the first plurality of protrusions (e.g., located at the midpoint of the dielectric barrier, or closer to the midpoint of the dielectric barrier than the outermost wall) and configured to support the central portion of the dielectric barrier to prevent the dielectric barrier from collapsing during an initial etching process. By sacrificing a portion of the capacitor's surface area, it is possible to create capacitors with reduced spacing between protrusions (e.g., less than 300 nanometers) without causing the dielectric barrier to collapse.

[0013] Figures 1A, 1B, and 1C illustrate a top view 100a and cross-sectional views 100b and 100c of some embodiments of a capacitor having dielectric pillars with separating capacitor protrusions. Cross-sectional view 100b of Figure 1B is taken along line A-A' of Figure 1A. Cross-sectional view 100c of Figure 1C is taken along line B-B' of Figure 1A.

[0014] The capacitor 102 is located in the interlayer dielectric layer 104. The capacitor 102 includes a first plurality of protrusions 106, a second plurality of protrusions 108, and a third plurality of protrusions 110. The first plurality of protrusions 106 are spaced apart from each other in a first direction 112. The second plurality of protrusions 108 are staggered with the first plurality of protrusions 106 in the first direction 112. The third plurality of protrusions 110 are staggered with the first plurality of protrusions 106 in the first direction 112 and spaced apart from the second plurality of protrusions in a second direction 114 perpendicular to the first direction 112.

[0015] A plurality of dielectric pillars 116 separate the second plurality of protrusions 108 from the third plurality of protrusions 110. The plurality of dielectric pillars 116 include portions of an interlayer dielectric layer 104 extending directly between the second plurality of protrusions 108 and the third plurality of protrusions 110. A plurality of dielectric barriers 118 include portions of an interlayer dielectric layer 104 extending between the first plurality of protrusions 106 and the second plurality of protrusions 108 and the third plurality of protrusions 110, located outside the plurality of dielectric pillars 116. The plurality of dielectric barriers 118 have a first thickness 120 measured in a first direction 112. The plurality of dielectric pillars 116 have a second thickness 122 measured in a second direction 114. The second thickness 122 is greater than or equal to the first thickness 120.

[0016] The plurality of dielectric pillars 116 are thicker than the plurality of dielectric barriers 118. Embodiments without the plurality of dielectric pillars experience collapse near the center of the plurality of dielectric barriers 118, partly due to the lack of nearby support walls and a reduced ability of the photolithography process to cover dielectric regions with small pitch and high critical dimensions. Therefore, the plurality of dielectric pillars 116 are configured to support the plurality of dielectric barriers 118 by increasing the thickness of the region where the plurality of dielectric barriers 118 are most prone to failure. Increasing the thickness at the central segment of the plurality of dielectric barriers 118 substantially eliminates the collapse of the plurality of dielectric barriers 118 due to etching of the interlayer dielectric layer 104.

[0017] As shown in the cross-sectional view 100b of FIG1B, a first plurality of protrusions 106 extend from the upper portion 124 of the capacitor 102 to the first line layer 126 of the interconnect structure 128. A second plurality of protrusions 108 extend from the upper portion 124 to the first line layer 126. In some embodiments, the first thickness 120 is approximately between 0.12 and 0.15 micrometers, approximately between 0.1 and 0.13 micrometers, approximately between 0.1 and 0.15 micrometers, or in another similar range. In some embodiments, the interlayer dielectric layer 104 includes a plurality of etch stop layers 130 extending between the plurality of dielectric layers 132.

[0018] The first plurality of protrusions 106 include a first bottom surface 106a coupled to the upper portion 124 via a first sleeve portion 106b. The second plurality of protrusions 108 include a second bottom surface 108a coupled to the upper portion 124 via a second sleeve portion 108b. The third plurality of protrusions 110 include a third bottom surface (not shown) coupled to the upper portion 124 via a third sleeve portion (not shown). In some embodiments, the sidewalls of the first sleeve portion 106b, the second sleeve portion 108b, and the third sleeve portion 110b are approximately aligned with a third third direction 115 perpendicular to the first direction 112 and the second direction 114 (e.g., within a 10-degree alignment range).

[0019] In some embodiments, the first thickness 120 is measured between the first sleeve portion 106b and the second sleeve portion 108b, at the junction of the sleeve portion and the upper portion 124. In other embodiments, the first thickness 120 is measured between the first sleeve portion 106b and the second sleeve portion 108b, at the junction of the sleeve portion and the first bottom surface 106a and the second bottom surface 108a. In other embodiments, the first thickness 120 is measured at a height between the first sleeve portion 106b and the second sleeve portion 108b, between the first bottom surface and the junction of the first sleeve portion 106b and the upper portion 124.

[0020] As shown in the cross-sectional view 100c of FIG1C, a plurality of dielectric pillars 116 are confined between dielectric barriers 118. Furthermore, the plurality of dielectric barriers 118 extend between the plurality of dielectric pillars 116 and the first plurality of protrusions 106. The upper portion 124 of the capacitor 102 has a bottom surface 134. A straight line segment 136 can be drawn on the bottom surface of the upper portion 124, extending from a first protrusion 138 of the first plurality of protrusions 106 to a second protrusion 140 of the first plurality of protrusions 106.

[0021] Figures 2A, 2B, and 2C illustrate a top view 200a and cross-sectional views 200b and 200c of a capacitor having a dielectric pillar with a separating protrusion and further including a barrier layer in some embodiments. Cross-sectional view 200b of Figure 2B is taken along line A-A' of Figure 2A. Cross-sectional view 200c of Figure 2C is taken along line B-B' of Figure 2A. Figures 2A, 2B, and 2C will be described simultaneously.

[0022] The capacitor 102 includes a bottom electrode 202, a top electrode 204, and an insulating layer 206 separating the bottom electrode 202 and the top electrode 204. In some embodiments, a metal barrier layer 208 separates the bottom electrode 202 from the interlayer dielectric layer 104. The top electrode 204 conforms to the upper surface and inner sidewall of the insulating layer 206. The insulating layer 206 conforms to the upper surface and inner sidewall of the bottom electrode 202. In some embodiments, the bottom electrode 202 conforms to the upper surface and inner sidewall of the metal barrier layer 208. In some embodiments, the metal barrier layer 208 is configured to space the bottom electrode 202 from the interlayer dielectric layer 104 to prevent material of the bottom electrode 202 from diffusing into the interlayer dielectric layer. In some embodiments, the second thickness 122 is about 0.17 to 0.2 micrometers, about 0.15 to 0.18 micrometers, about 0.15 to 0.2 micrometers, or in another similar range.

[0023] The first sleeve portion 106b of the first plurality of protrusions 106 extends a first distance 210 between the first outermost wall 106c and the second outermost wall 106d. The first distance 210 is substantially equal to the distance between the first outermost wall 108c of the second sleeve portion 108b and the first outermost wall 110c of the third sleeve portion 110b. That is, in some embodiments, the first outermost wall 108c of the second plurality of protrusions 108 is substantially aligned with the first outermost wall 106c of the first plurality of protrusions 106, and the first outermost wall 110c of the third plurality of protrusions 110 is substantially aligned with the second outermost wall 106d of the first plurality of protrusions 106. In some embodiments, the first distance 210 is approximately between 1.4 micrometers and 1.55 micrometers, approximately between 1.45 and 1.6 micrometers, approximately between 1.4 and 1.6 micrometers, or in another similar range.

[0024] The second outermost wall 108d of the second plurality of protrusions 108 is opposite to the first outermost wall 108c and faces the third plurality of protrusions 110. The second outermost wall 108d is a second distance 220 from the first outermost wall 108c. The second outermost wall 110d of the third plurality of protrusions 110 is opposite to the first outermost wall 110c and faces the second plurality of protrusions 108. The second outermost wall 110d is a third distance 222 from the first outermost wall 110c, wherein the third distance 222 is substantially equal to (e.g., within 5%) the second distance 220.

[0025] From a top viewpoint, the first protrusion 212, the second protrusion 214, the third protrusion 216, and the fourth protrusion 218 have substantially rectangular cross-sections. In some embodiments, the length of the first protrusion 212, the second protrusion 214, the third protrusion 216, and the fourth protrusion 218 extending in the second direction 114 is greater than the width extending in the first direction 112. The second plurality of protrusions 108 have sidewalls substantially aligned with the sidewalls of the third plurality of protrusions 110 extending in the second direction 114. The substantially aligned sidewalls of the second plurality of protrusions 108 and the third plurality of protrusions 110 extend a second distance 220 in the second direction, which is less than the first distance 210.

[0026] The first plurality of protrusions 106 have a first protrusion 212, the second plurality of protrusions 108 have a second protrusion 214, and the third plurality of protrusions 110 have a third protrusion 216. The first plurality of protrusions 106 have a fourth protrusion 218, which is spaced apart from the first protrusion 212 by the second protrusion 214 and the third protrusion 216. The second protrusion 214, the third protrusion 216, and the dielectric pillar 116a separating the second protrusion 214 and the third protrusion 216 are confined therebetween in a first direction 112 by the outer sidewalls of the first protrusion 212 and the fourth protrusion 218. In some embodiments, from a top view, the continuous portion of the interlayer dielectric layer 104 extending directly between the protrusions of the first plurality of protrusions 106, the second plurality of protrusions 108, and the third plurality of protrusions 110 forms one or more "H" shapes 224.

[0027] Figure 3 illustrates a top view 300 of a capacitor having multiple protrusions in some embodiments, which are aligned with multiple parallel lines and separated by dielectric pillars.

[0028] In some embodiments, the fourth plurality of protrusions 302 are spaced apart from the third plurality of protrusions 110 by a second plurality of dielectric pillars 304. The second plurality of dielectric pillars 304 are configured to stabilize the plurality of dielectric barriers 118 together with the plurality of dielectric pillars 116. In embodiments where the first row of dielectric pillars (e.g., the plurality of dielectric pillars 116) cannot eliminate or mitigate the collapse of the plurality of dielectric barriers 118 (e.g., because the length of the dielectric barrier over the first distance 210 is between approximately 1.6 and 2.1 micrometers, between approximately 2 and 2.4 micrometers, in another similar range, or for other reasons), a second row of dielectric pillars (e.g., a second plurality of dielectric pillars 304) is introduced.

[0029] In some embodiments, a plurality of dielectric pillars 116 are arranged on a first straight line 306 extending along a first direction 112, and a second plurality of dielectric pillars 304 are arranged on a second straight line 308 extending along the first direction 112. In some embodiments, the first straight line 306 is equidistant from the second straight line 308 and from a first plane 310 extending along the first outer sidewall of the first plurality of protrusions 106 in the first direction 112. In some embodiments, the second straight line 308 is equidistant from the first straight line 306 and from a second plane 312 extending along the second outer sidewall of the first plurality of protrusions in the first direction 112. It is understood that some embodiments have an additional arrangement of dielectric pillars between the first plane 310 and the second plane 312.

[0030] Figure 4 illustrates a top view 400 of a capacitor having a first row of dielectric pillars in some embodiments, these dielectric pillars being closer to the first plane than the second plane. In some embodiments, the plurality of dielectric pillars 116 on a first straight line 306 are not equidistant from the first plane 310 and the second plane 312. That is, the first straight line 306 is closer to one of the first plane 310 or the second plane 312 than to the other of the first plane 310 or the second plane 312. In embodiments where the plurality of dielectric barriers 118 are prone to failure in specific areas due to positioning or variation in the wafer fabrication process (e.g., variation in lithography or etching processes), changing the position of the plurality of dielectric pillars 116 to be closer to specific areas of the plurality of dielectric barriers 118 can further mitigate fabrication errors during capacitor manufacturing.

[0031] Figure 5 illustrates a cross-sectional view 500 of a capacitor having dielectric pillars on a substrate in some embodiments.

[0032] In some embodiments, capacitor 102 covers substrate 502. A plurality of semiconductor devices 504 are located on or above the substrate. In some embodiments, the plurality of semiconductor devices 504 are or include transistor devices (e.g., planar FET, fin field-effect transistor (FinFET), gate-all-around (GAA) devices, etc.). The plurality of semiconductor devices 504 are coupled to interconnect structure 128 via a plurality of contacts 506. Interconnect structure 128 has a plurality of line layers 508 (including a first line layer 126) and a plurality of via layers 510. In some embodiments, capacitor 102 extends through one or more line layers 508 and the plurality of via layers 510. Top electrode 204 is coupled to the plurality of line layers 508 via a first via 512. In some embodiments, bottom electrode 202 is coupled to the plurality of line layers by direct contact with the first line layer 126 or by contact of the first line layer 126 with a metal barrier layer 208. In other embodiments, the bottom electrode 202 is coupled to the interconnect structure 128 via a second via (not shown).

[0033] Figures 6 to 7, 8A, 8B, and 9 to 15 illustrate a series of cross-sectional views 600-700, 800a, 900-1500, and a top view 800b of a method for forming a capacitor with separating capacitor protrusions in some embodiments. Although Figures 6 to 7, 8A, 8B, and 9 to 14 are described as a series of actions, it should be understood that these actions are not limiting, as the order of actions may change in other embodiments, and the disclosed method is applicable to other structures. In other embodiments, some illustrated and / or described actions may be omitted in whole or in part. Cross-sectional view 800a of Figure 8A is taken along line A-A' of Figure 8B.

[0034] As shown in the cross-sectional view 600 of FIG6, a plurality of semiconductor devices 504 are formed on the substrate 502. In some embodiments, the plurality of semiconductor devices 504 are or include transistor devices (e.g., planar field-effect transistors, fin field-effect transistors (FinFETs), gate-all-around (GAA) devices, etc.). The plurality of semiconductor devices 504 include a pair of source / drain regions, a semiconductor channel, a gate dielectric layer, and a gate terminal. In some embodiments, the source / drain regions are formed using an implantation process. In some embodiments, the gate dielectric layer and the gate terminal are formed using multiple etching processes, multiple deposition processes, or similar methods.

[0035] As shown in the cross-sectional view 700 of FIG7, a first portion of the interconnect structure 128 is formed within the interlayer dielectric layer 104. The first portion of the interconnect structure 128 includes a plurality of line layers 508, including a first line layer 126 and a first upper line layer 702, wherein the first upper line layer 702 is the uppermost line layer in the first portion of the interconnect structure 128. The first portion of the interconnect structure 128 also includes a plurality of via layers 510 extending between the plurality of line layers 508. A plurality of contacts 506 extend between a plurality of semiconductor devices and the interconnect structure 128. In some embodiments, the interconnect structure 128 includes a conductive material, such as copper, aluminum, tungsten, a conductive metal alloy, or similar materials.

[0036] The interlayer dielectric layer 104 includes a plurality of etch stop layers 130 and a plurality of dielectric layers 132. In some embodiments, the plurality of dielectric layers 132 are or include an insulating material, such as silicon dioxide (SiO2) or a similar material. In some embodiments, the plurality of etch stop layers 130 are or include an insulating material different from the material of the plurality of dielectric layers 132, such as silicon nitride (Si3N4) or a similar material. In some embodiments, the interlayer dielectric layer 104 is formed using one or more of physical vapor deposition (PVD), atomic layer deposition (ALD), and chemical vapor deposition (CVD). In some embodiments, the interconnect structure 128 is formed using one or more of PVD, ALD, CVD, damascene process, and dual damascene process.

[0037] As shown in the cross-sectional view 800a of FIG8A, a first masking layer 804 is formed on the interlayer dielectric layer 104. In some embodiments, the first masking layer 804 is or includes a photoresist. In some embodiments, the first masking layer 804 is formed on the interlayer dielectric layer 104 using one or more methods of physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), and spin-on processes. Subsequently, the first masking layer 804 is patterned. In some embodiments, the first masking layer 804 is patterned using photolithography to expose portions of the interlayer dielectric layer 104 corresponding to the first, second, and third plurality of protrusions (see 106, 108, 110 in FIG1A).

[0038] After forming and patterning the first mask layer 804, a first etching process 802 is performed on the interlayer dielectric layer 104. The first etching process 802 causes a plurality of openings 806 to extend into the interlayer dielectric layer 104, exposing the first line layer 126. In some embodiments, the first etching process 802 is an anisotropic dry etching process. After the first etching process 802, the first mask layer 804 is removed from the interlayer dielectric layer. In some embodiments, the plurality of openings 806 extend below the first upper line layer 702.

[0039] As shown in the top view 800b of FIG8B, after the formation of the plurality of openings 806, a plurality of dielectric pillars 116 and a plurality of dielectric barriers 118 remain on the first line layer 126. The second thickness 122 of the plurality of dielectric pillars 116 is greater than or equal to the first thickness 120 of the plurality of dielectric barriers 118, and the mechanical coupling of the plurality of dielectric pillars 116 with the central portion of the plurality of dielectric barriers 118 stabilizes the plurality of dielectric barriers 118. This stability eliminates or substantially eliminates the collapse of the plurality of dielectric barriers 118 during the first etching process (see 802 of FIG8A).

[0040] The plurality of openings 806 includes a first plurality of openings 806a extending from a first vertical plane 808 perpendicular to the second direction 114 to a second vertical plane 810 perpendicular to the second direction 114. The plurality of openings 806 also includes a second plurality of openings 806b extending from the first vertical plane 808 a second distance 220 to one of the dielectric pillars 116. The plurality of openings 806 also includes a third plurality of openings 806c extending from the second vertical plane 810 a third distance 222 to one of the dielectric pillars 116. After the plurality of openings 806 are formed, a plurality of dielectric barriers 118 remain on the substrate (see 502 in FIG. 5). The plurality of dielectric barriers 118 extend from the first vertical plane 808 to the second vertical plane 810 and are substantially parallel to each other and parallel to the second direction 114.

[0041] As shown in the cross-sectional view 900 of FIG9, a conformal barrier layer 902 is deposited on the interlayer dielectric layer 104 and enters a plurality of openings 806. In some embodiments, the conformal barrier layer 902 is or includes a conductive metal layer that diffuses into silicon at a lower rate than copper, such as nickel (Ni), aluminum (Al), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), tungsten (W), or the like. In some embodiments, the conformal barrier layer 902 is deposited using one or more of physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), or similar methods.

[0042] As shown in the cross-sectional view 1000 of FIG10, a conformal bottom electrode layer 1002, a conformal insulating layer 1004, and a conformal top electrode layer 1006 are formed on the interlayer dielectric layer, filling a plurality of openings 806 (shown in dashed lines). In some embodiments, the conformal bottom electrode layer 1002 and the conformal top electrode layer 1006 are or include conductive materials, such as copper (Cu), gold (Au), nickel (Ni), aluminum (Al), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), tungsten (W), or the like. In some embodiments, the conformal insulating layer 1004 is or includes a high-k dielectric material, such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2), or the like. In some embodiments, the conformal bottom electrode layer 1002, the conformal insulating layer 1004, and the conformal top electrode layer 1006 are formed using multiple deposition processes (e.g., physical vapor deposition, atomic layer deposition, chemical vapor deposition) or similar methods. In a further embodiment, a seed layer is formed on the underlying material before the conformal bottom electrode layer 1002 and the conformal top electrode layer 1006 are formed to improve the deposition of the conductive material. In some embodiments, an additional etch stop layer (not shown) is formed on the conformal top electrode layer 1006 to help pattern the conformal bottom electrode layer 1002 and the conformal barrier layer 902 (see FIG. 13).

[0043] As shown in the cross-sectional view 1100 of FIG11, the second masking layer 1104 is formed on the conformal top electrode layer (see 1006 in FIG10). In some embodiments, the second masking layer 1104 is or includes photoresist and is patterned using photolithography. The pattern of the second masking layer 1104 corresponds to the position of the top electrode 204.

[0044] After forming the second masking layer 1104, a second etching process 1102 is performed to remove portions of the conformal top electrode layer (see 1006 in FIG. 10) and the conformal insulating layer (see 1004 in FIG. 10), leaving the top electrode 204 and the insulating layer 206 on the conformal bottom electrode layer 1002 and the conformal barrier layer 902. In embodiments where an additional etch stop layer (not shown) is formed on the conformal top electrode layer (see 1006 in FIG. 10), the additional etch stop layer is also etched by the second etching process 1102. The second masking layer 1104 is then removed.

[0045] As shown in the cross-sectional view 1200 of FIG12, a conformal dielectric layer 1202 is formed on the top electrode 204 and the conformal bottom electrode layer 1002. In some embodiments, the conformal dielectric layer 1202 is or includes an insulating material, such as silicon dioxide (SiO2), silicon nitride (Si3N4), or the like. In some embodiments, the conformal dielectric layer 1202 is formed using one or more deposition processes, such as physical vapor deposition, atomic layer deposition, chemical vapor deposition, or similar methods. In embodiments with an additional etch stop layer, the conformal dielectric layer 1202 conforms to the upper surface and sidewalls of the additional etch stop layer.

[0046] As shown in the cross-sectional view 1300 of FIG13, a third etching process 1302 (e.g., a dry etching process) is performed. The third etching process 1302 causes a portion of the conformal dielectric layer (see 1202 in FIG12) to be removed from the upper surface of the top electrode 204, leaving the remaining dielectric 1304 directly above the upper surface of the conformal bottom electrode layer 1002. The remaining dielectric 1304 protects the top electrode 204 and the outer sidewalls of the insulating layer 206 from conductive residues generated by subsequent etching processes.

[0047] As shown in the cross-sectional view 1400 of FIG14, a third masking layer 1404 is formed on the top electrode 204 and the remaining dielectric 1304. In some embodiments, the third masking layer 1404 is or includes photoresist. In some embodiments, the third masking layer 1404 is formed on the top electrode 204 using one or more of physical vapor deposition, atomic layer deposition, chemical vapor deposition, spin coating, or similar methods. Subsequently, the third masking layer 1404 is patterned. In some embodiments, the third masking layer 1404 is patterned using photolithography to cover a portion of the conformal bottom electrode layer corresponding to the bottom electrode 202 (see 1002 in FIG10) and expose a portion of the conformal bottom electrode layer beyond the bottom electrode 202 (see 1002 in FIG10).

[0048] After forming and patterning the third masking layer 1404, a fourth etching process 1402 is performed on the interlayer dielectric layer 104. The fourth etching process 1402 causes the conformal bottom electrode layer (see 1002 in FIG. 10) and the conformal barrier layer (see 902 in FIG. 9) to be patterned into a bottom electrode 202 and a metal barrier layer 208, respectively. In some embodiments, the fourth etching process 1402 is an anisotropic dry etching process. After the fourth etching process 1402, the third masking layer 1404 is removed.

[0049] As shown in the cross-sectional view 1500 of FIG15, a second portion of the interconnect structure 128 is formed on the capacitor 102. In some embodiments, the second portion of the interconnect structure 128 is electrically coupled to the first portion of the interconnect structure via a first upper line layer 702. In some embodiments, the second portion of the interconnect structure is made of or comprises the same material as the first portion of the interconnect structure 128 and is formed using the same method as the first portion of the interconnect structure 128.

[0050] Figure 16 illustrates a flowchart 1600 of some embodiments of a method for forming a capacitor with a dielectric pillar having a discrete capacitor protrusion. Although this method and other methods illustrated and / or described herein are illustrated as a series of actions or events, it should be understood that this disclosure is not limited to the illustrated sequence or actions. Therefore, in some embodiments, actions may be performed in a different sequence than illustrated, and / or may be performed simultaneously. Furthermore, in some embodiments, the illustrated actions or events may be subdivided into multiple actions or events that may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events may be omitted, while other unillustrated actions or events may be included.

[0051] In step 1602, a first portion of the interconnect structure is formed over the substrate, the first portion of the interconnect structure including an interlayer dielectric and a first wire layer. A drawing example illustrating this step can be found in Figure 6.

[0052] In step 1604, the interlayer dielectric is patterned to form a first plurality of openings extending from a first vertical plane to a second vertical plane, a second plurality of openings extending from the first vertical plane to the remaining plurality of dielectric pillars in the interlayer dielectric, and a third plurality of openings extending from the second vertical plane to the plurality of dielectric pillars, the first, second, and third plurality of openings exposing the first line layer. A drawing example illustrating this step can be found in Figures 8A to 8B.

[0053] In step 1606, the bottom electrode, insulating layer, and top electrode are formed above the interlayer dielectric, such that the bottom electrode conforms to the sidewalls of the interlayer dielectric in the first plurality of openings, the second plurality of openings, and the third plurality of openings. A drawing example illustrating this step can be found in Figures 9 to 14.

[0054] In step 1608, a second portion of the interconnect structure is formed above the top electrode. A drawing example illustrating this step can be found in Figure 14.

[0055] Some embodiments relate to an integrated device including: an interconnect structure above a substrate; and a capacitor in the interconnect structure, the capacitor including: a bottom electrode having an upper portion, a first bottom surface, a second bottom surface, and a third bottom surface, a top electrode covering the bottom electrode, and an insulating layer separating the bottom electrode from the top electrode; wherein the first bottom surface, the second bottom surface, and the third bottom surface are coupled to the upper portion by a first sleeve portion, a second sleeve portion, and a third sleeve portion, respectively; wherein the first sleeve portion is spaced apart from the second sleeve portion and the third sleeve portion by a first distance measured in a first direction; and wherein the second sleeve portion and the third sleeve portion are spaced apart by a second distance measured in a second direction perpendicular to the first direction, the second distance being greater than the first distance.

[0056] In some embodiments, the first sleeve portion has a first width measured in the second direction, and a third distance exists between the outermost wall of the second sleeve portion and the outermost wall of the third sleeve portion, the third distance being substantially equal to the first width. In some embodiments, the capacitor further includes a fourth bottom surface and a fourth sleeve portion, the fourth sleeve portion coupling the fourth bottom surface to the upper portion, wherein the fourth sleeve portion is spaced apart from the first sleeve portion in the first direction by the second sleeve portion and the third sleeve portion. In some embodiments, the second sleeve portion and the third sleeve portion are confined between the outermost wall of the first sleeve portion and the outermost wall of the fourth sleeve portion. In some embodiments, the first sleeve portion has a substantially rectangular cross-section when viewed from a top view, the length of the substantially rectangular cross-section extending in the second direction being greater than its width extending in the first direction; wherein the first outer wall of the first sleeve portion is substantially parallel to the second direction; wherein the second sleeve portion and the third sleeve portion have a second substantially rectangular cross-section when viewed from a top view, the length of the second substantially rectangular cross-section extending in the second direction being greater than its width extending in the first direction; and wherein the second outer wall of the second sleeve portion and the third outer wall of the third sleeve portion are substantially aligned, and the second outer wall and the third outer wall extend primarily in the second direction. In some embodiments, the second outer wall of the second sleeve portion and the third outer wall of the third sleeve portion face the first outer wall of the first sleeve portion.

[0057] Other embodiments relate to an integrated device including: an interconnect structure covering a substrate; and a capacitor located within the interconnect structure, the capacitor including: a first upper portion; a first plurality of protrusions extending from the first upper portion, spaced apart from each other in a first direction, and extending a first distance in a second direction between a first outer sidewall and a second outer sidewall of the first plurality of protrusions; a second plurality of protrusions extending from the first upper portion, having a first outermost outer wall substantially aligned with the first outer sidewall of the first plurality of protrusions, and extending a second distance in a second direction, the second distance being less than the first distance; and a third plurality of protrusions extending from the first upper portion, having a first outermost outer wall substantially aligned with the second outer sidewall of the first plurality of protrusions, and extending a third distance in a second direction toward the second plurality of protrusions, the third distance being substantially equal to the second distance.

[0058] In some embodiments, the second plurality of protrusions further includes a second outermost wall opposite to the first outermost wall of the second plurality of protrusions, the second outermost wall being a second distance from the first outermost wall of the second plurality of protrusions and facing the third plurality of protrusions; and wherein the third plurality of protrusions further includes a second outermost wall opposite to the first outermost wall of the third plurality of protrusions, the second outermost wall of the third plurality of protrusions being a third distance from the first outermost wall of the third plurality of protrusions and facing the second plurality of protrusions. In some embodiments, the first plurality of protrusions, the second plurality of protrusions, and the third plurality of protrusions extend to a first metal layer and are separated by an interlayer dielectric layer. In some embodiments, the integrated device further includes a plurality of dielectric pillars located within the interlayer dielectric layer, the plurality of dielectric pillars space the second plurality of protrusions from the third plurality of protrusions and having a thickness measured in a second direction; and a plurality of dielectric barriers located within the interlayer dielectric layer, space the protrusions of the first plurality of protrusions from the protrusions of the second plurality of protrusions in the first direction, wherein the thickness of the plurality of dielectric barriers measured in the first direction is less than the thickness of the plurality of dielectric pillars measured in the second direction. In some embodiments, the first plurality of protrusions includes a first protrusion and a second protrusion, and wherein a straight segment extends from the first protrusion to the second protrusion without contacting the second plurality of protrusions or the third plurality of protrusions. In some embodiments, the integrated device further includes an interlayer dielectric layer extending between the outer walls of the first plurality of protrusions, the second plurality of protrusions, and the third plurality of protrusions, and wherein the interlayer dielectric layer extends directly over a continuous portion between the protrusions of the first plurality of protrusions, the second plurality of protrusions, and the third plurality of protrusions to form one or more H-shapes from a top view.

[0059] Further embodiments relate to a method of forming an integrated device, comprising: forming a first portion of an interconnect structure over a substrate, the first portion of the interconnect structure including an interlayer dielectric layer and a first line layer; patterning the interlayer dielectric layer to form a first plurality of openings extending from a first vertical plane to a second vertical plane, a second plurality of openings extending from the first vertical plane to a plurality of dielectric pillars remaining in the interlayer dielectric layer, and a third plurality of openings extending from the second vertical plane to the plurality of dielectric pillars, the first plurality of openings, the second plurality of openings and the third plurality of openings exposing the first line layer; and forming a bottom electrode, an insulating layer and a top electrode on the interlayer dielectric layer, such that the bottom electrode conforms to the sidewalls of the interlayer dielectric layer within the first plurality of openings, the second plurality of openings and the third plurality of openings.

[0060] In some embodiments, the first plurality of openings are spaced apart from the second plurality of openings and the third plurality of openings by a first thickness, the first thickness being measured in a first direction, and the plurality of dielectric pillars have a second thickness measured in a second direction perpendicular to the first direction, wherein the second thickness is greater than the first thickness. In some embodiments, the bottom electrode includes a plurality of bottom surfaces in the openings of the first plurality of openings, the second plurality of openings, and the third plurality of openings, wherein the plurality of bottom surfaces are electrically coupled to the first line layer. In some embodiments, forming the bottom electrode, the insulating layer, and the top electrode further includes: forming a conformal bottom electrode layer on the interlayer dielectric layer, the conformal bottom electrode layer conforming to the inner sidewall of the interlayer dielectric layer; depositing a conformal insulating layer on the conformal bottom electrode layer, the conformal insulating layer conforming to the inner sidewall of the conformal bottom electrode layer; and forming a conformal top electrode layer on the conformal insulating layer, filling the first plurality of openings, the second plurality of openings, and the third plurality of openings and conforming to the inner sidewall of the conformal insulating layer. In some embodiments, the first vertical plane is parallel to the second vertical plane. In some embodiments, the first plurality of openings, the second plurality of openings, and the third plurality of openings are patterned simultaneously. In some embodiments, after the interlayer dielectric layer is patterned, dielectric barrier portions of the interlayer dielectric layer extend from the first vertical plane and the second vertical plane to the plurality of dielectric pillars. In some embodiments, the dielectric barrier portions of the interlayer dielectric layer are substantially parallel to each other.

[0061] It should be understood that the terms "first," "second," "third," etc., used in this written description and in the following claims are merely general identifiers used for ease of explanation to distinguish different elements in a figure or series of figures. In themselves, these terms do not imply any temporal order or structural proximity of the elements, and are not intended to describe corresponding elements in different illustrated embodiments and / or embodiments not shown. For example, "first dielectric layer" illustrated in conjunction with the first figure may not necessarily correspond to "first dielectric layer" illustrated in conjunction with another figure, and may not necessarily correspond to "first dielectric layer" in embodiments not shown.

[0062] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0063] The following detailed description, taken in conjunction with the accompanying drawings, will provide the best understanding of the nature of this disclosure. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figures 1A, 1B, and 1C illustrate top and cross-sectional views of some embodiments of a capacitor having dielectric pillars separating capacitor protrusions. Figures 2A, 2B, and 2C illustrate top and cross-sectional views of some embodiments of a capacitor having dielectric pillars separating protrusions, the capacitor further including a barrier layer. Figure 3 illustrates a top view of some embodiments of a capacitor having multiple protrusions aligned with multiple parallel lines and separated by dielectric pillars. Figure 4 illustrates a top view of some embodiments of a capacitor having dielectric pillars with a first line, these dielectric pillars being closer to the first plane than the second plane. Figure 5 illustrates a cross-sectional view of some embodiments of a capacitor having dielectric pillars on a substrate. Figures 6-7, 8A, 8B, and 9-15 illustrate a series of cross-sectional and top views of some embodiments of a method for forming a capacitor having dielectric pillars separating capacitor protrusions. Figure 16 illustrates flowcharts of some embodiments of a method for forming a capacitor with dielectric pillars having separating capacitor protrusions.

Claims

1. An integrated device, comprising: Interconnection structure above the substrate; And a capacitor in an interconnect structure, the capacitor comprising: a bottom electrode having an upper portion, a first bottom surface, a second bottom surface and a third bottom surface, a top electrode covering the bottom electrode, and an insulating layer separating the bottom electrode from the top electrode; The first bottom surface, the second bottom surface, and the third bottom surface are respectively coupled to the upper portion via a first sleeve portion, a second sleeve portion, and a third sleeve portion; wherein the first sleeve portion is spaced apart from the second sleeve portion and the third sleeve portion by a first distance in a first direction; and wherein the second sleeve portion and the third sleeve portion are spaced apart from each other by a second distance in a second direction perpendicular to the first direction, the second distance being greater than the first distance.

2. The integral device as claimed in claim 1, wherein the first sleeve portion has a first width measured in the second direction, and wherein there is a third distance between the outermost wall of the second sleeve portion and the outermost wall of the third sleeve portion, the third distance being substantially equal to the first width.

3. The integrated device as claimed in claim 1, wherein the capacitor further includes a fourth bottom surface and a fourth sleeve portion, the fourth sleeve portion coupling the fourth bottom surface to the upper portion, wherein the fourth sleeve portion is spaced apart from the first sleeve portion in the first direction by the second sleeve portion and the third sleeve portion.

4. The integrated device as claimed in claim 1, wherein the first sleeve portion has a substantially rectangular cross-section in a top view, the substantially rectangular cross-section having a length extending in the second direction greater than its width extending in the first direction; wherein a first outer wall of the first sleeve portion is substantially parallel to the second direction; wherein the second sleeve portion and the third sleeve portion have a second substantially rectangular cross-section in a top view, the second substantially rectangular cross-section having a length extending in the second direction greater than its width extending in the first direction; and wherein the second outer wall of the second sleeve portion is substantially aligned with the third outer wall of the third sleeve portion, and the second outer wall and the third outer wall extend primarily in the second direction.

5. An integrated device, comprising: Interconnect structure covering the substrate; and a capacitor located within the interconnect structure, the capacitor comprising: a first upper portion; a first plurality of protrusions extending from the first upper portion, spaced apart from each other in a first direction, and extending a first distance in a second direction between a first outer sidewall and a second outer sidewall of the first plurality of protrusions; a second plurality of protrusions extending from the first upper portion, having a first outermost outer wall substantially aligned with the first outer sidewall of the first plurality of protrusions, and extending a second distance in the second direction, the second distance being less than the first distance; and a third plurality of protrusions extending from the first upper portion, having a first outermost outer wall substantially aligned with the second outer sidewall of the first plurality of protrusions, and extending a third distance in the second direction toward the second plurality of protrusions, the third distance being substantially equal to the second distance.

6. The integral device as claimed in claim 5, wherein the second plurality of protrusions further includes a second outermost wall opposite to the first outermost wall of the second plurality of protrusions, the second outermost wall being at a second distance from the first outermost wall of the second plurality of protrusions and facing the third plurality of protrusions; and wherein the third plurality of protrusions further includes a second outermost wall opposite to the first outermost wall of the third plurality of protrusions, the second outermost wall of the third plurality of protrusions being at a third distance from the first outermost wall of the third plurality of protrusions and facing the second plurality of protrusions.

7. The integrated device as claimed in claim 5, wherein the first plurality of protrusions, the second plurality of protrusions and the third plurality of protrusions extend to a first metal layer and are separated by an interlayer dielectric layer.

8. A method of forming an integrated device, comprising: A first portion of an interconnect structure is formed over a substrate, the first portion of the interconnect structure comprising an interlayer dielectric layer and a first wire layer; The interlayer dielectric layer is patterned to form a first plurality of openings extending from a first vertical plane to a second vertical plane, a second plurality of openings extending from the first vertical plane to a plurality of dielectric pillars remaining within the interlayer dielectric layer, and a third plurality of openings extending from the second vertical plane to the plurality of dielectric pillars, the first plurality of openings, the second plurality of openings and the third plurality of openings exposing the first line layer; and a bottom electrode, an insulating layer and a top electrode are formed on the interlayer dielectric layer such that the bottom electrode conforms to the sidewalls of the interlayer dielectric layer within the first plurality of openings, the second plurality of openings and the third plurality of openings.

9. The method of claim 8, wherein the first plurality of openings are spaced apart from the second plurality of openings and the third plurality of openings by a first thickness, the first thickness being measured in a first direction, and the plurality of dielectric pillars have a second thickness measured in a second direction perpendicular to the first direction, wherein the second thickness is greater than the first thickness.

10. The method of claim 8, wherein the first vertical plane is parallel to the second vertical plane.