Semiconductor die stacks and methods for forming the same

Abstract

A semiconductor assembly is provided, which includes a through-substrate-via-containing semiconductor die, an adhesive layer, and a semiconductor carrier substrate. The through-substrate-via-containing semiconductor die includes a first semiconductor substrate having through-substrate-via structures formed therein, first semiconductor devices, and front connection pads located on a front side of the first semiconductor substrate, and backside metal interconnect structures located on a backside of the first semiconductor substrate. The semiconductor assembly may be attached to a carrier wafer using a die attachment film. The semiconductor carrier substrate and the adhesive layer may be removed from the semiconductor assembly.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor grain stacking and a method for forming the same. Prior Technology

[0002] In the semiconductor industry, with the continued growth in demand for improved performance and functionality, the trend towards integrating multiple semiconductor dies in a three-dimensional (3D) configuration is becoming increasingly apparent. Related semiconductor die stacking methods, particularly for large dies exceeding 200 square millimeters, face challenges related to yield, reliability, and manufacturing costs. Large semiconductor dies are prone to defects that reduce yield, especially when employing advanced technology nodes with smaller features. This leads to increased production costs and reduced overall yield. Furthermore, related die stacking methods, such as face-to-back (F2B) or face-to-face (F2F) stacking, are limited by the use of microbumps to achieve high-density interconnects, especially when fine-pitch interconnects are required. The desire to implement complex through-silicon via (TSV) structures further exacerbates manufacturing complexity, often resulting in inefficient processes and difficulty in maintaining the structural integrity of the entire stack. These problems are particularly pronounced in applications requiring the integration of large active dies to meet performance and design standards. Therefore, there is a strong desire for new semiconductor die stacking methods to address these challenges and provide cost-effective and high-yield solutions for integrating large active dies in 3D configurations. Summary of the Invention

[0003] A method for forming a semiconductor structure is provided, comprising: attaching semiconductor components to a carrier wafer, wherein each of the semiconductor components includes a semiconductor die and a semiconductor carrier substrate, wherein the semiconductor die includes a first semiconductor substrate having a substrate through-hole structure formed therein, a first semiconductor element, a front-side connection pad located on a front side of the first semiconductor substrate, and a back-side metal interconnect structure located on a back side of the first semiconductor substrate; removing the semiconductor carrier substrate from the combination of the carrier wafer and the semiconductor components; and after removing the semiconductor carrier substrate, forming a first molding compound matrix in the gaps between the semiconductor dies.

[0004] A semiconductor package is provided, comprising: a semiconductor die including a first semiconductor substrate having a substrate through-hole structure, a first semiconductor element, a front connection pad located on the front side of the first semiconductor substrate and embedded in at least one front dielectric capping layer, and a back metal interconnect structure located on the back side of the first semiconductor substrate; a first molding compound matrix laterally surrounding the semiconductor die; a first dielectric bonding layer located on the back metal interconnect structure; a first bump structure located on the first dielectric bonding layer; a second dielectric bonding layer located on the front connection pad; and a second bump structure located on the second dielectric bonding layer, wherein the outer wall of the at least one front dielectric capping layer is laterally offset inward relative to the outer wall of the first molding compound matrix, and the outer wall of the second dielectric bonding layer is perpendicularly coincident with the outer wall of the first molding compound matrix.

[0005] A method for forming a semiconductor structure is provided, comprising: providing a semiconductor assembly, wherein the semiconductor assembly includes a semiconductor die and a semiconductor carrier substrate, wherein the semiconductor die includes a first semiconductor substrate having a substrate through-hole structure formed therein, a first semiconductor element, a front-side connection pad located on the front side of the first semiconductor substrate, and a first back-side metal interconnect structure located on the back side of the first semiconductor substrate; attaching the semiconductor carrier substrate to a carrier wafer; and forming a first molding compound matrix around the semiconductor assembly and in the gaps between adjacent semiconductor assemblies. Simple Explanation of the Diagram

[0006] The best understanding of all aspects of this disclosure can be obtained from the detailed description below when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various feature components are not drawn to scale. In fact, for clarity, the dimensions of the various feature components may be arbitrarily increased or decreased. Figures 1A to 1N are successive vertical cross-sectional views of the structure of the first embodiment during a series of process steps according to the embodiments disclosed herein. Figure 10 is a first flowchart including a set of process steps used during the manufacture of the structure of the first embodiment. Figures 2A to 2N are successive vertical cross-sectional views of the structure of the second embodiment during a series of process steps according to the embodiments disclosed herein. Figure 20 is a second flowchart including a set of process steps used during the manufacture of the structure of the second embodiment. Figures 3A to 3N are successive vertical cross-sectional views of the structure of the third embodiment during a series of process steps according to the embodiments disclosed herein. Figure 30 is a third flowchart including a set of process steps used during the manufacture of the structure of the third embodiment. Figures 4A to 4M are successive vertical cross-sectional views of the structure of the fourth embodiment during a series of process steps according to the embodiments disclosed herein. Figure 4N is a fourth flowchart that includes a set of process steps used during the manufacture of the structure of the fourth embodiment. Figures 5A to 5L are successive vertical cross-sectional views of the structure of the fifth embodiment during a series of process steps according to the embodiments disclosed herein. Figure 5M is a fifth flowchart that includes a set of process steps used during the manufacture of the structure of the fifth embodiment. Figures 6A to 6L are successive vertical cross-sectional views of the structure of the sixth embodiment during a series of process steps according to the embodiments disclosed herein. Figure 6M is a sixth flowchart that includes a set of process steps used during the manufacture of the structure of the sixth embodiment. Implementation

[0007] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are merely examples and are not limiting. The drawings are not to scale. Elements with the same reference numerals refer to the same elements and are assumed to have the same material composition and the same thickness range unless explicitly stated otherwise. All features of the original embodiments are assumed to exist in any derived embodiments unless explicitly disclosed otherwise. Therefore, features described in the drawings and / or specifications with reference to relevant embodiments support features in the embodiments. Multiple embodiments are explicitly contemplated in which multiple instances of any described element are repeated unless explicitly stated otherwise. Embodiments in which non-essential elements are omitted are explicitly contemplated, even if such embodiments are not explicitly disclosed but are known in the art.

[0008] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar expressions may be used herein to describe the geometric characteristics between the elements shown in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein will be interpreted accordingly. Unless otherwise expressly stated, each element with the same reference number is assumed to have the same material composition and a thickness within the same thickness range.

[0009] This disclosure addresses semiconductor structures and packaging solutions designed to address the challenges of integrating large semiconductor dies containing through-substrate-vias (TSVs), such as those exceeding 200 square millimeters in area. Related methods, such as face-to-back (F2B) and face-to-face (F2F) stacks, face-to-face suffer from limitations in yield and reliability due to defects and the complexity of fine-pitch interconnects. The various embodiments disclosed herein introduce methods to improve yield by utilizing novel combinations of advanced bump structures, dielectric bonding layers, and molding compounds, thereby providing structural stability and thermal management.

[0010] According to the aspects disclosed herein, a first molding compound matrix can be formed around the semiconductor die containing TSVs, which provides lateral support and reduces mechanical stress in subsequent process steps. Various embodiments can further provide high-density interconnects by utilizing dielectric bonding layers and bump structures, facilitating efficient vertical and horizontal signal routing between semiconductor dies of stacked devices. Furthermore, the use of underfill material around the solder array provides partial mechanical reinforcement and reduces the likelihood of failure due to thermal expansion mismatch. Embodiments of this disclosure simplify the manufacturing process and reduce production costs while maintaining high interconnect density and minimizing defects. Embodiments of this disclosure can be used to manufacture semiconductor packages for advanced technology nodes and high-performance applications. Various aspects of the methods and structures of the embodiments of this disclosure will now be described with reference to the accompanying drawings.

[0011] Figures 1A to 1N are sequential vertical cross-sectional views of the structure of the first embodiment during a series of process steps according to the present disclosure.

[0012] Referring to FIG1A, a device wafer 300W is illustrated, which includes a first semiconductor substrate 310 and structural elements formed therein and on it. The first semiconductor substrate 310 may include a semiconductor wafer, such as a commercial silicon wafer with a diameter of 150 mm, 200 mm, 300 mm, or 450 mm. A two-dimensional array of semiconductor dies 300 containing substrate through-holes (TSVs) may be formed in the device wafer 300W. As used herein, a semiconductor die containing substrate through-holes refers to a semiconductor die containing a substrate through-hole (TSV) structure, i.e., a through-hole structure of the substrate extending vertically through the semiconductor die. It should be understood that the semiconductor die 300 containing substrate through-holes (TSVs) shown in FIG1A is an in-process structure in which a TSV structure 304 is formed on the upper part of the first semiconductor substrate 310, and the TSV structure 304 does not extend vertically through the first semiconductor substrate 310. In addition, the TSV structure 304 is provided in a configuration that extends vertically through the thinned first semiconductor substrate 310 during subsequent thinning of the first semiconductor substrate 310 from the back side.

[0013] The two-dimensional array of semiconductor dies 300 containing substrate through-vessels (TSVs) can be a rectangular periodic array having a first spacing along a first horizontal direction and a second spacing along a second horizontal direction. The first spacing may be greater than 5 mm, and / or greater than 10 mm, and / or greater than 20 mm. The second spacing may be greater than 5 mm, and / or greater than 10 mm, and / or greater than 20 mm. The boundary between adjacent pairs of semiconductor dies 300 containing substrate through-vessels (TSVs) includes dicing channels. Each semiconductor die 300 containing a substrate through-vessel (TSV) is located within its respective set of dicing channels. Although only a single semiconductor die 300 containing a substrate through-vessel (TSV) is shown in Figure 1A, it should be understood that the device wafer 300W typically contains a two-dimensional periodic array of semiconductor dies 300 containing substrate through-vessels (TSVs).

[0014] Typically, an array of via cavities can be formed on the upper portion of the first semiconductor substrate 310. The lateral dimension of each via cavity can range from 0.3 micrometers to 20 micrometers, for example from 1 micrometer to 10 micrometers, although smaller and larger lateral dimensions can also be used. The depth of each via cavity can range from 1 micrometer to 30 micrometers, for example from 3 micrometers to 15 micrometers, although smaller and larger depths can also be used. An insulating material layer can be conformally deposited in the peripheral region of the via cavities. The thickness of the insulating material layer can range from 10 nanometers to 300 nanometers, although smaller and larger thicknesses can also be used. At least one conductive material, such as at least one metallic material, can be deposited in the remaining volume of the via cavities. A planarization process can be performed to remove portions of at least one conductive material and the insulating material layer above the horizontal plane where the top surface of the first semiconductor substrate 310 is located. The remaining portion of the at least one conductive material includes a substrate through-hole (TSV) structure 304. The remaining portion of the insulating material layer includes insulating spacer walls 302.

[0015] A first semiconductor element 320 may be formed on the top surface of a first semiconductor substrate 310. The first semiconductor element 320 may include active elements such as field-effect transistors and may optionally include passive elements such as capacitors, resistors, inductors, etc. The first semiconductor element 320 may include a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a digital signal processor (DSP), embedded volatile memory, and / or embedded non-volatile memory.

[0016] A first metal interconnect structure 360 ​​formed in the first dielectric material layer 350 may be formed on the first semiconductor element 320. The first metal interconnect structure 360 ​​may include metal wires, metal via structures, metal pads, or any other metal structure that can be used to provide electrical interconnects for the semiconductor element. The first dielectric material layer 350 may include any interlayer dielectric (ILD) material known to those skilled in the art. In one embodiment, the first dielectric material layer 350 may include, and / or may be composed of at least one inorganic dielectric material, such as undoped silicate glass, doped silicate glass, organic silicate glass, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, dielectric metal oxide, etc. It is worth noting that, despite the name, "organic silicate glass" used in the semiconductor industry is an inorganic material. Organosilicate glass (OSG) refers to a dielectric material based on silicon dioxide (SiO₂) with organic groups, typically alkyl groups such as methyl or ethyl, incorporated to alter its properties. These organic groups are introduced to lower the dielectric constant of the material, thereby reducing parasitic capacitance in integrated circuits and improving performance. However, the core structure of OSG remains primarily composed of silicon-oxygen bonds, a characteristic of inorganic materials. Therefore, although OSG contains organic components as functional additives, it is classified as an inorganic material due to its dominant silicon-oxygen framework.

[0017] At least one front dielectric capping layer (370, 372) and a front connection pad 378 may subsequently be formed on the first metal interconnect structure 360. At least one front dielectric capping layer (370, 372) may include a stack of the first front dielectric capping layer 370 and the second front dielectric capping layer 372. In one embodiment, the front connection pad 378 may include a metal via portion extending vertically through the first front dielectric capping layer 370 and a metal pad portion formed in the second front dielectric capping layer 372. In one embodiment, the first front dielectric capping layer 370 may be formed on the first metal interconnect structure 360, and a via opening may be formed in the first front dielectric capping layer 370. A metal layer may be deposited in the via opening and on the top surface of the first front dielectric capping layer 370, and may subsequently be patterned to form the front connection pad 378. The second front dielectric capping layer 372 may be formed by depositing and planarizing a dielectric material on the front connector pad 378. The top surface of the front connector pad 378 may be physically exposed and may be formed in a horizontal plane including the top surface of the second front dielectric capping layer 372. In one embodiment, the first front dielectric capping layer 370 may include silicon nitride, and the second front dielectric capping layer 372 may include silicon oxide. The front connector pad 378 may include copper or aluminum.

[0018] Referring to FIG1B, the device wafer 300W may be attached to the handle wafer 701, for example, using a die attachment film 731. The handle wafer 701 may be any wafer that can be used to provide mechanical support during subsequent processing of the device wafer 300W. In one embodiment, the handle wafer 701 may include a glass carrier wafer having the same lateral dimensions as the device wafer 300W.

[0019] Referring to Figure 1C, the device wafer 300W can be inverted and thinned from the back side. The back side of the first semiconductor substrate 310 can be removed by grinding, polishing, anisotropic etching processes and / or isotropic etching processes. The back surface of the substrate through-hole (TSV) structure 304 can be actually exposed during the thinning of the first semiconductor substrate 310. The substrate through-hole (TSV) structure 304 extends vertically through the thinned first semiconductor substrate 310.

[0020] The back surface of the first semiconductor substrate 310 may be further thinned by performing an etching process (which may include anisotropic etching or isotropic etching). An insulating material (e.g., silicon oxide) may be deposited on the recessed back surface of the first semiconductor substrate 310. Excess of the insulating material above the horizontal plane including the back surface of the substrate through-hole (TSV) structure 304 may be removed by performing a planarization process (e.g., chemical mechanical polishing). The remaining portion of the insulating material constitutes the back insulating layer 316. The back surface actually exposed by the substrate through-hole (TSV) structure 304 may be coplanar with the horizontal surface actually exposed by the back insulating layer 316.

[0021] At least one metal layer may be deposited on the back surface of the substrate through-via (TSV) structure 304 and may subsequently be patterned to form a first back-side metal interconnect structure 340. The first back-side metal interconnect structure 340 may include metal pad structures, metal line structures, and / or metal pillar structures. The device wafer 300W includes an array of semiconductor dies 300 containing substrate through-vias (TSVs).

[0022] Referring to Figure 1D, the semiconductor carrier wafer 924W can be attached to the device wafer 300W using a continuous adhesive layer 914W. The semiconductor carrier wafer 924W may include a commercially available semiconductor wafer (e.g., a silicon wafer) having the same lateral extent as the device wafer 300W. The continuous adhesive layer 914W may include an adhesive layer. For example, the continuous adhesive layer 914W may include a thermosetting adhesive, such as benzocyclobutene (BCB) or an epoxy-based adhesive. The continuous adhesive layer 914W provides adhesion between the device wafer 300W and the semiconductor carrier wafer 924W. Optionally, the semiconductor carrier wafer 924W may be thinned to a desired target thickness before or after bonding to the device wafer 300W. The thickness of the semiconductor carrier wafer 924W can range from 60 micrometers to 1 millimeter, for example from 150 micrometers to 600 micrometers, although smaller and larger thicknesses are also possible. A wafer-level bonding assembly (300W, 914W, 924W) is formed, consisting of a device wafer 300W, a continuous adhesive layer 914W, and a semiconductor carrier wafer 924W.

[0023] Referring to FIG1E, the die adhesion film 731 can be deactivated to facilitate the separation of the processed wafer 701 from the wafer-level bonding components (300W, 914W, 924W). For example, the die adhesion film 731 may comprise a UV-degradable material, and the processed wafer 701 may comprise a transparent wafer (such as a glass substrate). In this embodiment, UV radiation can pass through the processed wafer 701 to irradiate the die adhesion film to disrupt its adhesive properties, making it easy to separate. Once the die adhesion film 731 is deactivated, the processed wafer 701 is removed, leaving the device wafer 300W firmly bonded to the semiconductor carrier wafer 924W through a continuous adhesive layer 914W. To prepare the surface for subsequent processing, any residual die adhesion film 731 can be removed through a cleaning process (such as solvent cleaning or plasma etching) to ensure a contaminated interface.

[0024] The wafer-level bonding assemblies (300W, 914W, 924W) can then be diced along a dicing channel. The dicing channel extends along the boundary between adjacent pairs of semiconductor dies 300 containing substrate through-vessels (TSVs). The diced portion of the wafer-level bonding assemblies (300W, 914W, 924W) includes semiconductor assemblies (300, 914, 924). Each semiconductor assembly (300, 914, 924) includes a semiconductor die 300 containing a substrate through-vessel (TSV), an adhesive layer 914, and a semiconductor carrier substrate 924. The semiconductor die 300 containing a substrate through-vessel (TSV) includes a first semiconductor substrate 310 having a substrate through-vessel (TSV) structure 304 formed therein, a first semiconductor element 320, a front-side connection pad 378 located on the front side of the first semiconductor substrate 310, and a back-side metal interconnect structure 340 located on the back side of the first semiconductor substrate 310.

[0025] Referring to FIG1F, multiple semiconductor components (300, 914, 924) provided through the process steps described with reference to FIGS. 1A to 1E can be attached to a carrier wafer 902 using a die attachment film 932. It should be understood that FIG1F and subsequent figures only illustrate the area surrounding a single semiconductor component (300, 914, 924). The carrier wafer 902 can be any carrier wafer known to those skilled in the art. For example, the carrier wafer 902 may include a glass substrate having a circular or rectangular shape in a plan view. The die attachment film 932 may include an ultraviolet-degradable adhesive material. The die attachment film 932 may be attached to the top surface of the carrier wafer 902, and a two-dimensional array of semiconductor components (300, 914, 924) may be attached to the die attachment film 932. In one embodiment, the two-dimensional array of semiconductor components (300, 914, 924) may be arranged as a two-dimensional rectangular array of semiconductor components (300, 914, 924). A gap may exist between each pair of adjacent semiconductor components (300, 914, 924).

[0026] Referring to Figure 1G, each semiconductor carrier substrate 924 in the semiconductor component (300, 914, 924) array can be separated from its respective semiconductor die 300 containing a substrate through-vessel (TSV). Each semiconductor carrier substrate 924 can be separated from its respective semiconductor die 300 containing a TSV by performing a debonding process using thermal stripping or solvent stripping. For example, each adhesive layer 914 can be deactivated to facilitate the separation of the semiconductor carrier substrate 924 from the semiconductor die 300 containing a TSV. Specifically, the adhesive layer 914, which may include a thermally decomposable material, can be decomposed by performing an annealing process at an elevated temperature in the range of 150 to 300 degrees Celsius. Alternatively, the adhesive layer 914 can be removed by dissolution using a suitable solvent. Once deactivated, the semiconductor carrier substrate 924 is removed, exposing the semiconductor die 300 containing a TSV and preparing it for subsequent processing. To ensure surface cleanliness, any residual adhesive on the adhesive layer 914 can be removed through cleaning processes (such as solvent cleaning or plasma etching), ensuring a contamination-free interface for further manufacturing steps. Therefore, the semiconductor carrier substrate 924 and the adhesive layer 914 can be removed from each semiconductor assembly (300, 914, 924). Removing the semiconductor carrier substrate 924 and the adhesive layer 914 from the semiconductor die 300 can create gaps 380 or cavities between adjacent semiconductor dies 300.

[0027] Referring to FIG1H, a first molding compound matrix 397 may be formed around a two-dimensional array of semiconductor dies 300 containing substrate through-vessels (TSVs). The first molding compound matrix 397 may include an epoxy molding compound (EMC). Typically, the EMC contains epoxy resin, a hardener, silica filler, and other additives to enhance its performance. High filler content (e.g., 85% by weight) may be used to reduce molding shrinkage, minimize warpage, and improve flowability during the encapsulation process. The filler is distributed throughout the molding process to suppress flow marks, thereby promoting smooth application of the EMC. The EMC can be cured at temperatures ranging from 125°C to 150°C, thereby maintaining the integrity of the component during the molding process. The first molding compound matrix 397 may also fill gaps 380 that appear between the semiconductor dies 300 after the removal of the semiconductor carrier substrate 924 and the adhesive layer 914 from the semiconductor dies 300. See, for example, FIG1G.

[0028] After curing, excess molding compound can be removed from the first back-side metal interconnect structure 340 by performing a planarization process. Specifically, the portion of cured EMC material covering the horizontal plane including the top surface of the first back-side metal interconnect structure 340 can be removed by performing a chemical mechanical polishing process. The remaining portion of the cured EMC material constitutes the first molding compound matrix 397.

[0029] The first molding compound matrix 397 can be embedded in a two-dimensional array of semiconductor dies 300 containing substrate through-vessels (TSVs), and may have a top surface located in a horizontal plane including the topmost surface of the first back-side metal interconnect structure 340, and may include a flat bottom surface that contacts the top surface of the die attachment film 932. The first molding compound matrix 397 provides mechanical support and environmental protection for the semiconductor dies 300 containing substrate through-vessels (TSVs). The first molding compound matrix 397 can contact the sidewalls of the back-side metal interconnect structure 340 and the horizontal top surface of the back-side insulating layer 316.

[0030] Referring to FIG1I, a first dielectric bonding layer 460 having a first bonding-level metal interconnect structure 480 formed therein may be formed on the top surface of a first molding compound matrix 397. The first dielectric bonding layer 460 includes at least one interlayer dielectric (ILD) layer, which may include at least one via-level dielectric layer and / or at least one line-level dielectric layer. The first dielectric bonding layer 460 may include, and / or may be substantially composed of at least one inorganic dielectric material, such as undoped silicate glass, doped silicate glass, organic silicate glass, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, dielectric metal oxide, etc. The first bonding-level metal interconnect structure 480 may include a metal via structure, a metal wire structure, a metal pad structure, etc.

[0031] A first bump structure 498 may be formed on the top layer of the first dielectric bonding layer 460. Each first bump structure 498 may be formed on a respective back-side metal interconnect structure 340 covering the first molding compound matrix 397. In an embodiment, the first bump structure 498 may include a via portion formed within and laterally surrounded by the first dielectric bonding layer 460. Furthermore, the first bump structure 498 may include a pillar structure or pad structure covering the top surface of the first dielectric bonding layer 460. In an embodiment, the first bump structure 498 may include a chip connection (C2) bonding structure, such as a microbump structure.

[0032] Referring to FIG1J, the component semiconductor die 100 may be attached to the first bump structure 498 using an array of solder portions 493. Each component semiconductor die 100 may include active components, such as field-effect transistors, and may optionally include passive components, such as capacitors, resistors, inductors, etc. Each component semiconductor die 100 may include a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a digital signal processor (DSP), embedded volatile memory, and / or embedded non-volatile memory. Each component semiconductor die 100 may have a smaller area in a planar view along the vertical direction than the semiconductor die 300 below containing a substrate through-via (TSV).

[0033] In one embodiment, each element semiconductor die 100 may include a semiconductor substrate 110, a respective set of second semiconductor elements 120 (which may be referred to as additional semiconductor elements), and a respective set of second dielectric material layers 150 having second metal interconnect structures 160 formed therein. In one embodiment, each element semiconductor die 100 may include a respective interconnect-level dielectric layer 180 having a respective set of interconnect metal pads 188, and a respective bump-level dielectric layer 190 having a respective set of second bump structures 198. The second bump structures 198 of the element semiconductor die 100 may be bonded to the first bump structure 498 through an array of solder portions.

[0034] An underfill material portion 495 may be formed around each set of solder portions 493 covering the semiconductor die 300 containing a substrate through-via (TSV). In one embodiment, each underfill material portion 495 may laterally surround all solder portions 493 that overlap in area with their respective underlying semiconductor die 300 containing a substrate through-via (TSV).

[0035] An underfill material portion 495 may be formed around each set of solder portions 493 covering the semiconductor die 300 containing a substrate through-vehicle (TSV). In one embodiment, the underfill material portion 495 may laterally surround all solder portions 493 that overlap in area with their respective underlying semiconductor die 300 containing a TSV. The underfill material provides structural support and reduces mechanical stress that may occur due to thermal cycling or mechanical shock. The material absorbs stress between the element semiconductor die 100 and the semiconductor die 300 containing a TSV. The underfill material may be applied using capillary underfill, molded underfill, or printed underfill techniques.

[0036] Capillary underfill relies on capillary action to distribute material between solder bumps, while molding and printing underfill techniques involve direct application. Underfill materials typically consist of epoxy resin with silica or other fillers. Filler content can be up to 85% by weight, which improves thermal conductivity and mechanical strength, and reduces shrinkage and warpage during curing. After application, the underfill material cures at a temperature below the solder reflow temperature to solidify and protect the underlying structure. Underfill materials reduce structural damage to the solder portion 493 in subsequent process steps and improve the overall durability of the semiconductor package.

[0037] Referring to Figure 1K, a second molding compound matrix 497 may be formed around the semiconductor die 100 and the underfill material portion 495, directly on the first dielectric bonding layer 460. The second molding compound matrix 497 may include an epoxy molding compound (EMC). The EMC can be cured in a temperature range of 125 to 150 degrees Celsius, thereby maintaining the integrity of the component during the molding process. After curing, excess molding compound above the semiconductor die 100 can be removed by performing a planarization process. Specifically, the cured EMC material portion covering the horizontal plane including the topmost surface of the semiconductor die 100 can be removed by performing a chemical mechanical polishing process. The remaining portion of the cured EMC material constitutes the second molding compound matrix 497.

[0038] The second molding compound matrix 497 can be embedded in a two-dimensional array of the device semiconductor die 100, and may have a top surface located in a horizontal plane including the topmost surface of the device semiconductor die 100, and may include a flat bottom surface that contacts the top surface of the first dielectric bonding layer 460. The second molding compound matrix 497 provides mechanical support and environmental protection for the device semiconductor die 100. Generally, the second molding compound matrix 497 is perpendicularly spaced from the first molding compound matrix 397 through the first dielectric bonding layer 460 and does not contact the first molding compound matrix 397. The second molding compound matrix 497 can be formed directly around the device semiconductor die 100 on the first dielectric bonding layer 460.

[0039] Referring to FIG1L, an additional carrier wafer 903 may be attached to the device semiconductor die 100 using an additional die adhesion film 933. The additional carrier wafer 903 may be any carrier wafer known to those skilled in the art. For example, the additional carrier wafer 903 may include a glass substrate having a circular or rectangular shape in a plan view. The additional die adhesion film 933 may include an ultraviolet-degradable adhesive material. The additional die adhesion film 933 may be attached to the top surface of the device semiconductor die 100 and the additional carrier wafer 903.

[0040] Subsequently, the carrier wafer 902 and the die-attachment film 932 can be removed. For example, an ultraviolet irradiation process can be performed to irradiate the die-attachment film 932 with an ultraviolet beam through the carrier wafer 902. The die-attachment film 932 can be deactivated by ultraviolet radiation. A suitable cleaning process can be performed to clean the physically exposed surfaces of the front bonding pad 378, the second front dielectric capping layer 372, and the first molding compound matrix 397.

[0041] Referring to FIG1M, a second dielectric bonding layer 560 having a second bonding-level metal interconnect structure 580 formed therein can be formed on the front-side connection pad 378. The second dielectric bonding layer 560 can be formed directly on the first molding compound matrix 397. The second dielectric bonding layer 560 includes at least one interlayer dielectric (ILD) layer, which may include at least one via-level dielectric layer and / or at least one line-level dielectric layer. The second dielectric bonding layer 560 may include, and / or may be substantially composed of at least one inorganic dielectric material, such as undoped silicate glass, doped silicate glass, organic silicate glass, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, dielectric metal oxide, etc. The second bonding-level metal interconnect structure 580 may include a metal via structure, a metal wire structure, a metal pad structure, etc.

[0042] Metal bump structures 598 may be formed on the top layer of the second dielectric bonding layer 560. Each metal bump structure 598 may be formed on a respective second bonding-level metal interconnect structure 580 that covers and contacts the first molding compound matrix 397. In one embodiment, the metal bump structure 598 may include a via portion formed within and laterally surrounded by the second dielectric bonding layer 560. Furthermore, the metal bump structure 598 may include a pad structure covering the top surface of the second dielectric bonding layer 560. In one embodiment, the metal bump structure 598 may include a controlled-collapse wafer interconnect (C4) pad. Each metal bump structure 598 may be formed directly on its respective second bonding-level metal interconnect structure 580 and located above the second dielectric bonding layer 560. Solder balls 593 may be attached to the metal bump structures 598.

[0043] Referring to FIG1N, the additional carrier wafer 903 and the additional die-attachment film 933 can be removed. For example, an ultraviolet irradiation process can be performed to irradiate the additional die-attachment film 933 with an ultraviolet beam through the additional carrier wafer 903. The additional die-attachment film 933 can be deactivated by ultraviolet radiation. A suitable cleaning process can be performed to clean the physically exposed surfaces of the element semiconductor die 100 and the second molding compound matrix 497.

[0044] A dicing process can be performed to dic (single-size) a reconstituted die comprising a two-dimensional array of semiconductor dies 300 with substrate through-vessels (TSVs), a first molding compound matrix 397, a first dielectric bonding layer 460, a two-dimensional array of groups of element semiconductor dies 100, a two-dimensional array of underfill material portions 495, and a second molding compound matrix 497. Generally, the reconstituted die includes at least a dielectric bonding layer 560, a first molding compound matrix 397, and a first dielectric bonding layer 460. The diced portions of the reconstituted die include composite dies 800. Each composite die 800 includes a diced portion of the semiconductor dies 300 with substrate through-vessels (TSVs), a diced portion of the second dielectric bonding layer 560, a diced portion of the first molding compound matrix 397, a diced portion of the first dielectric bonding layer 460, and a diced portion of the second molding compound matrix 497.

[0045] The example structure shown in Figure 1N includes a semiconductor package comprising: a semiconductor die 300 with a substrate through-vessel (TSV), including a first semiconductor substrate 310 having a substrate through-vessel (TSV) structure 304 formed therein, a first semiconductor element 320 and a front-side connector pad 378 located on the front side of the first semiconductor substrate 310, and a back-side metal interconnect structure 340 located on the back side of the first semiconductor substrate 310; a first molding compound matrix 397 laterally surrounding the semiconductor die 300 with the substrate through-vessel (TSV); a first dielectric bonding layer 460 located on the back-side metal interconnect structure 340; and a first bump structure 498 located on the first dielectric bonding layer 460.

[0046] In one embodiment, the semiconductor package includes a component semiconductor die 100 attached to a first bump structure 498 through an array of solder material portions 493. In one embodiment, the semiconductor package includes: an underfill material portion 495 laterally surrounding the array of solder material portions 493; and a second molding compound matrix 497 laterally surrounding the component semiconductor die 100 and the underfill material portion 495. In one embodiment, the sidewalls of a first dielectric bonding layer 460 are perpendicularly aligned with the outer sidewalls of the second molding compound matrix 497. In one embodiment, the second molding compound matrix 497 is perpendicularly spaced from the first molding compound matrix 397 through the first dielectric bonding layer 460.

[0047] In one embodiment, the sidewalls of the first dielectric bonding layer 460 are perpendicularly aligned with the outer sidewalls of the first molding compound matrix 397. In one embodiment, the semiconductor package includes a second dielectric bonding layer 560, wherein a bonding-level metal interconnect structure 580 is formed to contact the front-side connection pad 378. In one embodiment, the second dielectric bonding layer 560 is contactable with the first molding compound matrix 397. In one embodiment, the sidewalls of the second dielectric bonding layer 560 are perpendicularly aligned with the outer sidewalls of the first molding compound matrix 397.

[0048] In one embodiment, the first dielectric bonding layer 460 may have a first bonding-level metal interconnect structure 480 formed therein. A first bump structure 498 contacts a subset of the first bonding-level metal interconnect structure 480. In one embodiment, a first molding compound matrix 397 contacts the sidewall of the back-side metal interconnect structure 340. In one embodiment, the semiconductor die 300 containing a substrate through-hole (TSV) includes a back-side insulating layer 316 interposed between the first semiconductor substrate 310 and the back-side metal interconnect structure 340. In one embodiment, the first molding compound matrix 397 contacts the horizontal surface of the back-side insulating layer 316. In one embodiment, the first semiconductor element 320 includes a first field-effect transistor; and each of the element semiconductor dies 100 includes a set of additional field-effect transistors.

[0049] Referring to FIG10, a first flowchart is provided, which includes a set of process steps for forming a semiconductor structure.

[0050] Referring to step 1110 and Figures 1A to 1E, a semiconductor component (300, 914, 924) is provided, which includes a semiconductor die 300 with a substrate through-hole (TSV), an adhesive layer 914, and a semiconductor carrier substrate 924. The semiconductor die 300 with a substrate through-hole (TSV) includes a first semiconductor substrate 310 with a substrate through-hole (TSV) structure 304, a first semiconductor element 320, a front-side connection pad 378 located on the front side of the first semiconductor substrate 310, and a back-side metal interconnect structure 340 located on the back side of the first semiconductor substrate 310.

[0051] Referring to step 1120 and Figure 1F, semiconductor components (300, 914, 924) can be attached to carrier wafer 902 using die attachment film 932.

[0052] Referring to step 1130 and Figures 1G to 1N, the semiconductor carrier substrate 924 and the adhesive layer 914 can be removed from the semiconductor components (300, 914, 924).

[0053] Figures 2A to 2N are continuous vertical cross-sectional views of the structure of the second embodiment in a series of process steps according to an embodiment of the present disclosure.

[0054] Referring to FIG2A, a device wafer 300W is illustrated, which includes a first semiconductor substrate 310 and structural elements formed therein and thereon. The device wafer 300W may be obtained by omitting the second front dielectric capping layer 372 formed in the device wafer 300W shown in FIG1A. In this embodiment, the front connection pad 378 may include a metal via portion extending vertically through the first front dielectric capping layer 370 and a metal pad portion covering the first front dielectric capping layer 370. In one embodiment, the first front dielectric capping layer 370 may be formed on a first metal interconnect structure 360, and a via opening may be formed in the first front dielectric capping layer 370. A metal layer may be deposited in the via opening and on the top surface of the first front dielectric capping layer 370, and may subsequently be patterned to form the front connection pad 378. The top surface and sidewalls of the metal pad portion of the front connection pad 378 may be physically exposed. In one embodiment, the first front dielectric capping layer 370 may include silicon nitride. The front connection pad 378 may include copper or aluminum.

[0055] Referring to Figure 2B, the device wafer 300W can be attached to the processing wafer 701, for example, using an adhesive layer 711. The adhesive layer 711 may include a thermally degradable material, a UV-degradable material, or a combination thereof, depending on the process specifications. In semiconductor manufacturing, adhesive layers are typically made of polymers such as polyimide, benzocyclobutene (BCB), epoxy-based adhesives, or other thermosetting resins. These materials are chosen based on their ability to provide strong adhesion while allowing for easy subsequent separation during the peeling process. For example, when the processing wafer 701 is a transparent substrate such as glass, a UV-degradable adhesive may be preferred, allowing UV light to penetrate the processing wafer to facilitate peeling. A thermally degradable adhesive may be used when heat treatment can be used to degrade the adhesive and separate the wafer. The adhesive layer 711 ensures strong adhesion during the processing and fabrication of the device wafer 300W. In this embodiment, the processing wafer 701 may include a glass carrier wafer with the same lateral dimensions as the device wafer 300W, providing mechanical support in subsequent steps of the manufacturing process.

[0056] Referring to Figure 2C, the device wafer 300W can be thinned from the back side. The back side of the first semiconductor substrate 310 can be removed by grinding, polishing, anisotropic etching processes and / or isotropic etching processes. The back surface of the substrate through-hole (TSV) structure 304 can be physically exposed during the thinning of the first semiconductor substrate 310. The substrate through-hole (TSV) structure 304 extends vertically through the thinned first semiconductor substrate 310.

[0057] The back surface of the first semiconductor substrate 310 may be further thinned by performing an etching process (which may include anisotropic etching or isotropic etching). An insulating material, such as silicon oxide, may be deposited on the recessed back surface of the first semiconductor substrate 310. Excess insulating material extending beyond the horizontal plane including the back surface of the substrate through-hole (TSV) structure 304 may be removed by performing a planarization process such as chemical mechanical polishing. The remaining portion of the insulating material constitutes the back insulating layer 316. The physically exposed back surface of the substrate through-hole (TSV) structure 304 may be coplanar with the physically exposed horizontal surface of the back insulating layer 316.

[0058] At least one metal layer may be deposited on the back surface of the substrate through-via (TSV) structure 304 and may subsequently be patterned to form a first back-side metal interconnect structure 340. The first back-side metal interconnect structure 340 may include metal pad structures, metal line structures, and / or metal pillar structures. The device wafer 300W includes an array of semiconductor dies 300 containing substrate through-vias (TSVs).

[0059] Referring to Figure 2D, the semiconductor carrier wafer 924W can be attached to the device wafer 300W using a continuous die attachment film 934W. For example, the continuous die attachment film 934W may include a thermally degradable adhesive material. The continuous die attachment film 934W provides adhesion between the device wafer 300W and the semiconductor carrier wafer 924W. Optionally, the semiconductor carrier wafer 924W can be thinned to a desired target thickness before or after bonding with the device wafer 300W. The thickness of the semiconductor carrier wafer 924W can range from 60 micrometers to 1 millimeter, for example from 150 micrometers to 600 micrometers, although smaller and larger thicknesses are also possible. A wafer-level bonding assembly (300W, 934W, 924W) of the device wafer 300W, the continuous die attachment film 934W, and the semiconductor carrier wafer 924W is formed.

[0060] Referring to Figure 2E, the adhesive layer 711 can be deactivated to facilitate the separation of the processed wafer 701 from the wafer-level bonding components (300W, 934W, 924W). For example, the adhesive layer 711 may comprise a UV-degradable material, while the processed wafer 701 may comprise a transparent wafer such as a glass substrate. In this embodiment, UV radiation can be applied to the die-attach film by irradiating the processed wafer 701 to degrade the adhesive properties of the film, making it easier to separate. Alternatively, the adhesive layer 711 may be dissolved in a solvent. Once the adhesive layer 711 is deactivated, the processed wafer 701 is removed, leaving the device wafer 300W firmly bonded to the semiconductor carrier wafer 924W through the continuous die-attach film 934W. To prepare the surface for subsequent processing, any residual adhesive layer can be removed by cleaning processes such as solvent cleaning or plasma etching, ensuring a contaminated interface.

[0061] The wafer-level bonding assemblies (300W, 934W, 924W) can then be diced along a dicing channel. The dicing channel extends along the boundary between adjacent pairs of semiconductor dies 300 containing substrate vias (TSVs). The diced portion of the wafer-level bonding assemblies (300W, 934W, 924W) includes semiconductor assemblies (300, 934, 924). Each semiconductor assembly (300, 934, 924) includes a semiconductor die 300 containing a substrate via (TSV), a die attachment film 934, and a semiconductor carrier substrate 924. The semiconductor die 300 containing a substrate via (TSV) includes a first semiconductor substrate 310 having a substrate via (TSV) structure 304 formed therein, a first semiconductor element 320, a front-side connection pad 378 located on the front side of the first semiconductor substrate 310, and a first back-side metal interconnect structure 340 located on the back side of the first semiconductor substrate 310.

[0062] Referring to Figure 2F, multiple semiconductor components (300, 934, 924) provided through the process steps described with reference to Figures 2A to 2E can be attached to a carrier wafer 902 using a die-attachment film 932. A gap 380 may exist between adjacent semiconductor components (300, 934, 924). It should be understood that Figure 2F and subsequent figures only illustrate the area surrounding a single semiconductor component (300, 934, 924). The carrier wafer 902 can be any carrier wafer known to those skilled in the art. For example, the carrier wafer 902 may include a glass substrate having a circular or rectangular shape in a planar view. The die-attachment film 932 may include an ultraviolet-degradable adhesive material. The die-attachment film 932 may be attached to the top surface of the carrier wafer 902, and a two-dimensional array of semiconductor components (300, 934, 924) may be attached to the die-attachment film 932. The horizontal surfaces of the first back-side metal interconnect structure 340 and the first back-side dielectric material layer 330 are accessible to the die attachment film 932. In one embodiment, the two-dimensional array of semiconductor components (300, 934, 924) can be arranged as a two-dimensional rectangular array of semiconductor components (300, 934, 924). A gap 380 may exist between each pair of adjacent semiconductor components (300, 934, 924).

[0063] Referring to Figure 2G, a first molding compound matrix 397 may be formed around a two-dimensional array of semiconductor dies 300 containing substrate through-vessels (TSVs). The first molding compound matrix 397 may also fill the gaps 380 that appear between adjacent semiconductor dies 300 in a two-dimensional rectangular array of semiconductor components (300, 934, 924). See, for example, Figure 2F.

[0064] The first molding compound matrix 397 may include an epoxy molding compound (EMC). Typically, EMC contains epoxy resin, hardener, silica filler, and other additives to enhance its properties. High filler content, such as 85% by weight, can be used to reduce molding shrinkage, minimize warpage, and improve flowability during the encapsulation process. The filler is distributed throughout the molding process to suppress flow marks, thereby promoting smooth application of the EMC. EMC can be cured in a temperature range of 125°C to 150°C, thus maintaining the integrity of the component during the molding process.

[0065] After curing, excess molding compound can be removed from above the front connector pad 378 by performing a planarization process. Specifically, the cured EMC material covering the horizontal plane including the topmost surface of the front connector pad 378 can be removed by performing a chemical mechanical polishing process. The remaining portion of the cured EMC material constitutes the first molding compound matrix 397.

[0066] A first molding compound matrix 397 can be embedded in a two-dimensional array of semiconductor dies 300 containing substrate through-vessels (TSVs), and may have a top surface located in a horizontal plane including the top surface of the front connector pad 378, and may include a flat bottom surface that contacts the top surface of the die attachment film 932. The first molding compound matrix 397 provides mechanical support and environmental protection for the semiconductor dies 300 containing TSVs. The first molding compound matrix 397 can contact the sidewalls of the front connector pad 378 and the horizontal top surface of the first front dielectric capping layer 370.

[0067] Referring to FIG2H, a first dielectric bonding layer 460 having a first bonding-level metal interconnect structure 480 formed therein may be formed on the top surface of the first molding compound matrix 397. The first dielectric bonding layer 460 includes at least one interlayer dielectric layer, which may include at least one via-level dielectric layer and / or at least one line-level dielectric layer. The first dielectric bonding layer 460 may include, and / or may be substantially composed of at least one inorganic dielectric material, such as undoped silicate glass, doped silicate glass, organic silicate glass, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, dielectric metal oxide, etc. The first bonding-level metal interconnect structure 480 may include a metal via structure, a metal wire structure, a metal pad structure, etc.

[0068] A first bump structure 498 may be formed on the top layer of the first dielectric bonding layer 460. Each first bump structure 498 may be formed on a respective back-side metal interconnect structure 340 covering the first molding compound matrix 397. In one embodiment, the first bump structure 498 may include a via portion formed within and laterally surrounded by the first dielectric bonding layer 460. Furthermore, the first bump structure 498 may include a pillar structure or pad structure covering the top surface of the first dielectric bonding layer 460. In one embodiment, the first bump structure 498 may include a wafer interconnect (C2) bonding structure, such as a microbump structure.

[0069] Referring to FIG2I, the component semiconductor die 100 may be attached to the first bump structure 498 using an array of solder portions 493. Each component semiconductor die 100 may include active components, such as field-effect transistors, and may optionally include passive components, such as capacitors, resistors, inductors, etc. Each component semiconductor die 100 may include a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, embedded volatile memory, and / or embedded non-volatile memory. In a plan view along the vertical direction, each component semiconductor die 100 may have a smaller area than the semiconductor die 300 below containing a substrate through-via (TSV).

[0070] In one embodiment, each element semiconductor die 100 may include a semiconductor substrate 110, a respective set of second semiconductor elements 120 (which may be referred to as additional semiconductor elements), and a respective set of second dielectric material layers 150 having a second metal interconnect structure 160 formed therein. In one embodiment, each element semiconductor die 100 may include a respective connection-level dielectric layer 180 having a respective set of connection metal pads 188 formed therein, and a respective bump-level dielectric layer 190 having a respective set of second bump structures 198 formed therein. The second bump structures 198 of the element semiconductor die 100 may be bonded to the first bump structure 498 through an array of solder portions 493.

[0071] An underfill material portion 495 may be formed around each set of solder portions 493 covering the semiconductor die 300 containing a substrate through-via (TSV). In one embodiment, each underfill material portion 495 may laterally surround all solder portions 493 that overlap in area with the semiconductor die 300 containing a substrate through-via (TSV) below it.

[0072] An underfill material portion 495 may be formed around each set of solder portions 493 covering the semiconductor die 300 containing a substrate through-hole (TSV). In one embodiment, the underfill material portion 495 may laterally surround all solder portions 493 that overlap in area with their respective underlying semiconductor die 300 containing a substrate through-hole (TSV). The underfill material provides structural support and reduces mechanical stress that may occur due to thermal cycling or mechanical shock. The material absorbs stress between the element semiconductor die 100 and the semiconductor die 300 containing a substrate through-hole (TSV). The underfill material may be applied using capillary underfill, molded underfill, or printed underfill techniques.

[0073] Capillary underfill relies on capillary action to distribute material between solder bumps, while molding and printing underfill techniques involve direct application. Underfill materials typically consist of epoxy resin with silica or other fillers. Filler content can be up to 85% by weight, which improves thermal conductivity and mechanical strength, and reduces shrinkage and warpage during the curing process. After application, the underfill material cures at a temperature below the solder reflow temperature to solidify and protect the underlying structure. Underfill materials reduce structural damage to the solder portion 493 in subsequent process steps and improve the overall durability of the semiconductor package.

[0074] Referring to FIG2J, a second molding compound matrix 497 may be formed around the semiconductor die 100 and the underfill material portion 495, and directly on the first dielectric bonding layer 460. The second molding compound matrix 497 may include an epoxy molding compound (EMC). The EMC can be cured in a temperature range of 125 to 150 degrees Celsius, thereby maintaining the integrity of the component during the molding process. After curing, excess molding compound above the semiconductor die 100 can be removed by performing a planarization process. Specifically, the cured EMC material portion covering a horizontal plane, including the topmost surface of the semiconductor die 100, can be removed by performing a chemical mechanical polishing (CMP) process. The remaining portion of the cured EMC material constitutes the second molding compound matrix 497.

[0075] The second molding compound matrix 497 can be embedded in a two-dimensional array of the device semiconductor die 100, and may have a top surface located in a horizontal plane including the topmost surface of the device semiconductor die 100, and may include a flat bottom surface that contacts the top surface of the first dielectric bonding layer 460. The second molding compound matrix 497 provides mechanical support and environmental protection for the device semiconductor die 100. Typically, the second molding compound matrix 497 is vertically spaced from the first molding compound matrix 397 by the first dielectric bonding layer 460 and does not contact the first molding compound matrix 397. The second molding compound matrix 497 may be formed directly around the device semiconductor die 100 on the first dielectric bonding layer 460.

[0076] Referring to Figure 2K, an additional carrier wafer 903 may be attached to the device semiconductor die 100 using an additional die attachment film 933. The additional carrier wafer 903 may be any carrier wafer known to those skilled in the art. For example, the additional carrier wafer 903 may include a glass substrate having a circular or rectangular shape in a plan view. The additional die attachment film 933 may include an ultraviolet-degradable adhesive material. The additional die attachment film 933 may be attached to the top surface of the device semiconductor die 100 and the additional carrier wafer 903.

[0077] Subsequently, the carrier wafer 902 and the die-attachment film 932 can be removed. For example, an ultraviolet irradiation process can be performed to irradiate the die-attachment film 932 through the carrier wafer 902. The die-attachment film 932 can be deactivated by ultraviolet radiation.

[0078] Referring to Figure 2L, a chemical mechanical polishing process can be performed to polish the semiconductor carrier substrate 924, the die-attachment film 934, and a portion of the first molding compound matrix 397 that is further away from the additional carrier wafer 903 than the horizontal plane including the interface between the first back-side metal interconnect structure 340 and the die-attachment film 934. The distal horizontal surface of the first back-side metal interconnect structure 340 and the back horizontal surface of the first back-side dielectric material layer 330 can be solidly exposed. The distal horizontal surface of the first back-side metal interconnect structure 340 and the back horizontal surface of the first back-side dielectric material layer 330 can be formed in the same horizontal plane as the polishing horizontal surface of the first molding compound matrix 397.

[0079] Referring to Figure 2M, a second dielectric bonding layer 560 having a second bonding-level metal interconnect structure 580 formed therein can be formed on the front connecting pad 378. The second dielectric bonding layer 560 can be formed directly on the first molding compound matrix 397. The second dielectric bonding layer 560 includes at least one interlayer dielectric (ILD) layer, which may include at least one via-level dielectric layer and / or at least one line-level dielectric layer. The second dielectric bonding layer 560 may include, and / or may be substantially composed of at least one inorganic dielectric material, such as undoped silicate glass, doped silicate glass, organic silicate glass, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, dielectric metal oxide, etc. The second bonding-level metal interconnect structure 580 may include a metal via structure, a metal wire structure, a metal pad structure, etc.

[0080] Metal bump structures 598 may be formed on the top layer of the second dielectric bonding layer 560. Each metal bump structure 598 may be formed on a respective second bonding level metal interconnect structure 580 that covers and contacts the first molding compound matrix 397. In one embodiment, the metal bump structure 598 may include via portions formed within and laterally surrounded by the first dielectric bonding layer 460. Furthermore, the metal bump structure 598 may include pad structures covering the top surface of the second dielectric bonding layer 560. In one embodiment, the metal bump structure 598 may include controlled collapse wafer interconnect (C4) pads. Each metal bump structure 598 may be formed directly on a respective second bonding level metal interconnect structure 580 and above the second dielectric bonding layer 560. Solder balls 593 may be attached to the metal bump structures 598.

[0081] Referring to FIG2N, the additional carrier wafer 903 and the additional die-attachment film 933 can be removed. For example, an ultraviolet irradiation process can be performed to irradiate the additional die-attachment film 933 with an ultraviolet beam through the additional carrier wafer 903. The additional die-attachment film 933 can be deactivated by ultraviolet radiation. A suitable cleaning process can be performed to clean the solid exposed surface of the device semiconductor die 100 and the horizontal surface of the second molding compound matrix 497.

[0082] A dicing process can be performed to dic (single-compute) a reconstructed grain comprising a two-dimensional array of semiconductor dies 300 with substrate through-vessels (TSVs), a first molding compound matrix 397, a first dielectric bonding layer 460, a two-dimensional array of groups of element semiconductor dies 100, a two-dimensional array of underfill material portions 495, and a second molding compound matrix 497. Generally, the reconstructed grain includes at least a dielectric bonding layer 560, a first molding compound matrix 397, and a first dielectric bonding layer 460. The diced portions of the reconstructed grain constitute a composite grain 800. Each composite grain 800 includes a diced portion of semiconductor dies 300 with substrate through-vessels (TSVs), a diced portion of the second dielectric bonding layer 560, a diced portion of the first molding compound matrix 397, a diced portion of the first dielectric bonding layer 460, and a diced portion of the second molding compound matrix 497.

[0083] The example structure shown in Figure 1N includes a semiconductor package comprising: a semiconductor die 300 with a substrate through-hole (TSV) including a first semiconductor substrate 310 having a substrate through-hole (TSV) structure 304 formed therein, a first semiconductor element 320 and a front-side connector pad 378 located on the front side of the first semiconductor substrate 310, and a first back-side metal interconnect structure 340 located on the back side of the first semiconductor substrate 310; a first molding compound matrix 397 laterally surrounding the semiconductor die 300 with the substrate through-hole (TSV); a first dielectric bonding layer 460 located on the front-side connector pad 378; and a first bump structure 498 located on the first dielectric bonding layer 460.

[0084] In one embodiment, the first molded compound matrix 397 may contact the sidewall of the front connector pad 378. In one embodiment, the semiconductor die 300 with a substrate through-hole (TSV) includes a first metal interconnect structure 360 ​​formed in a first dielectric material layer 350 and interposed between the first semiconductor substrate 310 and the front connector pad 378. In one embodiment, the semiconductor die 300 with a substrate through-hole (TSV) includes a front dielectric capping layer 370 that laterally surrounds the through-hole portion of the front connector pad 378 and has a horizontal surface in contact with the first molded compound matrix 397.

[0085] In one embodiment, the sidewalls of the first dielectric bonding layer 460 are perpendicularly aligned with the outer sidewalls of the first molding compound matrix 397. In one embodiment, the semiconductor package includes a second dielectric bonding layer 560 having a bonding-level metal interconnect structure 580 formed therein and contacting a first back-side metal interconnect structure 340. In one embodiment, the second dielectric bonding layer 560 is in contact with the first molding compound matrix 397. In one embodiment, the sidewalls of the second dielectric bonding layer 560 are perpendicularly aligned with the outer sidewalls of the first molding compound matrix 397.

[0086] In one embodiment, the semiconductor package includes a device semiconductor die 100 attached to a first bump structure 498 through an array of solder portions 493. In one embodiment, the semiconductor package includes: a bottom filler material portion 495 laterally surrounding the array of solder portions 493; and a second molding compound matrix 497 laterally surrounding the device semiconductor die 100 and the bottom filler material portion 495. In one embodiment, the sidewalls of a first dielectric bonding layer 460 are perpendicularly coincident with the outer sidewalls of the second molding compound matrix 497. In one embodiment, the second molding compound matrix 497 is perpendicularly spaced from the first molding compound matrix 397 through the first dielectric bonding layer 460. In one embodiment, the first dielectric bonding layer 460 has a first bonding level metal interconnect structure 480 formed therein. The first bump structure 498 contacts a subset of the first bonding level metal interconnect structure 480. In one embodiment, a first semiconductor element 320 includes a first field-effect transistor; and each of the device semiconductor dies 100 includes a set of additional field-effect transistors.

[0087] Referring to FIG20, a second flowchart is provided, which includes a subset of process steps for forming a semiconductor structure.

[0088] Referring to step 1210 and Figures 2A to 2E, a semiconductor component (300, 934, 924) is provided, which includes a semiconductor die 300 with a substrate through-vessel (TSV), a die attachment film 934, and a semiconductor carrier substrate 924. The semiconductor die 300 with a substrate through-vessel (TSV) includes a first semiconductor substrate 310 having a substrate through-vessel (TSV) structure 304 formed therein, a first semiconductor element 320, a front-side connection pad 378 located on the front side of the first semiconductor substrate 310, and a first back-side metal interconnect structure 340 located on the back side of the first semiconductor substrate 310.

[0089] Referring to step 1220 and Figure 2F, the semiconductor carrier substrate 924 of the semiconductor components (300, 934, 924) can be attached to the carrier wafer 902 using a die attachment film 932.

[0090] Referring to steps 1230 and Figures 2G to 2N, a first molding compound matrix 397 can be formed around the semiconductor components (300, 934, 924).

[0091] Figures 3A to 3N are successive vertical cross-sectional views of the structure of the third embodiment during a series of process steps according to an embodiment of the present disclosure.

[0092] Referring to FIG3A, a device wafer 300W is described, which includes a first semiconductor substrate 310 and structural elements formed therein and thereon. The device wafer 300W may be the same as the device wafer 300W illustrated in FIG1A.

[0093] Referring to FIG3B, the device wafer 300W may be attached to the processing wafer 701, for example, using a die attachment film 731. The processing wafer 701 may be any wafer that can be used to provide mechanical support during subsequent processing of the device wafer 300W. In one embodiment, the processing wafer 701 may include a glass carrier wafer having the same lateral dimensions as the device wafer 300W.

[0094] Referring to Figure 3C, the device wafer 300W can be thinned from the back side. The back side of the first semiconductor substrate 310 can be removed by grinding, polishing, anisotropic etching processes and / or isotropic etching processes. The back surface of the substrate through-hole (TSV) structure 304 can be physically exposed during the thinning of the first semiconductor substrate 310. The substrate through-hole (TSV) structure 304 extends vertically through the thinned first semiconductor substrate 310.

[0095] The back surface of the first semiconductor substrate 310 may be further thinned by performing an etching process (which may include anisotropic etching or isotropic etching). An insulating material, such as silicon oxide, may be deposited on the recessed back surface of the first semiconductor substrate 310. Excess portions of the insulating material above the horizontal plane including the back surface of the substrate through-hole (TSV) structure 304 may be removed by performing a planarization process (such as a chemical mechanical polishing process). The remaining portion of the insulating material constitutes the back insulating layer 316. The physically exposed back surface of the substrate through-hole (TSV) structure 304 may be coplanar with the physically exposed horizontal surface of the back insulating layer 316.

[0096] At least one metal layer may be deposited on the back surface of the substrate through-via (TSV) structure 304, and may subsequently be patterned to form a first back-side metal interconnect structure 340. The first back-side metal interconnect structure 340 may include metal pad structures, metal line structures, and / or metal pillar structures. The device wafer 300W includes an array of semiconductor dies 300 containing substrate through-vias (TSVs).

[0097] Referring to Figure 3D, the semiconductor carrier wafer 924W can be attached to the device wafer 300W using a continuous die attachment film 934W. For example, the continuous die attachment film 934W may include a thermally degradable adhesive material. The continuous die attachment film 934W provides adhesion between the device wafer 300W and the semiconductor carrier wafer 924W. Optionally, the semiconductor carrier wafer 924W can be thinned to a desired target thickness before or after bonding with the device wafer 300W. The thickness of the semiconductor carrier wafer 924W can range from 60 micrometers to 1 millimeter, for example from 150 micrometers to 600 micrometers, although smaller and larger thicknesses are also possible. This forms a wafer-level bonding assembly (300W, 934W, 924W) consisting of the device wafer 300W, the continuous die attachment film 934W, and the semiconductor carrier wafer 924W.

[0098] Referring to FIG3E, the die adhesion film 731 can be deactivated to facilitate the separation of the processed wafer 701 from the wafer-level bonding components (300W, 934W, 924W). For example, the die adhesion film 731 may include a UV-degrading material, and the processed wafer 701 may include a transparent wafer such as a glass substrate. In this embodiment, UV radiation can be applied to the die adhesion film by irradiating the processed wafer 701 to disrupt the adhesive properties of the film, making it easier to separate. Once the die adhesion film 731 is deactivated, the processed wafer 701 is removed, leaving the device wafer 300W firmly bonded to the semiconductor carrier wafer 924W through the continuous die adhesion film 934W. To prepare the surface for subsequent processing, any residual adhesive layer can be removed through cleaning processes (such as solvent cleaning or plasma etching) to ensure a contaminated interface.

[0099] The wafer-level bonding assemblies (300W, 934W, 924W) can then be diced along a dicing channel. The dicing channel extends along the boundary between adjacent pairs of semiconductor dies 300 containing substrate vias (TSVs). The diced portion of the wafer-level bonding assemblies (300W, 934W, 924W) includes semiconductor assemblies (300, 934, 924). Each semiconductor assembly (300, 934, 924) includes a semiconductor die 300 containing a substrate via (TSV), a die attachment film 934, and a semiconductor carrier substrate 924. The semiconductor die 300 containing a substrate via (TSV) includes a first semiconductor substrate 310 in which a substrate via (TSV) structure 304 is formed, a first semiconductor element 320, a front-side connection pad 378 located on the front side of the first semiconductor substrate 310, and a first back-side metal interconnect structure 340 located on the back side of the first semiconductor substrate 310.

[0100] Referring to Figure 3F, a plurality of semiconductor components (300, 934, 924) provided through the process steps described with reference to Figures 3A to 3E can be attached to a carrier wafer 902 using a die-attach film 932. It should be understood that Figure 3F and subsequent figures only illustrate the area surrounding a single semiconductor component (300, 934, 924). The carrier wafer 902 can be any carrier wafer known in the art. For example, the carrier wafer 902 may include a glass substrate having a circular or rectangular shape in a plan view. The die-attach film 932 may include an ultraviolet-degradable adhesive material. The die-attach film 932 may be attached to the top surface of the carrier wafer 902, and a two-dimensional array of semiconductor components (300, 934, 924) may be attached to the die-attach film 932. The horizontal surfaces of the front bonding pad 378 and the second front dielectric capping layer 372 may contact the die-attach film 932. In one embodiment, the two-dimensional array of semiconductor components (300, 934, 924) can be arranged as a two-dimensional rectangular array of semiconductor components (300, 934, 924). A gap 380 may exist between each pair of adjacent semiconductor components (300, 934, 924).

[0101] Referring to Figure 3G, a first molding compound matrix 397 can be formed around a two-dimensional array of semiconductor dies 300 containing substrate through-vessels (TSVs). The first molding compound matrix 397 can also fill gaps 380 appearing between adjacent semiconductor dies 300 in the two-dimensional rectangular array of semiconductor components (300, 934, 924). See, for example, Figure 3F. The first molding compound matrix 397 may include an epoxy molding compound (EMC). Typically, EMC contains epoxy resin, hardener, silica filler, and other additives to enhance its performance. High filler content (e.g., 85% by weight) can be used to reduce mold shrinkage, minimize warpage, and improve flowability in the encapsulation process. The filler distribution in the molding process suppresses flow marks, thereby facilitating the smooth application of EMC. EMC can be cured in a temperature range of 125°C to 150°C, thereby maintaining the integrity of the component during the molding process.

[0102] After curing, excess molding compound can be removed from above the semiconductor carrier substrate 924 by performing a planarization process (e.g., CMP process). Specifically, the cured EMC material portion covering the horizontal plane including the back side of the semiconductor carrier substrate 924 can be removed by performing a chemical mechanical polishing process. The remaining portion of the cured EMC material constitutes the first molding compound matrix 397.

[0103] A first molding compound matrix 397 can be embedded in a two-dimensional array of semiconductor dies 300 containing substrate through-vessels (TSVs), and may have a top surface located in a horizontal plane including the back side of a semiconductor carrier substrate 924, and may include a planar bottom surface that contacts the top surface of the die attachment film 932. The first molding compound matrix 397 provides mechanical support and environmental protection for the semiconductor dies 300 containing TSVs. The first molding compound matrix 397 can contact the sidewalls of each semiconductor die 300 containing a TSV, each die attachment film 934, and each semiconductor carrier substrate 924.

[0104] Referring to FIG3H, a chemical mechanical polishing (CMP) process can be performed to polish the semiconductor carrier substrate 924, the die attachment film 934, and a portion of the first molding compound matrix 397 that is further away from the carrier wafer 902 than the horizontal plane including the interface between the first back-side metal interconnect structure 340 and the die attachment film 934. The distal horizontal surface of the first back-side metal interconnect structure 340 and the back horizontal surface of the first back-side dielectric material layer 330 can be physically exposed. The distal horizontal surface of the first back-side metal interconnect structure 340 and the back horizontal surface of the first back-side dielectric material layer 330 can be formed in the same horizontal plane as the polishing horizontal surface of the first molding compound matrix 397.

[0105] Referring to FIG3I, a first dielectric bonding layer 460 having a first bonding-level metal interconnect structure 480 formed therein can be formed on the top surface of the first molding compound matrix 397. The first dielectric bonding layer 460 includes at least one interlayer dielectric (ILD) layer, which may include at least one via-level dielectric layer and / or at least one line-level dielectric layer. The first dielectric bonding layer 460 may comprise, and / or may be substantially composed of at least one inorganic dielectric material, such as undoped silicate glass, doped silicate glass, organic silicate glass, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, dielectric metal oxide, etc. The first bonding-level metal interconnect structure 480 may include a metal via structure, a metal wire structure, a metal pad structure, etc.

[0106] A first bump structure 498 may be formed on the top layer of the first dielectric bonding layer 460. Each first bump structure 498 may be formed on a respective back-side metal interconnect structure 340 covering the first molding compound matrix 397. In one embodiment, the first bump structure 498 may include a via portion formed within and laterally surrounded by the first dielectric bonding layer 460. Furthermore, the first bump structure 498 may include a pillar structure or pad structure covering the top surface of the first dielectric bonding layer 460. In one embodiment, the first bump structure 498 may include a wafer interconnect (C2) bonding structure, such as a microbump structure.

[0107] Referring to FIG3J, the component semiconductor die 100 may be attached to the first bump structure 498 using an array of solder portions 493. Each component semiconductor die 100 may include active components such as field-effect transistors and may optionally include passive components such as capacitors, resistors, inductors, etc. Each component semiconductor die 100 may include a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a digital signal processor (DSP), embedded volatile memory, and / or embedded non-volatile memory. In a plan view along the vertical direction, each component semiconductor die 100 may have a smaller area than the semiconductor die 300 below containing a substrate through-via (TSV).

[0108] In one embodiment, each element semiconductor die 100 may include a semiconductor substrate 110, a respective set of second semiconductor elements 120 (which may be referred to as additional semiconductor elements), and a respective set of second dielectric material layers 150 having second metal interconnect structures 160 formed therein. In one embodiment, each element semiconductor die 100 may include a respective interconnect-level dielectric layer 180 in which a respective set of interconnect metal pads 188 are formed, and a respective bump-level dielectric layer 190 in which a respective set of second bump structures 198 are formed. The second bump structures 198 of the element semiconductor die 100 may be bonded to the first bump structure 498 through an array of solder portions 493.

[0109] An underfill material portion 495 may be formed around each set of solder portions 493 covering the semiconductor die 300 containing a substrate through-via (TSV). In one embodiment, each underfill material portion 495 may laterally surround all solder portions 493 that overlap in area with the semiconductor die 300 containing a substrate through-via (TSV) below it.

[0110] An underfill material portion 495 may be formed around each set of solder portions 493 covering the semiconductor die 300 containing a substrate through-hole (TSV). In one embodiment, the underfill material portion 495 may laterally surround all solder portions 493 that overlap in area with their respective underlying semiconductor die 300 containing a substrate through-hole (TSV). The underfill material provides structural support and reduces mechanical stress that may occur due to thermal cycling or mechanical shock. The material absorbs stress between the element semiconductor die 100 and the semiconductor die 300 containing a substrate through-hole (TSV). The underfill material may be applied using capillary underfill, molded underfill, or printed underfill techniques.

[0111] Capillary underfill relies on capillary action to distribute material between solder bumps, while molding and printing underfill techniques involve direct application. Underfill materials typically consist of epoxy resin with silica or other fillers. Filler content can be up to 85% (by weight), which improves thermal conductivity and mechanical strength, and reduces shrinkage and warpage during the curing process. After application, the underfill material cures below the solder reflow temperature to solidify and protect the underlying structure. Underfill materials reduce structural damage to the solder portion 493 in subsequent process steps and improve the overall durability of the semiconductor package.

[0112] Referring to Figure 3K, a second molding compound matrix 497 may be formed around the semiconductor die 100 and the underfill material portion 495, and directly on the first dielectric bonding layer 460. The second molding compound matrix 497 may include an epoxy molding compound (EMC). The EMC can be cured in a temperature range of 125 to 150 degrees Celsius, thereby maintaining the integrity of the component during the molding process. After curing, excess molding compound above the semiconductor die 100 can be removed by performing a planarization process. Specifically, the cured EMC material portion covering the horizontal plane including the topmost surface of the semiconductor die 100 can be removed by performing a chemical mechanical polishing process. The remaining portion of the cured EMC material constitutes the second molding compound matrix 497.

[0113] The second molding compound matrix 497 can be embedded in a two-dimensional array of the semiconductor die 100, and may have a top surface located in a horizontal plane including the topmost surface of the semiconductor die 100, and may include a flat bottom surface that contacts the top surface of the first dielectric bonding layer 460. The second molding compound matrix 497 provides mechanical support and environmental protection for the semiconductor die 100. Generally, the second molding compound matrix 497 is perpendicularly spaced from the first molding compound matrix 397 through the first dielectric bonding layer 460 and does not contact the first molding compound matrix 397. The second molding compound matrix 497 may be formed directly on the first dielectric bonding layer 460 around the semiconductor die 100.

[0114] Referring to Figure 3L, an additional carrier wafer 903 may be attached to the device semiconductor die 100 using an additional die adhesion film 933. The additional carrier wafer 903 may be any carrier wafer known to those skilled in the art. For example, the additional carrier wafer 903 may include a glass substrate having a circular or rectangular shape in a plan view. The additional die adhesion film 933 may include an ultraviolet-degradable adhesive material. The additional die adhesion film 933 may be attached to the top surface of the device semiconductor die 100 and the additional carrier wafer 903.

[0115] Subsequently, the carrier wafer 902 and the die attachment film 932 can be removed. For example, an ultraviolet irradiation process can be performed to irradiate the die attachment film 932 with an ultraviolet beam through the carrier wafer 902. The die attachment film 932 can be deactivated by ultraviolet radiation.

[0116] Referring to FIG3M, a metal bump structure 598 may be formed on the second front dielectric capping layer 372. Each metal bump structure 598 may be formed on a respective front connection pad 378. In one embodiment, the metal bump structure 598 may include a pad structure contacting the planar surface of the second front dielectric capping layer 372. In one embodiment, the metal bump structure 598 may include a controlled collapse wafer connection (C4) pad. Each metal bump structure 598 may be formed directly on its respective front connection pad 378 and above the second front dielectric capping layer 372. Solder balls 593 may be attached to the metal bump structure 598.

[0117] Referring to Figure 3N, the additional carrier wafer 903 and the additional die-attachment film 933 can be removed. For example, an ultraviolet irradiation process can be performed to irradiate the additional die-attachment film 933 with an ultraviolet beam through the additional carrier wafer 903. The additional die-attachment film 933 can be deactivated by ultraviolet radiation. A suitable cleaning process can be performed to clean the physically exposed surfaces of the device semiconductor die 100 and the horizontal surfaces of the second molding compound matrix 497.

[0118] A dicing process can be performed to dic (singleify) reconstructed dies, including a two-dimensional array of semiconductor dies 300 containing substrate through-vessels (TSVs), a first molding compound matrix 397, a first dielectric bonding layer 460, a two-dimensional array of groups of device semiconductor dies 100, a two-dimensional array of underfill material portions 495, and a second molding compound matrix 497. Generally, the reconstructed die includes at least a dielectric bonding layer 560, a first molding compound matrix 397, and a first dielectric bonding layer 460. The diced portions of the reconstructed die include composite dies 800. Each composite die 800 includes a diced portion of the semiconductor dies 300 containing substrate through-vessels (TSVs), a diced portion of the first dielectric bonding layer 460, a diced portion of the first molding compound matrix 397, and a diced portion of the second molding compound matrix 497.

[0119] The example structure illustrated in Figure 3N includes a semiconductor package comprising: a semiconductor die 300 with a substrate through-hole (TSV), including a first semiconductor substrate 310 having a substrate through-hole structure 304 formed therein, a first semiconductor element 320 and a front-side connector pad 378 located on the front side of the first semiconductor substrate 310, and a first back-side metal interconnect structure 340 located on the back side of the first semiconductor substrate 310; a first molding compound matrix 397 laterally surrounding the semiconductor die 300 with the substrate through-hole (TSV); a first dielectric bonding layer 460 located on the first back-side metal interconnect structure 340; and a first bump structure 498 located on the first dielectric bonding layer 460.

[0120] In one embodiment, the first molded compound matrix 397 contacts the frame-like horizontal surface of the first dielectric bonding layer 460. In one embodiment, the semiconductor die 300 containing a substrate through-vessel (TSV) includes a first back-side dielectric layer 330, in which a first back-side metal interconnect structure 340 is formed, and includes sidewalls that contact the inner sidewalls of the first molded compound matrix 397. In one embodiment, the semiconductor die 300 containing a substrate through-vessel (TSV) includes a first back-side metal interconnect structure 340 formed within the first back-side dielectric layer 330. In one embodiment, all outer sidewalls of the first back-side dielectric layer 330 and all outer sidewalls of at least one front dielectric capping layer (370, 372) contact the inner sidewalls of the first molded compound matrix 397.

[0121] In one embodiment, the sidewalls of the first dielectric bonding layer 460 are perpendicularly aligned with the outer sidewalls of the first molding compound matrix 397. In another embodiment, the semiconductor package includes metal bump structures 598 that contact a respective front-side connection pad 378. The sidewalls of the first dielectric bonding layer 460 are perpendicularly aligned with the outer sidewalls of the first molding compound matrix 397.

[0122] In one embodiment, the semiconductor package includes a component semiconductor die 100 attached to a first bump structure 498 through an array of solder material portions 493. In another embodiment, the semiconductor package includes: an underfill material portion 495 laterally surrounding the array of solder material portions 493; and a second molding compound matrix 497 laterally surrounding the component semiconductor die 100 and the underfill material portion 495. In one embodiment, the second molding compound matrix 497 is perpendicularly spaced from the first molding compound matrix 397 through a first dielectric bonding layer 460. The sidewalls of the first dielectric bonding layer 460 are perpendicularly coincident with the outer sidewalls of the second molding compound matrix 497.

[0123] In one embodiment, the first dielectric bonding layer 460 may have a first bonding level metal interconnect structure 480 formed therein, wherein the first bump structure 498 contacts a subset of the first bonding level metal interconnect structure 480. In one embodiment, the first semiconductor element 320 includes a first field-effect transistor; and each of the element semiconductor dies 100 includes a set of additional field-effect transistors.

[0124] Referring to Figure 3O, a third flowchart is shown, which includes a subset of process steps for forming a semiconductor structure.

[0125] Referring to step 1310 and Figures 3A to 3E, a semiconductor assembly (300, 934, 924) is provided. The semiconductor assembly (300, 934, 924) includes a semiconductor die 300 with a substrate through-vessel (TSV), a die attachment film 934, and a semiconductor carrier substrate 924. The semiconductor die 300 with a substrate through-vessel (TSV) includes a first semiconductor substrate 310 having a substrate through-vessel (TSV) structure 304 formed therein, a first semiconductor element 320, a front-side connection pad 378 located on the front side of the first semiconductor substrate 310, and a first back-side metal interconnect structure 340 located on the back side of the first semiconductor substrate 310.

[0126] Referring to step 1320 and Figure 3F, the front connection pad 378 of the semiconductor components (300, 934, 924) can be attached to the carrier wafer 902 using a die attachment film 932.

[0127] Referring to step 1330 and Figures 3G to 3N, the semiconductor carrier substrate 924 and the grain attachment film 934 can be removed.

[0128] Figures 4A to 4M are sequential vertical cross-sectional views of the structure of the fourth embodiment according to an embodiment of the present disclosure during a series of process steps.

[0129] Referring to FIG4A, a device wafer 300W is illustrated, which includes a first semiconductor substrate 310 and structural elements formed therein and thereon. The device wafer 300W may be derived from the device wafer 300W shown in FIG1A, omitting the formation of at least one front dielectric capping layer (370, 372) and front interconnect pad 378. Therefore, the top surface of the first dielectric material layer 350 and the top surface of the first metal interconnect structure 360 ​​may actually be exposed.

[0130] Referring to Figure 4B, the semiconductor carrier wafer 924W can be attached to the device wafer 300W using a continuous die attachment film 934W. For example, the continuous die attachment film 934W may include a thermally degradable adhesive material. The continuous die attachment film 934W provides adhesion between the device wafer 300W and the semiconductor carrier wafer 924W. Optionally, the semiconductor carrier wafer 924W can be thinned to a desired target thickness before or after bonding with the device wafer 300W. The thickness of the semiconductor carrier wafer 924W can range from 60 micrometers to 1 millimeter, for example from 150 micrometers to 600 micrometers, although smaller and larger thicknesses are also possible. A wafer-level bonding assembly (300W, 934W, 924W) is formed by the device wafer 300W, the continuous die attachment film 934W, and the semiconductor carrier wafer 924W.

[0131] Referring to Figure 4C, the device wafer 300W can be thinned from the back side. The back side of the first semiconductor substrate 310 can be removed by grinding, polishing, anisotropic etching processes and / or isotropic etching processes. The back surface of the substrate through-hole (TSV) structure 304 can be actually exposed during the thinning of the first semiconductor substrate 310. The substrate through-hole (TSV) structure 304 passes perpendicularly through the thinned first semiconductor substrate 310.

[0132] The back surface of the first semiconductor substrate 310 may be further thinned by performing an etching process (which may include anisotropic etching or isotropic etching). An insulating material, such as silicon oxide, may be deposited on the recessed back surface of the first semiconductor substrate 310. Excess portions of the insulating material above the horizontal plane including the back surface of the substrate through-hole (TSV) structure 304 may be removed by performing a planarization process, such as chemical mechanical polishing (CMP). The remaining portion of the insulating material constitutes the back insulating layer 316. The actual exposed back surface of the substrate through-hole (TSV) structure 304 may be coplanar with the actual exposed horizontal surface of the back insulating layer 316.

[0133] At least one metal layer may be deposited on the back surface of the substrate through-via (TSV) structure 304, and may subsequently be patterned to form a first back-side metal interconnect structure 340. The first back-side metal interconnect structure 340 may include metal pad structures, metal line structures, and / or metal pillar structures. The device wafer 300W includes an array of semiconductor dies 300 containing substrate through-vias (TSVs).

[0134] Referring to FIG4D, the wafer-level bonding assemblies (300W, 934W, 924W) can subsequently be diced along a dicing channel. The dicing channel extends along the boundary between adjacent pairs of semiconductor dies 300 containing substrate vias (TSVs). The diced portion of the wafer-level bonding assemblies (300W, 934W, 924W) includes semiconductor assemblies (300, 934, 924). Each semiconductor assembly (300, 934, 924) includes a semiconductor die 300 containing a substrate via (TSV), a die attachment film 934, and a semiconductor carrier substrate 924. The semiconductor die 300 containing a substrate via (TSV) includes a first semiconductor substrate 310 having a substrate via (TSV) structure 304 formed therein, a first semiconductor element 320, a front-side connection pad 378 located on the front side of the first semiconductor substrate 310, and a first back-side metal interconnect structure 340 located on the back side of the first semiconductor substrate 310.

[0135] Referring to Figure 4E, multiple semiconductor components (300, 934, 924) provided through the process steps described with reference to Figures 3A to 3E can be attached to a carrier wafer 902 using a die-attachment film 932. It should be understood that Figure 4D and subsequent figures only illustrate the area surrounding a single semiconductor component (300, 934, 924). The carrier wafer 902 can be any carrier wafer known to those skilled in the art. For example, the carrier wafer 902 may include a glass substrate having a circular or rectangular shape in a plan view. The die-attachment film 932 may include an ultraviolet-degradable adhesive material. The die-attachment film 932 may be attached to the top surface of the carrier wafer 902, and a two-dimensional array of semiconductor components (300, 934, 924) may be attached to the die-attachment film 932. The horizontal surfaces of the first back-side metal interconnect structure 340 and the first back-side dielectric material layer 330 may contact the die-attachment film 932. In one embodiment, the two-dimensional array of semiconductor components (300, 934, 924) can be arranged as a two-dimensional rectangular array of semiconductor components (300, 934, 924). A gap 380 may exist between each pair of adjacent semiconductor components (300, 934, 924).

[0136] Referring to Figure 4F, a first molding compound matrix 397 may be formed around a two-dimensional array of semiconductor dies 300 containing substrate through-vessels (TSVs). The first molding compound matrix 397 may also fill gaps 380 appearing between adjacent semiconductor dies 300 in a two-dimensional rectangular array of semiconductor components (300, 934, 924). See, for example, Figure 4E. The first molding compound matrix 397 may include an epoxy molding compound (EMC). Typically, EMC contains epoxy resin, a hardener, silica filler, and other additives to enhance its performance. High filler content, such as 85% by weight, may be used to reduce mold shrinkage, minimize warpage, and improve flowability during the encapsulation process. The filler is distributed throughout the molding process to suppress flow marks, thereby facilitating the smooth application of the EMC. The EMC can be cured in a temperature range of 125°C to 150°C, thereby maintaining the integrity of the component during the molding process.

[0137] After curing, excess molding compound on the semiconductor carrier substrate 924 can be removed by performing a planarization process (e.g., CMP process). Specifically, the cured EMC material covering the horizontal surface including the back side of the semiconductor carrier substrate 924 can be removed by performing a chemical mechanical polishing process. The remaining portion of the cured EMC material constitutes the first molding compound matrix 397.

[0138] A first molding compound matrix 397 can be embedded in a two-dimensional array of semiconductor dies 300 containing substrate through-vessels (TSVs), and may have a top surface located in a horizontal plane including the back side of a semiconductor carrier substrate 924, and may include a planar bottom surface that contacts the top surface of the die attachment film 932. The first molding compound matrix 397 provides mechanical support and environmental protection for the semiconductor dies 300 containing substrate through-vessels (TSVs). The first molding compound matrix 397 can contact the sidewalls of each semiconductor die 300 containing a substrate through-vessel (TSV), each die attachment film 934, and each semiconductor carrier substrate 924.

[0139] Referring to Figure 4G, a chemical mechanical polishing (CMP) process can be performed to polish the semiconductor carrier substrate 924, the die-attachment film 934, and a portion of the first molding compound matrix 397 that is further away from the carrier wafer 902 than the horizontal plane including the interface between the first back-side metal interconnect structure 340 and the die-attachment film 934. The distal horizontal surface of the first back-side metal interconnect structure 340 and the back horizontal surface of the first back-side dielectric material layer 330 can be physically exposed. The distal horizontal surface of the first back-side metal interconnect structure 340 and the back horizontal surface of the first back-side dielectric material layer 330 can be formed in the same horizontal plane as the polishing horizontal surface of the first molding compound matrix 397.

[0140] Referring to FIG4H, a first dielectric bonding layer 460 having a first bonding-level metal interconnect structure 480 formed therein can be formed on the top surface of the first molding compound matrix 397. The first dielectric bonding layer 460 includes at least one interlayer dielectric (ILD) layer, which may include at least one via-level dielectric layer and / or at least one line-level dielectric layer. The first dielectric bonding layer 460 may include, and / or may be substantially composed of at least one inorganic dielectric material, such as undoped silicate glass, doped silicate glass, organic silicate glass, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, dielectric metal oxide, etc. The first bonding-level metal interconnect structure 480 may include a metal via structure, a metal wire structure, a metal pad structure, etc.

[0141] A first bump structure 498 may be formed on the top layer of the first dielectric bonding layer 460. Each first bump structure 498 may be formed on a respective back-side metal interconnect structure 340 covering the first molding compound matrix 397. In one embodiment, the first bump structure 498 may include a via portion formed within and laterally surrounded by the first dielectric bonding layer 460. Furthermore, the first bump structure 498 may include a pillar structure or pad structure covering the top surface of the first dielectric bonding layer 460. In one embodiment, the first bump structure 498 may include a wafer interconnect (C2) bonding structure, such as a microbump structure.

[0142] Referring to FIG4I, the component semiconductor die 100 may be attached to the first bump structure 498 using an array of solder portions 493. Each component semiconductor die 100 may include active components, such as field-effect transistors, and may optionally include passive components, such as capacitors, resistors, inductors, etc. Each component semiconductor die 100 may include a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a digital signal processor (DSP), embedded volatile memory, and / or embedded non-volatile memory. In a plan view along the vertical direction, each component semiconductor die 100 may have a smaller area than the semiconductor die 300 below containing a substrate through-via (TSV).

[0143] In one embodiment, each element semiconductor die 100 may include a semiconductor substrate 110, a respective set of second semiconductor elements 120 (which may be referred to as additional semiconductor elements), and a respective set of second dielectric material layers 150 having second metal interconnect structures 160 formed therein. In one embodiment, each element semiconductor die 100 may include a respective interconnect-level dielectric layer 180 having a respective set of interconnect metal pads 188 formed therein, and a respective bump-level dielectric layer 190 having a respective set of second bump structures 198 formed therein. The second bump structures 198 of the element semiconductor die 100 may be bonded to the first bump structure 498 through an array of solder portions 493.

[0144] An underfill material portion 495 may be formed around each set of solder portions 493 covering the semiconductor die 300 containing a substrate through-via (TSV). In one embodiment, each underfill material portion 495 may laterally surround all solder portions 493 that overlap in area with the semiconductor die 300 containing a substrate through-via (TSV) below it.

[0145] An underfill material portion 495 may be formed around each set of solder portions 493 covering the semiconductor die 300 containing a substrate through-hole (TSV). In one embodiment, the underfill material portion 495 may laterally surround all solder portions 493 that overlap in area with their respective underlying semiconductor die 300 containing a substrate through-hole (TSV). The underfill material provides structural support and reduces mechanical stress that may occur due to thermal cycling or mechanical shock. The material absorbs stress between the element semiconductor die 100 and the semiconductor die 300 containing a substrate through-hole (TSV). The underfill material may be applied using capillary underfill, molded underfill, or printed underfill techniques.

[0146] Capillary underfill relies on capillary action to distribute material between solder bumps, while molding and printing underfill techniques involve direct application. Underfill materials typically consist of epoxy resin with silica or other fillers. Filler content can be up to 85% by weight, which improves thermal conductivity and mechanical strength, and reduces shrinkage and warpage during curing. After application, the underfill material cures at a temperature below the solder reflow temperature to solidify and protect the underlying structure. Underfill materials reduce structural damage to the solder portion 493 in subsequent process steps and improve the overall durability of the semiconductor package.

[0147] Referring to Figure 4J, a second molding compound matrix 497 may be formed around the semiconductor die 100 and the underfill material portion 495, and directly on the first dielectric bonding layer 460. The second molding compound matrix 497 may include an epoxy molding compound (EMC). The EMC can be cured in a temperature range of 125 to 150 degrees Celsius, thereby maintaining the integrity of the component during the molding process. After curing, excess molding compound above the semiconductor die 100 can be removed by performing a planarization process. Specifically, the cured EMC material portion covering the horizontal plane including the topmost surface of the semiconductor die 100 can be removed by performing a chemical mechanical polishing process. The remaining portion of the cured EMC material constitutes the second molding compound matrix 497.

[0148] The second molding compound matrix 497 can be embedded in a two-dimensional array of the device semiconductor die 100, and may have a top surface located in a horizontal plane including the topmost surface of the device semiconductor die 100, and may include a flat bottom surface that contacts the top surface of the first dielectric bonding layer 460. The second molding compound matrix 497 provides mechanical support and environmental protection for the device semiconductor die 100. Typically, the second molding compound matrix 497 is vertically spaced from the first molding compound matrix 397 by the first dielectric bonding layer 460 and does not contact the first molding compound matrix 397. The second molding compound matrix 497 may be formed directly around the device semiconductor die 100 on the first dielectric bonding layer 460.

[0149] Referring to Figure 4K, an additional carrier wafer 903 may be attached to the device semiconductor die 100 using an additional die adhesion film 933. The additional carrier wafer 903 may be any carrier wafer known to those skilled in the art. For example, the additional carrier wafer 903 may include a glass substrate having a circular or rectangular shape in a plan view. The additional die adhesion film 933 may include an ultraviolet-degradable adhesive material. The additional die adhesion film 933 may be attached to the top surface of the device semiconductor die 100 and the additional carrier wafer 903.

[0150] Subsequently, the carrier wafer 902 and the die attachment film 932 can be removed. For example, an ultraviolet irradiation process can be performed to irradiate the die attachment film 932 with an ultraviolet beam through the carrier wafer 902. The die attachment film 932 can be deactivated by ultraviolet radiation.

[0151] Referring to FIG4L, a second dielectric bonding layer 560 having a second bonding-level metal interconnect structure 580 formed therein can be formed on the first back-side metal interconnect structure 340 and the first back-side dielectric material layer 330. The second dielectric bonding layer 560 can be formed directly on the first molding compound matrix 397. The second dielectric bonding layer 560 includes at least one interlayer dielectric (ILD) layer, which may include at least one via-level dielectric layer and / or at least one line-level dielectric layer. The second dielectric bonding layer 560 may include, and / or may be substantially composed of at least one inorganic dielectric material, such as undoped silicate glass, doped silicate glass, organic silicate glass, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, dielectric metal oxide, etc. The second bonding-level metal interconnect structure 580 may include a metal via structure, a metal wire structure, a metal pad structure, etc.

[0152] Metal bump structures 598 may be formed on the first back-side metal interconnect structure 340 and the second dielectric bonding layer 560. Each of the metal bump structures 598 may be formed on one of the first back-side metal interconnect structures 340. In one embodiment, the metal bump structure 598 may include a via portion formed within and laterally surrounded by the second dielectric bonding layer 560. Furthermore, the metal bump structure 598 may include a pad structure covering the topmost surface of the second dielectric bonding layer 560. In one embodiment, the metal bump structure 598 may include a controlled-collapse wafer interconnect (C4) pad. Each of the metal bump structures 598 may be formed directly on one of the second bonding-level metal interconnect structures 580 and located above the second dielectric bonding layer 560. Solder balls 593 may be attached to the metal bump structures 598.

[0153] Referring to Figure 4M, the additional carrier wafer 903 and the additional die-attachment film 933 can be removed. For example, an ultraviolet irradiation process can be performed to irradiate the additional die-attachment film 933 with an ultraviolet beam through the additional carrier wafer 903. The additional die-attachment film 933 can be deactivated by ultraviolet radiation. A suitable cleaning process can be performed to clean the physically exposed surface of the semiconductor die 100 and the horizontal surface of the second molding compound matrix 497.

[0154] A dicing process can be performed to dice reconstructed dies, including a two-dimensional array of semiconductor dies 300 containing substrate through-vessels (TSVs), a first molding compound matrix 397, a first dielectric bonding layer 460, a two-dimensional array of a group of device semiconductor dies 100, a two-dimensional array of underfill material portions 495, and a second molding compound matrix 497. Generally, the reconstructed die includes at least a dielectric bonding layer 560, a first molding compound matrix 397, and a first dielectric bonding layer 460. The diced portions of the reconstructed die include composite dies 800. Each composite die 800 includes a diced portion of the semiconductor dies 300 containing substrate through-vessels (TSVs), a diced portion of the second dielectric bonding layer 560, a diced portion of the first molding compound matrix 397, a diced portion of the first dielectric bonding layer 460, and a diced portion of the second molding compound matrix 497.

[0155] The example structure shown in Figure 4M includes a semiconductor package comprising: a first semiconductor substrate 310 having a substrate through-hole structure 304 formed therein; a first semiconductor element 320 and a first metal interconnect structure 360 ​​located on the front side of the first semiconductor substrate 310; and a first back-side metal interconnect structure 340 located on the back side of the first semiconductor substrate 310; a first molding compound matrix 397 laterally surrounding a semiconductor die 300 containing a substrate through-hole (TSV); a first dielectric bonding layer 460 located on the first metal interconnect structure 360; and a first bump structure 498 located on the first dielectric bonding layer 460.

[0156] In one embodiment, a first molding compound matrix 397 contacts a frame-shaped horizontal surface of a first dielectric bonding layer 460. In one embodiment, the semiconductor package further includes a component semiconductor die 100 attached to a first bump structure 498 through an array of solder portions 493. In one embodiment, the semiconductor package includes: an underfill material portion 495 laterally surrounding the array of solder portions 493; and a second molding compound matrix 497 laterally surrounding the component semiconductor die 100 and the underfill material portion 495.

[0157] In one embodiment, the second molding compound matrix 497 is perpendicularly spaced from the first molding compound matrix 397 by the first dielectric bonding layer 460. In one embodiment, the sidewalls of the first dielectric bonding layer 460 are perpendicularly coincident with the outer sidewalls of the second molding compound matrix 497. In one embodiment, the element semiconductor die 100 includes a horizontal surface located within a horizontal plane containing the horizontal surface of the second molding compound matrix 497.

[0158] In one embodiment, the sidewalls of the first dielectric bonding layer 460 are perpendicularly aligned with the outer sidewalls of the first molded compound matrix 397. In another embodiment, a first bonding-level metal interconnect structure 480 is formed in the first dielectric bonding layer 460, wherein a first bump structure 498 contacts a subset of the first bonding-level metal interconnect structure 480.

[0159] In one embodiment, the semiconductor package includes a second dielectric bonding layer 560 having a bonding-level metal interconnect structure 580 formed therein and located on a back-side metal interconnect structure 340. In one embodiment, the second dielectric bonding layer 560 contacts a frame-like horizontal surface of a first molding compound matrix 397. In one embodiment, the sidewalls of the second dielectric bonding layer 560 perpendicularly coincide with the outer sidewalls of the first molding compound matrix 397. In one embodiment, the semiconductor package includes metal bump structures 598 that contact a subset of the bonding-level metal interconnect structure 580. In one embodiment, a first semiconductor element 320 includes a first field-effect transistor; and each of the element semiconductor dies 100 includes a set of additional field-effect transistors.

[0160] Referring to Figure 4N, a fourth flowchart is illustrated, which includes a set of process steps for forming a semiconductor structure.

[0161] Referring to step 1410 and Figures 4A to 4D, a semiconductor component (300, 934, 924) is provided. It includes a semiconductor die 300 with a substrate through-vessel (TSV), a die attachment film 934, and a semiconductor carrier substrate 924. The semiconductor die 300 with a substrate through-vessel (TSV) includes a first semiconductor substrate 310 having a substrate through-vessel (TSV) structure 304 formed therein, a first semiconductor element 320 and a first metal interconnect structure 360 ​​located on the front side of the first semiconductor substrate 310, and a first back-side metal interconnect structure 340 located on the back side of the first semiconductor substrate 310.

[0162] Referring to step 1420 and Figure 4E, the first back-side metal interconnect structure 340 of the semiconductor components (300, 934, 924) can be attached to the carrier wafer 902 using a die attachment film 932.

[0163] Referring to step 1430 and Figures 4F to 4M, the semiconductor carrier substrate 924 and the grain attachment film 934 can be removed.

[0164] Figures 5A to 5L are successive vertical cross-sectional views of the structure of the fifth embodiment during a series of process steps according to an embodiment of the present disclosure.

[0165] Referring to FIG5A, a device wafer 300W is described, which includes a first semiconductor substrate 310 and structural elements formed therein and thereon. The device wafer 300W illustrated in FIG5A may be the same as the device wafer 300W illustrated in FIG1A.

[0166] Referring to FIG5B, the device wafer 300W may be attached to the processing wafer 701, for example, using a die attachment film 731. The processing wafer 701 may be any wafer that can be used to provide mechanical support during subsequent processing of the device wafer 300W. In one embodiment, the processing wafer 701 may include a glass carrier wafer having the same lateral dimensions as the device wafer 300W.

[0167] Referring to Figure 5C, the device wafer 300W can be thinned from the back side. The back side of the first semiconductor substrate 310 can be removed by grinding, polishing, anisotropic etching processes and / or isotropic etching processes. The back surface of the substrate through-hole (TSV) structure 304 can be physically exposed during the thinning of the first semiconductor substrate 310. The substrate through-hole (TSV) structure 304 extends vertically through the thinned first semiconductor substrate 310.

[0168] The back surface of the first semiconductor substrate 310 can be further thinned by performing an etching process (which may include anisotropic etching or isotropic etching). An insulating material, such as silicon oxide, can be deposited on the recessed back surface of the first semiconductor substrate 310. Excess portion of the insulating material above the horizontal plane including the back surface of the substrate through-hole (TSV) structure 304 can be removed by performing a planarization process (such as a chemical mechanical polishing (CMP) process). The remaining portion of the insulating material constitutes the back insulating layer 316. The physically exposed back surface of the substrate through-hole (TSV) structure 304 can be coplanar with the physically exposed horizontal surface of the back insulating layer 316.

[0169] A metal layer may be deposited on the back surface of the substrate through-via (TSV) structure 304 and subsequently patterned to form a first back-side metal interconnect structure 340. The first back-side metal interconnect structure 340 may include metal pad structures, metal line structures, and / or metal pillar structures. The device wafer 300W includes an array of semiconductor dies 300 containing substrate through-vias (TSVs).

[0170] A back-side bump structure 348 may be formed on a first back-side metal interconnect structure 340. For example, the back-side bump structure 348 may be formed by depositing a metal seed layer, depositing and patterning a photoresist mask layer, performing an electroplating process, and removing the photoresist mask layer and removing unmasked portions of the metal seed layer. Each back-side bump structure 348 may be formed on its respective first back-side metal interconnect structure 340. In one embodiment, the back-side bump structure 348 may include a grain-connection (C2) bump structure, such as a microbump structure. Solder portions 493 may be formed on the back-side bump structure.

[0171] Referring to Figure 5D, the semiconductor carrier wafer 924W can be attached to the device wafer 300W using a continuous adhesive layer 914W. The semiconductor carrier wafer 924W may include a commercially available semiconductor wafer (such as a silicon wafer) having the same lateral extent as the device wafer 300W. The continuous adhesive layer 914W may include an adhesive layer. For example, the continuous adhesive layer 914W may include a thermosetting adhesive, such as benzocyclobutene (BCB), or an epoxy-based adhesive. The continuous adhesive layer 914W provides adhesion between the device wafer 300W and the semiconductor carrier wafer 924W. Optionally, the semiconductor carrier wafer 924W may be thinned to a desired target thickness before or after bonding to the device wafer 300W. The thickness of the semiconductor carrier wafer 924W can range from 60 micrometers to 1 millimeter, for example from 150 micrometers to 600 micrometers, although smaller and larger thicknesses are also possible. A wafer-level bonding assembly (300W, 914W, 924W) is formed, consisting of a device wafer 300W, a continuous adhesive layer 914W, and a semiconductor carrier wafer 924W.

[0172] Referring to FIG5E, the die-attachment film 731 can be deactivated to facilitate the separation of the processed wafer 701 from the wafer-level bonding components (300W, 914W, 924W). For example, the die-attachment film 731 may comprise a UV-degradable material, while the processed wafer 701 may comprise a transparent wafer, such as a glass substrate. In this embodiment, UV radiation can pass through the processed wafer 701 to irradiate the die-attachment film to disrupt its adhesive properties, enabling easy separation. Once the die-attachment film 731 is deactivated, the processed wafer 701 is removed, leaving the device wafer 300W firmly bonded to the semiconductor carrier wafer 924W through a continuous adhesive layer 914W. To prepare the surface for subsequent processing, any residual die-attachment film 731 can be removed through a cleaning process (such as solvent cleaning or plasma etching) to ensure a contaminated interface.

[0173] The wafer-level bonding assemblies (300W, 914W, 924W) can then be diced along a dicing channel. The dicing channel extends along the boundary between adjacent pairs of semiconductor dies 300 containing substrate vias (TSVs). The diced portion of the wafer-level bonding assemblies (300W, 914W, 924W) includes semiconductor assemblies (300, 914, 924). Each semiconductor assembly (300, 914, 924) includes a semiconductor die 300 containing a substrate via (TSV), an adhesive layer 914, and a semiconductor carrier substrate 924. The semiconductor die 300 containing a substrate via (TSV) includes a first semiconductor substrate 310 containing a substrate via (TSV) structure 304, a first semiconductor element 320, and a front-side connection pad 378 located on the front side of the first semiconductor substrate 310, and a back-side metal interconnect structure 340 located on the back side of the first semiconductor substrate 310.

[0174] Referring to FIG5F, multiple semiconductor components (300, 914, 924) provided through the process steps described with reference to FIG5A to 5E can be attached to a carrier wafer 902 using a die attachment film 932. It should be understood that FIG5F and subsequent figures illustrate the area surrounding a single semiconductor component (300, 914, 924). The carrier wafer 902 can be any carrier wafer known in the art. For example, the carrier wafer 902 may include a glass substrate having a circular or rectangular shape in a plan view. The die attachment film 932 may include an ultraviolet-degradable adhesive material. The die attachment film 932 may be attached to the top surface of the carrier wafer 902, and a two-dimensional array of semiconductor components (300, 914, 924) may be attached to the die attachment film 932. In one embodiment, the two-dimensional array of semiconductor components (300, 914, 924) may be arranged as a two-dimensional rectangular array of semiconductor components (300, 914, 924). A gap may exist between each pair of adjacent semiconductor components (300, 914, 924).

[0175] Referring to Figure 5G, each semiconductor carrier substrate 924 in the semiconductor component (300, 914, 924) array can be separated from its respective semiconductor die 300 containing substrate through-holes (TSVs). Each semiconductor carrier substrate 924 can be separated from its respective semiconductor die 300 containing TSVs by performing a peeling process using thermal separation or solvent separation. For example, each adhesive layer 914 can be deactivated to facilitate the separation of the semiconductor carrier substrate 924 from the semiconductor die 300 containing TSVs. Specifically, the adhesive layer 914, which may include thermally decomposable materials, can be decomposed by performing an annealing process at an elevated temperature in the range of 150 to 300 degrees Celsius. Alternatively, the adhesive layer 914 can be removed by dissolution using a suitable solvent. Once deactivated, the semiconductor carrier substrate 924 is removed, leaving the exposed semiconductor die 300 containing TSVs, ready for subsequent processing. To ensure surface cleanliness, any residual adhesive from the adhesive layer 914 can be removed through cleaning processes (such as solvent cleaning or plasma etching), ensuring a contamination-free interface for further manufacturing steps. Therefore, the semiconductor carrier substrate 924 and the adhesive layer 914 can be removed from each semiconductor component (300, 914, 924). The array of solder material portions 493 can be physically exposed.

[0176] Referring to FIG5H, the semiconductor die 100 can be attached to the back bump structure 348 through an array of solder material portions 493. Each of the semiconductor dies 100 may include active components, such as field-effect transistors, and may optionally include passive components, such as capacitors, resistors, inductors, etc. Each of the semiconductor dies 100 may include a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a digital signal processor (DSP), embedded volatile memory, and / or embedded non-volatile memory. Each of the semiconductor dies 100 may have a smaller area in a planar view along the vertical direction than the semiconductor die 300 below which contains a substrate through-via (TSV). Each of the semiconductor dies 100 is attached to the back bump structure 348 through its respective array of solder material portions 493.

[0177] In one embodiment, each of the semiconductor die 100 may include a semiconductor substrate 110, a respective set of second semiconductor elements 120 (which may be referred to as additional semiconductor elements), and a respective set of second dielectric material layers 150, wherein a second metal interconnect structure 160 is formed. In one embodiment, each of the semiconductor die 100 may include a respective interconnect-level dielectric layer 180, wherein a respective set of interconnect metal pads 188 is formed, and a respective bump-level dielectric layer 190, wherein a respective set of second bump structures 198 is formed. The second bump structures 198 of the semiconductor die 100 may be bonded to the first bump structure 498 through an array of solder material portions 493. A gap 380 may exist between adjacent semiconductor dies 300.

[0178] Referring to FIG5I, an underfill material portion 495 may be formed around each set of solder material portions 493 covering the semiconductor die 300 containing a substrate through-vessel (TSV). In one embodiment, each underfill material portion 495 may laterally surround all solder material portions 493 that have an area overlap with the respective underlying semiconductor die 300 containing a substrate through-vessel (TSV).

[0179] An underfill material portion 495 may be formed around each set of solder material portions 493 covering the semiconductor die 300 containing a substrate through-hole (TSV). In one embodiment, the underfill material portion 495 may laterally surround all solder material portions 493 that overlap in area with their respective underlying semiconductor die 300 containing a substrate through-hole (TSV). The underfill material provides structural support and reduces mechanical stress that may occur due to thermal cycling or mechanical shock. The material absorbs stress between the element semiconductor die 100 and the semiconductor die 300 containing a substrate through-hole (TSV). The underfill material may be applied using capillary underfill, molded underfill, or printed underfill techniques.

[0180] Capillary underfill relies on capillary action to distribute material between solder bumps, while molding and printing underfill techniques involve direct application. Underfill materials typically consist of epoxy resin with silica or other fillers. Filler content can be up to 85% (by weight), which improves thermal conductivity and mechanical strength, and reduces shrinkage and warpage during the curing process. After application, the underfill material cures below the solder reflow temperature to solidify and protect the underlying structure. Underfill materials reduce structural damage to the solder material portion 493 in subsequent process steps and improve the overall durability of the semiconductor package.

[0181] A molding compound matrix 497 may be formed around the semiconductor die 100 and the underfill material portion 495, and directly on the sidewalls of the semiconductor die 300 containing substrate through-vessels (TSVs). The molding compound matrix 497 may also fill the gaps 380 between adjacent semiconductor dies 300. The molding compound matrix 497 may include an epoxy molding compound (EMC). The EMC can be cured in a temperature range of 125 to 150 degrees Celsius, thereby maintaining the integrity of the component during the molding process. After curing, excess molding compound can be removed from above the semiconductor die 100 by performing a planarization process. Specifically, the cured EMC material portion covering the horizontal plane including the top surface of the semiconductor die 100 can be removed by performing a chemical mechanical polishing process. The remaining portion of the cured EMC material constitutes the molding compound matrix 497.

[0182] The molding compound matrix 497 can be embedded in a two-dimensional array of semiconductor die 100 and a two-dimensional array of semiconductor dies 300 containing substrate through-holes (TSVs). The molding compound matrix 497 may have a top surface located within a horizontal plane including the topmost surface of the semiconductor die 100, and may include a planar bottom surface that contacts the top surface of the die attachment film 932. The molding compound matrix 497 provides mechanical support and environmental protection for the semiconductor die 100 and the semiconductor dies 300 containing substrate through-holes (TSVs).

[0183] Referring to FIG5J, an additional carrier wafer 903 may be attached to the device semiconductor die 100 using an additional die adhesion film 933. The additional carrier wafer 903 may be any carrier wafer known to those skilled in the art. For example, the additional carrier wafer 903 may include a glass substrate having a circular or rectangular shape in a plan view. The additional die adhesion film 933 may include an ultraviolet-degradable adhesive material. The additional die adhesion film 933 may be attached to the top surface of the device semiconductor die 100 and the additional carrier wafer 903.

[0184] Subsequently, the carrier wafer 902 and the die attachment film 932 can be removed. For example, an ultraviolet irradiation process can be performed to irradiate the die attachment film 932 through the carrier wafer 902. The die attachment film 932 can be deactivated by ultraviolet radiation. A suitable cleaning process can be performed to clean the physically exposed surfaces of the front bonding pad 378, the second front dielectric capping layer 372, and the first molding compound matrix 397.

[0185] Referring to FIG5K, a dielectric bonding layer 560 having a bonding-level metal interconnect structure 580 therein can be formed on the front-side connection pad 378. The dielectric bonding layer 560 can be formed directly on the first molding compound matrix 397. The dielectric bonding layer 560 includes at least one interlayer dielectric (ILD) layer, which may include at least one via-level dielectric layer and / or at least one line-level dielectric layer. The dielectric bonding layer 560 may include, and / or may be substantially composed of at least one inorganic dielectric material, such as undoped silicate glass, doped silicate glass, organic silicate glass, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, dielectric metal oxide, etc. The bonding-level metal interconnect structure 580 may include a metal via structure, a metal wire structure, a metal pad structure, etc.

[0186] Metal bump structures 598 may be formed on the top layer of dielectric bonding layer 560. Each metal bump structure 598 may be formed on a respective bonding-level metal interconnect structure 580 that covers and contacts the first molding compound matrix 397. In one embodiment, the metal bump structure 598 may include via portions formed within and laterally surrounded by the dielectric bonding layer 560. Furthermore, the metal bump structure 598 may include pad structures covering the top surface of the dielectric bonding layer 560. In one embodiment, the metal bump structure 598 may include controlled-collapse wafer interconnect (C4) pads. Each metal bump structure 598 may be formed directly on its respective bonding-level metal interconnect structure 580 and above the dielectric bonding layer 560. Solder balls 593 may be attached to the metal bump structures 598.

[0187] Referring to Figure 5L, the additional carrier wafer 903 and the additional die-attachment film 933 can be removed. For example, an ultraviolet irradiation process can be performed to irradiate the additional die-attachment film 933 with an ultraviolet beam through the additional carrier wafer 903. The additional die-attachment film 933 can be deactivated by ultraviolet radiation. A suitable cleaning process can be performed to clean the physically exposed surfaces of the element semiconductor die 100 and the molding compound matrix 497.

[0188] A dicing process can be performed to dicing a reconstructed die comprising a two-dimensional array of semiconductor dies 300 with substrate through-vessels (TSVs), a two-dimensional array of device semiconductor dies 100, a two-dimensional array of underfill material portions 495, a molded compound matrix 497, and a dielectric bonding layer 560. The diced portion of the reconstructed die includes a composite die 800. Each composite die 800 includes a diced portion of the semiconductor dies 300 with substrate through-vessels (TSVs), the device semiconductor dies 100, the underfill material portions 495, and the dielectric bonding layer 560.

[0189] The example structure shown in Figure 5L includes a semiconductor package comprising: a semiconductor die 300 with a substrate through-vessel (TSV) including a first semiconductor substrate 310 having a substrate through-vessel (TSV) structure 304 therein, a first semiconductor element 320 and a front bonding pad 378 located on the front side of the first semiconductor substrate 310, and a back bump structure 348 located on the back side of the first semiconductor substrate 310; an element semiconductor die 100 bonded to the back bump structure 348; a molded compound matrix 497 laterally surrounding the element semiconductor die 100; and a dielectric bonding layer 560 having a bonding-level metal interconnect structure 580 therein and located on the front bonding pad 378.

[0190] In one embodiment, each element semiconductor die 100 is attached to the back-side bump structure 348 via a respective array of solder portions 493. In one embodiment, the package structure includes an underfill material portion 495 laterally surrounding the array of solder portions 493 and formed in a molding compound matrix 497. In one embodiment, the underfill material portion 495 contacts the back-side bump structure 348.

[0191] In one embodiment, the dielectric bonding layer 560 contacts the molding compound matrix 497 and the back insulating layer 316 of the semiconductor die 300 containing a substrate through-hole (TSV). In one embodiment, the lateral extension of the dielectric bonding layer 560 is greater than that of the semiconductor die 300 containing the substrate through-hole (TSV).

[0192] In one embodiment, the sidewalls of the dielectric bonding layer 560 are perpendicularly aligned with the outer sidewalls of the molding compound matrix 497. In one embodiment, all sidewalls of the semiconductor die 300 containing a substrate through-vessel (TSV) contact the inner sidewalls of the molding compound matrix 497. In one embodiment, the package structure includes metal bump structures 598 located on the bonding-level metal interconnect structure 580 and the dielectric bonding layer 560.

[0193] In one embodiment, the first semiconductor element 320 includes a first field-effect transistor; and each element semiconductor die 100 includes a set of additional field-effect transistors. In one embodiment, each element semiconductor die 100 includes a horizontal surface that lies entirely within a horizontal plane of a planar frame-shaped surface including a molded compound matrix 497. In one embodiment, the semiconductor die 300 containing a substrate through-hole (TSV) includes a first metal interconnect structure 360 ​​formed in a first dielectric material layer 350 and interposed between a front-side connection pad 378 and the first semiconductor element 320.

[0194] Referring to Figure 5M, a fifth flowchart is illustrated, which includes a set of process steps for forming a semiconductor structure.

[0195] Referring to step 1510 and Figures 5A to 5E, a semiconductor assembly (300, 914, 924) is provided. The semiconductor assembly (300, 914, 924) includes a semiconductor die 300 with a substrate through-vessel (TSV), an adhesive layer 914, and a semiconductor carrier substrate 924. The semiconductor die 300 with a substrate through-vessel (TSV) includes a first semiconductor substrate 310 having a substrate through-vessel (TSV) structure 304 formed therein, a first semiconductor element 320, a front-side connection pad 378 located on the front side of the first semiconductor substrate 310, and a back-side bump structure 348 located on the back side of the first semiconductor substrate 310.

[0196] Referring to step 1520 and Figure 5F, the semiconductor components (300, 914, 924) are attached to the carrier wafer 902 using the die attachment film 932.

[0197] Referring to step 1530 and Figures 5G to 5L, the semiconductor carrier substrate 924 and the adhesive layer 914 can be removed from the semiconductor components (300, 914, 924).

[0198] Figures 6A to 6L are continuous vertical cross-sectional views of the structure of the sixth embodiment according to an embodiment of the present disclosure during a series of process steps.

[0199] Referring to FIG6A, a device wafer 300W is illustrated, which includes a first semiconductor substrate 310 and structural elements formed therein and thereon. The device wafer 300W shown in FIG5A may be derived from the device wafer 300W shown in FIG1A, but the formation of at least one front dielectric capping layer (370, 372) and front interconnect pad 378 is omitted. A front bump structure 398 may be formed on the front side of the first semiconductor substrate 310, located on a set of first metal interconnect structures 360 formed in a first dielectric material layer 350. Each front bump structure 398 may be formed on its respective first metal interconnect structure 360. In one embodiment, the front bump structure 398 may include a via portion formed inside and laterally surrounded by a selected top dielectric layer in the first dielectric material layer 350. Furthermore, the front bump structure 398 may include a pillar structure or pad structure covering the top surface of the first dielectric material layer 350. In one embodiment, the front bump structure 398 may include a grain connection (C2) bonding structure, such as a microbump structure.

[0200] Referring to Figure 6B, the device wafer 300W can be attached to the processing wafer 701, for example, using an adhesive layer 711. The adhesive layer 711 may comprise a thermally degradable material, a UV-degradable material, or a combination thereof, depending on the process specifications. In semiconductor manufacturing, adhesive layers are typically made of polymers such as polyimide, benzocyclobutene (BCB), epoxy-based adhesives, or other thermosetting resins. These materials are chosen based on their ability to provide strong adhesion while allowing for easy subsequent separation during the peeling process. For example, when the processing wafer 701 is a transparent substrate (such as glass), a UV-degradable adhesive may be preferred, allowing UV light to penetrate the processing wafer to facilitate peeling. Thermally degradable adhesives may be used when thermal treatment can degrade the adhesive and separate the wafer. The adhesive layer 711 ensures secure attachment during processing and fabrication of the device wafer 300W. In this embodiment, the processing wafer 701 may include a glass carrier wafer having the same lateral dimensions as the device wafer 300W, providing mechanical support in subsequent steps of the manufacturing process.

[0201] Referring to Figure 6C, the device wafer 300W can be thinned from the back side. The back side of the first semiconductor substrate 310 can be removed by grinding, polishing, anisotropic etching processes, and / or isotropic etching processes. The back surface of the substrate through-hole (TSV) structure 304 can be actually exposed during the thinning of the first semiconductor substrate 310. The substrate through-hole (TSV) structure 304 passes perpendicularly through the thinned first semiconductor substrate 310.

[0202] The back surface of the first semiconductor substrate 310 may be further thinned by performing an etching process (which may include anisotropic etching or isotropic etching). An insulating material (such as silicon oxide) may be deposited on the recessed back surface of the first semiconductor substrate 310. Excess insulating material extending beyond the horizontal plane including the back surface of the substrate through-hole (TSV) structure 304 may be removed by performing a planarization process (such as a chemical mechanical polishing (CMP) process). The remaining portion of the insulating material constitutes the back insulating layer 316. The back surface actually exposed by the substrate through-hole (TSV) structure 304 may be coplanar with the horizontal surface actually exposed by the back insulating layer 316.

[0203] A metal layer may be deposited on the back surface of the substrate through-via (TSV) structure 304 and may subsequently be patterned to form a first back-side metal interconnect structure 340. The first back-side metal interconnect structure 340 may include metal pad structures, metal line structures, and / or metal pillar structures. The device wafer 300W includes an array of semiconductor dies 300 containing substrate through-vias (TSVs).

[0204] Referring to Figure 6D, the semiconductor carrier wafer 924W can be attached to the device wafer 300W using a continuous die adhesion film 934W. The semiconductor carrier wafer 924W may include a commercially available semiconductor wafer (such as a silicon wafer) having the same lateral extent as the device wafer 300W. The continuous die adhesion film 934W may include an adhesive layer. For example, the continuous die adhesion film 934W may include a thermosetting adhesive, such as benzocyclobutene (BCB), or an epoxy-based adhesive. The surface of the first back-side metal interconnect structure 340 is accessible to the continuous die adhesion film 934W. The continuous die adhesion film 934W provides adhesion between the device wafer 300W and the semiconductor carrier wafer 924W. The semiconductor carrier wafer 924W may be selectively thinned to a desired target thickness before or after bonding with the device wafer 300W. The thickness of the semiconductor carrier wafer 924W can range from 60 micrometers to 1 millimeter, such as from 150 micrometers to 600 micrometers, although smaller and larger thicknesses are also possible. Wafer-level bonding components (300W, 934W, 924W) are formed of the device wafer 300W, the continuous die-attached film 934W, and the semiconductor carrier wafer 924W.

[0205] Referring to Figure 6E, the die-attachment film 731 can be deactivated to facilitate the separation of the processed wafer 701 from the wafer-level bonding components (300W, 934W, 924W). For example, the die-attachment film 731 may comprise a UV-degradable material, and the processed wafer 701 may comprise a transparent wafer (such as a glass substrate). In this embodiment, UV radiation can pass through the processed wafer 701 to irradiate the die-attachment film to degrade the film's adhesive properties, enabling easy separation. Once the die-attachment film 731 is deactivated, the processed wafer 701 is removed, leaving the device wafer 300W firmly bonded to the semiconductor carrier wafer 924W through a continuous die-attachment film 934W. To prepare the surface for subsequent processing, any residual die-attachment film 731 can be removed through a cleaning process (such as solvent cleaning or plasma etching) to ensure a contaminated interface.

[0206] The wafer-level bonding assemblies (300W, 934W, 924W) can then be diced along a dicing channel. The dicing channel extends along the boundary between adjacent pairs of semiconductor dies 300 containing substrate vias (TSVs). The diced portion of the wafer-level bonding assemblies (300W, 934W, 924W) includes semiconductor assemblies (300, 934, 924). Each semiconductor assembly (300, 934, 924) includes a semiconductor die 300 containing a substrate via (TSV), a die attachment film 934, and a semiconductor carrier substrate 924. The semiconductor die 300 containing a substrate via (TSV) includes a first semiconductor substrate 310 containing a substrate via (TSV) structure 304, a first semiconductor element 320, and a front-side connection pad 378 located on the front side of the first semiconductor substrate 310, and a back-side metal interconnect structure 340 located on the back side of the first semiconductor substrate 310.

[0207] Referring to Figure 6F, multiple semiconductor components (300, 934, 924) provided through the process steps described with reference to Figures 6A to 6E can be attached to a carrier wafer 902 using a die-attachment film 932. It should be understood that Figure 6F and subsequent figures only illustrate the area surrounding a single semiconductor component (300, 934, 924). The carrier wafer 902 can be any carrier wafer known to those skilled in the art. For example, the carrier wafer 902 may include a glass substrate having a circular or rectangular shape in a planar view. The die-attachment film 932 may include an ultraviolet-degradable adhesive material. The die-attachment film 932 may be attached to the top surface of the carrier wafer 902, and a two-dimensional array of semiconductor components (300, 934, 924) may be attached to the die-attachment film 932. In one embodiment, a semiconductor carrier substrate 924 for each semiconductor component (300, 934, 924) may be attached to the carrier wafer 902. In one embodiment, the two-dimensional array of semiconductor components (300, 934, 924) can be arranged as a two-dimensional rectangular array of semiconductor components (300, 934, 924). Gaps may exist between adjacent pairs of semiconductor components (300, 934, 924).

[0208] Referring to Figure 6G, the semiconductor die 100 can be attached to the front bump structure 398 via an array of solder portions 493. Each semiconductor die 100 may include active components such as field-effect transistors and may optionally include passive components such as capacitors, resistors, inductors, etc. Each semiconductor die 100 may include a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a digital signal processor (DSP), embedded volatile memory, and / or embedded non-volatile memory. In a planar view along the vertical direction, each semiconductor die 100 may have a smaller area than the semiconductor die 300 below with a substrate through-via (TSV). Each semiconductor die 100 is attached to the back bump structure 348 via its respective array of solder portions 493.

[0209] In one embodiment, each semiconductor die 100 may include a semiconductor substrate 110, a respective set of second semiconductor elements 120 (which may be referred to as additional semiconductor elements), and a respective set of second dielectric material layers 150, wherein a second metal interconnect structure 160 is formed. In one embodiment, each semiconductor die 100 may include a respective interconnect-level dielectric layer 180, wherein a respective set of interconnect metal pads 188 is formed, and a respective bump-level dielectric layer 190, wherein a respective set of second bump structures 198 is formed. The second bump structures 198 of the semiconductor die 100 may be bonded to the first bump structure 498 through an array of solder portions 493.

[0210] Referring to FIG6H, an underfill material portion 495 may be formed around each set of solder portions 493 covering the semiconductor die 300 containing a substrate through-hole (TSV). In one embodiment, each underfill material portion 495 may laterally surround all solder portions 493 that overlap in area with the respective underlying semiconductor die 300 containing a substrate through-hole (TSV).

[0211] An underfill material portion 495 may be formed around each set of solder portions 493 covering the semiconductor die 300 containing a substrate through-hole (TSV). In one embodiment, the underfill material portion 495 may laterally surround all solder portions 493 that overlap in area with their respective underlying semiconductor die 300 containing a substrate through-hole (TSV). The underfill material provides structural support and reduces mechanical stress that may occur due to thermal cycling or mechanical shock. The material absorbs stress between the element semiconductor die 100 and the semiconductor die 300 containing a substrate through-hole (TSV). The underfill material may be applied using capillary underfill, molded underfill, or printed underfill techniques.

[0212] Capillary underfill relies on capillary action to distribute material between solder bumps, while molding and printing underfill techniques involve direct application. Underfill materials typically consist of epoxy resin with silica or other fillers. Filler content can be up to 85% by weight, which improves thermal conductivity and mechanical strength, and reduces shrinkage and warpage during the curing process. After application, the underfill material cures at a temperature below the solder reflow temperature to solidify and protect the underlying structure. Underfill materials reduce structural damage to the solder portion 493 in subsequent process steps and improve the overall durability of the semiconductor package.

[0213] A molding compound matrix 497 may be formed around the semiconductor die 100 and the underfill material portion 495, and directly on the sidewalls of the semiconductor die 300 containing substrate through-vessels (TSVs). The molding compound matrix 497 may include an epoxy molding compound (EMC). The EMC can be cured in a temperature range of 125 to 150 degrees Celsius, thereby maintaining the integrity of the component during the molding process. After curing, excess molding compound can be removed from above the semiconductor die 100 by performing a planarization process. Specifically, the cured EMC material portion covering a horizontal plane including the topmost surface of the semiconductor die 100 can be removed by performing a chemical mechanical polishing process. The remaining portion of the cured EMC material constitutes the molding compound matrix 497.

[0214] The molding compound matrix 497 can be embedded in a two-dimensional array of semiconductor dies 100 and a two-dimensional array of semiconductor dies 300 containing substrate through-holes (TSVs). The molding compound matrix 497 may have a top surface located in a horizontal plane including the topmost surface of the semiconductor dies 100, and may include a flat bottom surface that contacts the top surface of the die attachment film 932. The molding compound matrix 497 provides mechanical support and environmental protection for the semiconductor dies 100 and the semiconductor dies 300 containing TSVs.

[0215] Referring to FIG6I, an additional carrier wafer 903 may be attached to the device semiconductor die 100 using an additional die adhesion film 933. The additional carrier wafer 903 may be any carrier wafer known to those skilled in the art. For example, the additional carrier wafer 903 may include a glass substrate having a circular or rectangular shape in plan view. The additional die adhesion film 933 may include an ultraviolet-degradable adhesive material. The additional die adhesion film 933 may be attached to the top surface of the device semiconductor die 100 and the additional carrier wafer 903.

[0216] Subsequently, the carrier wafer 902 and the die-attachment film 932 can be removed. For example, an ultraviolet irradiation process can be performed to irradiate the die-attachment film 932 with an ultraviolet beam through the carrier wafer 902. The die-attachment film 932 can be deactivated by ultraviolet radiation. A suitable cleaning process can be performed to clean the physically exposed surfaces of the front bonding pad 378, the second front dielectric capping layer 372, and the molded compound matrix 497.

[0217] Referring to Figure 6J, a chemical mechanical polishing (CMP) process can be performed to polish the semiconductor carrier substrate 924, the die-attachment film 934, and the molded compound matrix 497 portion which is further away from the additional carrier wafer 903 than the horizontal plane including the interface between the first back-side metal interconnect structure 340 and the die-attachment film 934. The distal horizontal surface of the first back-side metal interconnect structure 340 and the back horizontal surface of the first back-side dielectric material layer 330 can be physically exposed. The distal horizontal surface of the first back-side metal interconnect structure 340 and the back horizontal surface of the first back-side dielectric material layer 330 can be formed in the same horizontal plane as the polishing horizontal surface of the molded compound matrix 497.

[0218] Referring to FIG6K, a dielectric bonding layer 560 having a bonding-level metal interconnect structure 580 formed therein can be formed on the first back-side metal interconnect structure 340. The dielectric bonding layer 560 can be formed directly on the molding compound matrix 497. The dielectric bonding layer 560 includes at least one interlayer dielectric (ILD) layer, which may include at least one via-level dielectric layer and / or at least one line-level dielectric layer. The dielectric bonding layer 560 may comprise, and / or may be substantially composed of at least one inorganic dielectric material, such as undoped silicate glass, doped silicate glass, organic silicate glass, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, dielectric metal oxide, etc. The bonding-level metal interconnect structure 580 may include a metal via structure, a metal wire structure, a metal pad structure, etc.

[0219] Metal bump structures 598 may be formed on the top layer of the dielectric bonding layer 560. Each metal bump structure 598 may be formed on a respective bonding-level metal interconnect structure 580 that covers and contacts the molding compound matrix 497. In one embodiment, the metal bump structure 598 may include via portions formed within and laterally surrounded by the dielectric bonding layer 560. Furthermore, the metal bump structure 598 may include pad structures covering the top surface of the dielectric bonding layer 560. In one embodiment, the metal bump structure 598 may include controlled-collapse wafer interconnect (C4) pads. Each metal bump structure 598 may be formed directly on its respective bonding-level metal interconnect structure 580 and above the dielectric bonding layer 560. Solder balls 593 may be attached to the metal bump structures 598.

[0220] Referring to Figure 6L, the additional carrier wafer 903 and the additional die-attachment film 933 can be removed. For example, an ultraviolet irradiation process can be performed to irradiate the additional die-attachment film 933 with an ultraviolet beam through the additional carrier wafer 903. The additional die-attachment film 933 can be deactivated by ultraviolet radiation. A suitable cleaning process can be performed to clean the physically exposed surfaces of the semiconductor die 100 and the horizontal surfaces of the molded compound matrix 497.

[0221] A dicing process can be performed to dic (singleify) reconstructed dies, which include a two-dimensional array of semiconductor dies 300 with substrate through-vessels (TSVs), a two-dimensional array of device semiconductor dies 100, a two-dimensional array of underfill material portions 495, a molding compound matrix 497, and a dielectric bonding layer 560. The diced portions of the reconstructed dies include composite dies 800. Each composite die 800 includes diced portions of semiconductor dies 300 with substrate through-vessels (TSVs), device semiconductor dies 100, underfill material portions 495, molding compound matrix 497, and dielectric bonding layer 560.

[0222] The example structure shown in Figure 6L includes a semiconductor package comprising: a first semiconductor substrate 310 having a substrate through-hole structure 304 formed therein; a first semiconductor element 320 and a front bump structure 398 located on the front side of the first semiconductor substrate 310; and a first back metal interconnect structure 340 located on the back side of the first semiconductor substrate 310; an element semiconductor die 100 bonded to the front bump structure 398; a molded compound matrix 497 laterally surrounding the element semiconductor die 100; and a dielectric bonding layer 560 having a bonding-level metal interconnect structure 580 formed therein and located on the first back metal interconnect structure 340.

[0223] In one embodiment, each semiconductor die 100 is attached to the front bump structure 398 via a respective array of solder portions 493. In one embodiment, the package structure includes an underfill material portion 495 laterally surrounding the array of solder portions 493 and formed within a molding compound matrix 497. In one embodiment, the underfill material portion 495 contacts the front bump structure 398 and a first dielectric layer 350 of the semiconductor die 300 containing a substrate through-vessel (TSV), wherein the first dielectric layer 350 is interposed between the first semiconductor element 320 and the front bump structure 398.

[0224] In one embodiment, the dielectric bonding layer 560 contacts the molding compound matrix 497. In one embodiment, the lateral extension of the dielectric bonding layer 560 is greater than that of the semiconductor die 300 containing the substrate through-hole (TSV). In one embodiment, the sidewalls of the dielectric bonding layer 560 are perpendicularly aligned with the outer sidewalls of the molding compound matrix 497. In one embodiment, all sidewalls of the semiconductor die 300 containing the substrate through-hole (TSV) contact the inner sidewalls of the molding compound matrix 497.

[0225] In one embodiment, the package structure includes metal bump structures 598 located on the bonding level metal interconnect structure 580 and the dielectric bonding layer 560. In one embodiment, the first semiconductor element 320 includes a first field-effect transistor; and each element semiconductor die 100 includes a set of additional field-effect transistors. In one embodiment, each element semiconductor die 100 includes a horizontal surface that lies entirely within a horizontal plane of a planar frame-like surface containing a molding compound matrix 497. In one embodiment, the semiconductor die 300 containing a substrate through-via (TSV) includes a first metal interconnect structure 360 ​​formed within a first dielectric material layer 350 and interposed between the front bump structure 398 and the first semiconductor element 320.

[0226] Referring to Figure 6M, a sixth flowchart illustrating a set of process steps for forming a semiconductor structure is shown.

[0227] Referring to step 1610 and Figures 6A to 6E, a semiconductor component (300, 934, 924) is provided, which includes a semiconductor die 300 with a substrate through-vessel (TSV), a die attachment film 934, and a semiconductor carrier substrate 924. The semiconductor die 300 with a substrate through-vessel (TSV) includes a first semiconductor substrate 310 having a substrate through-vessel (TSV) structure 304 formed therein, a first semiconductor element 320 and a front bump structure 398 located on the front side of the first semiconductor substrate 310, and a back metal interconnect structure 340 located on the back side of the first semiconductor substrate 310.

[0228] Referring to step 1620 and Figure 6F, the semiconductor components (300, 934, 924) are attached to the carrier wafer 902 using the die attachment film 932.

[0229] Referring to step 1630 and Figures 6G to 6M, the semiconductor die 100 of the component is attached to the front bump structure 398.

[0230] The disclosed embodiments address challenges related to yield reliability and manufacturing costs in semiconductor packaging, particularly in the processing of large-area dies. These embodiments utilize a semiconductor carrier substrate 924 to provide temporary mechanical support during processing stages such as wafer thinning and back-side interconnect formation. The semiconductor carrier substrate 924 helps maintain the structural stability of the semiconductor die 300 containing substrate through-holes (TSVs), minimizing the risk of warpage or mechanical deformation that may occur during processing. By providing this temporary structural support, the die maintains proper alignment and integrity throughout the manufacturing process, facilitating more efficient semiconductor package production.

[0231] After completing the necessary process steps, the semiconductor carrier substrate 924 is separated, allowing the semiconductor die 300 containing substrate through-holes (TSVs) to undergo the remaining processes without the need for permanent structural additions. The temporary use of the semiconductor carrier substrate 924 facilitates assembly and bonding operations while maintaining the structural integrity of the semiconductor die. This method enhances stability during processing, thereby improving manufacturing yield and reducing production costs.

[0232] In the first embodiment shown in Figures 1A to 10, the semiconductor carrier substrate 924 is introduced by attaching it to the device wafer 300W using a continuous adhesive layer 914W, providing mechanical support during the thinning of the first semiconductor substrate 310 and subsequent process steps. After processing, the semiconductor carrier substrate 924 is removed by thermally or chemically deactivating the adhesive layer 914. The composite die 800 may include a first molding compound matrix 397 surrounding the semiconductor die 300 containing substrate through-holes (TSVs), providing lateral support. The back-side metal interconnect structure 340 further enhances the electrical connectivity of the package, allowing for improved signal transmission. The combination of the molding compound and the back-side interconnect helps ensure stability under thermal and mechanical stresses encountered in subsequent processing stages.

[0233] In the second embodiment shown in Figures 2A to 2O, the semiconductor carrier substrate 924 is attached to the device wafer 300W via a continuous adhesive layer 914W, providing necessary mechanical support throughout the process. After the second molding compound matrix 497 is formed around the device semiconductor die 100, the semiconductor carrier substrate 924 is removed by deactivating the adhesive layer 914. The composite die 800 may include a vertical spacing structure between the first molding compound matrix 397 and the second molding compound matrix 497, separated by a first dielectric bonding layer 460. This spacing helps maintain electrical isolation between layers, prevents short circuits, and also provides mechanical stability for the stacked layers. Furthermore, by stacking the device semiconductor die 100 on top of the semiconductor die 300 containing substrate through-vessels (TSVs), a multilayer package with enhanced density and electrical performance is created.

[0234] In the third embodiment shown in Figures 3A to 3O, the semiconductor carrier substrate 924 is bonded to the device wafer 300W using a continuous adhesive layer 914W, providing mechanical support during the formation of the back-side metal interconnect structure 340 and the second dielectric bonding layer 560. After these structures are formed, the semiconductor carrier substrate 924 is removed by deactivating the adhesive layer. The composite die 800 may include a second dielectric bonding layer 560 having a bonding-level metal interconnect structure 580 formed therein. These interconnects enhance the electrical connection between the front-side connection pad 378 and external components, while the metal bump structure 598 provides bonding with other devices. Including the back-side metal interconnect structure 340 helps optimize signal routing for high-performance applications.

[0235] In the fourth embodiment shown in Figures 4A to 4O, the semiconductor carrier substrate 924 is introduced by bonding it to the device wafer 300W using a continuous adhesive layer 914W, providing structural support during the attachment of the additional carrier wafer 903 and subsequent processing. After the formation of the second molding compound matrix 497, the semiconductor carrier substrate 924 is removed by deactivating the adhesive layer. The composite die 800 may include stacked element semiconductor dies 100, supported by the additional carrier wafer 903 during processing. Removing the original carrier wafer 902 and die attachment film 932 after the formation of the second molding compound matrix 497 allows for better contact with the underlying structure for further bonding or processing.

[0236] In the fifth embodiment shown in Figures 5A to 5O, a semiconductor carrier substrate 924 is attached to a device wafer 300W via a continuous adhesive layer 914W, providing mechanical support during the simultaneous formation of multiple semiconductor components. After forming a first molding compound matrix 397 and a second dielectric bonding layer 560 around the components, the semiconductor carrier substrate 924 is removed by deactivating the adhesive layer. The composite die 800 may include multiple semiconductor components attached to a single carrier wafer 902, with the first molding compound matrix 397 providing lateral support and the second dielectric bonding layer 560 improving electrical connections between components. This embodiment allows for efficient mass production by processing multiple components simultaneously.

[0237] In the sixth embodiment shown in Figures 6A to 6O, the semiconductor carrier substrate 924 is introduced by attaching it to the device wafer 300W using a continuous die attachment film 934W, allowing for wafer-level processing. After the wafer-level bonding assembly is diced into individual semiconductor components, the semiconductor carrier substrate 924 is removed by deactivating the adhesive layer. The composite die 800 may include a uniform bonding structure across the entire wafer. This wafer-level bonding method simplifies the assembly process by reducing the number of individual die bonding steps, allowing for mass production with consistent structural integrity and electrical performance across the entire semiconductor component array.

[0238] The invention disclosed herein offers a consistent advantage across all embodiments: utilizing a semiconductor carrier substrate 924 as a temporary structural component to enhance mechanical support during critical stages of semiconductor manufacturing. The semiconductor carrier substrate 924 is introduced early in the process to stabilize the semiconductor die 300 and device wafer 300W containing substrate through-vessels (TSVs) during processes such as wafer thinning, back-side interconnect formation, and molding compound application. By providing this temporary support, the risk of structural warpage or deformation is minimized, thereby improving manufacturing yield. After processing, the semiconductor carrier substrate 924 is removed, leaving no permanent structural elements in the final product, ensuring that the semiconductor die 300 containing TSVs and its associated components remain free of excess material. This approach improves the efficiency and yield of semiconductor packaging by maintaining the structural and electrical integrity of the die while simplifying handling and assembly operations.

[0239] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Each embodiment described using the term "comprising" also inherently discloses that the term "comprising" may be replaced in some embodiments with "substantially constitutes" or "consisting of," unless otherwise explicitly disclosed herein. Whenever two or more elements are listed as alternatives in the same or different paragraphs, it may also imply a disclosure including a Markus group comprising those two or more elements. Whenever the auxiliary verb "may" is used in this disclosure to describe the formation of an element or the execution of a process step, embodiments in which that element or process step is not performed are also explicitly considered, provided that the resulting apparatus or device provides an equivalent result. Therefore, when applied to the formation of an element or the execution of a process step, the auxiliary verb "may" should also be interpreted as "may" or "may, or may not," provided that omitting the formation of the element or process step provides the same or equivalent result, including slightly better and slightly worse results. Those skilled in the art will understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or benefits as the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from its spirit and scope.

[0240] 100: Component Semiconductor Die 110: Semiconductor substrate 120: Second semiconductor element 150: Second dielectric material layer 160: Second metal interconnect structure 180: Connector-level dielectric layer 188: Connecting metal pad 190: Bump-level dielectric layer 198: Second bump structure 300: Semiconductor grains containing substrate through-holes 300W: Device wafer 302: Insulating gap wall 304: Substrate through-hole structure 310: First semiconductor substrate 316: Backside insulation layer 320: First semiconductor element 330: First back-side dielectric material layer 340: First back-side metal interconnect structure 348: Backside protrusion structure 350: First dielectric material layer 360: First metal interconnect structure 370: First front dielectric top cap layer 372: Second front dielectric capping layer 378: Front connecting pad 380: Gap 397: First molded compound matrix 398: Front bump structure 460: First dielectric bonding layer 480: First bonding level metal interconnect structure 493: Solder section 495: Bottom filler material section 497: Second molded compound matrix 498: First bump structure 560: Second dielectric bonding layer 580: Second bonding level metal interconnect structure 593: Solder ball 598: Metal bump structure 701: Processing Wafers 711, 914: Adhesive layer 731, 932, 934: Grain-attached films 800: Composite grains 902: Carrier wafer 903: Additional Carrier Wafer 914W: Continuous adhesive layer 924: Semiconductor carrier substrate 924W: Semiconductor carrier wafer 933: Additional chip bonding film 934W: Continuous Grain-Modified Film 1110, 1120, 1130, 1210, 1220, 1230, 1310, 1320, 1330, 1410, 1420, 1430, 1510, 1520, 1530, 1610, 1620, 1630: Steps

Claims

1. A method for forming a semiconductor structure, comprising: Attaching semiconductor components to a carrier wafer, each of the semiconductor components comprising a semiconductor die and a semiconductor carrier substrate, wherein the semiconductor die comprises a first semiconductor substrate having a substrate through-hole structure formed therein, a first semiconductor element, a front-side connection pad located on the front side of the first semiconductor substrate, and a back-side metal interconnect structure located on the back side of the first semiconductor substrate; removing the semiconductor carrier substrate from the combination of the carrier wafer and the semiconductor components. And after removing the semiconductor carrier substrate, a first molding compound matrix is ​​formed in the gaps between the semiconductor grains, wherein the back-side metal interconnect structure is a metal layer excluding the dielectric layer, and the sidewalls of the metal layer are covered by the first molding compound matrix.

2. The method as described in request item 1, wherein: Each of the semiconductor components includes an adhesive layer that provides adhesion between the semiconductor die and the semiconductor carrier substrate; and the method includes removing the adhesive layer after removing the semiconductor carrier substrate.

3. The method of claim 2, further comprising forming a first dielectric bonding layer and a first bump structure over the back-side metal interconnect structure of the first molded compound matrix and the semiconductor die.

4. The method of claim 3 further includes using an array of solder portions to attach a component semiconductor die to the first bump structure.

5. The method described in claim 4 further includes: An underfill material portion is formed around the array of solder portions; A second molded compound matrix is ​​formed around the semiconductor die of the element and the underfill material portion, and directly on the first dielectric bonding layer.

6. The method of claim 5, wherein the second molding compound matrix is ​​perpendicularly spaced from the first molding compound matrix through the first dielectric bonding layer and does not contact the first molding compound matrix.

7. The method described in claim 4 further includes: An additional carrier wafer is attached to the semiconductor die of the device using an additional die-attachment film; And remove the additional carrier wafer and the additional die-attachment film.

8. The method of claim 7, further comprising forming a dielectric bonding layer on the front connecting pad into an embedded bonding-level metal interconnect structure.

9. A semiconductor package, comprising: A semiconductor die includes a first semiconductor substrate with a substrate through-hole structure, a first semiconductor element, a front connection pad located on the front side of the first semiconductor substrate and embedded in at least one front dielectric capping layer, and a back metal interconnect structure located on the back side of the first semiconductor substrate; a first molding compound matrix laterally surrounding the semiconductor die, wherein the back metal interconnect structure is a metal layer excluding a dielectric layer, and the sidewalls of the metal layer are covered by the first molding compound matrix; a first dielectric bonding layer located on the back metal interconnect structure; a first bump structure located on the first dielectric bonding layer; a second dielectric bonding layer located on the front connection pad; and a second bump structure located on the second dielectric bonding layer, wherein the outer wall of the at least one front dielectric capping layer is laterally offset inward relative to the outer wall of the first molding compound matrix, and the outer wall of the second dielectric bonding layer is perpendicularly coincident with the outer wall of the first molding compound matrix.

10. A method for forming a semiconductor structure, comprising: A semiconductor assembly is provided, wherein the semiconductor assembly includes a semiconductor die and a semiconductor carrier substrate, wherein the semiconductor die includes a first semiconductor substrate having a substrate through-hole structure formed therein, a first semiconductor element, a front-side connection pad located on the front side of the first semiconductor substrate, and a first back-side metal interconnect structure located on the back side of the first semiconductor substrate; the semiconductor carrier substrate is attached to a carrier wafer; and a first molding compound matrix is ​​formed around the semiconductor assembly and in the gaps between adjacent semiconductor assemblies, wherein the back-side metal interconnect structure is a metal layer excluding a dielectric layer, and the sidewalls of the metal layer are covered by the first molding compound matrix.