Clock doubler and method of clock cycle correction

Abstract

A synthesizable clock doubler is disclosed. The clock doubler is implemented using unique combination of logic cells from a standard cell library. At the core of the clock doubler is a high-frequency ring oscillator that generates timing information for clock measurements. Replica ring oscillators are used to generate programmable delays for the correction of the output clock imperfection, such as cycle-to-cycle variation and duty cycle of the doubled clock.

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