Data processing apparatus and method for operating data processing apparatus

Abstract

Disclosed is a data processing apparatus, such as a memory-constrained system (100), comprising at least one main processor (120a-n) configured to process data, at least one main memory (140; 140a-n) configured to store data in a plurality of memory locations, each memory location being associated with a corresponding tag bit indicating whether a corresponding value stored in the corresponding memory location is an index, and memory interconnects (130), such as memory buses (130), configured to exchange data between the main processor (120A-N) and the main memory (140; 140A-N). The data processing apparatus (100) further includes at least one deactivation entity (135; 135a, b) for invalidating one or more indices (140; 140a-n) pointing to one or more released objects in the main memory. The undo entity (135; 135a, b) is located between the memory interconnect (130) and the main memory (140; 140a-n) and configured to perform an undo operation, including loading a value from the current memory location (140; 140a-n) of the main memory, and if the value is an index pointing to a released object, overwriting the tag bits associated with the current memory location (140; 140a-n) of the main memory. The undo entity (135; 135a, b) is further configured to detect (i.e. monitor) storage operations on the main memory (140; 140a-n) by the main processor (120a-n), and if a storage operation (140; 140a-n) on the current memory location of the main memory is detected during the undo operation, the undo operation is aborted. A data processing apparatus, e.g. a memory constrained system, (100) is disclosed, comprising at least one main processor (120a-n) configured to process data, at least one main memory (140; 140a-n) configured to store data at a plurality of memory locations, wherein each of the plurality of memory locations is associated with a respective tag bit indicating whether a respective value stored at the respective memory location is a pointer, and a memory interconnect (130), e.g. a memory bus (130), configured to exchange data between the main processor (120a-n) and the main memory (140; 140a-n). The data processing apparatus (100) further comprises at least one revocation entity (135; 135a,b) for invalidating one or more pointers referring to one or more deallocated objects in the main memory (140; 140a-n).The revocation entity (135; 135a,b) is arranged between the memory interconnect (130) and the main memory (140; 140a-n), and configured to implement a revocation operation, comprising loading a value from a current memory location of the main memory (140; 140a-n), and overwriting the tag bit associated with the current memory location of the main memory (140; 140a-n), if the loaded value is a pointer referring to a deallocated object. The revocation entity (135; 135a,b) is further configured to detect, i.e. monitor store operations of the main processor (120a-n) to the main memory (140; 140a-n) and to abort the revocation operation, if during the revocation operation a store operation to the current memory location of the main memory (140; 140a-n) is detected.

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