Memory device generating per-pin reference voltage

Abstract

A memory device comprises a plurality of reference voltage generators, each of which corresponds to a plurality of data pins and generates a reference voltage for each of the corresponding data pins, with each of the plurality of reference voltage generators comprising a voltage divider that divides a power supply voltage into a plurality of divided voltages; a control logic that receives a first code indicating internal reference voltage level information and a second code indicating offset voltage information for a corresponding data pin, and that generates a control code based on the first and second codes; and a reference voltage selector comprising tree-structured transfer gates that select one of the plurality of divided voltages in response to the control code and output the selected one as a reference voltage.

Images