Memory device

Abstract

This invention provides a high-speed memory device. One embodiment of the memory device includes a bit line, a source line, a first cell transistor between the bit line and the source line, a second cell transistor between the first cell transistor and the bit line, a third cell transistor between the first cell transistor and the source line, a first word line connected to the gate of the first cell transistor, a second word line connected to the gate of the second cell transistor, and a third word line connected to the gate of the third cell transistor. A first voltage is applied to the source line during a first period. At a first moment within the first period, a second voltage greater than or equal to the threshold voltage of the first, second, and third cell transistors is applied to at least one of the second and third word lines. At a second moment later than the first moment within the first period, a third voltage greater than or equal to the threshold voltage of the first, second, and third cell transistors is applied to the first word line.

Description

Technical Field

[0001] The implementation form is generally related to a memory device. Prior Technology

[0002] The memory device is required to operate at high speed. Summary of the Invention

[0003] A memory device capable of high-speed operation is provided.

[0004] A memory device according to one embodiment includes bit lines, source lines, a first transistor between the bit lines and the source lines, a second transistor between the first transistor and the bit lines, a third transistor between the first transistor and the source lines, a first word line connected to the gate of the first transistor, a second word line connected to the gate of the second transistor, and a third word line connected to the gate of the third transistor. A first voltage is applied to the source lines during a first traversal period. At a first moment during the first period, a second voltage greater than or equal to the threshold voltage of the first, second, and third transistors is applied to at least one of the second and third word lines. At a second moment during the first period, later than the first moment, a third voltage greater than or equal to the threshold voltage of the first, second, and third transistors is applied to the first word line. Simple Explanation of the Diagram

[0005] Figure 1 is a block diagram of the memory device in the first embodiment. Figure 2 is a circuit diagram of one block of the memory device in the first embodiment. Figure 3 schematically shows an example of a partial structure of the memory cell array of the memory device in the first embodiment. Figure 4 shows the components of the column decoder of the memory device in the first embodiment and the connection of the components. Figure 5 shows the components of the driver of the memory device in the first embodiment and the connection of the components. Figure 6 shows the classification of the driver circuits in the memory device of the first embodiment. Figure 7 shows a portion of the components of the driver of the memory device in the first embodiment and the connection of the components. Figure 8 shows an example of the distribution of the threshold voltage of the cellular transistor storing 3 bits of data in the memory device of the first embodiment, and the matching of the data. Figure 9 shows one of the states of the driver during data readout of the memory device in the first embodiment. Figure 10 shows the potentials of several wirings during the data readout period of the memory device in the first embodiment, along the timeline. Figure 11 shows a summary of the writing operations in the memory device of the first embodiment along time. Figure 12 shows the order in which data is written to the memory device in the first embodiment. Figure 13 shows the potentials of several nodes in the memory device of the first embodiment during the verification period along time. Figure 14 shows the potentials of several nodes in the memory device of the first embodiment during the verification period along time. Figure 15 shows the potentials of several nodes in the memory device of the first embodiment during the verification period along time. Figure 16 shows the components and connection examples of the voltage generation circuit of the memory device in the second embodiment. Figure 17 shows the potential of several wirings during the data readout period of the memory device in the second embodiment along the timeline. Implementation

[0006] The implementation form is described below with reference to the diagram.

[0007] To distinguish between multiple constituent elements with roughly the same function and structure in a particular embodiment or different embodiments, numbers or words may be added to the end of the reference symbol. In an embodiment that follows a previously described embodiment, the main differences from the previously described embodiment are described. All descriptions related to a particular embodiment, unless explicitly or clearly excluded, also apply to the descriptions of other embodiments.

[0008] Each functional block can be implemented using either hardware or computer software, or a combination of both. Functional blocks do not necessarily have to be distinguished as shown in the example below. Some functions may be executed by functional blocks different from those shown, or they may be divided into finer functional sub-blocks.

[0009] In this specification and the claims, a first element "connected to" another second element includes the first element being connected to the second element directly or via an element that is always or selectively conductive.

[0010] The following uses a 3D orthogonal coordinate system to describe the implementation configuration. The direction of the x-axis is called the X-direction. The direction opposite to the X-direction is called the -X-direction. The direction of the y-axis is called the Y-direction. The direction opposite to the Y-direction is called the -Y-direction. The direction of the z-axis is called the Z-direction (pointing upwards to the Z-direction). The direction opposite to the Z-direction is called the -Z-direction.

[0011] 1. First Implementation Form Figure 1 is a block diagram of the memory device in the first embodiment. The memory device 1 is a device that uses memory cells to store data. The memory device 1 operates based on the instruction CMD and address information ADD received from the memory controller 2. The memory device 1 receives the written data DAT and outputs the data stored in the memory device 1.

[0012] The memory device 1 includes components such as a memory cell array 10, an input / output circuit 11, a logic controller 12, a temporary register 13, a sequencer 14, a driver 15, a column decoder 16, and a sensing amplifier 17.

[0013] The memory cell array 10 is a collection of arranged memory cells. The memory cell array 10 contains j (j is a positive integer) memory blocks (BLKs). Each block BLK contains a plurality of cellular transistors MTs. Each cellular transistor MT functions as one memory cell. In the area where the memory cell array 10 is set, a plurality of word lines WL (not shown) and bit lines BL (not shown) are also configured.

[0014] Input / output circuit 11 transmits and receives various signals with memory controller 2. Input / output circuit 11 sends and receives input / output signals DQ_0, DQ_1, DQ_2, DQ_3, DQ_4, DQ_5, DQ_6, and DQ_7, as well as signals DQS and DQS. The symbol "￣" indicates the inversion logic of the signal whose name does not include the symbol "￣", and indicates that the signal whose name includes the symbol "￣" has valid logic (or is established) at a low ("L") level. Input / output signals DQ_0 to DQ_7 include group transfer instructions (CMD), write data or read data (DAT), address information (ADD), and status (STA). Signals DQS and DQS indicate the fetch timing of input / output signals DQ_0 to DQ_7.

[0015] Logic controller 12 sends and receives signals with memory controller 2. Logic controller 12 sends and receives signals CE, CLE, ALE, WE, RE, RE, WP, and RY / BY. Signal CE activates memory device 1. Signal CLE instructs memory device 1 to send an input / output signal DQ. Signal ALE instructs memory device 1 to send the address information ADD of input / output signal DQ. Signal WE instructs memory device 1 to retrieve input / output signal DQ. Signal RE instructs memory device 1 to output input / output signal DQ. The ready / busy signal RY / BY indicates whether memory device 1 is ready or busy, with the busy state indicated by the low-order bit. When memory device 1 is ready, it accepts instructions; when it is busy, it does not accept instructions.

[0016] Temporary register 13 is a circuit that stores the instruction CMD and address information ADD received from memory device 1. The instruction CMD instructs sequencer 14 to perform various operations including data reading, data writing, and data erasure. In one example, the address information ADD includes block address, page address, and row address. The block address, page address, and row address each specify the block BLK, word line WL, and bit line BL.

[0017] The sequencer 14 is a circuit that controls the operation of the entire memory device 1. Based on the instruction CMD received from the register 13, the sequencer 14 controls the driver 15, the column decoder 16, and the sense amplifier 17 to perform various operations including data reading, data writing, and data erasure.

[0018] The driver 15 is a circuit that applies various voltages required for the operation of the memory device 1 to several constituent components. The driver 15 receives power supply voltage from the memory controller 2 and generates a plurality of voltages from the power supply voltage. The driver 15 supplies the generated voltages to the memory cell array 10, the column decoder 16, and the sense amplifier 17.

[0019] The column decoder 16 is a circuit used to select a block BLK. The column decoder 16 transmits the voltage supplied from the driver 15 to select a block BLK based on the block address received from the register 13.

[0020] The sense amplifier 17 is a circuit that outputs a signal based on data stored in the memory cell array 10. The sense amplifier 17 senses the state of the cellular transistor MT and generates read data based on the sensed state. The sense amplifier 17 applies a voltage based on the write data to the bit line BL.

[0021] Figure 2 is a circuit diagram of one block of the memory device in the first embodiment. Multiple blocks BLK, for example, all blocks BLK, contain the components and connections shown in Figure 2.

[0022] One block BLK contains a plurality of string units SU. Figure 2 shows an example of 5 string units SU_0~SU_4.

[0023] As shown in Figure 2, each of the m bit lines BL_0 to BL_m-1 in each block BLK is connected to one NAND string NS from each of the string units SU_0 to SU_4. m is a positive integer.

[0024] Each NAND string NS contains one select-gate transistor ST, n cellular transistors MT (MT_0~MT_n-1), and one select-gate transistor DT (DT_0, DT_1, DT_2, DT_3, or DT_4). n is a positive integer. The cellular transistor MT functions as a memory cell and is a non-volatile data storage element. The cellular transistor MT includes a control gate electrode or gate electrode (word line WL) and a charge storage film insulated from the surroundings. Data is stored non-volatilely based on the charge in the charge storage film. Data is written to the cellular transistor MT by injecting electrons into the charge storage film.

[0025] Selective gate transistor ST, cell transistors MT_0~MT_n-1, and selective gate transistor DT are connected in series between the source line SL and one bit line BL.

[0026] A series cell SU is formed by multiple NAND strings NS connected to different multiple bit lines BL. In each series cell SU, the control gate electrodes of the cell transistors MT_0 to MT_n-1 are connected to the word lines WL_0 to WL_n-1 respectively. The group of cell transistors MT that share the word line WL in a series cell SU is called the cell CU.

[0027] Selector gate transistors DT_0 to DT_4 belong to serial units SU_0 to SU_4, respectively. In Figure 2, the selection gate transistors DT_2, DT_3, and DT_4 are omitted from the illustration. The gate of the selector gate transistor DT0 for each of the plurality of NAND strings NS in serial unit SU_0 is connected to the select gate line SGDL_0. Similarly, the gates of the selector gate transistors DT_1, DT_2, DT_3, and DT_4 for each of the plurality of NAND strings NS in serial units SU_1, SU_2, SU_3, and SU_4 are connected to the select gate lines SGDL_1, SGDL_2, SGDL_3, and SGDL_4, respectively.

[0028] The gate of the select gate transistor ST is connected to the select gate line SGSL.

[0029] As long as the circuit shown in Figure 2 is implemented, each block BLK can have any structure. For example, each block BLK can have the structure shown in Figure 3. Figure 3 schematically shows an example of a partial structure of the memory cell array of the memory device in the first embodiment.

[0030] As shown in Figure 3, an insulator INS is provided. A conductor CC is provided on the upper surface of the insulator INS. The conductor CC functions as part of the source line SL. Figure 3 is based on an example where n is 8.

[0031] Above conductor CC, there is one conductor CS, n (i.e., 8) conductors CW, and conductor CD. Conductors CS, CW, and CD are arranged sequentially and at intervals along the z-axis and extend along the y-axis. Conductors CS, CW, and CD each function as the select gate line SGSL, word lines WL_0~WL_7, and select gate line SGDL of each NAND string NS.

[0032] Above the conductor CC, a memory pillar MP is disposed. The memory pillar MP penetrates the conductors CS, CW, and CD. The lower surface of the memory pillar MP lies within the conductor CC. The memory pillar MP comprises an insulator IC, a semiconductor (layer) SF, a tunnel insulator (layer) IT, a charge storage film IA, a barrier insulator (layer) IB, and a conductor (layer) CT.

[0033] The insulator IC has a columnar shape extending along the z-axis, located at the center of the memory column MP. A semiconductor SF covers the sides of the insulator IC. The semiconductor SF is connected to the conductor CC in a portion of its lower surface. The semiconductor SF functions as the channel region and body of the cellular transistor MT and the select gate transistor DT and ST. The channel region is the area that forms the channel.

[0034] The tunnel insulator IT covers the sides of the semiconductor SF. The charge storage film IA, which is either an insulator or a conductor, covers the sides of the tunnel insulator IT. The barrier insulator IB covers the sides of the tunnel insulator IT.

[0035] The conductive material CT covers the surface above the insulator IC and the surface above the semiconductor SF.

[0036] Several conductive bodies CT have their upper surfaces connected to conductive bodies CB via conductive plugs CP. The conductive bodies CB extend along the x-axis and are arranged along the y-axis. The conductive bodies CB function as bit lines BL.

[0037] The portions of each memory column MP that intersect with the conductors CS, CW, and CD function as the select gate transistor ST, cell transistor MT, and select gate transistor DT, respectively.

[0038] Figure 4 shows the components and connections of the column decoder of the memory device in the first embodiment. As shown in Figure 4, the column decoder 16 includes j column decoder circuits RD_0 to RD_j-1.

[0039] The column decoder circuits RD_0 to RD_j-1 are connected to blocks BLK_0 to BLK_j-1 respectively. The column decoder circuit RD sets the block BLK connected to it to the selected state. The column decoder circuit RD includes a block decoder BD, a number of transistors XSD_0 to XSD_4 (the same number as the number of serial units SU in block 1 BLK), n transistors XS_0 to XS_n-1, and a transistor XSS.

[0040] The block decoder BD decodes the block address information (block address information). The block decoder BD is connected to the gates of transistors XSD_0~XSD_4, XS_0~XS_n-1, and XSS via wiring TG. When the block address information is a block BLK connected to the column decoder circuit RD containing itself, the block decoder 111 applies a high-level voltage to wiring TG. This high-level voltage has the magnitude that allows transistors XSD_0~XSD_4, XS_0~XS_n-1, and XSS to apply a voltage received at one end to the other.

[0041] In one example, transistors XSD_0~XSD_4, XS_0~XS_n-1, and XSS are MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Hereinafter, one of the source and drain terminals of a transistor will be referred to as terminal 1, and the other as terminal 2. Transistors XSD_0~XSD_4 are connected to wiring SGDI_0~SGDI_4 at their respective terminals 1. Transistors XSD_0~XSD_4 are connected to select gate lines SGDL_0~SGDL_4 at their respective terminals 2.

[0042] Transistors XS_0 to XS_n-1 are connected to wiring CGI_0 to CGI_n-1 at their respective first terminals. Transistors XS_0 to XS_n-1 are connected to word lines WL_0 to WL_n-1 at their respective second terminals.

[0043] Transistor XSS is connected between wiring SGSI and select gate line SGSL.

[0044] Driver 15 applies voltage to wiring SGDI_0~SGDI_4, CGI_0~CGI_n-1, and SGSI.

[0045] Figure 5 shows the components and connections of the driver of the memory device in the first embodiment. As shown in Figure 5, the driver 15 includes voltage generation circuits VG_sgd, VG_read1, VG_read2, VG_pgm, VG_cgr, VG_sgs, driver circuits SGDIdr_0~SGDIdr_4, CGIdr_0~CGIdr_n-1, and SGSdr, and control circuit 21.

[0046] The voltage generation circuit VG_sgd applies voltage VSG to the wiring LGSD. Voltage VSG is used for data readout. In one example, the voltage generation circuit VG_sgd generates voltage VSG from the power supply voltage VDD. In another example, voltage VSG has a constant magnitude.

[0047] The voltage generation circuit VG_read1 applies a voltage VREAD to the wiring Nvread1. The voltage VREAD is used for data reading. In one example, the voltage generation circuit VG_read1 generates the voltage VREAD from the power supply voltage VDD. In another example, the voltage VREAD has a constant magnitude.

[0048] The voltage generation circuit VG_read2 applies a voltage VREAD to the wiring Nvread2. The voltage VREAD is used for data reading. In one example, the voltage generation circuit VG_read2 generates the voltage VREAD from the power supply voltage VDD. In another example, the voltage VREAD has a constant magnitude.

[0049] The voltage generation circuit VG_pgm applies a programming voltage VPGM to the wiring Nvpgm. The programming voltage VPGM is used for data writing. In one example, the voltage generation circuit VG_pgm generates the programming voltage VPGM from the power supply voltage VDD. The programming voltage VPGM has a variable magnitude. The programming voltage VPGM is a high voltage that can raise the threshold voltage of the selector crystal MTsel. The selector crystal MTsel is the crystal MT that is used for both data writing and data reading.

[0050] The voltage generation circuit VG_cgr applies a readout voltage VCGR to the wiring Nvcgr. The readout voltage VCGR is used for data readout. In one example, the voltage generation circuit VG_cgr generates the readout voltage VCGR from the power supply voltage VDD. The readout voltage VCGR has a variable magnitude.

[0051] The voltage generation circuit VG_sgs applies voltage VSG to the wiring LSGS. Voltage VSG is used for data readout. In one example, the voltage generation circuit VG_sgs generates voltage VSG from the power supply voltage VDD.

[0052] The driver circuit SGDIdr_0 is connected to wiring LSGD and LVSS. Furthermore, the driver circuit SGDIdr_0 is connected to wiring SGDI_0. Wiring LVSS receives the ground voltage (or reference voltage) VSS. The driver circuit SGDIdr_0 dynamically selects one of the voltages applied to wiring LSGD and LVSS and transmits it to wiring SGDI_0. The voltage applied to wiring SGDI_0 is selected by the control circuit 21.

[0053] Similarly, each of the driver circuits SGDIdr_1 to SGDIdr_4 is connected to the LSGD and LVSS wirings. Furthermore, driver circuits SGDIdr_1 to SGDIdr_4 are respectively connected to wirings SGDI_1 to SGDI_4. Driver circuits SGDIdr_1 to SGDIdr_4 dynamically select one voltage from those applied to wirings LSGD and LVSS and transmit it to wirings SGDI_1 to SGDI_4 respectively. The voltage applied to wirings SGDI_1 to SGDI_4 is selected by the control circuit 21.

[0054] The driver circuit CGIdr_0 is connected to wirings Nvread1, Nvread2, Nvpgm, Nvcgr, and LVSS. Furthermore, the driver circuit CGIdr_0 is connected to wiring CGI_0. The driver circuit CGIdr_0 dynamically selects one of the voltages applied to wirings Nvread1, Nvread2, Nvpgm, Nvcgr, and LVSS to transmit (or apply) to wiring CGI_0. The voltage applied to wiring CGI_0 is selected by the control circuit 21.

[0055] Similarly, driver circuits CGIdr_1 to CGIdr_n-1 are connected to wirings Nvread1, Nvread2, Nvpgm, Nvcgr, and LVSS. Furthermore, driver circuits CGIdr_1 to CGIdr_n-1 are connected to wirings CGI_1 to CGI_n-1 respectively. Driver circuits CGIdr_1 to CGIdr_n-1 dynamically select one of the voltages applied to wirings Nvread1, Nvread2, Nvpgm, Nvcgr, and LVSS and transmits it to wirings CGI_1 to CGI_n-1 respectively. The voltage applied to wirings CGI_1 to CGI_n-1 is selected by the control circuit 21.

[0056] The driver circuit SGSdr is connected to wiring LSGS and LVSS. Also, the driver circuit SGSdr is connected to wiring SGSI. The driver circuit SGSdr dynamically selects one of the voltages applied to wiring LSGS and LVSS and transmits it to wiring SGSI. The voltage applied to wiring SGSI is selected by the control circuit 21.

[0057] The timing sequence of the output voltage VSG of the control voltage generation circuit VG_sgd controlled by control circuit 21. The timing sequence of the output voltage VPGM of the control voltage generation circuit VG_pgm controlled by control circuit 21. The timing sequence of the output read voltage VCGR of the control voltage generation circuit VG_cgr controlled by control circuit 21. The timing sequence of the output voltage VREAD of the control voltage generation circuit VG_read1 controlled by control circuit 21. The timing sequence of the output voltage VREAD of the control voltage generation circuit VG_read2 controlled by control circuit 21. The timing sequence of the output voltage VSG of the control voltage generation circuit VG_sgs controlled by control circuit 21.

[0058] Driver 15 may include additional voltage generation circuitry. This additional voltage generation circuitry generates voltages other than the voltages VSG, VPGM, and VCGR used for data read, write, and erase operations. An example of such voltage is the voltage VPASS. The voltage VPASS is supplied to driver circuits CGIdr_0 to CGIIdr_n-1. Driver circuits CGIdr_0 to CGIIdr_n-1 transmit the voltage VPASS to wirings CGI_0 to CGII_n-1 respectively.

[0059] Figure 6 shows the classification of the driver circuits in the memory device of the first embodiment. As shown in Figure 6, the driver circuits CGIdr_0 to CGIdr_n-1 are divided into three groups. The first group contains driver circuits CGIdr_0 to CGIdr_k-1, where k is an integer less than or equal to n-1. The second group contains driver circuits CGIdr_k to CGIdr_q-1, where q is an integer greater than k but less than or equal to n-1. The third group contains driver circuits CGIdr_q to CGIdr_n-1.

[0060] In other words, the first group includes driver circuits CGIdr connected to a plurality of word lines WL closest to the select gate line SGSL. The third group includes driver circuits CGIdr connected to a plurality of word lines WL closest to the select gate line SGDL. The second group includes driver circuits CGIdr connected to word lines WL, wherein the word lines WL are located between the word lines WL connected to the first group of driver circuits CGIdr and the word lines WL connected to the third group of driver circuits CGIdr.

[0061] The following are instances where the driver circuit CGIdr included in Group 1 is referred to as driver circuit CGIdra. The driver circuit CGIdr included in Group 2 is referred to as driver circuit CGIdrb. The driver circuit CGIdr included in Group 3 is referred to as driver circuit CGIdrc.

[0062] Driver circuits CGIdra_0 to CGIdra_k-1 are connected to wiring CGI_0 to CGI_k-1 respectively. Driver circuits CGIdrb_k to CGIdrb_q-1 are connected to wiring CGI_k to CGI_q-1 respectively. Driver circuits CGIdrc_q to CGIdrc_n-1 are connected to wiring CGI_q to CGI_n-1 respectively.

[0063] There are cases where the character lines WL connected to the CGI via the column decoder 16 (more specifically, the transistor XS in the column decoder 16) are referred to as character lines WLa, WLb, or WLc, respectively. Lines CGI_0 to CGI_k-1 are connected to character lines WLa_0 to WLa_k-1 via the column decoder 16, respectively. Lines CGI_k to CGI_q-1 are connected to character lines WLb_k to WLb_q-1 via the column decoder 16, respectively. Lines CGI_q to CGI_n-1 are connected to character lines WLc_q to WLc_n-1 via the column decoder 16, respectively.

[0064] Figure 7 shows some of the components of the driver of the memory device in the first embodiment and the connections of the components. Figure 7 only shows the voltage generation circuits VG_read1 and VG_read2, the driver circuits CGIdr (CGIdra, CGIdrb, and CGIdrc), and the control circuit 21.

[0065] The driver circuits CGIdra, CGIdrb, and CGIdrc each contain transistors TTr1 and TTr2.

[0066] Each transistor TTr1 of the driver circuit CGIdra is connected between wiring Nvread1 and any of wirings CGI_0 to CGI_k-1. Each transistor TTr1 of the driver circuit CGIdra receives voltage VRDECH1a at its gate. Voltage VRDECH1a has a magnitude that allows transistor TTr1 to transmit the potential at terminal 1, i.e., the voltage Vread received at terminal 1, to terminal 2. Voltage VRDECH1a is supplied by control circuit 21.

[0067] Each transistor TTr2 in the driver circuit CGIdra is connected between wiring Nvread2 and any of wirings CGI_0 to CGI_k-1. Each transistor TTr2 in the driver circuit CGIdra receives voltage VRDECH2a at its gate. Voltage VRDECH2a has a magnitude sufficient to cause transistor TTr2 to transfer the potential at terminal 1 (i.e., the voltage Vread received at terminal 1) to terminal 2. Voltage VRDECH2a is supplied by the control circuit 21.

[0068] Each transistor TTr1 of the driver circuit CGIdrb is connected between wiring Nvread1 and any of wirings CGI_k to CGI_q-1. Each transistor TTr1 of the driver circuit CGIdrb receives voltage VRDECH1b at its gate. Voltage VRDECH1b has a magnitude that allows transistor TTr1 to transmit the potential at terminal 1, i.e., the voltage Vread received at terminal 1, to terminal 2. Voltage VRDECH1b is supplied by control circuit 21.

[0069] Each transistor TTr2 in the driver circuit CGIdrb is connected between wiring Nvread2 and any of wirings CGI_k to CGI_q-1. Each transistor TTr2 in the driver circuit CGIdrb receives voltage VRDECH2b at its gate. Voltage VRDECH2b has a magnitude sufficient to cause transistor TTr2 to transfer the potential at terminal 1 (i.e., the voltage Vread received at terminal 1) to terminal 2. Voltage VRDECH2b is supplied by the control circuit 21.

[0070] Each transistor TTr1 in the driver circuit CGIdrc is connected between wiring Nvread1 and any of wirings CGI_q to CGI_n-1. Each transistor TTr1 in the driver circuit CGIdrc receives voltage VRDECH1c at its gate. Voltage VRDECH1c has a magnitude sufficient to cause transistor TTr1 to transfer the potential at terminal 1 (i.e., the voltage Vread received at terminal 1) to terminal 2. Voltage VRDECH1c is supplied by the self-control circuit 21.

[0071] Each transistor TTr2 in the driver circuit CGIdrc is connected between wiring Nvread2 and any of wirings CGI_q to CGI_n-1. Each transistor TTr2 in the driver circuit CGIdrc receives voltage VRDECH2c at its gate. Voltage VRDECH2c has a magnitude sufficient to cause transistor TTr2 to transfer the potential at terminal 1 (i.e., the voltage Vread received at terminal 1) to terminal 2. Voltage VRDECH2c is supplied by the self-control circuit 21.

[0072] Control circuit 21 supplies a start signal VGEN1 to voltage generation circuit VG_read1. Voltage generation circuit VG_read1 operates during the period when it receives the valid start signal VGEN1, that is, it applies voltage Vread to wiring Nvread1.

[0073] Control circuit 21 supplies a start signal VGEN2 to voltage generation circuit VG_read2. Voltage generation circuit VG_read2 operates during the period when it receives the valid start signal VGEN2, that is, it applies voltage Vread to wiring Nvread2.

[0074] 1.2. Actions The memory device 1 can store more than two bits of data in a single cellular transistor MT. Figure 8 shows an example of the distribution of threshold voltages of the cellular transistors storing three bits of data in the memory device of the first embodiment, and the matching of the data. The threshold voltage of each cellular transistor MT is based on the amount of electrons in the charge accumulation membrane CA and has a magnitude corresponding to the stored data. When storing three bits, each cellular transistor MT is in one of the states "S0", "S1", "S2", "S3", "S4", "S5", "S6", and "S7" corresponding to the threshold voltage. The cellular transistor MTs in the states "S0", "S1", "S2", "S3", "S4", "S5", "S6", and "S7" have progressively higher threshold voltages. When the threshold voltage is reduced by erasing data, the cellular transistor MT transitions to the "S0" state.

[0075] By writing data, the cellular transistor (MT) of the object being written to maintain the "S0" state or transition to any of the "S1", "S2", "S3", "S4", "S5", "S6", and "S7" states based on the written data. Even multiple cellular transistors (MTs) that store the same 3-bit data may have different threshold voltages. The set of threshold voltages in a certain state is called the threshold voltage lobe.

[0076] Each state can be assigned 3 bits of data in any form. In one example, each state is treated as having the following 3 bits of data. In the following “αβγ”, α, β, and γ represent the values ​​of the upper, middle, and lower bits, respectively. "S0" status: "111" "S1" status: "110" "S2" status: "100" "S3" status: "000" "S4" status: "010" "S5" status: "011" "S6" status: "001" "S7" status: "101" Data readout is based on the determination of the state of the cellular transistor MT of the readout object. To determine the state, multiple readout voltages VCGR of different magnitudes are used. When the cellular transistor MT has a threshold voltage VCGR or higher, it remains open even if the VCGR is received at the control gate electrode; when the threshold voltage is below VCGR, it is turned on when the VCGR is received at the control gate electrode. Based on this, it is determined whether the threshold voltage of the cellular transistor MT of the readout object exceeds the readout voltage VCGR.

[0077] The reading voltages V1, V2, V3, V4, V5, V6, and V7 are used to determine whether the target cellular transistor MT is in a state higher than "S0", "S1", "S2", "S3", "S4", "S5", "S6", and "S7". The reading voltages V1, V2, V3, V4, V5, V6, and V7 increase sequentially. The group of bits that indicate whether the cellular transistor MT is on or off when reading voltages V1, V2, V3, V4, V5, V6, and V7 are displayed (data readout) and are respectively named 1R, 2R, 3R, 4R, 5R, 6R, and 7R.

[0078] A page is formed by groups of bit data at the same position (bit) of the cellular transistor MT of each cell unit CU. The group (or bit row) of the lowest-order (first bit from the bottom) bits (lower part bits) of the cellular transistor MT of each cell unit CU is called the lower page. The group (or bit row) of the second bit (middle bit) from the lowest-order of the cellular transistor MT of each cell unit CU is called the middle page. The group (or bit row) of the third bit (upper part bits) from the lowest-order of the cellular transistor MT of each cell unit CU is called the upper page.

[0079] The lower page is read using 1R and 5R. 1R and 5R can be used to determine the data on the lower page.

[0080] The intermediate page is read using 2R, 4R, and 6R. The data on the intermediate page can be determined by 2R, 4R, and 6R.

[0081] The top page is read using 3R and 7R. 3R and 7R can be used to determine the data on the top page.

[0082] The voltage VREAD has a magnitude that causes the cellular transistor MT to turn on regardless of the state of the cellular transistor MT.

[0083] Figure 9 shows one state of the driver during data readout of the memory device in the first embodiment. As shown in Figure 9, transistor TTr1 of driver circuit CGIdra receives voltage VREDCH1a at its gate. Also, transistor TTr2 of driver circuit CGIdra receives voltage VREDCH2a at its gate. Therefore, driver circuit CGIdra is in a state where the potential of wiring Nvread1 can be transmitted to wiring CGI. Hereinafter, a state in which a transistor receives a voltage at its gate that is large enough to transmit the potential at terminal 1 of the transistor to terminal 2 is called transistor ON. A state in which a voltage is applied to an ON transistor is called a high voltage level (H). On the other hand, a state in which a transistor does not receive a voltage at its gate that is large enough to transmit the potential at terminal 1 of the transistor to terminal 2 is called transistor OFF. A state in which no voltage is applied to an OFF transistor is called a low voltage level (L).

[0084] The transistor TTr1 of the driver circuit CGIdrb receives a low-level voltage VREDCH1b at its gate. Conversely, the transistor TTr2 of the driver circuit CGIdrb receives a high-level voltage VREDCH2b at its gate. Therefore, the driver circuit CGIdrb is in a state where it can transmit the potential of wiring Nvread2 to wiring CGI.

[0085] The transistor TTr1 in the driver circuit CGIdrc receives a high-level voltage VREDCH1c at its gate. Conversely, the transistor TTr2 in the driver circuit CGIdrc receives a low-level voltage VREDCH2c at its gate. Therefore, the driver circuit CGIdrc is in a state where it can transmit the potential of wiring Nvread1 to wiring CGI.

[0086] Thus, in each of the driver circuits CGIdra, CGIdrb, and CGIdrc, one of the transistors TTr1 and TTr2 remains on, while the other remains off.

[0087] Figure 10 shows the potentials of several wirings during data readout of the memory device in the first embodiment, along the timeline. The operations described below with reference to Figure 10 are not dependent on the page to which the data is read out. Figure 10 shows data readout from the lower page as an example. Figure 10 also shows the block BLK containing the cell CU to which the data is read out. Hereinafter, the cell CU to which the data is read out may be referred to as the selection cell CUsel. The character line WL connected to the cell CU to which the data is read out may be referred to as the selection character line WLsel. The selection character line WLsel may be any of the character lines WLa, WLb, and WLc. Character lines WL other than the selection character line WLsel may be referred to as non-selection character lines WL. The string unit SU containing the selection cell CU may be referred to as the selection string unit SUsel. String units SU other than the selection string unit SUsel may be referred to as non-selection string units SU.

[0088] At the start of the period shown in Figure 10, each wiring and signal has the following potentials or levels. Bit line BL, source line SL, and select gate line SGSL are subjected to a ground voltage VSS, and therefore have a ground potential Vss. Potential VSS is the potential obtained by the wiring receiving the ground voltage VSS. Selected select gate line SGDL and unselected (non-selected) select gate line SGDL are subjected to a ground voltage VSS, and therefore have a ground potential VSS. Selected select gate line SGDL is the select gate line SGDL connected to the select string unit SUsel. Non-selected select gate line SGDL is the select gate line SGDL connected to the string unit SU other than the select string unit SU.

[0089] The start signals VGEN1 and VGEN2 are at a low level. Therefore, the voltage generation circuits VG_read1 and VG_read2 do not operate, and thus, the wirings Nvread1 and Nvread2 have a ground potential VSS. The character lines WLa, WLb, WLc and the select character line Wlsel are applied with a ground voltage VSS, and therefore have a ground potential VSS.

[0090] In Figure 10, solid lines represent examples where character line WLsel is selected as character line WLb. Dashed lines in Figure 10 represent examples where character line WLsel is selected as character line WLa or WLc.

[0091] The period from time t1 to time t5 is the period for preparing data for reading out.

[0092] At time t1, the selected gate line SGDL, the unselected gate line SGDL, and the selected gate line SGSL are all subjected to a voltage VSG. This sets the potential of the selected gate line SGDL, the unselected gate line SGDL, and the selected gate line SGSL to the potential VSG, thus turning on the selected gate transistors DT and ST.

[0093] At time t2, the start signal VGEN1 is set to a high level. This initiates the operation of the voltage generation circuit VG_read1. Upon activation, the potential of the wiring Nvread1 rises, reaching potential VREAD at time t4. Potential VREAD is obtained by the wiring receiving voltage VREAD.

[0094] At the same time that the potential of wiring Nvread1 begins to rise, the potentials of word lines WLa and WLc rise from time t2, and have potential VREAD at time t4.

[0095] At time t3, the start signal VGEN2 is set to a high level. This initiates the operation of voltage generation circuit VG_read2. Upon activation, the potential of wiring Nvread2 rises, reaching potential VREAD at time t5. Voltage generation circuit VG_read1 begins operation after VG_read2. Therefore, wiring Nvread1 reaches potential VREAD before wiring Nvread2. Simultaneously with the rise in potential of wiring Nvread2, the potential of word line WLb rises from time t3, reaching potential VREAD at time t5.

[0096] From time t1 to time t5, the driver 15 has the state shown in Figure 9.

[0097] At time t5, the potential of the select word line WLsel is set to the ground potential VSS. This is achieved by the driver circuit CGIdrb, which is connected to the select word line WLsel, cutting off the voltage generation circuit VG_read2 and the wiring CGI, and connecting the node receiving the ground voltage VSS to the wiring CGI.

[0098] At time t5, the potential of the non-selected gate line SGDL is set to the ground potential VSS.

[0099] The actual data readout period begins after time t7. After time t7, the source line SL continues to maintain the ground potential VSS. The potential of the source line SL can be maintained at a slightly higher potential than the ground potential VSS. From time t7 onwards, the potential of the bit line BL is set to potential VBL. Potential VBL is higher than the ground potential VSS.

[0100] Starting at time t8, a readout voltage VCGR is applied based on the page size of the data readout object in the select cell CUSEL. If, as currently described, the data is read from the lower page, then at time t8, the potential of the select word line WLsel is set to potential V1. Potential V1 is the potential obtained by applying the readout voltage V1 through the wiring.

[0101] At time t9, the potential of the select character line WLsel is set to potential V5. Potential V5 is the potential obtained by applying a read voltage V5 through the wiring.

[0102] Time t10 is the timing sequence for ending the readout of data from the select cell CUsel to the select gate lines SGDL and SGSL, and the word line WL. That is, the action at time t10 occurs simultaneously with the termination of the readout voltage VCGR, which is determined based on the page of the data readout target. In the case of readout based on the lower page, the action at time t10 occurs simultaneously with the termination of the applied voltages V1 and V5. At time t10, the potentials of the select gate lines SGDL and SGSL, and the word line BL, connected to the select string cell SUsel, are set to ground potential VSS.

[0103] At time t10, the start signal VGEN1 is set to low level. As a result, the potential of wiring Nvread1 becomes the ground potential VSS, and the potentials of word lines WLa and WLc become the ground potential VSS.

[0104] At time t10, the start signal VGEN2 is set to low level. As a result, the potential of wiring Nvread2 becomes the ground potential VSS, and the potential of word line WLb becomes the ground potential VSS.

[0105] The actions in memory device 1 can also be applied to verification performed during data writing. Figure 11 shows a summary of the write operations in the memory device of the first embodiment along time. As shown in Figure 11, memory device 1 repeatedly executes a programming cycle during the write operation. Each programming cycle includes programming and verification.

[0106] Programming is an action used to raise the threshold voltage of the transistor MT that is the data being written to. During data writing, there is a transistor MT that is the data being written to, referred to as a select transistor MTsel. During programming, the select transistor MTsel is set to a programming state or a non-programmable state. Whether it is set to a programming state or a non-programmable state depends on the target state of each select transistor MTsel. The target state is the intended state that each select transistor MTsel changes to based on the data being written. When a select transistor MTsel has a threshold voltage that is not determined to be included in the target state, it is set to a programming state. When a select transistor MTsel has a threshold voltage that is determined to be included in the target state, it is set to a non-programmable state.

[0107] During programming, programming voltages VPGM of various magnitudes are applied to the select word line WLsel.

[0108] The programming voltage VPGM increases with each cycle number. When the programming voltage VPGM is applied to the select word line WLsel, the threshold voltage of the select cell transistor MTsel in the programmed state rises. The rise in the threshold voltage of the select cell transistor MTsel in the disabled programming state is suppressed.

[0109] The verification process involves confirming whether the threshold voltage of the selected cellular transistor MTsel is above the threshold voltage that is considered to be included in the target state; this is known as data readout. Hereinafter, "data readout" is used to refer to the verification process. During verification, it is determined whether the threshold voltage of the selected cellular transistor MTsel is above the variable-sized verification voltage Vp. The sensing amplifier 17 outputs data based on whether the threshold voltage of each selected cellular transistor MTsel is above the verification voltage Vp. When the threshold voltage of the selected cellular transistor MTsel is above the verification voltage Vp, the output displays data indicating successful verification. The verification voltage Vp is dependent on the target state and is below the minimum threshold voltage that the selected cellular transistor MTsel should possess to transition to the target state. In one example, the verification voltages Vp1, Vp2, Vp3, Vp4, Vp5, Vp6, and Vp7 used for states “S0”, “S1”, “S2”, “S3”, “S4”, “S5”, “S6”, and “S7” are the same as the readout voltages V1, V2, V3, V4, V5, V6, and V7, respectively. In another example, the verification voltages Vp1, Vp2, Vp3, Vp4, Vp5, Vp6, and Vp7 are slightly lower than the readout voltages V1, V2, V3, V4, V5, V6, and V7, respectively.

[0110] Figure 12 shows the data writing sequence in the memory device of the first embodiment. As shown in Figure 12, data is written in the order from the cell CU closer to the bit line BL to the cell CU closer to the source line SL. That is, data is written to the cell CU closer to the bit line BL first. The cellular transistor MT of the cell CU that has not been written with data is in the erase state, i.e., the "S0" state.

[0111] Figures 13-15 show the potentials of several nodes in the memory device of the first embodiment during the verification period along the timeline.

[0112] Figure 13 shows the data writing for cells CU belonging to group 3. Group 3 includes cells CU connected to word lines WLc. That is, group 3 includes cells CU_q to CU_n-1. Cells CU_q to CU_n-1 are cells CU connected to word lines WLc_q to WLc_n-1 respectively, and are cells CU connected to the driver circuit CGIdrc of group 3. During the verification shown in Figure 13, by the same control as described with reference to Figure 9, each of the driver circuits CGIdra and CGIdrb is in a state that can transmit the potential of wiring Nvread1 to the wiring CGI to which it is connected. On the other hand, during the verification shown in Figure 13, by the same control as described with reference to Figure 9, the driver circuit CGIdrc is in a state that can transmit the potential of wiring Nvread2 to the wiring CGI to which it is connected.

[0113] The waveform shown in Figure 13 differs from that shown in Figure 10 in that the word line WL with the potential set to VREAD is different. As shown in Figure 13, simultaneously with the potential of line Nvread1 rising from time t2, the potentials of word lines WLa and WLb also rise from time t2, exhibiting potential VREAD. Simultaneously with the potential of line Nvread2 rising from time t3, the potential of word line WLc also rises from time t3, exhibiting potential VREAD.

[0114] Figure 14 shows the data writing for cells CU belonging to Group 2. Group 2 includes cells CU connected to word lines WLb. That is, Group 2 includes cells CU_k to CU_q-1. Cells CU_k to CU_q-1 are cells CU connected to word lines WLb_k to WLb_q-1 respectively, and are cells CU connected to the driver circuit CGIdrb of Group 2. During the verification shown in Figure 14, by means of the same control as described with reference to Figure 9, the driver circuit CGIdrc is in a state that can transmit the potential of wiring Nvread1 to the wiring CGI to which it is connected. On the other hand, during the verification shown in Figure 14, by means of the same control as described with reference to Figure 9, each of the driver circuits CGIdra and CGIdrb is in a state that can transmit the potential of wiring Nvread2 to the wiring CGI to which it is connected.

[0115] The waveform shown in Figure 14 differs from that in Figure 10 in that the word line WL with the potential set to VREAD is different. As shown in Figure 14, simultaneously with the rise in potential of line Nvread1 from time t2, the potential of word line WLc also rises from time t2, exhibiting potential VREAD. Simultaneously with the rise in potential of line Nvread2 from time t3, the potentials of word lines WLa and WLb also rise from time t3, exhibiting potential VREAD.

[0116] Figure 15 shows the data writing for cells CU belonging to Group 1. Group 1 includes cells CU connected to word lines WLa. That is, Group 1 includes cells CU_0 to CU_k-1. Cells CU_0 to CU_k-1 are cells CU connected to word lines WLa_0 to WLa_k-1 respectively, and are cells CU connected to the driver circuit CGIdra of Group 1. During the verification shown in Figure 15, by the same control as described with reference to Figure 9, each of the driver circuits CGIdra and CGIdrc is in a state that can transmit the potential of wiring Nvread1 to the wiring CGI to which it is connected. On the other hand, during the verification shown in Figure 15, by the same control as described with reference to Figure 9, the driver circuit CGIdrb is in a state that can transmit the potential of wiring Nvread2 to the wiring CGI to which it is connected.

[0117] The waveform shown in Figure 15 differs from that in Figure 10 in that the word line WL with the potential set to VREAD is different. As shown in Figure 15, simultaneously with the rise in potential of line Nvread1 from time t2, the potentials of word lines WLa and WLc also rise from time t2, exhibiting potential VREAD. Simultaneously with the rise in potential of line Nvread2 from time t3, the potential of word line WLb also rises from time t3, exhibiting potential VREAD.

[0118] 1.3. Advantages (Effects) According to the first embodiment, as described below, a memory device for high-speed data readout is provided.

[0119] In memory devices such as memory device 1, when voltage is first applied to the wiring used for data readout (hereinafter referred to as the initial data readout phase), at least all string cells SU in the block BLK containing the select cell CU are connected to the bit line BL and / or the source line SL. For this purpose, the wiring potential is set as follows: Except during traversal data readout, when the potentials of the select gate line SGSL and the selected select gate line SGDL are set to potential VSG, during the initial data readout phase, the potential of the select gate line SGDL of the non-selected string cell SU is also set to potential VSG. Furthermore, during the initial data readout phase, except for the select word line WL, a voltage VREAD is temporarily applied to the select word line WLsel. In this way, the cellular transistor MT is turned on, forming a channel of the cellular transistor MT, and then each channel of the cellular transistor MT is connected to the bit line BL and the source line SL through the channels of other cellular transistor MTs. This suppresses readout interference caused by the formation of hot carriers during data readout. The following section refers to the action of turning on the select gate transistor DT of the non-selective string cell SU at the initial stage of data readout as the non-selective string discharge action.

[0120] During the non-selective string discharge operation, the lower the threshold voltage of the cellular transistor MT, the earlier it is turned on. Therefore, the channel region of the cellular transistor MT sandwiched by the still-disconnected cellular transistor MT is in a state of voltage boost (having a higher potential) due to capacitive coupling with the word line WL with potential VREAD. Therefore, the capacitance of the channel region of the disconnected cellular transistor MT does not function as the load capacitance of the word line WL connected to these disconnected cellular transistor MTs. As time passes and the number of connected cellular transistor MTs increases, the word line WL with the added channel region capacitance increases as the voltage boost in the channel region ends.

[0121] Furthermore, by turning on the cellular transistor MT, the channel region of the adjacent cellular transistor MT connected to the turned-on cellular transistor MT is connected to the turned-on cellular transistor MT. At this time, the boost voltage of the channel region of the adjacent cellular transistor MT is released. When the turned-on cellular transistor MT has a ground potential VSS by connecting to the bit line BL or the source line SL, the potential of the channel region of the adjacent cellular transistor MT decreases towards the ground potential VSS. At this time, because the word line WL is capacitively coupled to the channel region in the adjacent cellular transistor MT, the potential of the word line WL of the adjacent cellular transistor MT decreases. This hinders the charging of the word line WL, thereby prolonging the time required for data readout.

[0122] On the other hand, the non-selective string discharge operation in the BLK block where no data has been written differs from the non-selective string discharge operation in the BLK block where data has been written. Hereinafter, the BLK block containing the cell CU with written data will be referred to as a closed block, and the BLK block not containing the cell CU with written data (i.e., in the erased state) will be referred to as an open block. In the initial stage of the non-selective string discharge operation, unlike the closed block, the open block lacks a channel region for voltage boosting during the non-selective string discharge operation. Therefore, in the initial stage, due to the load capacitance for the word line WL, the potential rise of the word line WL in the open block is slower than that in the closed block. On the other hand, after the initial stage of the non-selective string discharge operation, as mentioned above, the potential of the word line WL decreases because the voltage boost in the channel region of the newly connected cell transistor MT ends; this situation does not occur in the open block. Therefore, after the initial stage of the non-selective string discharge operation, the charging speed of the word line WL in the open block is faster. Thus, in the open block, the charging speed of the word line WL is slower in the initial stage, but ultimately completes charging of the word line WL earlier than that of the word line WL in the closed block.

[0123] To accelerate the charging of the character line WL, the capability of the voltage generation circuit is considered. However, memory devices contain multiple blocks BLK and serial units SU to achieve large memory capacity. Increasing the capability of the voltage generation circuit increases the peak current. Consequently, the peak current may exceed the upper limit, making it impossible to further increase the capability of the voltage generation circuit.

[0124] According to the first embodiment, the voltage VREAD is applied to the word line WL closer to the bit line BL and the source line SL before the voltage VREAD is applied to the word lines WL farther from the bit line BL and the source line SL. Therefore, the word line WL closer to the bit line BL and the source line SL has a potential VREAD earlier than the word lines WL farther from the bit line BL and the source line SL. Therefore, the cell transistor MT closer to the bit line BL and the source line SL is turned on at the initial stage of the non-selective string discharge operation. This helps multiple cell transistor MTs to be turned on at the initial stage of the non-selective string discharge operation, forming a situation close to the formation of an open block. Therefore, the charging of the word line WL is advanced. Furthermore, since multiple cell transistor MTs are turned on at the initial stage of the non-selective string discharge operation, fewer cell transistor MTs are included in the boosted channel region. Therefore, the potential drop of the word line WL caused by the potential drop of the boosted channel region when the cell transistor MTs are turned on is suppressed. This helps to suppress the current consumption of memory device 1.

[0125] According to the first embodiment, during the verification period, the voltage VREAD is applied to the word line WL that is closer to the bit line BL and the source line SL, or to the word line WL connected to the cell CU that has not been written with data, before the voltage VREAD is applied to the select word line WL. Therefore, based on the same principle as for data readout, a state close to that formed by open blocks is created in the initial stage of the non-selection string discharge operation. Thus, the charging of the word line WL is advanced, and the current consumption of the memory device 1 is suppressed.

[0126] 1.4. Variation Example During data reading, only one of the driver circuits CGIdra and CGIdrb can output the voltage VREAD first. That is, one of the driver circuits CGIdra and CGIdrb can be controlled in the same way as the driver circuit CGIdrb.

[0127] Data can be written sequentially from the cell CU closer to the source line SL to the cell CU closer to the bit line BL. That is, data is written to the cell CU closer to the bit line BL first. In this case, the descriptions related to the word line Wla, as shown in Figures 13-15, and the descriptions related to the word line WLc will be replaced for the word line WLc that were applied first to the word line VREAD.

[0128] 2. Second Implementation Form The difference between the second embodiment and the first embodiment lies in the method of applying the voltage VREAD.

[0129] Figure 16 shows the components and connection examples of the voltage generation circuit of the memory device in the second embodiment. As shown in Figure 16, the voltage generation circuit VG (i.e., each of VG_read1 and VG_read2) includes a charge pump circuit 22 and a limiter circuit 23.

[0130] The charge pump circuit 22 receives the power supply voltage and generates a higher voltage from it. The output of the charge pump circuit 22 functions as wiring Nvread (i.e., wiring Nvread1 or Nvread2). The charge pump circuit 22 receives the start signal CPEN. The charge pump circuit 22 operates during the period when it receives the valid start signal CPEN.

[0131] The limiter circuit 23 is a circuit that controls the operation of the charge pump circuit 22 based on the output of the charge pump circuit 22. The limiter circuit 23 includes a resistor 231, a variable resistor circuit 232, and an operational amplifier 233.

[0132] Resistor 231 is connected between node Vread and node VMON. Resistor 231 has a constant value.

[0133] A variable resistor circuit 232 is connected between node NMON and the node at ground potential VSS. The variable resistor circuit 232 receives a control signal SVM. The variable resistor circuit 232 displays a resistance based on the value displayed by the control signal SVM. In one example, the control signal SVM contains multiple bits. The control signal SVM is supplied from the control circuit 21. A voltage based on the value of the variable resistor circuit 232 is applied to node VMON.

[0134] Operational amplifier 233 receives a reference voltage VREF at its non-inverting input terminal. Operational amplifier 233 is connected to node VMON at its inverting input terminal. Operational amplifier 233 outputs a start signal CPEN at its output terminal. During the period when the potential of node VMON is lower than the magnitude of the reference voltage VREF, the established start signal CPEN is output. During the period when the potential of node VMON is higher than the magnitude of the reference voltage VREF, an invalid (or negated) logic signal CPEN is output. By controlling the value of the start signal CPEN, the magnitude of the variable resistor circuit 232 is controlled, thereby controlling the operation and non-operation of the charge pump circuit 22, and consequently controlling the potential rise of the wiring Nvread.

[0135] Both voltage generation circuits VG_read1 and VG_read2 are started by the start signal VGEN. The start signal VGEN is supplied by the self-control circuit 21. The start signals VGEN1 and VGEN2 are the same as those in the first embodiment, and the start signals VGEN1 and VGEN2 may have the same logic.

[0136] Figure 17 shows the potentials of several lines during data readout of the memory device in the second embodiment along time. As shown in Figure 17, at time t2, the start signal VGEN is set to a high level. This causes voltage generation circuits VG_read1 and VG_read2 to start operating. Meanwhile, the control circuit 21 of the driver 15 controls the voltage generation circuits VG_read1 and VG_read2 in different ways. That is, the control circuit 21 causes the potentials of lines Nvread1 and Nvread2 to rise at the same time, but at different rates. The control circuit 21 causes the potential of line Nvread1 to rise at a faster rate than the potential of line Nvread2. This is achieved by making the value of the control signal SVM supplied to voltage generation circuit VG_read1 different from the value of the control signal SVM supplied to voltage generation circuit VG_read2. From time t2 to time t4, the value of the control signal SVM can be constant or variable. Because the potential of wiring Nvread1 rises faster than that of wiring Nvread2, wiring Nvread1 has a potential Vread at time t4. On the other hand, wiring Nvread2 has a potential Vread at time t5.

[0137] According to the memory device of the second embodiment, the voltage VREAD applied to the word line WL closer to the bit line BL and the source line SL rises faster than the voltage VREAD applied to the word line WL farther from both the bit line BL and the source line SL. Therefore, similar to the first embodiment, the word line WL closer to the bit line BL and the source line SL reaches a potential VREAD earlier than the word line WL farther from both the bit line BL and the source line SL. Therefore, the same advantages as the first embodiment can be obtained.

[0138] Although several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and similarly, within the scope of the invention described in the claims and its equivalents.

[0139] 1: Memory device 1R~7R: Group 2: Memory controller 10: Memory Cell Array 11: Input / output circuit 12: Logic Controller 13: Temporary Register 14: Sequencer 15: Driver 16: Column Decoder 17: Sensing Amplifier 21: Control Circuit 22: Charge pump circuit 23: Limiter Circuit 231: Resistor 232: Variable Resistor Circuit 233: Operational amplifier ADD: Address Information ALE: Signal BD: Block Decoder BL, BL_0~BL_m-1: Bit lines BLK_0~BLK_j: Blocks CB, CC, CD: Conductors ￣CE: Signal CGI, CGI_0~CGI_n-1: Wiring CGIdr_0~CGIdr_n-1: Driver circuit CGIdra, CGIdra_0~CGIdra_k-1: Driver circuit CGIdrb, CGIdrb_k ~ CGIdrb_q-1: Driver circuit CGIdrc, CGIdrc_q ~ CGIdrc_n-1: Driver circuit CLE: Signal CMD command CP: Plug CPEN: Start signal CS: Conductor CT: Conductor CU,CU_0~CU_n-1: Cell units CW: Conductor DAT: Data DQ_0~DQ_7: Input / output signals DQS: Signal DQS: Signal DT, DT_0~DT_4: Selector gate transistor H: Level IA: Charge storage membrane IB: Barrier Insulator IC: Insulator INS: Insulator IT: Tunnel Insulator L: Level LSGD: Wiring LSGS: Wiring LVSS: Wiring MP: Memory Column MT_0~MT_n-1: Cellular electrochemical crystals NS: NAND string Nvcgr, Nvpgm: Wiring Nvread1, Nvread2: Wiring RD_0~RD_j: Column decoder circuit RE: Signal ￣RE: signal RY / BY: Ready and Busy Signal S0~S7: Status SF: Semiconductor SGSdr: Driver Circuit SGDI_0~SGDI_4: Wiring SGDIdr_0~SGDIdr_4: Driver circuit SGDL, SGDL_0~SGDL_4: Select gate line SGSI: Wiring SGSL: Select Gate Line SL: Source Line ST: Selective Gate Transistor SU_0~SU_4: Serial units SVM: Control Signal t1~t5: Time points t7~t10: Time points TG: Wiring TTr1,TTr2: Transistors V1~V7: Readout voltage VBL: Potential VCGR: Readout Voltage VGEN, VGEN1, VGEN2: Start signals VG_cgr, VG_pgm, VG_read1, VG_read2, VG_sgd, VG_sgs: Voltage generation circuit VMON: Node Vp1~Vp5: Verification voltage VPGM: Programming Voltage VREAD: Voltage VREF: Reference voltage VRDECH1a, VRDECH2a, VRDECH1b, VRDECH2b, VRDECH1c, VRDECH2c: Voltage VSG: Voltage VSS: Grounding voltage XS_0~XS_n-1: Transistor XSD_0~XSD_4: Transistors XSS: Transistor ￣WE: Signal WL_0~WL_n-1: Character lines WLa, WLb, WLc: Character lines WLa_0~WLa_k-1: Character lines WLb_k~WLb_q-1: Character lines WLc_q~WLc_n-1: Character lines WLsel: Select character lines ￣WP: Signal

Claims

1. A memory device comprising: a bit line; a source line; a first transistor between the bit line and the source line; a second transistor between the first transistor and the bit line; a third transistor between the first transistor and the source line; a first word line connected to the gate of the first transistor; a second word line connected to the gate of the second transistor; and a third word line connected to the gate of the third transistor; and applying a first voltage to the source line during a first period; and applying a second voltage greater than a threshold voltage of the first, second, and third transistors to at least one of the second word line and the third word line at a first moment during the first period. During the first period, at a second time later than the first time, a third voltage above the threshold voltage of the first, second, and third cell transistors is applied to the first character line.

2. The memory device of claim 1 further comprises: a first transistor between the bit line and the second cell transistor; and a second transistor between the source line and the third cell transistor; and during the first period, the first transistor and the second transistor are kept on.

3. The memory device of claim 2 further comprises: a fourth cell transistor between the first transistor and the second transistor; and a fourth word line connected to the gate of the fourth cell transistor; and at a third time after the first period, a fourth voltage lower than the second voltage and the third voltage is applied to the fourth word line; the second voltage is applied to the second word line and the third word line from the first time until after the third time; the third voltage is applied to the first word line from the second time until after the third time.

4. The memory device of claim 3, wherein the first transistor and the second transistor remain on from the first period until after the third time.

5. The memory device of claim 4 further comprises: a fifth transistor located between the bit line and the source line, having a gate connected to the first word line; a third transistor between the bit line and the fifth transistor; and a fourth transistor between the source line and the fifth transistor; and during the first period, the third transistor and the fourth transistor are kept on.

6. The memory device as claimed in claim 5, wherein the third transistor is disconnected at the third time mentioned above.

7. The memory device of claim 6 further comprises: a sixth transistor located between the fifth transistor and the third transistor, having a gate connected to the second word line; a seventh transistor located between the fifth transistor and the fourth transistor, having a gate connected to the third word line; and an eighth transistor located between the third transistor and the fourth transistor, having a gate connected to the fourth word line.

8. A memory device comprising: a bit line; a source line; a first transistor between the bit line and the source line; a second transistor between the first transistor and the bit line; a third transistor between the first transistor and the source line; a first word line connected to the gate of the first transistor; a second word line connected to the gate of the second transistor; and a third word line connected to the gate of the third transistor; and applying a first voltage to the source line during a first period; applying a second voltage greater than or equal to a threshold voltage of the first, second, and third transistors to at least one of the second and third word lines during the first period; and applying a third voltage greater than or equal to a threshold voltage of the first, second, and third transistors to the first word line during the first period. The second voltage is reached after a second period since the voltage began to rise; and the third voltage is reached after a third period longer than the second period since the voltage began to rise.

9. The memory device of claim 8 further comprises: a first transistor between the bit line and the second cell transistor; and a second transistor between the source line and the third cell transistor; and during the first period, the first transistor and the second transistor are kept on.

10. The memory device of claim 9 further comprises: a fourth cell transistor between the first transistor and the second transistor; and a fourth word line connected to the gate of the fourth cell transistor; and at a first moment after the first period, a fourth voltage lower than the second voltage and the third voltage is applied to the fourth word line; the second voltage is applied to the second word line and the third word line from the first period until after the first moment; the third voltage is applied to the first word line from the first period until after the first moment.

11. The memory device of claim 10, wherein the first transistor and the second transistor remain on from the first period until after the first time.

12. The memory device of claim 11 further comprises: a fifth transistor located between the bit line and the source line, having a gate connected to the first word line; a third transistor between the bit line and the fifth transistor; and a fourth transistor between the source line and the fifth transistor; and during the first period, the third transistor and the fourth transistor are kept on.

13. The memory device of claim 12, wherein the third transistor is disconnected at the first time mentioned above.

14. The memory device of claim 13 further comprises: a sixth transistor located between the fifth transistor and the third transistor, having a gate connected to the second word line; a seventh transistor located between the fifth transistor and the fourth transistor, having a gate connected to the third word line; and an eighth transistor located between the third transistor and the fourth transistor, having a gate connected to the fourth word line.