Rectifier circuit and operating method thereof

Abstract

A rectifier circuit includes a transistor string, a bias generator, and a first level shifter. The transistor string includes a first transistor and a second transistor coupled in series. The bias generator is coupled to a control terminal of the second transistor, generates a first bias voltage according to a reference voltage and a output voltage of the rectifier circuit, and provides the first bias voltage to the control terminal of the second transistor. The first level shifter is coupled between a control terminal of the first transistor and the control terminal of the second transistor, shifts a voltage level of the first bias to generate a first offset voltage, and provides the first offset voltage to the control terminal of the first transistor.

Description

[Technical Field]

[0001] This invention relates to a circuit for stabilizing a power supply, and more particularly to a rectifier circuit and its operating method. [Previous Technology]

[0002] Transistors in rectifier circuits need to operate in the saturation region to function properly, for example, to filter power supply noise and perform rectification. In conventional rectifier circuits, the transistor channel is turned on by applying a constant bias voltage. However, due to the variable power supply voltage, unstable operational amplifier output voltage, and unstable rectifier circuit output voltage, this operating method cannot ensure that the transistor operates in the saturation region, which may result in poor rectifier circuit performance. [Summary of the Invention]

[0003] The present invention provides a rectifier circuit and its operating method, which can operate on a relatively wide range of power supply voltages and effectively suppress power supply noise.

[0004] The rectifier circuit of this embodiment includes a transistor string, a bias generator, and a first quasi-offsetter. The transistor string includes a first transistor and a second transistor connected in series. The bias generator is coupled to the control terminal of the second transistor, generates a first bias voltage based on a reference voltage and the output voltage of the rectifier circuit, and provides the first bias voltage to the control terminal of the second transistor. The first quasi-offsetter is coupled between the control terminals of the first transistor and the second transistor, offsets the voltage level of the first bias voltage to generate a first offset voltage, and provides the first offset voltage to the control terminal of the first transistor.

[0005] An embodiment of the present invention further provides an operation method for a rectifier circuit. The operation method includes: providing a transistor string having a first transistor and a second transistor connected in series; providing a bias generator to generate a first bias voltage based on a reference voltage and the output voltage of the rectifier circuit; providing the first bias voltage to a control terminal of the second transistor; providing a first quasi-offsetter to offset the voltage level of the first bias voltage to generate a first offset voltage; and providing the first offset voltage to a control terminal of the first transistor.

[0006] Based on the above, the rectifier circuit and its operation method of the present invention ensure that each transistor in the rectifier circuit operates in the saturation region through a level offset device, thereby maintaining the output voltage of the rectifier circuit stable.

[0007] To make the foregoing easier to understand, several embodiments with accompanying drawings are described in detail below.

Implementation Method

[0009] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description are considered to be the same or similar components when they appear in different drawings. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples within the scope of the present invention's patent application.

[0010] Please refer to Figure 1, which is a schematic diagram of a rectifier circuit 100 according to an embodiment of the present invention. As shown in Figure 1, the rectifier circuit 100 includes a transistor string 110, a bias generator 120, and a level shifter LS1. The transistor string 110 includes transistors M1 and M2. Transistors M1 and M2 are connected in series and coupled to each other. In detail, the first terminal of transistor M1 receives the power supply voltage VDD, the second terminal of transistor M1 is coupled to the first terminal of transistor M2, and the second terminal of transistor M2 forms the output terminal n2 of the rectifier circuit 100 and generates an output voltage Vout.

[0011] Bias generator 120 is coupled to the control terminal of transistor M2 at node n1. In operation, bias generator 120 generates a bias voltage Vop based on the reference voltage Vref and the output voltage Vout of rectifier circuit 100, and provides the bias voltage Vop to the control terminal of transistor M2. Level offset device LS1 is coupled between the control terminals of transistor M1 and transistor M2. In operation, level offset device LS1 is used to offset the voltage level of bias voltage Vop to generate offset voltage Vg1, and provides the offset voltage Vg1 to the control terminal of transistor M1. The level shifter LS1 is a low-to-high level shifter. Thus, the voltage difference (source voltage) VDS_2 between the first and second terminals of transistor M2 can be expressed as: VDS_2 = (Vg1 - Vop) - (Vth1 - Vth2) (1), where Vth1 and Vth2 are the threshold voltages of transistors M1 and M2, respectively, and the voltage difference (Vg1 - Vop) is related to the offset provided by the level shifter LS1. Therefore, the source voltage of transistor M2 can be adjusted by the level shifter LS1 to ensure that transistor M2 operates within the saturation region.

[0012] In this embodiment, the bias generator 120 can be an operational amplifier. When the bias generator 120 is an operational amplifier, its coupling and operation are as follows: The first input terminal of the operational amplifier is coupled to the output terminal n2 of the rectifier circuit 100. The second input terminal of the operational amplifier receives the reference voltage Vref. The output terminal of the operational amplifier is coupled to the control terminal of the transistor M2 at node n1 and generates a bias voltage Vop. In some embodiments, the first input terminal is the negative input terminal of the operational amplifier, and the second input terminal can be the positive input terminal of the operational amplifier, that is, the operational amplifier is in a negative feedback state. In this embodiment, the level offset LS1 can be implemented using a level offset circuit well known to those skilled in the art, without fixed limitations.

[0013] Furthermore, the rectifier circuit 100 may further include a load Load_R. The load Load_R is coupled between the output terminal n2 of the rectifier circuit 100 and the reference ground terminal GND. The reference ground voltage of the reference ground terminal GND is less than the power supply voltage VDD, but is not limited to zero. In this embodiment, the load Load_R can actually be an internal circuit of the rectifier circuit 100.

[0014] Incidentally, in this embodiment, the control terminal of transistor M1 can be coupled to level offset device LS1 through resistor R1, and thereby receive offset voltage Vg1.

[0015] Please refer to Figure 2, which is a schematic diagram of a rectifier circuit 200 according to an embodiment of the present invention. In addition to the circuit configuration identical to that of the rectifier circuit 100 described above, the transistor string of the rectifier circuit 200 may further include a transistor M3. The transistor M3 is coupled to the path where the transistor M1 receives the power supply voltage VDD, and the control terminal of the transistor M3 can receive a bias voltage VB, which can be a constant voltage. In this embodiment, the rectifier circuit 200 may further include a resistor R2 on the path where the control terminal of the transistor M3 receives the bias voltage VB, so that the control terminal of the transistor M3 can receive the bias voltage VB through the resistor R2. Furthermore, it should be understood that the number of transistors in the transistor string 110 is merely illustrative and is not intended to limit the present invention. Those skilled in the art can increase the number of transistors coupled in series in the transistor string 110 according to actual needs.

[0016] In this embodiment, transistors M1 to M3 can all be N-type transistors.

[0017] Please refer to Figure 3, which is a schematic diagram of a rectifier circuit 300 according to an embodiment of the present invention. The rectifier circuit 300 has a similar circuit architecture to the rectifier circuit 200 of the aforementioned embodiment, and the same parts will not be described in detail here. It is worth noting that, unlike the rectifier circuit 200, the rectifier circuit 300 further includes a level offsetter LS2. As shown in Figure 3, the level offsetter LS2 is coupled between the control terminal of transistor M1 and the control terminal of transistor M3. In operation, the level offsetter LS2 is used to offset the voltage level of the offset voltage Vg1 to generate an offset voltage Vg2, and provides the offset voltage Vg2 as a bias voltage to the control terminal of transistor M3. Similar to the level offsetter LS1, the level offsetter LS2 is a low-to-high level offsetter, which can be used to adjust the drain voltage of transistor M1 to ensure that transistor M1 is operated in the saturation region. Incidentally, in this embodiment, the control terminal of transistor M3 can be coupled to level offset device LS2 through resistor R2, thereby receiving offset voltage Vg2. The other configurations of rectifier circuit 300 are the same as those of rectifier circuit 200, and therefore will not be described further here.

[0018] Incidentally, in this embodiment, level offsetters LS1 and LS2 may provide the same voltage level offset, or may provide different voltage level offsets, without any specific limitation. Level offsetters LS1 and LS2 may have the same circuit architecture.

[0019] Please refer to Figures 2 and 4 together. Figure 4 is a schematic diagram of a rectifier circuit 400 according to an embodiment of the present invention. In this embodiment, those skilled in the art can selectively couple a capacitor between the control terminal of at least one of the transistors M1, M2, and M3 and the reference ground terminal GND, according to actual needs. In addition to the same circuit configuration as the rectifier circuit 200 described above, in Figure 4, the rectifier circuit 400 further includes capacitors C1, C2, and C3. Capacitors C1, C2, and C3 are respectively coupled between the control terminal of transistors M1, M2, and M3 and the reference ground terminal GND.

[0020] Furthermore, as shown in Figure 4, transistors M1 and M2 are coupled to each other at coupling node n3; transistors M2 and M3 are coupled to each other at coupling node n4. Those skilled in the art can also selectively couple capacitors between at least one of coupling nodes n3 and n4 and the reference ground terminal GND according to actual needs. In this embodiment, the rectifier circuit 400 may further include capacitors C4 and C5. Capacitor C4 is coupled between coupling node n3 and the reference ground terminal GND; capacitor C5 is coupled between coupling node n4 and the reference ground terminal GND. Other configurations of the rectifier circuit 400 are the same as those of the rectifier circuit 200, and therefore will not be described again here.

[0021] It is worth mentioning that in this embodiment, by setting capacitors C2, C4 and C5, the power supply rejection ratio (PSRR) of the rectifier circuit 400 can be effectively improved, thereby reducing the interference of power supply noise on the output voltage Vout.

[0022] Please refer to Figures 1, 2, and 5 together. Figure 5 is a schematic diagram of a rectifier circuit 500 according to an embodiment of the present invention. The difference between rectifier circuit 500 and rectifier circuit 200 lies in the conductivity of transistors M1 to M3. The other configurations of rectifier circuit 500 are the same as those of rectifier circuit 200, and therefore will not be described again here.

[0023] Unlike rectifier circuit 200, transistors M1 to M3 in rectifier circuit 500 can all be P-type transistors.

[0024] Incidentally, those skilled in the art can determine the conductivity of any of the transistors M1 to M3 in the rectifier circuits 100, 200, and 500 in the foregoing embodiments according to actual needs. In this embodiment, the transistors (e.g., transistors M1 to M3) in the transistor string can all have the same conductivity, or the transistors (e.g., transistors M1 to M3) in the transistor string can have different conductivity values; there are no fixed limitations.

[0025] Please refer to Figures 1 and 6 together. Figure 6 is a flowchart illustrating the operation method of a rectifier circuit according to an embodiment of the present invention. The following description uses rectifier circuit 100 as an example. In step S610, a transistor string 110 having transistors M1 and M2 connected in series is provided; in step S620, a bias generator 120 is provided to generate a bias voltage Vop based on a reference voltage Vref and the output voltage Vout of rectifier circuit 100; in step S630, the bias voltage Vop is provided to the control terminal of transistor M2; in step S640, a level offsetter LS2 is provided to offset the voltage level of bias voltage Vop to generate an offset voltage Vg1. In step S650, the offset voltage Vg1 is provided to the control terminal of transistor M1.

[0026] The implementation details of the above steps have been described in detail in the foregoing embodiments, and will not be repeated here.

[0027] In summary, the rectifier circuit and its operation method of the present invention can ensure that the transistor operates in the saturation region by adding a level offset device. In this way, the rectifier circuit can operate stably under a relatively wide range of power supply voltages, and the ability to suppress power supply noise and the operating range of the rectifier circuit can be improved.

[0028] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0008] Figure 1 is a schematic diagram of a rectifier circuit according to an embodiment of the present invention. Figure 2 is a schematic diagram of a rectifier circuit according to an embodiment of the present invention. Figure 3 is a schematic diagram of a rectifier circuit according to an embodiment of the present invention. Figure 4 is a schematic diagram of a rectifier circuit according to an embodiment of the present invention. Figure 5 is a schematic diagram of a rectifier circuit according to an embodiment of the present invention. Figure 6 is a flowchart of the operation method of the rectifier circuit according to an embodiment of the present invention.

Claims

1. A rectifier circuit, comprising: a transistor string including a first transistor and a second transistor connected in series; a bias generator coupled to a control terminal of the second transistor, generating a first bias voltage based on a reference voltage and an output voltage of the rectifier circuit, and providing the first bias voltage to the control terminal of the second transistor; and a first level offsetter coupled between the control terminals of the first transistor and the second transistor, offsetting the voltage level of the first bias voltage to generate a first offset voltage, and providing the first offset voltage to the control terminal of the first transistor.

2. The rectifier circuit as claimed in claim 1, wherein the second transistor is connected in series between the first transistor and the output terminal of the rectifier circuit.

3. The rectifier circuit as claimed in claim 1, wherein the bias generator is an operational amplifier, the first input terminal of the operational amplifier receives the reference voltage, the second input terminal of the operational amplifier receives the output voltage, and the output terminal of the operational amplifier generates the bias voltage.

4. The rectifier circuit as claimed in claim 1, wherein the first transistor and the second transistor have the same conductivity polarity.

5. The rectifier circuit as claimed in claim 1, wherein the first transistor and the second transistor are both P-type transistors or both N-type transistors.

6. The rectifier circuit as claimed in claim 1 further includes: a load coupled between the output terminal of the rectifier circuit and a reference ground terminal.

7. The rectifier circuit as claimed in claim 1, wherein the transistor string further comprises: a third transistor coupled to the path in which the first transistor receives a power supply voltage, wherein the control terminal of the third transistor receives a second bias voltage.

8. The rectifier circuit as described in claim 7, further comprising: A second level offset is coupled between the control terminal of the first transistor and the control terminal of the third transistor to offset the voltage level of the first offset voltage to generate a second offset voltage and provide the second offset voltage as the second bias voltage.

9. The rectifier circuit as described in claim 7, further comprising: Multiple capacitors are respectively coupled between the control terminals of the first transistor, the second transistor, and the third transistor and a reference ground terminal.

10. The rectifier circuit as described in claim 7, further comprising: Multiple resistors are respectively coupled to the control terminals of the first transistor and the third transistor, wherein the control terminals of the first transistor and the third transistor receive the first offset voltage and the second bias voltage through the resistors respectively.

11. A method of operating a rectifier circuit, comprising: providing a transistor string having a first transistor and a second transistor connected in series; providing a bias generator to generate a first bias voltage based on a reference voltage and an output voltage of the rectifier circuit; providing the first bias voltage to a control terminal of the second transistor; providing a first level offsetter to offset the voltage level of the first bias voltage to generate a first offset voltage; and providing the first offset voltage to a control terminal of the first transistor.

12. The method of operation as claimed in claim 11, wherein the transistor string further has a third transistor coupled in series with the first transistor, the method further comprising: providing a constant second bias voltage to a control terminal of the third transistor.

13. The method of operation as claimed in claim 11, wherein the transistor string further has a third transistor connected in series with the first transistor, the method further comprising: providing a second level offset to offset the voltage level of the first offset voltage to generate a second offset voltage; and providing the second offset voltage to a control terminal of the third transistor.

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