Staggered bit lines for advanced dram

Abstract

The present technology includes vertical cell dynamic random-access memory (DRAM) structures with improve bit line capacitance. Structures include a plurality of lower bit lines arranged in a first horizontal direction in a first horizontal plane. Structures include a plurality of upper bit lines arranged in the first horizontal direction in a second horizontal plane, where the first horizontal plane is vertically spaced apart from the second horizontal plane. Structures include one or more word lines arranged in a second horizontal direction. Structures include one or more channels extending in a vertical direction that is generally orthogonal to the first horizontal direction and the second horizontal direction such that the plurality of lower bit lines and plurality of upper bit lines intersect with a source / drain region of the one or more channels, and the one or more word lines intersect with a gated region of the one or more channels.

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